1//Original:/proj/frio/dv/testcases/core/c_dsp32alu_mix/c_dsp32alu_mix.dsp
2// Spec Reference: dsp32alu mix
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8	R0 = 0;
9	ASTAT = R0;
10
11// ALU operations include parallel addition, subtraction, MAX, MIN, ABS on 16-bit
12// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
13
14	imm32 r2, 0x44445555;
15	imm32 r3, 0x66667777;
16	imm32 r4, 0x88889999;
17	imm32 r5, 0xaaaabbbb;
18	imm32 r6, 0xccccdddd;
19	imm32 r7, 0xeeeeffff;
20
21	imm32 r0, 0x456789ab;
22	imm32 r1, 0x6789abcd;
23// Use only single ALU (ALU0 only), with saturation (S)
24	R2 = R1 + R0 (NS);	/* 0xACF13578 */
25	R3 = R2 + R0 (NS);	/* 0xACF13578 */
26	CHECKREG r2, 0xACF13578;
27	CHECKREG r3, 0xF258BF23;
28	R2 = R1 + R0 (S);	/* 0x7FFFFFFF */
29	R3 = R1 - R0 (NS);	/* 0x22222222 */
30	R4.L = R1.L + R0.L (NS);	/* 0x88883578 */
31	R5.L = R1.L + R0.H (NS);	/* 0xAAAAF134 */
32	R6.L = R1.H + R0.L (NS);	/* 0xCCCCF134 */
33	R7.L = R1.H + R0.H (NS);	/* 0xEEEEACF0 */
34	CHECKREG r2, 0x7FFFFFFF;
35	CHECKREG r3, 0x22222222;
36	CHECKREG r4, 0x88883578;
37	CHECKREG r5, 0xAAAAF134;
38	CHECKREG r6, 0xCCCCF134;
39	CHECKREG r7, 0xEEEEACF0;
40
41	R4.H = R1.L + R0.L (S);	/* 0x80003578 */
42	R5.H = R1.L + R0.H (S);	/* 0xF134F134 */
43	R6.H = R1.H + R0.L (S);	/* 0xF134F134 */
44	CHECKREG r4, 0x80003578;
45	CHECKREG r5, 0xF134F134;
46	CHECKREG r6, 0xF134F134;
47
48	R4.H = R1.L + R0.L (S);	/* 0x80003578 */
49	R5.H = R1.L + R0.H (S);	/* 0xF134F134 */
50	R6.H = R1.H + R0.L (S);	/* 0xF134F134 */
51	CHECKREG r4, 0x80003578;	/* 0x         */
52	CHECKREG r5, 0xF134F134;	/* 0x         */
53	CHECKREG r6, 0xF134F134;	/* 0x         */
54
55	R4.H = R1.L + R0.L (S);	/* 0x80003578 */
56	R5.H = R1.L + R0.H (S);	/* 0xF134F134 */
57	R6.H = R1.H + R0.L (S);	/* 0xF134F134 */
58	R7.H = R1.H + R0.H (S);	/* 0x7FFFACF0 */
59	CHECKREG r4, 0x80003578;	/* 0x         */
60	CHECKREG r5, 0xF134F134;	/* 0x         */
61	CHECKREG r6, 0xF134F134;	/* 0x         */
62	CHECKREG r7, 0x7FFFACF0;	/* 0x         */
63
64// Dual
65	R2 = R0 +|+ R1 (SCO);	/* 0x80007FFF */
66	R3 = R0 +|- R1 (S);	/* 0x7FFFDDDE */
67	R4 = R0 -|+ R1 (SCO);	/* 0x8000DDDE)*/
68	R5 = R0 -|- R1 (SCO);	/* 0xDDDEDDDE */
69	CHECKREG r2, 0x80007FFF;
70	CHECKREG r3, 0x7FFFDDDE;
71	CHECKREG r4, 0x8000DDDE;
72	CHECKREG r5, 0xDDDEDDDE;
73	R2 = R0 +|+ R1, R3 = R0 -|- R1 (SCO);	/* 0x         */
74CHECKREG r2, 0x7FFF8000;
75	R4 = R0 +|- R1 , R5 = R0 -|+ R1 (CO);	/* 0x         */
76	R6 = R0 + R1, R7 = R0 - R1 (S);	/* 0x         */
77	CHECKREG r2, 0x7FFF8000;
78	CHECKREG r3, 0xDDDEDDDE;
79	CHECKREG r4, 0xACF0DDDE;
80	CHECKREG r5, 0x3578DDDE;
81	CHECKREG r6, 0x7FFFFFFF;
82	CHECKREG r7, 0xDDDDDDDE;
83
84// Max min abs types
85	R3 = MAX ( R0 , R1 );	/* 0x6789ABCD */
86	R4 = MIN ( R0 , R1 );	/* 0x456789AB */
87	R5 = ABS R0;	/* 0x456789AB */
88	CHECKREG r3, 0x6789ABCD;
89	CHECKREG r4, 0x456789AB;
90	CHECKREG r5, 0x456789AB;
91	R3 = MAX ( R0 , R1 ) (V);	/* 0x6789ABCD */
92	R4 = MIN ( R0 , R1 ) (V);	/* 0x456789AB */
93	R5 = ABS R0 (V);	/* 0x45677655 */
94	CHECKREG r3, 0x6789ABCD;
95	CHECKREG r4, 0x456789AB;
96	CHECKREG r5, 0x45677655;
97
98// RND types
99	R2.H = R2.L = SIGN(R0.H) * R1.H + SIGN(R0.L) * R1.L;
100	R3.L = R0 + R1 (RND12);	/* 0x         */
101	R4.H = R0 - R1 (RND12);	/* 0x         */
102	R5.L = R0 + R1 (RND20);	/* 0x         */
103	R6.H = R0 - R1 (RND20);	/* 0x         */
104	R7.H = R1 (RND);	/* 0x         */
105	CHECKREG r2, 0xBBBCBBBC;
106	CHECKREG r3, 0x67897FFF;
107	CHECKREG r4, 0x800089AB;
108	CHECKREG r5, 0x45670ACF;
109	CHECKREG r6, 0xFDDEFFFF;
110	CHECKREG r7, 0x678ADDDE;
111
112	R7 = - R0 (V);	/* 0x         */
113	CHECKREG r7, 0xBA997655;
114// A0 & A1 types
115	A0 = 0;
116	A1 = 0;
117	A0.L = R0.L;
118	A0.H = R0.H;
119	A0 = A1;
120	A0.x = R0.L;
121	A1.x = R0.L;
122	R2.L = A0.x;	/* 0x         */
123	R3.L = A1.x;	/* 0x         */
124	R4 = ( A0 += A1 );	/* 0x         */
125	R5.L = ( A0 += A1 );	/* 0x         */
126	R5.H = ( A0 += A1 );	/* 0x         */
127	CHECKREG r2, 0xBBBCffAB;	/* 0x         */
128	CHECKREG r3, 0x6789ffAB;	/* 0x         */
129	CHECKREG r4, 0x80000000;	/* 0x         */
130	CHECKREG r5, 0x80008000;	/* 0x         */
131	A0 += A1;
132	A0 -= A1;
133	R6 = A1.L + A1.H, R7 = A0.L + A0.H;	/* 0x         */
134	CHECKREG r6, 0x00000000;
135	CHECKREG r7, 0x00000000;
136
137	pass
138