1# mach: aarch64
2
3# Check the load single 1-element structure to one lane instructions:
4# ld1, ld2, ld3, ld4.
5# Check the addressing modes: no offset, post-index immediate offset,
6# post-index register offset.
7
8.include "testutils.inc"
9
10	.data
11	.align 4
12input:
13	.word 0x04030201
14	.word 0x08070605
15	.word 0x0c0b0a09
16	.word 0x100f0e0d
17	.word 0x14131211
18	.word 0x18171615
19	.word 0x1c1b1a19
20	.word 0x201f1e1d
21
22	start
23	adrp x0, input
24	add x0, x0, :lo12:input
25
26	mov x2, x0
27	mov x3, #1
28	mov x4, #4
29	ld1 {v0.b}[0], [x2], 1
30	ld1 {v0.b}[1], [x2], x3
31	ld1 {v0.h}[1], [x2], 2
32	ld1 {v0.s}[1], [x2], x4
33	ld1 {v0.d}[1], [x2]
34	addv b1, v0.16b
35	mov x5, v1.d[0]
36	cmp x5, #136
37	bne .Lfailure
38
39	mov x2, x0
40	mov x3, #16
41	mov x4, #4
42	ld2 {v0.d, v1.d}[0], [x2], x3
43	ld2 {v0.s, v1.s}[2], [x2], 8
44	ld2 {v0.h, v1.h}[6], [x2], x4
45	ld2 {v0.b, v1.b}[14], [x2], 2
46	ld2 {v0.b, v1.b}[15], [x2]
47	addv b2, v0.16b
48	addv b3, v1.16b
49	mov x5, v2.d[0]
50	mov x6, v3.d[0]
51	cmp x5, #221
52	bne .Lfailure
53	cmp x6, #51
54	bne .Lfailure
55
56	mov x2, x0
57	ld3 {v0.s, v1.s, v2.s}[0], [x2], 12
58	ld3 {v0.s, v1.s, v2.s}[1], [x2]
59	mov x2, x0
60	mov x3, #12
61	ld3 {v0.s, v1.s, v2.s}[2], [x2], x3
62	ld3 {v0.s, v1.s, v2.s}[3], [x2]
63	addv b3, v0.16b
64	addv b4, v1.16b
65	addv b5, v2.16b
66	mov x4, v3.d[0]
67	mov x5, v4.d[0]
68	mov x6, v5.d[0]
69	cmp x4, #136
70	bne .Lfailure
71	cmp x5, #200
72	bne .Lfailure
73	cmp x6, #8
74	bne .Lfailure
75
76	mov x2, x0
77	ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
78	ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2]
79	mov x2, x0
80	mov x3, #16
81	ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3
82	ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
83	addv b4, v0.16b
84	addv b5, v1.16b
85	addv b6, v2.16b
86	addv b7, v3.16b
87	mov x4, v4.d[0]
88	mov x5, v5.d[0]
89	mov x6, v6.d[0]
90	mov x7, v7.d[0]
91	cmp x4, #168
92	bne .Lfailure
93	cmp x5, #232
94	bne .Lfailure
95	cmp x6, #40
96	bne .Lfailure
97	cmp x7, #104
98	bne .Lfailure
99
100	pass
101.Lfailure:
102	fail
103