1/* Copyright 2016-2023 Free Software Foundation, Inc.
2   Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
3
4   This file is part of the PRU simulator.
5
6   This library is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3 of the License, or
9   (at your option) any later version.
10
11   This program is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program; if not, see <http://www.gnu.org/licenses/>.  */
18
19#ifndef PRU_SIM_MAIN
20#define PRU_SIM_MAIN
21
22#include <stdint.h>
23#include <stddef.h>
24#include "pru.h"
25#include "sim-basics.h"
26
27#include "sim-base.h"
28
29/* The machine state.
30   This state is maintained in host byte order.  The
31   fetch/store register functions must translate between host
32   byte order and the target processor byte order.
33   Keeping this data in target byte order simplifies the register
34   read/write functions.  Keeping this data in host order improves
35   the performance of the simulator.  Simulation speed is deemed more
36   important.  */
37
38/* For clarity, please keep the same relative order in this enum as in the
39   corresponding group of GP registers.
40
41   In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
42   the GP registers.  MAC registers are implicitly addressed when executing
43   the XIN/XOUT instructions to access them.  Transfer to/from a MAC register
44   can happen only from/to its corresponding GP peer register.  */
45
46enum pru_macreg_id {
47    /* MAC register	  CPU GP register     Description.  */
48    PRU_MACREG_MODE,	  /* r25 */	      /* Mode (MUL/MAC).  */
49    PRU_MACREG_PROD_L,	  /* r26 */	      /* Lower 32 bits of product.  */
50    PRU_MACREG_PROD_H,	  /* r27 */	      /* Higher 32 bits of product.  */
51    PRU_MACREG_OP_0,	  /* r28 */	      /* First operand.  */
52    PRU_MACREG_OP_1,	  /* r29 */	      /* Second operand.  */
53    PRU_MACREG_ACC_L,	  /* N/A */	      /* Accumulator (not exposed)  */
54    PRU_MACREG_ACC_H,	  /* N/A */	      /* Higher 32 bits of MAC
55						 accumulator.  */
56    PRU_MAC_NREGS
57};
58
59struct pru_regset
60{
61  uint32_t	  regs[32];		/* Primary registers.  */
62  uint16_t	  pc;			/* IMEM _word_ address.  */
63  uint32_t	  pc_addr_space_marker; /* IMEM virtual linker offset.  This
64					   is the artificial offset that
65					   we invent in order to "separate"
66					   the DMEM and IMEM memory spaces.  */
67  unsigned int	  carry : 1;
68  uint32_t	  ctable[32];		/* Constant offsets table for xBCO.  */
69  uint32_t	  macregs[PRU_MAC_NREGS];
70  uint32_t	  scratchpads[XFRID_MAX + 1][32];
71  struct {
72    uint16_t looptop;			/* LOOP top (PC of loop instr).  */
73    uint16_t loopend;			/* LOOP end (PC of loop end label).  */
74    int loop_in_progress;		/* Whether to check for PC==loopend.  */
75    uint32_t loop_counter;		/* LOOP counter.  */
76  } loop;
77  int		  cycles;
78  int		  insts;
79};
80
81struct _sim_cpu {
82  struct pru_regset pru_cpu;
83  sim_cpu_base base;
84};
85
86#endif /* PRU_SIM_MAIN */
87