1/* Main header for the Hitachi h8/300 architecture.  */
2
3#include "bfd.h"
4
5#ifndef SIM_MAIN_H
6#define SIM_MAIN_H
7
8#define DEBUG
9
10/* These define the size of main memory for the simulator.
11
12   Note the size of main memory for the H8/300H is only 256k.  Keeping it
13   small makes the simulator run much faster and consume less memory.
14
15   The linker knows about the limited size of the simulator's main memory
16   on the H8/300H (via the h8300h.sc linker script).  So if you change
17   H8300H_MSIZE, be sure to fix the linker script too.
18
19   Also note that there's a separate "eightbit" area aside from main
20   memory.  For simplicity, the simulator assumes any data memory reference
21   outside of main memory refers to the eightbit area (in theory, this
22   can only happen when simulating H8/300H programs).  We make no attempt
23   to catch overlapping addresses, wrapped addresses, etc etc.  */
24
25#define H8300_MSIZE (1 << 16)
26
27/* avolkov:
28   Next 2 macros are ugly for any workstation, but while they're work.
29   Memory size MUST be configurable.  */
30#define H8300H_MSIZE (1 << 24)
31#define H8300S_MSIZE (1 << 24)
32
33#define CSIZE 1024
34
35enum h8_regnum {
36  R0_REGNUM = 0,
37  R1_REGNUM = 1,
38  R2_REGNUM = 2,
39  R3_REGNUM = 3,
40  R4_REGNUM = 4,
41  R5_REGNUM = 5,
42  R6_REGNUM = 6,
43  R7_REGNUM = 7,
44
45  SP_REGNUM = R7_REGNUM,	/* Contains address of top of stack */
46  FP_REGNUM = R6_REGNUM,	/* Contains address of executing
47				   stack frame */
48  CCR_REGNUM = 8,		/* Contains processor status */
49  PC_REGNUM  = 9,		/* Contains program counter */
50  CYCLE_REGNUM = 10,
51  EXR_REGNUM  = 11,
52  INST_REGNUM = 12,
53  TICK_REGNUM = 13,
54  MACH_REGNUM = 14,
55  MACL_REGNUM = 15,
56  SBR_REGNUM =  16,
57  VBR_REGNUM =  17,
58
59  ZERO_REGNUM = 18
60};
61
62enum h8_typecodes {
63  OP_NULL,
64  OP_REG,		/* Register direct.  */
65  OP_LOWREG,		/* Special reg syntax for "bra".  */
66  OP_DISP,		/* Register indirect w/displacement.  */
67  /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
68  OP_PREDEC,		/* Register indirect w/pre-decrement.  */
69  OP_POSTDEC,		/* Register indirect w/post-decrement.  */
70  OP_PREINC,		/* Register indirect w/pre-increment.  */
71  OP_POSTINC,		/* Register indirect w/post-increment.  */
72  OP_PCREL,		/* PC Relative.  */
73  OP_MEM,		/* Absolute memory address.  */
74  OP_CCR,		/* Condition Code Register.  */
75  OP_IMM,		/* Immediate value.  */
76  /*OP_ABS*/		/* Un-used (duplicates op_mem?).  */
77  OP_EXR,		/* EXtended control Register.  */
78  OP_SBR, 		/* Vector Base Register.  */
79  OP_VBR,		/* Short-address Base Register.  */
80  OP_MACH,		/* Multiply Accumulator - high.  */
81  OP_MACL,		/* Multiply Accumulator - low.   */
82  /* FIXME: memory indirect?  */
83  OP_INDEXB,		/* Byte index mode */
84  OP_INDEXW,		/* Word index mode */
85  OP_INDEXL,		/* Long index mode */
86  OP_REG_DEC,		/* Register direct. affect address decrement. */
87  OP_REG_INC,		/* Register direct. affect address increment. */
88};
89
90#include "sim-basics.h"
91#include "sim-base.h"
92
93/* Structure used to describe addressing */
94
95typedef struct
96{
97  int type;
98  int reg;
99  int literal;
100} ea_type;
101
102/* Struct for instruction decoder.  */
103typedef struct
104{
105  ea_type src;
106  ea_type dst;
107  ea_type op3;
108  int opcode;
109  int next_pc;
110  int oldpc;
111  int cycles;
112#ifdef DEBUG
113  struct h8_opcode *op;
114#endif
115} decoded_inst;
116
117struct _sim_cpu {
118  unsigned int regs[20];	/* 8 GR's plus ZERO, SBR, and VBR.  */
119  unsigned int pc;
120
121  int macS;			/* MAC Saturating mode */
122  int macV;			/* MAC Overflow */
123  int macN;			/* MAC Negative */
124  int macZ;			/* MAC Zero     */
125
126  int delayed_branch;
127  char **command_line;		/* Pointer to command line arguments.  */
128
129  unsigned char *memory;
130  int mask;
131
132  sim_cpu_base base;
133};
134
135struct h8300_sim_state {
136  unsigned long memory_size;
137#ifdef ADEBUG
138  int stats[O_LAST];
139#endif
140};
141#define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
142
143/* The current state of the processor; registers, memory, etc.  */
144
145#define cpu_set_pc(CPU, VAL)	(((CPU)->pc)  = (VAL))
146#define cpu_get_pc(CPU)		(((CPU)->pc))
147
148/* Magic numbers used to distinguish an exit from a breakpoint.  */
149#define LIBC_EXIT_MAGIC1 0xdead
150#define LIBC_EXIT_MAGIC2 0xbeef
151/* Local version of macros for decoding exit status.
152   (included here rather than try to find target version of wait.h)
153*/
154#define SIM_WIFEXITED(V)	(((V) & 0xff) == 0)
155#define SIM_WIFSTOPPED(V)	(!SIM_WIFEXITED (V))
156#define SIM_WEXITSTATUS(V)	(((V) >> 8) & 0xff)
157#define SIM_WSTOPSIG(V)		((V) & 0x7f)
158
159#endif /* SIM_MAIN_H */
160