1/* This file is part of SIS (SPARC instruction simulator)
2
3   Copyright (C) 1995-2023 Free Software Foundation, Inc.
4   Contributed by Jiri Gaisler, European Space Agency
5
6   This program is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3 of the License, or
9   (at your option) any later version.
10
11   This program is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18
19/* The control space devices */
20
21/* This must come before any other includes.  */
22#include "defs.h"
23
24#include <sys/types.h>
25#include <stdio.h>
26#include <string.h>
27#ifdef HAVE_TERMIOS_H
28#include <termios.h>
29#endif
30#include <sys/fcntl.h>
31#include <sys/file.h>
32#include <unistd.h>
33#include "sis.h"
34#include "sim-config.h"
35
36extern int      ctrl_c;
37extern int32_t    sis_verbose;
38extern int32_t    sparclite, sparclite_board;
39extern int      rom8,wrp,uben;
40extern char     uart_dev1[], uart_dev2[];
41
42int dumbio = 0; /* normal, smart, terminal oriented IO by default */
43
44/* MEC registers */
45#define MEC_START 	0x01f80000
46#define MEC_END 	0x01f80100
47
48/* Memory exception waitstates */
49#define MEM_EX_WS 	1
50
51/* ERC32 always adds one waitstate during RAM std */
52#define STD_WS 1
53
54#ifdef ERRINJ
55extern int errmec;
56#endif
57
58#define MEC_WS	0		/* Waitstates per MEC access (0 ws) */
59#define MOK	0
60
61/* MEC register addresses */
62
63#define MEC_MCR		0x000
64#define MEC_SFR  	0x004
65#define MEC_PWDR  	0x008
66#define MEC_MEMCFG	0x010
67#define MEC_IOCR	0x014
68#define MEC_WCR		0x018
69
70#define MEC_MAR0  	0x020
71#define MEC_MAR1  	0x024
72
73#define MEC_SSA1 	0x020
74#define MEC_SEA1 	0x024
75#define MEC_SSA2 	0x028
76#define MEC_SEA2 	0x02C
77#define MEC_ISR		0x044
78#define MEC_IPR		0x048
79#define MEC_IMR 	0x04C
80#define MEC_ICR 	0x050
81#define MEC_IFR 	0x054
82#define MEC_WDOG  	0x060
83#define MEC_TRAPD  	0x064
84#define MEC_RTC_COUNTER	0x080
85#define MEC_RTC_RELOAD	0x080
86#define MEC_RTC_SCALER	0x084
87#define MEC_GPT_COUNTER	0x088
88#define MEC_GPT_RELOAD	0x088
89#define MEC_GPT_SCALER	0x08C
90#define MEC_TIMER_CTRL	0x098
91#define MEC_SFSR	0x0A0
92#define MEC_FFAR	0x0A4
93#define MEC_ERSR	0x0B0
94#define MEC_DBG		0x0C0
95#define MEC_TCR		0x0D0
96
97#define MEC_BRK		0x0C4
98#define MEC_WPR		0x0C8
99
100#define MEC_UARTA	0x0E0
101#define MEC_UARTB	0x0E4
102#define MEC_UART_CTRL	0x0E8
103#define SIM_LOAD	0x0F0
104
105/* Memory exception causes */
106#define PROT_EXC	0x3
107#define UIMP_ACC	0x4
108#define MEC_ACC		0x6
109#define WATCH_EXC	0xa
110#define BREAK_EXC	0xb
111
112/* Size of UART buffers (bytes) */
113#define UARTBUF	1024
114
115/* Number of simulator ticks between flushing the UARTS. 	 */
116/* For good performance, keep above 1000			 */
117#define UART_FLUSH_TIME	  3000
118
119/* MEC timer control register bits */
120#define TCR_GACR 1
121#define TCR_GACL 2
122#define TCR_GASE 4
123#define TCR_GASL 8
124#define TCR_TCRCR 0x100
125#define TCR_TCRCL 0x200
126#define TCR_TCRSE 0x400
127#define TCR_TCRSL 0x800
128
129/* New uart defines */
130#define UART_TX_TIME	1000
131#define UART_RX_TIME	1000
132#define UARTA_DR	0x1
133#define UARTA_SRE	0x2
134#define UARTA_HRE	0x4
135#define UARTA_OR	0x40
136#define UARTA_CLR	0x80
137#define UARTB_DR	0x10000
138#define UARTB_SRE	0x20000
139#define UARTB_HRE	0x40000
140#define UARTB_OR	0x400000
141#define UARTB_CLR	0x800000
142
143#define UART_DR		0x100
144#define UART_TSE	0x200
145#define UART_THE	0x400
146
147/* MEC registers */
148
149static char     fname[256];
150static int32_t    find = 0;
151static uint32_t   mec_ssa[2];	/* Write protection start address */
152static uint32_t   mec_sea[2];	/* Write protection end address */
153static uint32_t   mec_wpr[2];	/* Write protection control fields */
154static uint32_t   mec_sfsr;
155static uint32_t   mec_ffar;
156static uint32_t   mec_ipr;
157static uint32_t   mec_imr;
158static uint32_t   mec_isr;
159static uint32_t   mec_icr;
160static uint32_t   mec_ifr;
161static uint32_t   mec_mcr;	/* MEC control register */
162static uint32_t   mec_memcfg;	/* Memory control register */
163static uint32_t   mec_wcr;	/* MEC waitstate register */
164static uint32_t   mec_iocr;	/* MEC IO control register */
165static uint32_t   posted_irq;
166static uint32_t   mec_ersr;	/* MEC error and status register */
167static uint32_t   mec_tcr;	/* MEC test comtrol register */
168
169static uint32_t   rtc_counter;
170static uint32_t   rtc_reload;
171static uint32_t   rtc_scaler;
172static uint32_t   rtc_scaler_start;
173static uint32_t   rtc_enabled;
174static uint32_t   rtc_cr;
175static uint32_t   rtc_se;
176
177static uint32_t   gpt_counter;
178static uint32_t   gpt_reload;
179static uint32_t   gpt_scaler;
180static uint32_t   gpt_scaler_start;
181static uint32_t   gpt_enabled;
182static uint32_t   gpt_cr;
183static uint32_t   gpt_se;
184
185static uint32_t   wdog_scaler;
186static uint32_t   wdog_counter;
187static uint32_t   wdog_rst_delay;
188static uint32_t   wdog_rston;
189
190enum wdog_type {
191    init, disabled, enabled, stopped
192};
193
194static enum wdog_type wdog_status;
195
196
197/* ROM size 1024 Kbyte */
198#define ROM_SZ	 	0x100000
199#define ROM_MASK 	0x0fffff
200
201/* RAM size 4 Mbyte */
202#define RAM_START 	0x02000000
203#define RAM_END 	0x02400000
204#define RAM_MASK 	0x003fffff
205
206/* SPARClite boards all seem to have RAM at the same place. */
207#define RAM_START_SLITE	0x40000000
208#define RAM_END_SLITE 	0x40400000
209#define RAM_MASK_SLITE 	0x003fffff
210
211/* Memory support variables */
212
213static uint32_t   mem_ramr_ws;	/* RAM read waitstates */
214static uint32_t   mem_ramw_ws;	/* RAM write waitstates */
215static uint32_t   mem_romr_ws;	/* ROM read waitstates */
216static uint32_t   mem_romw_ws;	/* ROM write waitstates */
217static uint32_t	mem_ramstart;	/* RAM start */
218static uint32_t	mem_ramend;	/* RAM end */
219static uint32_t	mem_rammask;	/* RAM address mask */
220static uint32_t   mem_ramsz;	/* RAM size */
221static uint32_t   mem_romsz;	/* ROM size */
222static uint32_t   mem_accprot;	/* RAM write protection enabled */
223static uint32_t   mem_blockprot;	/* RAM block write protection enabled */
224
225static unsigned char	romb[ROM_SZ];
226static unsigned char	ramb[RAM_END - RAM_START];
227
228
229/* UART support variables */
230
231static int32_t    fd1, fd2;	/* file descriptor for input file */
232static int32_t    Ucontrol;	/* UART status register */
233static unsigned char aq[UARTBUF], bq[UARTBUF];
234static int32_t    anum, aind = 0;
235static int32_t    bnum, bind = 0;
236static char     wbufa[UARTBUF], wbufb[UARTBUF];
237static unsigned wnuma;
238static unsigned wnumb;
239static FILE    *f1in, *f1out, *f2in, *f2out;
240#ifdef HAVE_TERMIOS_H
241static struct termios ioc1, ioc2, iocold1, iocold2;
242#endif
243static int      f1open = 0, f2open = 0;
244
245static char     uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
246static uint32_t   uart_stat_reg;
247static uint32_t   uarta_data, uartb_data;
248
249#ifdef ERA
250int era = 0;
251int erareg;
252#endif
253
254/* Forward declarations */
255
256static void	decode_ersr (void);
257#ifdef ERRINJ
258static void	iucomperr (void);
259#endif
260static void	mecparerror (void);
261static void	decode_memcfg (void);
262static void	decode_wcr (void);
263static void	decode_mcr (void);
264static void	close_port (void);
265static void	mec_reset (void);
266static void	mec_intack (int32_t level);
267static void	chk_irq (void);
268static void	mec_irq (int32_t level);
269static void	set_sfsr (uint32_t fault, uint32_t addr,
270			  uint32_t asi, uint32_t read);
271static int32_t	mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
272static int	mec_write (uint32_t addr, uint32_t data);
273static void	port_init (void);
274static uint32_t	read_uart (uint32_t addr);
275static void	write_uart (uint32_t addr, uint32_t data);
276static void	flush_uart (void);
277static void	uarta_tx (int32_t);
278static void	uartb_tx (int32_t);
279static void	uart_rx (int32_t);
280static void	uart_intr (int32_t);
281static void	uart_irq_start (void);
282static void	wdog_intr (int32_t);
283static void	wdog_start (void);
284static void	rtc_intr (int32_t);
285static void	rtc_start (void);
286static uint32_t	rtc_counter_read (void);
287static void	rtc_scaler_set (uint32_t val);
288static void	rtc_reload_set (uint32_t val);
289static void	gpt_intr (int32_t);
290static void	gpt_start (void);
291static uint32_t	gpt_counter_read (void);
292static void	gpt_scaler_set (uint32_t val);
293static void	gpt_reload_set (uint32_t val);
294static void	timer_ctrl (uint32_t val);
295static void *	get_mem_ptr (uint32_t addr, uint32_t size);
296static void	store_bytes (unsigned char *mem, uint32_t waddr,
297			uint32_t *data, int sz, int32_t *ws);
298
299extern int	ext_irl;
300
301
302/* One-time init */
303
304void
305init_sim(void)
306{
307    port_init();
308}
309
310/* Power-on reset init */
311
312void
313reset(void)
314{
315    mec_reset();
316    uart_irq_start();
317    wdog_start();
318}
319
320static void
321decode_ersr(void)
322{
323    if (mec_ersr & 0x01) {
324	if (!(mec_mcr & 0x20)) {
325	    if (mec_mcr & 0x40) {
326	        sys_reset();
327	        mec_ersr = 0x8000;
328	        if (sis_verbose)
329	            printf("Error manager reset - IU in error mode\n");
330	    } else {
331	        sys_halt();
332	        mec_ersr |= 0x2000;
333	        if (sis_verbose)
334	            printf("Error manager halt - IU in error mode\n");
335	    }
336	} else
337	    mec_irq(1);
338    }
339    if (mec_ersr & 0x04) {
340	if (!(mec_mcr & 0x200)) {
341	    if (mec_mcr & 0x400) {
342	        sys_reset();
343	        mec_ersr = 0x8000;
344	        if (sis_verbose)
345	            printf("Error manager reset - IU comparison error\n");
346	    } else {
347	        sys_halt();
348	        mec_ersr |= 0x2000;
349	        if (sis_verbose)
350	            printf("Error manager halt - IU comparison error\n");
351	    }
352	} else
353	    mec_irq(1);
354    }
355    if (mec_ersr & 0x20) {
356	if (!(mec_mcr & 0x2000)) {
357	    if (mec_mcr & 0x4000) {
358	        sys_reset();
359	        mec_ersr = 0x8000;
360	        if (sis_verbose)
361	            printf("Error manager reset - MEC hardware error\n");
362	    } else {
363	        sys_halt();
364	        mec_ersr |= 0x2000;
365	        if (sis_verbose)
366	            printf("Error manager halt - MEC hardware error\n");
367	    }
368	} else
369	    mec_irq(1);
370    }
371}
372
373#ifdef ERRINJ
374static void
375iucomperr()
376{
377    mec_ersr |= 0x04;
378    decode_ersr();
379}
380#endif
381
382static void
383mecparerror(void)
384{
385    mec_ersr |= 0x20;
386    decode_ersr();
387}
388
389
390/* IU error mode manager */
391
392void
393error_mode(uint32_t pc)
394{
395
396    mec_ersr |= 0x1;
397    decode_ersr();
398}
399
400
401/* Check memory settings */
402
403static void
404decode_memcfg(void)
405{
406    if (rom8) mec_memcfg &= ~0x20000;
407    else mec_memcfg |= 0x20000;
408
409    mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
410    mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
411
412    if (sparclite_board) {
413	mem_ramstart = RAM_START_SLITE;
414	mem_ramend = RAM_END_SLITE;
415	mem_rammask = RAM_MASK_SLITE;
416    }
417    else {
418	mem_ramstart = RAM_START;
419	mem_ramend = RAM_END;
420	mem_rammask = RAM_MASK;
421    }
422    if (sis_verbose)
423	printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
424	       mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
425}
426
427static void
428decode_wcr(void)
429{
430    mem_ramr_ws = mec_wcr & 3;
431    mem_ramw_ws = (mec_wcr >> 2) & 3;
432    mem_romr_ws = (mec_wcr >> 4) & 0x0f;
433    if (rom8) {
434    	if (mem_romr_ws > 0 )  mem_romr_ws--;
435	mem_romr_ws = 5 + (4*mem_romr_ws);
436    }
437    mem_romw_ws = (mec_wcr >> 8) & 0x0f;
438    if (sis_verbose)
439	printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
440	       mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
441}
442
443static void
444decode_mcr(void)
445{
446    mem_accprot = (mec_wpr[0] | mec_wpr[1]);
447    mem_blockprot = (mec_mcr >> 3) & 1;
448    if (sis_verbose && mem_accprot)
449	printf("Memory block write protection enabled\n");
450    if (mec_mcr & 0x08000) {
451	mec_ersr |= 0x20;
452	decode_ersr();
453    }
454    if (sis_verbose && (mec_mcr & 2))
455	printf("Software reset enabled\n");
456    if (sis_verbose && (mec_mcr & 1))
457	printf("Power-down mode enabled\n");
458}
459
460/* Flush ports when simulator stops */
461
462void
463sim_halt(void)
464{
465#ifdef FAST_UART
466    flush_uart();
467#endif
468}
469
470int
471sim_stop(SIM_DESC sd)
472{
473  ctrl_c = 1;
474  return 1;
475}
476
477static void
478close_port(void)
479{
480    if (f1open && f1in != stdin)
481	fclose(f1in);
482    if (f2open && f2in != stdin)
483	fclose(f2in);
484}
485
486void
487exit_sim(void)
488{
489    close_port();
490}
491
492static void
493mec_reset(void)
494{
495    int             i;
496
497    find = 0;
498    for (i = 0; i < 2; i++)
499	mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
500    mec_mcr = 0x01350014;
501    mec_iocr = 0;
502    mec_sfsr = 0x078;
503    mec_ffar = 0;
504    mec_ipr = 0;
505    mec_imr = 0x7ffe;
506    mec_isr = 0;
507    mec_icr = 0;
508    mec_ifr = 0;
509    mec_memcfg = 0x10000;
510    mec_wcr = -1;
511    mec_ersr = 0;		/* MEC error and status register */
512    mec_tcr = 0;		/* MEC test comtrol register */
513
514    decode_memcfg();
515    decode_wcr();
516    decode_mcr();
517
518    posted_irq = 0;
519    wnuma = wnumb = 0;
520    anum = aind = bnum = bind = 0;
521
522    uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
523    uarta_data = uartb_data = UART_THE | UART_TSE;
524
525    rtc_counter = 0xffffffff;
526    rtc_reload = 0xffffffff;
527    rtc_scaler = 0xff;
528    rtc_enabled = 0;
529    rtc_cr = 0;
530    rtc_se = 0;
531
532    gpt_counter = 0xffffffff;
533    gpt_reload = 0xffffffff;
534    gpt_scaler = 0xffff;
535    gpt_enabled = 0;
536    gpt_cr = 0;
537    gpt_se = 0;
538
539    wdog_scaler = 255;
540    wdog_rst_delay = 255;
541    wdog_counter = 0xffff;
542    wdog_rston = 0;
543    wdog_status = init;
544
545#ifdef ERA
546    erareg = 0;
547#endif
548
549}
550
551
552
553static void
554mec_intack(int32_t level)
555{
556    int             irq_test;
557
558    if (sis_verbose)
559	printf("interrupt %d acknowledged\n", level);
560    irq_test = mec_tcr & 0x80000;
561    if ((irq_test) && (mec_ifr & (1 << level)))
562	mec_ifr &= ~(1 << level);
563    else
564	mec_ipr &= ~(1 << level);
565   chk_irq();
566}
567
568static void
569chk_irq(void)
570{
571    int32_t           i;
572    uint32_t          itmp;
573    int		    old_irl;
574
575    old_irl = ext_irl;
576    if (mec_tcr & 0x80000) itmp = mec_ifr;
577    else itmp  = 0;
578    itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
579    ext_irl = 0;
580    if (itmp != 0) {
581	for (i = 15; i > 0; i--) {
582	    if (((itmp >> i) & 1) != 0) {
583		if ((sis_verbose) && (i > old_irl))
584		    printf("IU irl: %d\n", i);
585		ext_irl = i;
586	        set_int(i, mec_intack, i);
587		break;
588	    }
589	}
590    }
591}
592
593static void
594mec_irq(int32_t level)
595{
596    mec_ipr |= (1 << level);
597    chk_irq();
598}
599
600static void
601set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
602{
603    if ((asi == 0xa) || (asi == 0xb)) {
604	mec_ffar = addr;
605	mec_sfsr = (fault << 3) | (!read << 15);
606	mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
607	switch (asi) {
608	case 0xa:
609	    mec_sfsr |= 0x0004;
610	    break;
611	case 0xb:
612	    mec_sfsr |= 0x1004;
613	    break;
614	}
615    }
616}
617
618static int32_t
619mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
620{
621
622    switch (addr & 0x0ff) {
623
624    case MEC_MCR:		/* 0x00 */
625	*data = mec_mcr;
626	break;
627
628    case MEC_MEMCFG:		/* 0x10 */
629	*data = mec_memcfg;
630	break;
631
632    case MEC_IOCR:
633	*data = mec_iocr;	/* 0x14 */
634	break;
635
636    case MEC_SSA1:		/* 0x20 */
637	*data = mec_ssa[0] | (mec_wpr[0] << 23);
638	break;
639    case MEC_SEA1:		/* 0x24 */
640	*data = mec_sea[0];
641	break;
642    case MEC_SSA2:		/* 0x28 */
643	*data = mec_ssa[1] | (mec_wpr[1] << 23);
644	break;
645    case MEC_SEA2:		/* 0x2c */
646	*data = mec_sea[1];
647	break;
648
649    case MEC_ISR:		/* 0x44 */
650	*data = mec_isr;
651	break;
652
653    case MEC_IPR:		/* 0x48 */
654	*data = mec_ipr;
655	break;
656
657    case MEC_IMR:		/* 0x4c */
658	*data = mec_imr;
659	break;
660
661    case MEC_IFR:		/* 0x54 */
662	*data = mec_ifr;
663	break;
664
665    case MEC_RTC_COUNTER:	/* 0x80 */
666	*data = rtc_counter_read();
667	break;
668    case MEC_RTC_SCALER:	/* 0x84 */
669	if (rtc_enabled)
670	    *data = rtc_scaler - (now() - rtc_scaler_start);
671	else
672	    *data = rtc_scaler;
673	break;
674
675    case MEC_GPT_COUNTER:	/* 0x88 */
676	*data = gpt_counter_read();
677	break;
678
679    case MEC_GPT_SCALER:	/* 0x8c */
680	if (rtc_enabled)
681	    *data = gpt_scaler - (now() - gpt_scaler_start);
682	else
683	    *data = gpt_scaler;
684	break;
685
686
687    case MEC_SFSR:		/* 0xA0 */
688	*data = mec_sfsr;
689	break;
690
691    case MEC_FFAR:		/* 0xA4 */
692	*data = mec_ffar;
693	break;
694
695    case SIM_LOAD:
696	fname[find] = 0;
697	if (find == 0)
698	    strcpy(fname, "simload");
699	find = bfd_load(fname);
700 	if (find == -1)
701	    *data = 0;
702	else
703	    *data = 1;
704	find = 0;
705	break;
706
707    case MEC_ERSR:		/* 0xB0 */
708	*data = mec_ersr;
709	break;
710
711    case MEC_TCR:		/* 0xD0 */
712	*data = mec_tcr;
713	break;
714
715    case MEC_UARTA:		/* 0xE0 */
716    case MEC_UARTB:		/* 0xE4 */
717	if (asi != 0xb) {
718	    set_sfsr(MEC_ACC, addr, asi, 1);
719	    return 1;
720	}
721	*data = read_uart(addr);
722	break;
723
724    case MEC_UART_CTRL:		/* 0xE8 */
725
726	*data = read_uart(addr);
727	break;
728
729    case 0xF4:		/* simulator RAM size in bytes */
730	*data = 4096*1024;
731	break;
732
733    case 0xF8:		/* simulator ROM size in bytes */
734	*data = 1024*1024;
735	break;
736
737    default:
738	set_sfsr(MEC_ACC, addr, asi, 1);
739	return 1;
740	break;
741    }
742    return MOK;
743}
744
745static int
746mec_write(uint32_t addr, uint32_t data)
747{
748    if (sis_verbose > 1)
749	printf("MEC write a: %08x, d: %08x\n",addr,data);
750    switch (addr & 0x0ff) {
751
752    case MEC_MCR:
753	mec_mcr = data;
754	decode_mcr();
755        if (mec_mcr & 0x08000) mecparerror();
756	break;
757
758    case MEC_SFR:
759	if (mec_mcr & 0x2) {
760	    sys_reset();
761	    mec_ersr = 0x4000;
762    	    if (sis_verbose)
763	    	printf(" Software reset issued\n");
764	}
765	break;
766
767    case MEC_IOCR:
768	mec_iocr = data;
769        if (mec_iocr & 0xC0C0C0C0) mecparerror();
770	break;
771
772    case MEC_SSA1:		/* 0x20 */
773        if (data & 0xFE000000) mecparerror();
774	mec_ssa[0] = data & 0x7fffff;
775	mec_wpr[0] = (data >> 23) & 0x03;
776	mem_accprot = mec_wpr[0] || mec_wpr[1];
777	if (sis_verbose && mec_wpr[0])
778	    printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
779		   mec_ssa[0] << 2, mec_sea[0] << 2);
780	break;
781    case MEC_SEA1:		/* 0x24 */
782        if (data & 0xFF800000) mecparerror();
783	mec_sea[0] = data & 0x7fffff;
784	break;
785    case MEC_SSA2:		/* 0x28 */
786        if (data & 0xFE000000) mecparerror();
787	mec_ssa[1] = data & 0x7fffff;
788	mec_wpr[1] = (data >> 23) & 0x03;
789	mem_accprot = mec_wpr[0] || mec_wpr[1];
790	if (sis_verbose && mec_wpr[1])
791	    printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
792		   mec_ssa[1] << 2, mec_sea[1] << 2);
793	break;
794    case MEC_SEA2:		/* 0x2c */
795        if (data & 0xFF800000) mecparerror();
796	mec_sea[1] = data & 0x7fffff;
797	break;
798
799    case MEC_UARTA:
800    case MEC_UARTB:
801        if (data & 0xFFFFFF00) mecparerror();
802    case MEC_UART_CTRL:
803        if (data & 0xFF00FF00) mecparerror();
804	write_uart(addr, data);
805	break;
806
807    case MEC_GPT_RELOAD:
808	gpt_reload_set(data);
809	break;
810
811    case MEC_GPT_SCALER:
812        if (data & 0xFFFF0000) mecparerror();
813	gpt_scaler_set(data);
814	break;
815
816    case MEC_TIMER_CTRL:
817        if (data & 0xFFFFF0F0) mecparerror();
818	timer_ctrl(data);
819	break;
820
821    case MEC_RTC_RELOAD:
822	rtc_reload_set(data);
823	break;
824
825    case MEC_RTC_SCALER:
826        if (data & 0xFFFFFF00) mecparerror();
827	rtc_scaler_set(data);
828	break;
829
830    case MEC_SFSR:		/* 0xA0 */
831        if (data & 0xFFFF0880) mecparerror();
832	mec_sfsr = 0x78;
833	break;
834
835    case MEC_ISR:
836        if (data & 0xFFFFE000) mecparerror();
837	mec_isr = data;
838	break;
839
840    case MEC_IMR:		/* 0x4c */
841
842        if (data & 0xFFFF8001) mecparerror();
843	mec_imr = data & 0x7ffe;
844	chk_irq();
845	break;
846
847    case MEC_ICR:		/* 0x50 */
848
849        if (data & 0xFFFF0001) mecparerror();
850	mec_ipr &= ~data & 0x0fffe;
851	chk_irq();
852	break;
853
854    case MEC_IFR:		/* 0x54 */
855
856        if (mec_tcr & 0x080000) {
857            if (data & 0xFFFF0001) mecparerror();
858	    mec_ifr = data & 0xfffe;
859	    chk_irq();
860	}
861	break;
862    case SIM_LOAD:
863	fname[find++] = (char) data;
864	break;
865
866
867    case MEC_MEMCFG:		/* 0x10 */
868        if (data & 0xC0E08000) mecparerror();
869	mec_memcfg = data;
870	decode_memcfg();
871	if (mec_memcfg & 0xc0e08000)
872	    mecparerror();
873	break;
874
875    case MEC_WCR:		/* 0x18 */
876	mec_wcr = data;
877	decode_wcr();
878	break;
879
880    case MEC_ERSR:		/* 0xB0 */
881	if (mec_tcr & 0x100000)
882	  if (data & 0xFFFFEFC0) mecparerror();
883	    mec_ersr = data & 0x103f;
884	break;
885
886    case MEC_TCR:		/* 0xD0 */
887        if (data & 0xFFE1FFC0) mecparerror();
888	mec_tcr = data & 0x1e003f;
889	break;
890
891    case MEC_WDOG:		/* 0x60 */
892	wdog_scaler = (data >> 16) & 0x0ff;
893	wdog_counter = data & 0x0ffff;
894	wdog_rst_delay = data >> 24;
895	wdog_rston = 0;
896	if (wdog_status == stopped)
897	    wdog_start();
898	wdog_status = enabled;
899	break;
900
901    case MEC_TRAPD:		/* 0x64 */
902	if (wdog_status == init) {
903	    wdog_status = disabled;
904	    if (sis_verbose)
905		printf("Watchdog disabled\n");
906	}
907	break;
908
909    case MEC_PWDR:
910	if (mec_mcr & 1)
911	    wait_for_irq();
912	break;
913
914    default:
915	set_sfsr(MEC_ACC, addr, 0xb, 0);
916	return 1;
917	break;
918    }
919    return MOK;
920}
921
922
923/* MEC UARTS */
924
925static int      ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
926
927void
928init_stdio(void)
929{
930    if (dumbio)
931        return; /* do nothing */
932#ifdef HAVE_TERMIOS_H
933    if (!ifd1)
934	tcsetattr(0, TCSANOW, &ioc1);
935    if (!ifd2)
936	tcsetattr(0, TCSANOW, &ioc2);
937#endif
938}
939
940void
941restore_stdio(void)
942{
943    if (dumbio)
944        return; /* do nothing */
945#ifdef HAVE_TERMIOS_H
946    if (!ifd1)
947	tcsetattr(0, TCSANOW, &iocold1);
948    if (!ifd2)
949	tcsetattr(0, TCSANOW, &iocold2);
950#endif
951}
952
953#define DO_STDIO_READ( _fd_, _buf_, _len_ )          \
954             ( dumbio                                \
955               ? (0) /* no bytes read, no delay */   \
956               : read( _fd_, _buf_, _len_ ) )
957
958
959static void
960port_init(void)
961{
962
963    if (uben) {
964    f2in = stdin;
965    f1in = NULL;
966    f2out = stdout;
967    f1out = NULL;
968    } else {
969    f1in = stdin;
970    f2in = NULL;
971    f1out = stdout;
972    f2out = NULL;
973    }
974    if (uart_dev1[0] != 0) {
975	if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
976	    printf("Warning, couldn't open output device %s\n", uart_dev1);
977	} else {
978	    if (sis_verbose)
979		printf("serial port A on %s\n", uart_dev1);
980	    f1in = f1out = fdopen(fd1, "r+");
981	    setbuf(f1out, NULL);
982	    f1open = 1;
983	}
984    }
985    if (f1in) ifd1 = fileno(f1in);
986    if (ifd1 == 0) {
987	if (sis_verbose)
988	    printf("serial port A on stdin/stdout\n");
989        if (!dumbio) {
990#ifdef HAVE_TERMIOS_H
991            tcgetattr(ifd1, &ioc1);
992            iocold1 = ioc1;
993            ioc1.c_lflag &= ~(ICANON | ECHO);
994            ioc1.c_cc[VMIN] = 0;
995            ioc1.c_cc[VTIME] = 0;
996#endif
997        }
998	f1open = 1;
999    }
1000
1001    if (f1out) {
1002	ofd1 = fileno(f1out);
1003    	if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1004    }
1005
1006    if (uart_dev2[0] != 0) {
1007	if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1008	    printf("Warning, couldn't open output device %s\n", uart_dev2);
1009	} else {
1010	    if (sis_verbose)
1011		printf("serial port B on %s\n", uart_dev2);
1012	    f2in = f2out = fdopen(fd2, "r+");
1013	    setbuf(f2out, NULL);
1014	    f2open = 1;
1015	}
1016    }
1017    if (f2in)  ifd2 = fileno(f2in);
1018    if (ifd2 == 0) {
1019	if (sis_verbose)
1020	    printf("serial port B on stdin/stdout\n");
1021        if (!dumbio) {
1022#ifdef HAVE_TERMIOS_H
1023            tcgetattr(ifd2, &ioc2);
1024            iocold2 = ioc2;
1025            ioc2.c_lflag &= ~(ICANON | ECHO);
1026            ioc2.c_cc[VMIN] = 0;
1027            ioc2.c_cc[VTIME] = 0;
1028#endif
1029        }
1030	f2open = 1;
1031    }
1032
1033    if (f2out) {
1034	ofd2 = fileno(f2out);
1035        if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1036    }
1037
1038    wnuma = wnumb = 0;
1039
1040}
1041
1042static uint32_t
1043read_uart(uint32_t addr)
1044{
1045
1046    unsigned        tmp;
1047
1048    tmp = 0;
1049    switch (addr & 0xff) {
1050
1051    case 0xE0:			/* UART 1 */
1052#ifndef _WIN32
1053#ifdef FAST_UART
1054
1055	if (aind < anum) {
1056	    if ((aind + 1) < anum)
1057		mec_irq(4);
1058	    return (0x700 | (uint32_t) aq[aind++]);
1059	} else {
1060	    if (f1open) {
1061	        anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1062	    }
1063	    if (anum > 0) {
1064		aind = 0;
1065		if ((aind + 1) < anum)
1066		    mec_irq(4);
1067		return (0x700 | (uint32_t) aq[aind++]);
1068	    } else {
1069		return (0x600 | (uint32_t) aq[aind]);
1070	    }
1071
1072	}
1073#else
1074	tmp = uarta_data;
1075	uarta_data &= ~UART_DR;
1076	uart_stat_reg &= ~UARTA_DR;
1077	return tmp;
1078#endif
1079#else
1080	return 0;
1081#endif
1082	break;
1083
1084    case 0xE4:			/* UART 2 */
1085#ifndef _WIN32
1086#ifdef FAST_UART
1087	if (bind < bnum) {
1088	    if ((bind + 1) < bnum)
1089		mec_irq(5);
1090	    return (0x700 | (uint32_t) bq[bind++]);
1091	} else {
1092	    if (f2open) {
1093		bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1094	    }
1095	    if (bnum > 0) {
1096		bind = 0;
1097		if ((bind + 1) < bnum)
1098		    mec_irq(5);
1099		return (0x700 | (uint32_t) bq[bind++]);
1100	    } else {
1101		return (0x600 | (uint32_t) bq[bind]);
1102	    }
1103
1104	}
1105#else
1106	tmp = uartb_data;
1107	uartb_data &= ~UART_DR;
1108	uart_stat_reg &= ~UARTB_DR;
1109	return tmp;
1110#endif
1111#else
1112	return 0;
1113#endif
1114	break;
1115
1116    case 0xE8:			/* UART status register	 */
1117#ifndef _WIN32
1118#ifdef FAST_UART
1119
1120	Ucontrol = 0;
1121	if (aind < anum) {
1122	    Ucontrol |= 0x00000001;
1123	} else {
1124	    if (f1open) {
1125	        anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1126            }
1127	    if (anum > 0) {
1128		Ucontrol |= 0x00000001;
1129		aind = 0;
1130		mec_irq(4);
1131	    }
1132	}
1133	if (bind < bnum) {
1134	    Ucontrol |= 0x00010000;
1135	} else {
1136	    if (f2open) {
1137		bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1138	    }
1139	    if (bnum > 0) {
1140		Ucontrol |= 0x00010000;
1141		bind = 0;
1142		mec_irq(5);
1143	    }
1144	}
1145
1146	Ucontrol |= 0x00060006;
1147	return Ucontrol;
1148#else
1149	return uart_stat_reg;
1150#endif
1151#else
1152	return 0x00060006;
1153#endif
1154	break;
1155    default:
1156	if (sis_verbose)
1157	    printf("Read from unimplemented MEC register (%x)\n", addr);
1158
1159    }
1160    return 0;
1161}
1162
1163static void
1164write_uart(uint32_t addr, uint32_t data)
1165{
1166    unsigned char   c;
1167
1168    c = (unsigned char) data;
1169    switch (addr & 0xff) {
1170
1171    case 0xE0:			/* UART A */
1172#ifdef FAST_UART
1173	if (f1open) {
1174	    if (wnuma < UARTBUF)
1175	        wbufa[wnuma++] = c;
1176	    else {
1177	        while (wnuma)
1178		    wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1179	        wbufa[wnuma++] = c;
1180	    }
1181	}
1182	mec_irq(4);
1183#else
1184	if (uart_stat_reg & UARTA_SRE) {
1185	    uarta_sreg = c;
1186	    uart_stat_reg &= ~UARTA_SRE;
1187	    event(uarta_tx, 0, UART_TX_TIME);
1188	} else {
1189	    uarta_hreg = c;
1190	    uart_stat_reg &= ~UARTA_HRE;
1191	}
1192#endif
1193	break;
1194
1195    case 0xE4:			/* UART B */
1196#ifdef FAST_UART
1197	if (f2open) {
1198	    if (wnumb < UARTBUF)
1199		wbufb[wnumb++] = c;
1200	    else {
1201		while (wnumb)
1202		    wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1203		wbufb[wnumb++] = c;
1204	    }
1205	}
1206	mec_irq(5);
1207#else
1208	if (uart_stat_reg & UARTB_SRE) {
1209	    uartb_sreg = c;
1210	    uart_stat_reg &= ~UARTB_SRE;
1211	    event(uartb_tx, 0, UART_TX_TIME);
1212	} else {
1213	    uartb_hreg = c;
1214	    uart_stat_reg &= ~UARTB_HRE;
1215	}
1216#endif
1217	break;
1218    case 0xE8:			/* UART status register */
1219#ifndef FAST_UART
1220	if (data & UARTA_CLR) {
1221	    uart_stat_reg &= 0xFFFF0000;
1222	    uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1223	}
1224	if (data & UARTB_CLR) {
1225	    uart_stat_reg &= 0x0000FFFF;
1226	    uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1227	}
1228#endif
1229	break;
1230    default:
1231	if (sis_verbose)
1232	    printf("Write to unimplemented MEC register (%x)\n", addr);
1233
1234    }
1235}
1236
1237static void
1238flush_uart(void)
1239{
1240    while (wnuma && f1open)
1241	wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1242    while (wnumb && f2open)
1243	wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1244}
1245
1246ATTRIBUTE_UNUSED
1247static void
1248uarta_tx(int32_t arg ATTRIBUTE_UNUSED)
1249{
1250
1251    while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1252    if (uart_stat_reg & UARTA_HRE) {
1253	uart_stat_reg |= UARTA_SRE;
1254    } else {
1255	uarta_sreg = uarta_hreg;
1256	uart_stat_reg |= UARTA_HRE;
1257	event(uarta_tx, 0, UART_TX_TIME);
1258    }
1259    mec_irq(4);
1260}
1261
1262ATTRIBUTE_UNUSED
1263static void
1264uartb_tx(int32_t arg ATTRIBUTE_UNUSED)
1265{
1266    while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1267    if (uart_stat_reg & UARTB_HRE) {
1268	uart_stat_reg |= UARTB_SRE;
1269    } else {
1270	uartb_sreg = uartb_hreg;
1271	uart_stat_reg |= UARTB_HRE;
1272	event(uartb_tx, 0, UART_TX_TIME);
1273    }
1274    mec_irq(5);
1275}
1276
1277ATTRIBUTE_UNUSED
1278static void
1279uart_rx(int32_t arg ATTRIBUTE_UNUSED)
1280{
1281    int32_t           rsize;
1282    char            rxd;
1283
1284
1285    rsize = 0;
1286    if (f1open)
1287        rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1288    if (rsize > 0) {
1289	uarta_data = UART_DR | rxd;
1290	if (uart_stat_reg & UARTA_HRE)
1291	    uarta_data |= UART_THE;
1292	if (uart_stat_reg & UARTA_SRE)
1293	    uarta_data |= UART_TSE;
1294	if (uart_stat_reg & UARTA_DR) {
1295	    uart_stat_reg |= UARTA_OR;
1296	    mec_irq(7);		/* UART error interrupt */
1297	}
1298	uart_stat_reg |= UARTA_DR;
1299	mec_irq(4);
1300    }
1301    rsize = 0;
1302    if (f2open)
1303        rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1304    if (rsize) {
1305	uartb_data = UART_DR | rxd;
1306	if (uart_stat_reg & UARTB_HRE)
1307	    uartb_data |= UART_THE;
1308	if (uart_stat_reg & UARTB_SRE)
1309	    uartb_data |= UART_TSE;
1310	if (uart_stat_reg & UARTB_DR) {
1311	    uart_stat_reg |= UARTB_OR;
1312	    mec_irq(7);		/* UART error interrupt */
1313	}
1314	uart_stat_reg |= UARTB_DR;
1315	mec_irq(5);
1316    }
1317    event(uart_rx, 0, UART_RX_TIME);
1318}
1319
1320static void
1321uart_intr(int32_t arg ATTRIBUTE_UNUSED)
1322{
1323    read_uart(0xE8);		/* Check for UART interrupts every 1000 clk */
1324    flush_uart();		/* Flush UART ports      */
1325    event(uart_intr, 0, UART_FLUSH_TIME);
1326}
1327
1328
1329static void
1330uart_irq_start(void)
1331{
1332#ifdef FAST_UART
1333    event(uart_intr, 0, UART_FLUSH_TIME);
1334#else
1335#ifndef _WIN32
1336    event(uart_rx, 0, UART_RX_TIME);
1337#endif
1338#endif
1339}
1340
1341/* Watch-dog */
1342
1343static void
1344wdog_intr(int32_t arg ATTRIBUTE_UNUSED)
1345{
1346    if (wdog_status == disabled) {
1347	wdog_status = stopped;
1348    } else {
1349
1350	if (wdog_counter) {
1351	    wdog_counter--;
1352	    event(wdog_intr, 0, wdog_scaler + 1);
1353	} else {
1354	    if (wdog_rston) {
1355		printf("Watchdog reset!\n");
1356		sys_reset();
1357		mec_ersr = 0xC000;
1358	    } else {
1359		mec_irq(15);
1360		wdog_rston = 1;
1361		wdog_counter = wdog_rst_delay;
1362		event(wdog_intr, 0, wdog_scaler + 1);
1363	    }
1364	}
1365    }
1366}
1367
1368static void
1369wdog_start(void)
1370{
1371    event(wdog_intr, 0, wdog_scaler + 1);
1372    if (sis_verbose)
1373	printf("Watchdog started, scaler = %d, counter = %d\n",
1374	       wdog_scaler, wdog_counter);
1375}
1376
1377
1378/* MEC timers */
1379
1380
1381static void
1382rtc_intr(int32_t arg ATTRIBUTE_UNUSED)
1383{
1384    if (rtc_counter == 0) {
1385
1386	mec_irq(13);
1387	if (rtc_cr)
1388	    rtc_counter = rtc_reload;
1389	else
1390	    rtc_se = 0;
1391    } else
1392	rtc_counter -= 1;
1393    if (rtc_se) {
1394	event(rtc_intr, 0, rtc_scaler + 1);
1395	rtc_scaler_start = now();
1396	rtc_enabled = 1;
1397    } else {
1398	if (sis_verbose)
1399	    printf("RTC stopped\n\r");
1400	rtc_enabled = 0;
1401    }
1402}
1403
1404static void
1405rtc_start(void)
1406{
1407    if (sis_verbose)
1408	printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1409    event(rtc_intr, 0, rtc_scaler + 1);
1410    rtc_scaler_start = now();
1411    rtc_enabled = 1;
1412}
1413
1414static uint32_t
1415rtc_counter_read(void)
1416{
1417    return rtc_counter;
1418}
1419
1420static void
1421rtc_scaler_set(uint32_t val)
1422{
1423    rtc_scaler = val & 0x0ff;	/* eight-bit scaler only */
1424}
1425
1426static void
1427rtc_reload_set(uint32_t val)
1428{
1429    rtc_reload = val;
1430}
1431
1432static void
1433gpt_intr(int32_t arg ATTRIBUTE_UNUSED)
1434{
1435    if (gpt_counter == 0) {
1436	mec_irq(12);
1437	if (gpt_cr)
1438	    gpt_counter = gpt_reload;
1439	else
1440	    gpt_se = 0;
1441    } else
1442	gpt_counter -= 1;
1443    if (gpt_se) {
1444	event(gpt_intr, 0, gpt_scaler + 1);
1445	gpt_scaler_start = now();
1446	gpt_enabled = 1;
1447    } else {
1448	if (sis_verbose)
1449	    printf("GPT stopped\n\r");
1450	gpt_enabled = 0;
1451    }
1452}
1453
1454static void
1455gpt_start(void)
1456{
1457    if (sis_verbose)
1458	printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1459    event(gpt_intr, 0, gpt_scaler + 1);
1460    gpt_scaler_start = now();
1461    gpt_enabled = 1;
1462}
1463
1464static uint32_t
1465gpt_counter_read(void)
1466{
1467    return gpt_counter;
1468}
1469
1470static void
1471gpt_scaler_set(uint32_t val)
1472{
1473    gpt_scaler = val & 0x0ffff;	/* 16-bit scaler */
1474}
1475
1476static void
1477gpt_reload_set(uint32_t val)
1478{
1479    gpt_reload = val;
1480}
1481
1482static void
1483timer_ctrl(uint32_t val)
1484{
1485
1486    rtc_cr = ((val & TCR_TCRCR) != 0);
1487    if (val & TCR_TCRCL) {
1488	rtc_counter = rtc_reload;
1489    }
1490    if (val & TCR_TCRSL) {
1491    }
1492    rtc_se = ((val & TCR_TCRSE) != 0);
1493    if (rtc_se && (rtc_enabled == 0))
1494	rtc_start();
1495
1496    gpt_cr = (val & TCR_GACR);
1497    if (val & TCR_GACL) {
1498	gpt_counter = gpt_reload;
1499    }
1500    if (val & TCR_GACL) {
1501    }
1502    gpt_se = (val & TCR_GASE) >> 2;
1503    if (gpt_se && (gpt_enabled == 0))
1504	gpt_start();
1505}
1506
1507/* Store data in host byte order.  MEM points to the beginning of the
1508   emulated memory; WADDR contains the index the emulated memory,
1509   DATA points to words in host byte order to be stored.  SZ contains log(2)
1510   of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1511   2 (one word), or 3 (two words); WS should return the number of
1512   wait-states.  */
1513
1514static void
1515store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
1516	     int32_t *ws)
1517{
1518    switch (sz) {
1519	case 0:
1520	    waddr ^= EBT;
1521	    mem[waddr] = *data & 0x0ff;
1522	    *ws = mem_ramw_ws + 3;
1523	    break;
1524	case 1:
1525#ifdef HOST_LITTLE_ENDIAN
1526	    waddr ^= 2;
1527#endif
1528	    memcpy (&mem[waddr], data, 2);
1529	    *ws = mem_ramw_ws + 3;
1530	    break;
1531	case 2:
1532	    memcpy (&mem[waddr], data, 4);
1533	    *ws = mem_ramw_ws;
1534	    break;
1535	case 3:
1536	    memcpy (&mem[waddr], data, 8);
1537	    *ws = 2 * mem_ramw_ws + STD_WS;
1538	    break;
1539    }
1540}
1541
1542
1543/* Memory emulation */
1544
1545int
1546memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
1547{
1548    uint32_t          asi;
1549    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1550	memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1551	*ws = mem_ramr_ws;
1552	return 0;
1553    } else if (addr < mem_romsz) {
1554	memcpy (data, &romb[addr & ~3], 4);
1555	*ws = mem_romr_ws;
1556	return 0;
1557    }
1558
1559    if (sis_verbose)
1560	printf ("Memory exception at %x (illegal address)\n", addr);
1561    if (sregs.psr & 0x080)
1562        asi = 9;
1563    else
1564        asi = 8;
1565    set_sfsr (UIMP_ACC, addr, asi, 1);
1566    *ws = MEM_EX_WS;
1567    return 1;
1568}
1569
1570int
1571memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
1572{
1573    int32_t           mexc;
1574
1575#ifdef ERRINJ
1576    if (errmec) {
1577	if (sis_verbose)
1578	    printf("Inserted MEC error %d\n",errmec);
1579	set_sfsr(errmec, addr, asi, 1);
1580	if (errmec == 5) mecparerror();
1581	if (errmec == 6) iucomperr();
1582	errmec = 0;
1583	return 1;
1584    }
1585#endif
1586
1587    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1588	memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1589	*ws = mem_ramr_ws;
1590	return 0;
1591    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1592	mexc = mec_read(addr, asi, data);
1593	if (mexc) {
1594	    set_sfsr(MEC_ACC, addr, asi, 1);
1595	    *ws = MEM_EX_WS;
1596	} else {
1597	    *ws = 0;
1598	}
1599	return mexc;
1600
1601#ifdef ERA
1602
1603    } else if (era) {
1604    	if ((addr < 0x100000) ||
1605	    ((addr>= 0x80000000) && (addr < 0x80100000))) {
1606	    memcpy (data, &romb[addr & ROM_MASK & ~3], 4);
1607	    *ws = 4;
1608	    return 0;
1609	} else if ((addr >= 0x10000000) &&
1610		   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1611		   (mec_iocr & 0x10))  {
1612	    memcpy (data, &erareg, 4);
1613	    return 0;
1614	}
1615
1616    } else  if (addr < mem_romsz) {
1617	memcpy (data, &romb[addr & ~3], 4);
1618	*ws = mem_romr_ws;
1619	return 0;
1620#else
1621    } else if (addr < mem_romsz) {
1622	memcpy (data, &romb[addr & ~3], 4);
1623	*ws = mem_romr_ws;
1624	return 0;
1625#endif
1626
1627    }
1628
1629    if (sis_verbose)
1630	printf ("Memory exception at %x (illegal address)\n", addr);
1631    set_sfsr(UIMP_ACC, addr, asi, 1);
1632    *ws = MEM_EX_WS;
1633    return 1;
1634}
1635
1636int
1637memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
1638{
1639    uint32_t          byte_addr;
1640    uint32_t          byte_mask;
1641    uint32_t          waddr;
1642    uint32_t         *ram;
1643    int32_t           mexc;
1644    int             i;
1645    int             wphit[2];
1646
1647#ifdef ERRINJ
1648    if (errmec) {
1649	if (sis_verbose)
1650	    printf("Inserted MEC error %d\n",errmec);
1651	set_sfsr(errmec, addr, asi, 0);
1652	if (errmec == 5) mecparerror();
1653	if (errmec == 6) iucomperr();
1654	errmec = 0;
1655	return 1;
1656    }
1657#endif
1658
1659    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1660	if (mem_accprot) {
1661
1662	    waddr = (addr & 0x7fffff) >> 2;
1663	    for (i = 0; i < 2; i++)
1664		wphit[i] =
1665		    (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1666		     ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1667		    ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1668
1669	    if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1670		((!mem_blockprot) &&
1671		 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1672		 )) {
1673		if (sis_verbose)
1674		    printf("Memory access protection error at 0x%08x\n", addr);
1675		set_sfsr(PROT_EXC, addr, asi, 0);
1676		*ws = MEM_EX_WS;
1677		return 1;
1678	    }
1679	}
1680	waddr = addr & mem_rammask;
1681	store_bytes (ramb, waddr, data, sz, ws);
1682	return 0;
1683    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1684	if ((sz != 2) || (asi != 0xb)) {
1685	    set_sfsr(MEC_ACC, addr, asi, 0);
1686	    *ws = MEM_EX_WS;
1687	    return 1;
1688	}
1689	mexc = mec_write(addr, *data);
1690	if (mexc) {
1691	    set_sfsr(MEC_ACC, addr, asi, 0);
1692	    *ws = MEM_EX_WS;
1693	} else {
1694	    *ws = 0;
1695	}
1696	return mexc;
1697
1698#ifdef ERA
1699
1700    } else if (era) {
1701    	if ((erareg & 2) &&
1702	((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1703	    addr &= ROM_MASK;
1704	    *ws = sz == 3 ? 8 : 4;
1705	    store_bytes (romb, addr, data, sz, ws);
1706            return 0;
1707	} else if ((addr >= 0x10000000) &&
1708		   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1709		   (mec_iocr & 0x10))  {
1710	    erareg = *data & 0x0e;
1711	    return 0;
1712	}
1713
1714    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1715               (((mec_memcfg & 0x20000) && (sz > 1)) ||
1716		(!(mec_memcfg & 0x20000) && (sz == 0)))) {
1717
1718	*ws = mem_romw_ws + 1;
1719	if (sz == 3)
1720	    *ws += mem_romw_ws + STD_WS;
1721	store_bytes (romb, addr, data, sz, ws);
1722        return 0;
1723
1724#else
1725    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1726               (((mec_memcfg & 0x20000) && (sz > 1)) ||
1727		(!(mec_memcfg & 0x20000) && (sz == 0)))) {
1728
1729	*ws = mem_romw_ws + 1;
1730	if (sz == 3)
1731            *ws += mem_romw_ws + STD_WS;
1732	store_bytes (romb, addr, data, sz, ws);
1733        return 0;
1734
1735#endif
1736
1737    }
1738
1739    *ws = MEM_EX_WS;
1740    set_sfsr(UIMP_ACC, addr, asi, 0);
1741    return 1;
1742}
1743
1744static void  *
1745get_mem_ptr(uint32_t addr, uint32_t size)
1746{
1747    if ((addr + size) < ROM_SZ) {
1748	return &romb[addr];
1749    } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1750	return &ramb[addr & mem_rammask];
1751    }
1752
1753#ifdef ERA
1754      else if ((era) && ((addr <0x100000) ||
1755	((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1756	return &romb[addr & ROM_MASK];
1757    }
1758#endif
1759
1760    return (void *) -1;
1761}
1762
1763int
1764sis_memory_write(uint32_t addr, const void *data, uint32_t length)
1765{
1766    void           *mem;
1767
1768    if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1769	return 0;
1770
1771    memcpy(mem, data, length);
1772    return length;
1773}
1774
1775int
1776sis_memory_read(uint32_t addr, void *data, uint32_t length)
1777{
1778    char           *mem;
1779
1780    if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1781	return 0;
1782
1783    memcpy(data, mem, length);
1784    return length;
1785}
1786
1787extern struct pstate sregs;
1788
1789void
1790boot_init (void)
1791{
1792    mec_write(MEC_WCR, 0);	/* zero waitstates */
1793    mec_write(MEC_TRAPD, 0);	/* turn off watch-dog */
1794    mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1795    mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1796    sregs.wim = 2;
1797    sregs.psr = 0x110010e0;
1798    sregs.r[30] = RAM_END;
1799    sregs.r[14] = sregs.r[30] - 96 * 4;
1800    mec_mcr |= 1;		/* power-down enabled */
1801}
1802