1/* Simulator for Analog Devices Blackfin processors. 2 3 Copyright (C) 2005-2023 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. and Mike Frysinger. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21/* This must come before any other includes. */ 22#include "defs.h" 23 24#include <stdlib.h> 25 26#include "sim-main.h" 27#include "gdb/sim-bfin.h" 28#include "bfd.h" 29 30#include "sim-hw.h" 31#include "devices.h" 32#include "dv-bfin_cec.h" 33#include "dv-bfin_dmac.h" 34 35static const SIM_MACH bfin_mach; 36 37struct bfin_memory_layout { 38 address_word addr, len; 39 unsigned mask; /* see mapmask in sim_core_attach() */ 40}; 41struct bfin_dev_layout { 42 address_word base, len; 43 unsigned int dmac; 44 const char *dev; 45}; 46struct bfin_dmac_layout { 47 address_word base; 48 unsigned int dma_count; 49}; 50struct bfin_port_layout { 51 /* Which device this routes to (name/port). */ 52 const char *dst, *dst_port; 53 /* Which device this routes from (name/port). */ 54 const char *src, *src_port; 55}; 56struct bfin_model_data { 57 bu32 chipid; 58 int model_num; 59 const struct bfin_memory_layout *mem; 60 size_t mem_count; 61 const struct bfin_dev_layout *dev; 62 size_t dev_count; 63 const struct bfin_dmac_layout *dmac; 64 size_t dmac_count; 65 const struct bfin_port_layout *port; 66 size_t port_count; 67}; 68 69#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, } 70#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, } 71#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0) 72#define PORT(_dst, _dst_port, _src, _src_port) \ 73 { \ 74 .dst = _dst, \ 75 .dst_port = _dst_port, \ 76 .src = _src, \ 77 .src_port = _src_port, \ 78 } 79#define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op) 80 81/* [1] Common sim code can't model exec-only memory. 82 http://sourceware.org/ml/gdb/2010-02/msg00047.html */ 83 84#define bf000_chipid 0 85static const struct bfin_memory_layout bf000_mem[] = {}; 86static const struct bfin_dev_layout bf000_dev[] = {}; 87static const struct bfin_dmac_layout bf000_dmac[] = {}; 88static const struct bfin_port_layout bf000_port[] = {}; 89 90#define bf50x_chipid 0x2800 91#define bf504_chipid bf50x_chipid 92#define bf506_chipid bf50x_chipid 93static const struct bfin_memory_layout bf50x_mem[] = 94{ 95 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 96 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 97 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ 98 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */ 99 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */ 100 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 101 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 102 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ 103 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */ 104}; 105#define bf504_mem bf50x_mem 106#define bf506_mem bf50x_mem 107static const struct bfin_dev_layout bf50x_dev[] = 108{ 109 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 110 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), 111 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 112 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 113 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 114 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 115 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 116 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 117 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 118 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 119 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 120 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 121 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 122 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 123 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 124 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 125 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 126 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), 127 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 128}; 129#define bf504_dev bf50x_dev 130#define bf506_dev bf50x_dev 131static const struct bfin_dmac_layout bf50x_dmac[] = 132{ 133 { BFIN_MMR_DMAC0_BASE, 12, }, 134}; 135#define bf504_dmac bf50x_dmac 136#define bf506_dmac bf50x_dmac 137static const struct bfin_port_layout bf50x_port[] = 138{ 139 SIC (0, 0, "bfin_pll", "pll"), 140/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 141 SIC (0, 2, "bfin_ppi@0", "stat"), 142 SIC (0, 3, "bfin_sport@0", "stat"), 143 SIC (0, 4, "bfin_sport@1", "stat"), 144 SIC (0, 5, "bfin_uart2@0", "stat"), 145 SIC (0, 6, "bfin_uart2@1", "stat"), 146 SIC (0, 7, "bfin_spi@0", "stat"), 147 SIC (0, 8, "bfin_spi@1", "stat"), 148 SIC (0, 9, "bfin_can@0", "stat"), 149 SIC (0, 10, "bfin_rsi@0", "int0"), 150/*SIC (0, 11, reserved),*/ 151 SIC (0, 12, "bfin_counter@0", "stat"), 152 SIC (0, 13, "bfin_counter@1", "stat"), 153 SIC (0, 14, "bfin_dma@0", "di"), 154 SIC (0, 15, "bfin_dma@1", "di"), 155 SIC (0, 16, "bfin_dma@2", "di"), 156 SIC (0, 17, "bfin_dma@3", "di"), 157 SIC (0, 18, "bfin_dma@4", "di"), 158 SIC (0, 19, "bfin_dma@5", "di"), 159 SIC (0, 20, "bfin_dma@6", "di"), 160 SIC (0, 21, "bfin_dma@7", "di"), 161 SIC (0, 22, "bfin_dma@8", "di"), 162 SIC (0, 23, "bfin_dma@9", "di"), 163 SIC (0, 24, "bfin_dma@10", "di"), 164 SIC (0, 25, "bfin_dma@11", "di"), 165 SIC (0, 26, "bfin_can@0", "rx"), 166 SIC (0, 27, "bfin_can@0", "tx"), 167 SIC (0, 28, "bfin_twi@0", "stat"), 168 SIC (0, 29, "bfin_gpio@5", "mask_a"), 169 SIC (0, 30, "bfin_gpio@5", "mask_b"), 170/*SIC (0, 31, reserved),*/ 171 SIC (1, 0, "bfin_gptimer@0", "stat"), 172 SIC (1, 1, "bfin_gptimer@1", "stat"), 173 SIC (1, 2, "bfin_gptimer@2", "stat"), 174 SIC (1, 3, "bfin_gptimer@3", "stat"), 175 SIC (1, 4, "bfin_gptimer@4", "stat"), 176 SIC (1, 5, "bfin_gptimer@5", "stat"), 177 SIC (1, 6, "bfin_gptimer@6", "stat"), 178 SIC (1, 7, "bfin_gptimer@7", "stat"), 179 SIC (1, 8, "bfin_gpio@6", "mask_a"), 180 SIC (1, 9, "bfin_gpio@6", "mask_b"), 181 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ 182 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ 183 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ 184 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ 185 SIC (1, 12, "bfin_wdog@0", "gpi"), 186 SIC (1, 13, "bfin_gpio@7", "mask_a"), 187 SIC (1, 14, "bfin_gpio@7", "mask_b"), 188 SIC (1, 15, "bfin_acm@0", "stat"), 189 SIC (1, 16, "bfin_acm@1", "int"), 190/*SIC (1, 17, reserved),*/ 191/*SIC (1, 18, reserved),*/ 192 SIC (1, 19, "bfin_pwm@0", "trip"), 193 SIC (1, 20, "bfin_pwm@0", "sync"), 194 SIC (1, 21, "bfin_pwm@1", "trip"), 195 SIC (1, 22, "bfin_pwm@1", "sync"), 196 SIC (1, 23, "bfin_rsi@0", "int1"), 197}; 198#define bf504_port bf50x_port 199#define bf506_port bf50x_port 200 201#define bf51x_chipid 0x27e8 202#define bf512_chipid bf51x_chipid 203#define bf514_chipid bf51x_chipid 204#define bf516_chipid bf51x_chipid 205#define bf518_chipid bf51x_chipid 206static const struct bfin_memory_layout bf51x_mem[] = 207{ 208 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ 209 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 210 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 211 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ 212 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */ 213 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */ 214 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 215 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 216 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 217 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 218 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 219 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 220}; 221#define bf512_mem bf51x_mem 222#define bf514_mem bf51x_mem 223#define bf516_mem bf51x_mem 224#define bf518_mem bf51x_mem 225static const struct bfin_dev_layout bf512_dev[] = 226{ 227 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 228 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 229 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 230 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 231 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 232 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 233 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 234 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 235 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 236 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 237 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 238 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 239 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 240 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 241 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 242 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 243 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 244 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 245 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 246 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 247 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 248 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), 249}; 250#define bf514_dev bf512_dev 251static const struct bfin_dev_layout bf516_dev[] = 252{ 253 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 254 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 255 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 256 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 257 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 258 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 259 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 260 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 261 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 262 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 263 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 264 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 265 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 266 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 267 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 268 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 269 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 270 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 271 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 272 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 273 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), 274 DEVICE (0, 0x20, "bfin_emac/eth_phy"), 275 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 276 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), 277}; 278#define bf518_dev bf516_dev 279#define bf512_dmac bf50x_dmac 280#define bf514_dmac bf50x_dmac 281#define bf516_dmac bf50x_dmac 282#define bf518_dmac bf50x_dmac 283static const struct bfin_port_layout bf51x_port[] = 284{ 285 SIC (0, 0, "bfin_pll", "pll"), 286/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 287 SIC (0, 2, "bfin_dmar@0", "block"), 288 SIC (0, 3, "bfin_dmar@1", "block"), 289 SIC (0, 4, "bfin_dmar@0", "overflow"), 290 SIC (0, 5, "bfin_dmar@1", "overflow"), 291 SIC (0, 6, "bfin_ppi@0", "stat"), 292 SIC (0, 7, "bfin_emac", "stat"), 293 SIC (0, 8, "bfin_sport@0", "stat"), 294 SIC (0, 9, "bfin_sport@1", "stat"), 295 SIC (0, 10, "bfin_ptp", "stat"), 296/*SIC (0, 11, reserved),*/ 297 SIC (0, 12, "bfin_uart@0", "stat"), 298 SIC (0, 13, "bfin_uart@1", "stat"), 299 SIC (0, 14, "bfin_rtc", "rtc"), 300 SIC (0, 15, "bfin_dma@0", "di"), 301 SIC (0, 16, "bfin_dma@3", "di"), 302 SIC (0, 17, "bfin_dma@4", "di"), 303 SIC (0, 18, "bfin_dma@5", "di"), 304 SIC (0, 19, "bfin_dma@6", "di"), 305 SIC (0, 20, "bfin_twi@0", "stat"), 306 SIC (0, 21, "bfin_dma@7", "di"), 307 SIC (0, 22, "bfin_dma@8", "di"), 308 SIC (0, 23, "bfin_dma@9", "di"), 309 SIC (0, 24, "bfin_dma@10", "di"), 310 SIC (0, 25, "bfin_dma@11", "di"), 311 SIC (0, 26, "bfin_otp", "stat"), 312 SIC (0, 27, "bfin_counter@0", "stat"), 313 SIC (0, 28, "bfin_dma@1", "di"), 314 SIC (0, 29, "bfin_gpio@7", "mask_a"), 315 SIC (0, 30, "bfin_dma@2", "di"), 316 SIC (0, 31, "bfin_gpio@7", "mask_b"), 317 SIC (1, 0, "bfin_gptimer@0", "stat"), 318 SIC (1, 1, "bfin_gptimer@1", "stat"), 319 SIC (1, 2, "bfin_gptimer@2", "stat"), 320 SIC (1, 3, "bfin_gptimer@3", "stat"), 321 SIC (1, 4, "bfin_gptimer@4", "stat"), 322 SIC (1, 5, "bfin_gptimer@5", "stat"), 323 SIC (1, 6, "bfin_gptimer@6", "stat"), 324 SIC (1, 7, "bfin_gptimer@7", "stat"), 325 SIC (1, 8, "bfin_gpio@6", "mask_a"), 326 SIC (1, 9, "bfin_gpio@6", "mask_b"), 327 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ 328 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ 329 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ 330 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ 331 SIC (1, 12, "bfin_wdog@0", "gpi"), 332 SIC (1, 13, "bfin_gpio@5", "mask_a"), 333 SIC (1, 14, "bfin_gpio@5", "mask_b"), 334 SIC (1, 15, "bfin_spi@0", "stat"), 335 SIC (1, 16, "bfin_spi@1", "stat"), 336/*SIC (1, 17, reserved),*/ 337/*SIC (1, 18, reserved),*/ 338 SIC (1, 19, "bfin_rsi@0", "int0"), 339 SIC (1, 20, "bfin_rsi@0", "int1"), 340 SIC (1, 21, "bfin_pwm@0", "trip"), 341 SIC (1, 22, "bfin_pwm@0", "sync"), 342 SIC (1, 23, "bfin_ptp", "stat"), 343}; 344#define bf512_port bf51x_port 345#define bf514_port bf51x_port 346#define bf516_port bf51x_port 347#define bf518_port bf51x_port 348 349#define bf522_chipid 0x27e4 350#define bf523_chipid 0x27e0 351#define bf524_chipid bf522_chipid 352#define bf525_chipid bf523_chipid 353#define bf526_chipid bf522_chipid 354#define bf527_chipid bf523_chipid 355static const struct bfin_memory_layout bf52x_mem[] = 356{ 357 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ 358 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 359 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 360 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */ 361 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */ 362 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 363 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 364 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 365 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 366 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 367 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 368 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 369}; 370#define bf522_mem bf52x_mem 371#define bf523_mem bf52x_mem 372#define bf524_mem bf52x_mem 373#define bf525_mem bf52x_mem 374#define bf526_mem bf52x_mem 375#define bf527_mem bf52x_mem 376static const struct bfin_dev_layout bf522_dev[] = 377{ 378 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 379 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 380 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 381 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 382 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 383 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 384 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 385 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 386 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 387 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 388 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 389 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 390 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 391 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 392 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 393 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 394 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 395 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 396 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 397 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 398 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), 399 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), 400}; 401#define bf523_dev bf522_dev 402#define bf524_dev bf522_dev 403#define bf525_dev bf522_dev 404static const struct bfin_dev_layout bf526_dev[] = 405{ 406 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 407 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 408 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 409 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 410 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 411 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 412 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 413 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 414 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 415 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 416 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 417 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 418 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 419 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 420 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 421 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 422 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 423 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 424 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 425 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 426 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), 427 DEVICE (0, 0x20, "bfin_emac/eth_phy"), 428 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"), 429 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"), 430}; 431#define bf527_dev bf526_dev 432#define bf522_dmac bf50x_dmac 433#define bf523_dmac bf50x_dmac 434#define bf524_dmac bf50x_dmac 435#define bf525_dmac bf50x_dmac 436#define bf526_dmac bf50x_dmac 437#define bf527_dmac bf50x_dmac 438static const struct bfin_port_layout bf52x_port[] = 439{ 440 SIC (0, 0, "bfin_pll", "pll"), 441/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 442 SIC (0, 2, "bfin_dmar@0", "block"), 443 SIC (0, 3, "bfin_dmar@1", "block"), 444 SIC (0, 4, "bfin_dmar@0", "overflow"), 445 SIC (0, 5, "bfin_dmar@1", "overflow"), 446 SIC (0, 6, "bfin_ppi@0", "stat"), 447 SIC (0, 7, "bfin_emac", "stat"), 448 SIC (0, 8, "bfin_sport@0", "stat"), 449 SIC (0, 9, "bfin_sport@1", "stat"), 450/*SIC (0, 10, reserved),*/ 451/*SIC (0, 11, reserved),*/ 452 SIC (0, 12, "bfin_uart@0", "stat"), 453 SIC (0, 13, "bfin_uart@1", "stat"), 454 SIC (0, 14, "bfin_rtc", "rtc"), 455 SIC (0, 15, "bfin_dma@0", "di"), 456 SIC (0, 16, "bfin_dma@3", "di"), 457 SIC (0, 17, "bfin_dma@4", "di"), 458 SIC (0, 18, "bfin_dma@5", "di"), 459 SIC (0, 19, "bfin_dma@6", "di"), 460 SIC (0, 20, "bfin_twi@0", "stat"), 461 SIC (0, 21, "bfin_dma@7", "di"), 462 SIC (0, 22, "bfin_dma@8", "di"), 463 SIC (0, 23, "bfin_dma@9", "di"), 464 SIC (0, 24, "bfin_dma@10", "di"), 465 SIC (0, 25, "bfin_dma@11", "di"), 466 SIC (0, 26, "bfin_otp", "stat"), 467 SIC (0, 27, "bfin_counter@0", "stat"), 468 SIC (0, 28, "bfin_dma@1", "di"), 469 SIC (0, 29, "bfin_gpio@7", "mask_a"), 470 SIC (0, 30, "bfin_dma@2", "di"), 471 SIC (0, 31, "bfin_gpio@7", "mask_b"), 472 SIC (1, 0, "bfin_gptimer@0", "stat"), 473 SIC (1, 1, "bfin_gptimer@1", "stat"), 474 SIC (1, 2, "bfin_gptimer@2", "stat"), 475 SIC (1, 3, "bfin_gptimer@3", "stat"), 476 SIC (1, 4, "bfin_gptimer@4", "stat"), 477 SIC (1, 5, "bfin_gptimer@5", "stat"), 478 SIC (1, 6, "bfin_gptimer@6", "stat"), 479 SIC (1, 7, "bfin_gptimer@7", "stat"), 480 SIC (1, 8, "bfin_gpio@6", "mask_a"), 481 SIC (1, 9, "bfin_gpio@6", "mask_b"), 482 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */ 483 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */ 484 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */ 485 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */ 486 SIC (1, 12, "bfin_wdog@0", "gpi"), 487 SIC (1, 13, "bfin_gpio@5", "mask_a"), 488 SIC (1, 14, "bfin_gpio@5", "mask_b"), 489 SIC (1, 15, "bfin_spi@0", "stat"), 490 SIC (1, 16, "bfin_nfc", "stat"), 491 SIC (1, 17, "bfin_hostdp", "stat"), 492 SIC (1, 18, "bfin_hostdp", "done"), 493 SIC (1, 20, "bfin_usb", "int0"), 494 SIC (1, 21, "bfin_usb", "int1"), 495 SIC (1, 22, "bfin_usb", "int2"), 496}; 497#define bf522_port bf51x_port 498#define bf523_port bf51x_port 499#define bf524_port bf51x_port 500#define bf525_port bf51x_port 501#define bf526_port bf51x_port 502#define bf527_port bf51x_port 503 504#define bf531_chipid 0x27a5 505#define bf532_chipid bf531_chipid 506#define bf533_chipid bf531_chipid 507static const struct bfin_memory_layout bf531_mem[] = 508{ 509 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ 510 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 511 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 512 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 513 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 514 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 515}; 516static const struct bfin_memory_layout bf532_mem[] = 517{ 518 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ 519 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 520 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 521 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 522 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 523 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 524 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ 525 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 526}; 527static const struct bfin_memory_layout bf533_mem[] = 528{ 529 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */ 530 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 531 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 532 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 533 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 534 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 535 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 536 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 537 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 538 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ 539 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 540}; 541static const struct bfin_dev_layout bf533_dev[] = 542{ 543 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 544 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 545 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 546 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 547 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 548 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 549 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 550 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 551 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 552 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 553 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 554}; 555#define bf531_dev bf533_dev 556#define bf532_dev bf533_dev 557static const struct bfin_dmac_layout bf533_dmac[] = 558{ 559 { BFIN_MMR_DMAC0_BASE, 8, }, 560}; 561#define bf531_dmac bf533_dmac 562#define bf532_dmac bf533_dmac 563static const struct bfin_port_layout bf533_port[] = 564{ 565 SIC (0, 0, "bfin_pll", "pll"), 566/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 567 SIC (0, 2, "bfin_ppi@0", "stat"), 568 SIC (0, 3, "bfin_sport@0", "stat"), 569 SIC (0, 4, "bfin_sport@1", "stat"), 570 SIC (0, 5, "bfin_spi@0", "stat"), 571 SIC (0, 6, "bfin_uart@0", "stat"), 572 SIC (0, 7, "bfin_rtc", "rtc"), 573 SIC (0, 8, "bfin_dma@0", "di"), 574 SIC (0, 9, "bfin_dma@1", "di"), 575 SIC (0, 10, "bfin_dma@2", "di"), 576 SIC (0, 11, "bfin_dma@3", "di"), 577 SIC (0, 12, "bfin_dma@4", "di"), 578 SIC (0, 13, "bfin_dma@5", "di"), 579 SIC (0, 14, "bfin_dma@6", "di"), 580 SIC (0, 15, "bfin_dma@7", "di"), 581 SIC (0, 16, "bfin_gptimer@0", "stat"), 582 SIC (0, 17, "bfin_gptimer@1", "stat"), 583 SIC (0, 18, "bfin_gptimer@2", "stat"), 584 SIC (0, 19, "bfin_gpio@5", "mask_a"), 585 SIC (0, 20, "bfin_gpio@5", "mask_b"), 586 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ 587 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ 588 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */ 589 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ 590 SIC (0, 23, "bfin_wdog@0", "gpi"), 591}; 592#define bf531_port bf533_port 593#define bf532_port bf533_port 594 595#define bf534_chipid 0x27c6 596#define bf536_chipid 0x27c8 597#define bf537_chipid bf536_chipid 598static const struct bfin_memory_layout bf534_mem[] = 599{ 600 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ 601 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 602 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 603 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ 604 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 605 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 606 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 607 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 608 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 609 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 610 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 611}; 612static const struct bfin_memory_layout bf536_mem[] = 613{ 614 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ 615 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 616 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 617 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ 618 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 619 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 620 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 621 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 622 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 623}; 624static const struct bfin_memory_layout bf537_mem[] = 625{ 626 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */ 627 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 628 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 629 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */ 630 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 631 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 632 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 633 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 634 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 635 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 636 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 637}; 638static const struct bfin_dev_layout bf534_dev[] = 639{ 640 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 641 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 642 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 643 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 644 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 645 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 646 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 647 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 648 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 649 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 650 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 651 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 652 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 653 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 654 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 655 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 656 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 657 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 658 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 659 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 660 DEVICE (0, 0, "glue-or@1"), 661 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"), 662 DEVICE (0, 0, "glue-or@2"), 663 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"), 664 DEVICE (0, 0, "glue-or@17"), 665 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"), 666 DEVICE (0, 0, "glue-or@18"), 667 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"), 668 DEVICE (0, 0, "glue-or@27"), 669 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"), 670 DEVICE (0, 0, "glue-or@31"), 671 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"), 672}; 673static const struct bfin_dev_layout bf537_dev[] = 674{ 675 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 676 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 677 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 678 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 679 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 680 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 681 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 682 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 683 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 684 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 685 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 686 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 687 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 688 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 689 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 690 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 691 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 692 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 693 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 694 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"), 695 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"), 696 DEVICE (0, 0x20, "bfin_emac/eth_phy"), 697 DEVICE (0, 0, "glue-or@1"), 698 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"), 699 DEVICE (0, 0, "glue-or@2"), 700 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"), 701 DEVICE (0, 0, "glue-or@17"), 702 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"), 703 DEVICE (0, 0, "glue-or@18"), 704 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"), 705 DEVICE (0, 0, "glue-or@27"), 706 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"), 707 DEVICE (0, 0, "glue-or@31"), 708 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"), 709}; 710#define bf536_dev bf537_dev 711#define bf534_dmac bf50x_dmac 712#define bf536_dmac bf50x_dmac 713#define bf537_dmac bf50x_dmac 714static const struct bfin_port_layout bf537_port[] = 715{ 716 SIC (0, 0, "bfin_pll", "pll"), 717 SIC (0, 1, "glue-or@1", "int"), 718/*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/ 719 PORT ("glue-or@1", "int", "bfin_dmar@0", "block"), 720 PORT ("glue-or@1", "int", "bfin_dmar@1", "block"), 721 PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"), 722 PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"), 723 SIC (0, 2, "glue-or@2", "int"), 724 PORT ("glue-or@2", "int", "bfin_can@0", "stat"), 725 PORT ("glue-or@2", "int", "bfin_emac", "stat"), 726 PORT ("glue-or@2", "int", "bfin_sport@0", "stat"), 727 PORT ("glue-or@2", "int", "bfin_sport@1", "stat"), 728 PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"), 729 PORT ("glue-or@2", "int", "bfin_spi@0", "stat"), 730 PORT ("glue-or@2", "int", "bfin_uart@0", "stat"), 731 PORT ("glue-or@2", "int", "bfin_uart@1", "stat"), 732 SIC (0, 3, "bfin_rtc", "rtc"), 733 SIC (0, 4, "bfin_dma@0", "di"), 734 SIC (0, 5, "bfin_dma@3", "di"), 735 SIC (0, 6, "bfin_dma@4", "di"), 736 SIC (0, 7, "bfin_dma@5", "di"), 737 SIC (0, 8, "bfin_dma@6", "di"), 738 SIC (0, 9, "bfin_twi@0", "stat"), 739 SIC (0, 10, "bfin_dma@7", "di"), 740 SIC (0, 11, "bfin_dma@8", "di"), 741 SIC (0, 12, "bfin_dma@9", "di"), 742 SIC (0, 13, "bfin_dma@10", "di"), 743 SIC (0, 14, "bfin_dma@11", "di"), 744 SIC (0, 15, "bfin_can@0", "rx"), 745 SIC (0, 16, "bfin_can@0", "tx"), 746 SIC (0, 17, "glue-or@17", "int"), 747 PORT ("glue-or@17", "int", "bfin_dma@1", "di"), 748 PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"), 749 SIC (0, 18, "glue-or@18", "int"), 750 PORT ("glue-or@18", "int", "bfin_dma@2", "di"), 751 PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"), 752 SIC (0, 19, "bfin_gptimer@0", "stat"), 753 SIC (0, 20, "bfin_gptimer@1", "stat"), 754 SIC (0, 21, "bfin_gptimer@2", "stat"), 755 SIC (0, 22, "bfin_gptimer@3", "stat"), 756 SIC (0, 23, "bfin_gptimer@4", "stat"), 757 SIC (0, 24, "bfin_gptimer@5", "stat"), 758 SIC (0, 25, "bfin_gptimer@6", "stat"), 759 SIC (0, 26, "bfin_gptimer@7", "stat"), 760 SIC (0, 27, "glue-or@27", "int"), 761 PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"), 762 PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"), 763 SIC (0, 28, "bfin_gpio@6", "mask_b"), 764 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */ 765 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */ 766 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */ 767 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */ 768 SIC (0, 31, "glue-or@31", "int"), 769 PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"), 770 PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"), 771}; 772#define bf534_port bf537_port 773#define bf536_port bf537_port 774 775#define bf538_chipid 0x27c4 776#define bf539_chipid bf538_chipid 777static const struct bfin_memory_layout bf538_mem[] = 778{ 779 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 780 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 781 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */ 782 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ 783 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ 784 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 785 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 786 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 787 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 788 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 789 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 790 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */ 791 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 792}; 793#define bf539_mem bf538_mem 794static const struct bfin_dev_layout bf538_dev[] = 795{ 796 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 797 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 798 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 799 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 800 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 801 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 802 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 803 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 804 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 805 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 806 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 807 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 808 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1), 809 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1), 810 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), 811 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1), 812 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), 813}; 814#define bf539_dev bf538_dev 815static const struct bfin_dmac_layout bf538_dmac[] = 816{ 817 { BFIN_MMR_DMAC0_BASE, 8, }, 818 { BFIN_MMR_DMAC1_BASE, 12, }, 819}; 820#define bf539_dmac bf538_dmac 821static const struct bfin_port_layout bf538_port[] = 822{ 823 SIC (0, 0, "bfin_pll", "pll"), 824 SIC (0, 1, "bfin_dmac@0", "stat"), 825 SIC (0, 2, "bfin_ppi@0", "stat"), 826 SIC (0, 3, "bfin_sport@0", "stat"), 827 SIC (0, 4, "bfin_sport@1", "stat"), 828 SIC (0, 5, "bfin_spi@0", "stat"), 829 SIC (0, 6, "bfin_uart@0", "stat"), 830 SIC (0, 7, "bfin_rtc", "rtc"), 831 SIC (0, 8, "bfin_dma@0", "di"), 832 SIC (0, 9, "bfin_dma@1", "di"), 833 SIC (0, 10, "bfin_dma@2", "di"), 834 SIC (0, 11, "bfin_dma@3", "di"), 835 SIC (0, 12, "bfin_dma@4", "di"), 836 SIC (0, 13, "bfin_dma@5", "di"), 837 SIC (0, 14, "bfin_dma@6", "di"), 838 SIC (0, 15, "bfin_dma@7", "di"), 839 SIC (0, 16, "bfin_gptimer@0", "stat"), 840 SIC (0, 17, "bfin_gptimer@1", "stat"), 841 SIC (0, 18, "bfin_gptimer@2", "stat"), 842 SIC (0, 19, "bfin_gpio@5", "mask_a"), 843 SIC (0, 20, "bfin_gpio@5", "mask_b"), 844 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ 845 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ 846 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */ 847 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ 848 SIC (0, 23, "bfin_wdog@0", "gpi"), 849 SIC (0, 24, "bfin_dmac@1", "stat"), 850 SIC (0, 25, "bfin_sport@2", "stat"), 851 SIC (0, 26, "bfin_sport@3", "stat"), 852/*SIC (0, 27, reserved),*/ 853 SIC (0, 28, "bfin_spi@1", "stat"), 854 SIC (0, 29, "bfin_spi@2", "stat"), 855 SIC (0, 30, "bfin_uart@1", "stat"), 856 SIC (0, 31, "bfin_uart@2", "stat"), 857 SIC (1, 0, "bfin_can@0", "stat"), 858 SIC (1, 1, "bfin_dma@8", "di"), 859 SIC (1, 2, "bfin_dma@9", "di"), 860 SIC (1, 3, "bfin_dma@10", "di"), 861 SIC (1, 4, "bfin_dma@11", "di"), 862 SIC (1, 5, "bfin_dma@12", "di"), 863 SIC (1, 6, "bfin_dma@13", "di"), 864 SIC (1, 7, "bfin_dma@14", "di"), 865 SIC (1, 8, "bfin_dma@15", "di"), 866 SIC (1, 9, "bfin_dma@16", "di"), 867 SIC (1, 10, "bfin_dma@17", "di"), 868 SIC (1, 11, "bfin_dma@18", "di"), 869 SIC (1, 12, "bfin_dma@19", "di"), 870 SIC (1, 13, "bfin_twi@0", "stat"), 871 SIC (1, 14, "bfin_twi@1", "stat"), 872 SIC (1, 15, "bfin_can@0", "rx"), 873 SIC (1, 16, "bfin_can@0", "tx"), 874 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */ 875 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */ 876 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */ 877 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */ 878}; 879#define bf539_port bf538_port 880 881#define bf54x_chipid 0x27de 882#define bf542_chipid bf54x_chipid 883#define bf544_chipid bf54x_chipid 884#define bf547_chipid bf54x_chipid 885#define bf548_chipid bf54x_chipid 886#define bf549_chipid bf54x_chipid 887static const struct bfin_memory_layout bf54x_mem[] = 888{ 889 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */ 890 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 891 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ 892 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ 893 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */ 894 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */ 895 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */ 896 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ 897 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 898 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 899 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 900 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 901 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */ 902 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */ 903 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 904}; 905#define bf542_mem bf54x_mem 906#define bf544_mem bf54x_mem 907#define bf547_mem bf54x_mem 908#define bf548_mem bf54x_mem 909#define bf549_mem bf54x_mem 910static const struct bfin_dev_layout bf542_dev[] = 911{ 912 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 913 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 914 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), 915 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 916 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 917 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 918 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), 919 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), 920 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), 921 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), 922 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), 923 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), 924 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), 925 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), 926 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), 927 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), 928 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), 929 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), 930 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), 931 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), 932 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), 933 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), 934 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 935 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 936 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 937 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 938 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 939 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 940 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 941 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 942 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), 943 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), 944 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 945 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), 946 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), 947 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), 948 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), 949}; 950static const struct bfin_dev_layout bf544_dev[] = 951{ 952 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 953 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 954 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), 955 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 956 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), 957 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), 958 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), 959 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 960 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 961 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), 962 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), 963 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), 964 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), 965 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), 966 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), 967 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), 968 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), 969 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), 970 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), 971 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), 972 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), 973 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), 974 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), 975 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), 976 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), 977 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), 978 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 979 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 980 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 981 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 982 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 983 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 984 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 985 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 986 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), 987 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), 988 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), 989 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 990 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), 991 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), 992 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), 993 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"), 994}; 995static const struct bfin_dev_layout bf547_dev[] = 996{ 997 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 998 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"), 999 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"), 1000 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 1001 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), 1002 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), 1003 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), 1004 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 1005 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 1006 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), 1007 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), 1008 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), 1009 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"), 1010 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"), 1011 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2), 1012 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2), 1013 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), 1014 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), 1015 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), 1016 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), 1017 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), 1018 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), 1019 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), 1020 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), 1021 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), 1022 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), 1023 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 1024 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 1025 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 1026 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 1027 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 1028 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 1029 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 1030 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 1031 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"), 1032 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1), 1033 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"), 1034 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 1035 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1), 1036 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1), 1037 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1), 1038 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"), 1039}; 1040#define bf548_dev bf547_dev 1041#define bf549_dev bf547_dev 1042static const struct bfin_dmac_layout bf54x_dmac[] = 1043{ 1044 { BFIN_MMR_DMAC0_BASE, 12, }, 1045 { BFIN_MMR_DMAC1_BASE, 12, }, 1046}; 1047#define bf542_dmac bf54x_dmac 1048#define bf544_dmac bf54x_dmac 1049#define bf547_dmac bf54x_dmac 1050#define bf548_dmac bf54x_dmac 1051#define bf549_dmac bf54x_dmac 1052#define PINT_PIQS(p, b, g) \ 1053 PORT (p, "piq0@"#b, g, "p0"), \ 1054 PORT (p, "piq1@"#b, g, "p1"), \ 1055 PORT (p, "piq2@"#b, g, "p2"), \ 1056 PORT (p, "piq3@"#b, g, "p3"), \ 1057 PORT (p, "piq4@"#b, g, "p4"), \ 1058 PORT (p, "piq5@"#b, g, "p5"), \ 1059 PORT (p, "piq6@"#b, g, "p6"), \ 1060 PORT (p, "piq7@"#b, g, "p7"), \ 1061 PORT (p, "piq8@"#b, g, "p8"), \ 1062 PORT (p, "piq9@"#b, g, "p9"), \ 1063 PORT (p, "piq10@"#b, g, "p10"), \ 1064 PORT (p, "piq11@"#b, g, "p11"), \ 1065 PORT (p, "piq12@"#b, g, "p12"), \ 1066 PORT (p, "piq13@"#b, g, "p13"), \ 1067 PORT (p, "piq14@"#b, g, "p14"), \ 1068 PORT (p, "piq15@"#b, g, "p15") 1069static const struct bfin_port_layout bf54x_port[] = 1070{ 1071 SIC (0, 0, "bfin_pll", "pll"), 1072 SIC (0, 1, "bfin_dmac@0", "stat"), 1073 SIC (0, 2, "bfin_eppi@0", "stat"), 1074 SIC (0, 3, "bfin_sport@0", "stat"), 1075 SIC (0, 4, "bfin_sport@1", "stat"), 1076 SIC (0, 5, "bfin_spi@0", "stat"), 1077 SIC (0, 6, "bfin_uart2@0", "stat"), 1078 SIC (0, 7, "bfin_rtc", "rtc"), 1079 SIC (0, 8, "bfin_dma@12", "di"), 1080 SIC (0, 9, "bfin_dma@0", "di"), 1081 SIC (0, 10, "bfin_dma@1", "di"), 1082 SIC (0, 11, "bfin_dma@2", "di"), 1083 SIC (0, 12, "bfin_dma@3", "di"), 1084 SIC (0, 13, "bfin_dma@4", "di"), 1085 SIC (0, 14, "bfin_dma@6", "di"), 1086 SIC (0, 15, "bfin_dma@7", "di"), 1087 SIC (0, 16, "bfin_gptimer@8", "stat"), 1088 SIC (0, 17, "bfin_gptimer@9", "stat"), 1089 SIC (0, 18, "bfin_gptimer@10", "stat"), 1090 SIC (0, 19, "bfin_pint@0", "stat"), 1091 PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"), 1092 PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"), 1093 SIC (0, 20, "bfin_pint@1", "stat"), 1094 PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"), 1095 PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"), 1096 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */ 1097 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */ 1098 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */ 1099 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */ 1100 SIC (0, 23, "bfin_wdog@0", "gpi"), 1101 SIC (0, 24, "bfin_dmac@1", "stat"), 1102 SIC (0, 25, "bfin_sport@2", "stat"), 1103 SIC (0, 26, "bfin_sport@3", "stat"), 1104 SIC (0, 27, "bfin_mxvr", "data"), 1105 SIC (0, 28, "bfin_spi@1", "stat"), 1106 SIC (0, 29, "bfin_spi@2", "stat"), 1107 SIC (0, 30, "bfin_uart2@1", "stat"), 1108 SIC (0, 31, "bfin_uart2@2", "stat"), 1109 SIC (1, 0, "bfin_can@0", "stat"), 1110 SIC (1, 1, "bfin_dma@18", "di"), 1111 SIC (1, 2, "bfin_dma@19", "di"), 1112 SIC (1, 3, "bfin_dma@20", "di"), 1113 SIC (1, 4, "bfin_dma@21", "di"), 1114 SIC (1, 5, "bfin_dma@13", "di"), 1115 SIC (1, 6, "bfin_dma@14", "di"), 1116 SIC (1, 7, "bfin_dma@5", "di"), 1117 SIC (1, 8, "bfin_dma@23", "di"), 1118 SIC (1, 9, "bfin_dma@8", "di"), 1119 SIC (1, 10, "bfin_dma@9", "di"), 1120 SIC (1, 11, "bfin_dma@10", "di"), 1121 SIC (1, 12, "bfin_dma@11", "di"), 1122 SIC (1, 13, "bfin_twi@0", "stat"), 1123 SIC (1, 14, "bfin_twi@1", "stat"), 1124 SIC (1, 15, "bfin_can@0", "rx"), 1125 SIC (1, 16, "bfin_can@0", "tx"), 1126 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */ 1127 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */ 1128 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */ 1129 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */ 1130 SIC (1, 19, "bfin_mxvr", "stat"), 1131 SIC (1, 20, "bfin_mxvr", "message"), 1132 SIC (1, 21, "bfin_mxvr", "packet"), 1133 SIC (1, 22, "bfin_eppi@1", "stat"), 1134 SIC (1, 23, "bfin_eppi@2", "stat"), 1135 SIC (1, 24, "bfin_uart2@3", "stat"), 1136 SIC (1, 25, "bfin_hostdp", "stat"), 1137/*SIC (1, 26, reserved),*/ 1138 SIC (1, 27, "bfin_pixc", "stat"), 1139 SIC (1, 28, "bfin_nfc", "stat"), 1140 SIC (1, 29, "bfin_atapi", "stat"), 1141 SIC (1, 30, "bfin_can@1", "stat"), 1142 SIC (1, 31, "bfin_dmar@0", "block"), 1143 SIC (1, 31, "bfin_dmar@1", "block"), 1144 SIC (1, 31, "bfin_dmar@0", "overflow"), 1145 SIC (1, 31, "bfin_dmar@1", "overflow"), 1146 SIC (2, 0, "bfin_dma@15", "di"), 1147 SIC (2, 1, "bfin_dma@16", "di"), 1148 SIC (2, 2, "bfin_dma@17", "di"), 1149 SIC (2, 3, "bfin_dma@22", "di"), 1150 SIC (2, 4, "bfin_counter@0", "stat"), 1151 SIC (2, 5, "bfin_kpad@0", "stat"), 1152 SIC (2, 6, "bfin_can@1", "rx"), 1153 SIC (2, 7, "bfin_can@1", "tx"), 1154 SIC (2, 8, "bfin_sdh", "mask0"), 1155 SIC (2, 9, "bfin_sdh", "mask1"), 1156/*SIC (2, 10, reserved),*/ 1157 SIC (2, 11, "bfin_usb", "int0"), 1158 SIC (2, 12, "bfin_usb", "int1"), 1159 SIC (2, 13, "bfin_usb", "int2"), 1160 SIC (2, 14, "bfin_usb", "dma"), 1161 SIC (2, 15, "bfin_otp", "stat"), 1162/*SIC (2, 16, reserved),*/ 1163/*SIC (2, 17, reserved),*/ 1164/*SIC (2, 18, reserved),*/ 1165/*SIC (2, 19, reserved),*/ 1166/*SIC (2, 20, reserved),*/ 1167/*SIC (2, 21, reserved),*/ 1168 SIC (2, 22, "bfin_gptimer@0", "stat"), 1169 SIC (2, 23, "bfin_gptimer@1", "stat"), 1170 SIC (2, 24, "bfin_gptimer@2", "stat"), 1171 SIC (2, 25, "bfin_gptimer@3", "stat"), 1172 SIC (2, 26, "bfin_gptimer@4", "stat"), 1173 SIC (2, 27, "bfin_gptimer@5", "stat"), 1174 SIC (2, 28, "bfin_gptimer@6", "stat"), 1175 SIC (2, 29, "bfin_gptimer@7", "stat"), 1176 SIC (2, 30, "bfin_pint@2", "stat"), 1177 PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"), 1178 PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"), 1179 PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"), 1180 PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"), 1181 PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"), 1182 PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"), 1183 PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"), 1184 PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"), 1185 SIC (2, 31, "bfin_pint@3", "stat"), 1186 PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"), 1187 PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"), 1188 PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"), 1189 PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"), 1190 PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"), 1191 PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"), 1192 PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"), 1193 PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"), 1194}; 1195#define bf542_port bf54x_port 1196#define bf544_port bf54x_port 1197#define bf547_port bf54x_port 1198#define bf548_port bf54x_port 1199#define bf549_port bf54x_port 1200 1201/* This is only Core A of course ... */ 1202#define bf561_chipid 0x27bb 1203static const struct bfin_memory_layout bf561_mem[] = 1204{ 1205 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 1206 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 1207 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */ 1208 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */ 1209 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */ 1210 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */ 1211 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */ 1212 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ 1213 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */ 1214}; 1215static const struct bfin_dev_layout bf561_dev[] = 1216{ 1217 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 1218 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 1219 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 1220 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 1221 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 1222 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 1223 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"), 1224 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"), 1225 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"), 1226 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"), 1227 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"), 1228 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 1229 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), 1230 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), 1231 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1), 1232 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"), 1233 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1), 1234 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 1235 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"), 1236 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"), 1237 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"), 1238 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"), 1239 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"), 1240}; 1241static const struct bfin_dmac_layout bf561_dmac[] = 1242{ 1243 { BFIN_MMR_DMAC0_BASE, 12, }, 1244 { BFIN_MMR_DMAC1_BASE, 12, }, 1245 /* XXX: IMDMA: { 0xFFC01800, 4, }, */ 1246}; 1247static const struct bfin_port_layout bf561_port[] = 1248{ 1249 /* SIC0 */ 1250 SIC (0, 0, "bfin_pll", "pll"), 1251/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 1252/*SIC (0, 2, "bfin_dmac@1", "stat"),*/ 1253/*SIC (0, 3, "bfin_imdmac", "stat"),*/ 1254 SIC (0, 4, "bfin_ppi@0", "stat"), 1255 SIC (0, 5, "bfin_ppi@1", "stat"), 1256 SIC (0, 6, "bfin_sport@0", "stat"), 1257 SIC (0, 7, "bfin_sport@1", "stat"), 1258 SIC (0, 8, "bfin_spi@0", "stat"), 1259 SIC (0, 9, "bfin_uart@0", "stat"), 1260/*SIC (0, 10, reserved),*/ 1261 SIC (0, 11, "bfin_dma@12", "di"), 1262 SIC (0, 12, "bfin_dma@13", "di"), 1263 SIC (0, 13, "bfin_dma@14", "di"), 1264 SIC (0, 14, "bfin_dma@15", "di"), 1265 SIC (0, 15, "bfin_dma@16", "di"), 1266 SIC (0, 16, "bfin_dma@17", "di"), 1267 SIC (0, 17, "bfin_dma@18", "di"), 1268 SIC (0, 18, "bfin_dma@19", "di"), 1269 SIC (0, 19, "bfin_dma@20", "di"), 1270 SIC (0, 20, "bfin_dma@21", "di"), 1271 SIC (0, 21, "bfin_dma@22", "di"), 1272 SIC (0, 22, "bfin_dma@23", "di"), 1273 SIC (0, 23, "bfin_dma@0", "di"), 1274 SIC (0, 24, "bfin_dma@1", "di"), 1275 SIC (0, 25, "bfin_dma@2", "di"), 1276 SIC (0, 26, "bfin_dma@3", "di"), 1277 SIC (0, 27, "bfin_dma@4", "di"), 1278 SIC (0, 28, "bfin_dma@5", "di"), 1279 SIC (0, 29, "bfin_dma@6", "di"), 1280 SIC (0, 30, "bfin_dma@7", "di"), 1281 SIC (0, 31, "bfin_dma@8", "di"), 1282 SIC (1, 0, "bfin_dma@9", "di"), 1283 SIC (1, 1, "bfin_dma@10", "di"), 1284 SIC (1, 2, "bfin_dma@11", "di"), 1285 SIC (1, 3, "bfin_gptimer@0", "stat"), 1286 SIC (1, 4, "bfin_gptimer@1", "stat"), 1287 SIC (1, 5, "bfin_gptimer@2", "stat"), 1288 SIC (1, 6, "bfin_gptimer@3", "stat"), 1289 SIC (1, 7, "bfin_gptimer@4", "stat"), 1290 SIC (1, 8, "bfin_gptimer@5", "stat"), 1291 SIC (1, 9, "bfin_gptimer@6", "stat"), 1292 SIC (1, 10, "bfin_gptimer@7", "stat"), 1293 SIC (1, 11, "bfin_gptimer@8", "stat"), 1294 SIC (1, 12, "bfin_gptimer@9", "stat"), 1295 SIC (1, 13, "bfin_gptimer@10", "stat"), 1296 SIC (1, 14, "bfin_gptimer@11", "stat"), 1297 SIC (1, 15, "bfin_gpio@5", "mask_a"), 1298 SIC (1, 16, "bfin_gpio@5", "mask_b"), 1299 SIC (1, 17, "bfin_gpio@6", "mask_a"), 1300 SIC (1, 18, "bfin_gpio@6", "mask_b"), 1301 SIC (1, 19, "bfin_gpio@7", "mask_a"), 1302 SIC (1, 20, "bfin_gpio@7", "mask_b"), 1303 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */ 1304 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */ 1305 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */ 1306 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */ 1307 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */ 1308 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */ 1309 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */ 1310 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */ 1311 SIC (1, 25, "bfin_imdma@0", "di"), 1312 SIC (1, 26, "bfin_imdma@1", "di"), 1313 SIC (1, 27, "bfin_wdog@0", "gpi"), 1314 SIC (1, 27, "bfin_wdog@1", "gpi"), 1315/*SIC (1, 28, reserved),*/ 1316/*SIC (1, 29, reserved),*/ 1317 SIC (1, 30, "bfin_sic", "sup_irq@0"), 1318 SIC (1, 31, "bfin_sic", "sup_irq@1"), 1319}; 1320 1321#define bf592_chipid 0x20cb 1322static const struct bfin_memory_layout bf592_mem[] = 1323{ 1324 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */ 1325 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ 1326 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */ 1327 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */ 1328 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */ 1329}; 1330static const struct bfin_dev_layout bf592_dev[] = 1331{ 1332 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"), 1333 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"), 1334 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"), 1335 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), 1336 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), 1337 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), 1338 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), 1339 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), 1340 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"), 1341 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), 1342 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), 1343}; 1344static const struct bfin_dmac_layout bf592_dmac[] = 1345{ 1346 /* XXX: there are only 9 channels, but mdma code below assumes that they 1347 start right after the dma channels ... */ 1348 { BFIN_MMR_DMAC0_BASE, 12, }, 1349}; 1350static const struct bfin_port_layout bf592_port[] = 1351{ 1352 SIC (0, 0, "bfin_pll", "pll"), 1353/*SIC (0, 1, "bfin_dmac@0", "stat"),*/ 1354 SIC (0, 2, "bfin_ppi@0", "stat"), 1355 SIC (0, 3, "bfin_sport@0", "stat"), 1356 SIC (0, 4, "bfin_sport@1", "stat"), 1357 SIC (0, 5, "bfin_spi@0", "stat"), 1358 SIC (0, 6, "bfin_spi@1", "stat"), 1359 SIC (0, 7, "bfin_uart@0", "stat"), 1360 SIC (0, 8, "bfin_dma@0", "di"), 1361 SIC (0, 9, "bfin_dma@1", "di"), 1362 SIC (0, 10, "bfin_dma@2", "di"), 1363 SIC (0, 11, "bfin_dma@3", "di"), 1364 SIC (0, 12, "bfin_dma@4", "di"), 1365 SIC (0, 13, "bfin_dma@5", "di"), 1366 SIC (0, 14, "bfin_dma@6", "di"), 1367 SIC (0, 15, "bfin_dma@7", "di"), 1368 SIC (0, 16, "bfin_dma@8", "di"), 1369 SIC (0, 17, "bfin_gpio@5", "mask_a"), 1370 SIC (0, 18, "bfin_gpio@5", "mask_b"), 1371 SIC (0, 19, "bfin_gptimer@0", "stat"), 1372 SIC (0, 20, "bfin_gptimer@1", "stat"), 1373 SIC (0, 21, "bfin_gptimer@2", "stat"), 1374 SIC (0, 22, "bfin_gpio@6", "mask_a"), 1375 SIC (0, 23, "bfin_gpio@6", "mask_b"), 1376 SIC (0, 24, "bfin_twi@0", "stat"), 1377/* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */ 1378 SIC (0, 25, "bfin_dma@9", "di"), 1379 SIC (0, 26, "bfin_dma@10", "di"), 1380 SIC (0, 27, "bfin_dma@11", "di"), 1381 SIC (0, 28, "bfin_dma@12", "di"), 1382/*SIC (0, 25, reserved),*/ 1383/*SIC (0, 26, reserved),*/ 1384/*SIC (0, 27, reserved),*/ 1385/*SIC (0, 28, reserved),*/ 1386 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */ 1387 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */ 1388 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */ 1389 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */ 1390 SIC (0, 31, "bfin_wdog", "gpi"), 1391}; 1392 1393static const struct bfin_model_data bfin_model_data[] = 1394{ 1395#define P(n) \ 1396 [MODEL_BF##n] = { \ 1397 bf##n##_chipid, n, \ 1398 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \ 1399 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \ 1400 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \ 1401 bf##n##_port, ARRAY_SIZE (bf##n##_port), \ 1402 }, 1403#include "proc_list.def" 1404#undef P 1405}; 1406 1407#define CORE_DEVICE(dev, DEV) \ 1408 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev) 1409static const struct bfin_dev_layout bfin_core_dev[] = 1410{ 1411 CORE_DEVICE (cec, CEC), 1412 CORE_DEVICE (ctimer, CTIMER), 1413 CORE_DEVICE (evt, EVT), 1414 CORE_DEVICE (jtag, JTAG), 1415 CORE_DEVICE (mmu, MMU), 1416 CORE_DEVICE (pfmon, PFMON), 1417 CORE_DEVICE (trace, TRACE), 1418 CORE_DEVICE (wp, WP), 1419}; 1420 1421static void 1422dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata, 1423 const char *dev) 1424{ 1425 size_t i; 1426 const char *sdev; 1427 1428 sdev = strchr (dev, '/'); 1429 if (sdev) 1430 ++sdev; 1431 else 1432 sdev = dev; 1433 1434 for (i = 0; i < mdata->port_count; ++i) 1435 { 1436 const struct bfin_port_layout *port = &mdata->port[i]; 1437 1438 /* There might be more than one mapping. */ 1439 if (!strcmp (sdev, port->src)) 1440 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev, 1441 port->src_port, port->dst_port, port->dst); 1442 } 1443} 1444 1445#define dv_bfin_hw_parse(sd, dv, DV) \ 1446 do { \ 1447 bu32 base = BFIN_MMR_##DV##_BASE; \ 1448 bu32 size = BFIN_MMR_##DV##_SIZE; \ 1449 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \ 1450 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \ 1451 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \ 1452 } while (0) 1453 1454static void 1455bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu) 1456{ 1457 const SIM_MODEL *model = CPU_MODEL (cpu); 1458 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); 1459 const struct bfin_board_data *board = STATE_BOARD_DATA (sd); 1460 int mnum = MODEL_NUM (model); 1461 unsigned i, j, dma_chan; 1462 1463 /* Map the core devices. */ 1464 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i) 1465 { 1466 const struct bfin_dev_layout *dev = &bfin_core_dev[i]; 1467 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); 1468 } 1469 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec"); 1470 1471 if (mnum == MODEL_BF000) 1472 goto done; 1473 1474 /* Map the system devices. */ 1475 dv_bfin_hw_parse (sd, sic, SIC); 1476 for (i = 7; i < 16; ++i) 1477 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i); 1478 1479 dv_bfin_hw_parse (sd, pll, PLL); 1480 1481 dma_chan = 0; 1482 for (i = 0; i < mdata->dmac_count; ++i) 1483 { 1484 const struct bfin_dmac_layout *dmac = &mdata->dmac[i]; 1485 1486 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num); 1487 1488 /* Hook up the non-mdma channels. */ 1489 for (j = 0; j < dmac->dma_count; ++j) 1490 { 1491 char dev[64]; 1492 1493 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan); 1494 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev, 1495 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE); 1496 dv_bfin_hw_port_parse (sd, mdata, dev); 1497 1498 ++dma_chan; 1499 } 1500 1501 /* Hook up the mdma channels -- assume every DMAC has 4. */ 1502 for (j = 0; j < 4; ++j) 1503 { 1504 char dev[64]; 1505 1506 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE); 1507 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev, 1508 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE, 1509 BFIN_MMR_DMA_SIZE); 1510 dv_bfin_hw_port_parse (sd, mdata, dev); 1511 } 1512 } 1513 1514 for (i = 0; i < mdata->dev_count; ++i) 1515 { 1516 const struct bfin_dev_layout *dev = &mdata->dev[i]; 1517 1518 if (dev->len) 1519 { 1520 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len); 1521 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num); 1522 } 1523 else 1524 { 1525 sim_hw_parse (sd, "/core/%s", dev->dev); 1526 } 1527 1528 dv_bfin_hw_port_parse (sd, mdata, dev->dev); 1529 if (strchr (dev->dev, '/')) 1530 continue; 1531 1532 if (!strncmp (dev->dev, "bfin_uart", 9) 1533 || !strncmp (dev->dev, "bfin_emac", 9) 1534 || !strncmp (dev->dev, "bfin_sport", 10)) 1535 { 1536 const char *sint = dev->dev + 5; 1537 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); 1538 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac); 1539 } 1540 else if (!strncmp (dev->dev, "bfin_wdog", 9)) 1541 { 1542 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev); 1543 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev); 1544 } 1545 } 1546 1547 done: 1548 /* Add any additional user board content. */ 1549 if (board->hw_file) 1550 sim_do_commandf (sd, "hw-file %s", board->hw_file); 1551 1552 /* Trigger all the new devices' finish func. */ 1553 hw_tree_finish (dv_get_device (cpu, "/")); 1554} 1555 1556#include "bfroms/all.h" 1557 1558struct bfrom { 1559 bu32 addr, len, alias_len; 1560 int sirev; 1561 const char *buf; 1562}; 1563 1564#define BFROMA(addr, rom, sirev, alias_len) \ 1565 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \ 1566 sirev, bfrom_bf##rom##_0_##sirev, } 1567#define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len) 1568#define BFROM_STUB { 0, 0, 0, 0, NULL, } 1569static const struct bfrom bf50x_roms[] = 1570{ 1571 BFROM (50x, 0, 0x1000000), 1572 BFROM_STUB, 1573}; 1574static const struct bfrom bf51x_roms[] = 1575{ 1576 BFROM (51x, 2, 0x1000000), 1577 BFROM (51x, 1, 0x1000000), 1578 BFROM (51x, 0, 0x1000000), 1579 BFROM_STUB, 1580}; 1581static const struct bfrom bf526_roms[] = 1582{ 1583 BFROM (526, 2, 0x1000000), 1584 BFROM (526, 1, 0x1000000), 1585 BFROM (526, 0, 0x1000000), 1586 BFROM_STUB, 1587}; 1588static const struct bfrom bf527_roms[] = 1589{ 1590 BFROM (527, 2, 0x1000000), 1591 BFROM (527, 1, 0x1000000), 1592 BFROM (527, 0, 0x1000000), 1593 BFROM_STUB, 1594}; 1595static const struct bfrom bf533_roms[] = 1596{ 1597 BFROM (533, 6, 0x1000000), 1598 BFROM (533, 5, 0x1000000), 1599 BFROM (533, 4, 0x1000000), 1600 BFROM (533, 3, 0x1000000), 1601 BFROM (533, 2, 0x1000000), 1602 BFROM (533, 1, 0x1000000), 1603 BFROM_STUB, 1604}; 1605static const struct bfrom bf537_roms[] = 1606{ 1607 BFROM (537, 3, 0x100000), 1608 BFROM (537, 2, 0x100000), 1609 BFROM (537, 1, 0x100000), 1610 BFROM (537, 0, 0x100000), 1611 BFROM_STUB, 1612}; 1613static const struct bfrom bf538_roms[] = 1614{ 1615 BFROM (538, 5, 0x1000000), 1616 BFROM (538, 4, 0x1000000), 1617 BFROM (538, 3, 0x1000000), 1618 BFROM (538, 2, 0x1000000), 1619 BFROM (538, 1, 0x1000000), 1620 BFROM (538, 0, 0x1000000), 1621 BFROM_STUB, 1622}; 1623static const struct bfrom bf54x_roms[] = 1624{ 1625 BFROM (54x, 4, 0x1000), 1626 BFROM (54x, 2, 0x1000), 1627 BFROM (54x, 1, 0x1000), 1628 BFROM (54x, 0, 0x1000), 1629 BFROMA (0xffa14000, 54x_l1, 4, 0x10000), 1630 BFROMA (0xffa14000, 54x_l1, 2, 0x10000), 1631 BFROMA (0xffa14000, 54x_l1, 1, 0x10000), 1632 BFROMA (0xffa14000, 54x_l1, 0, 0x10000), 1633 BFROM_STUB, 1634}; 1635static const struct bfrom bf561_roms[] = 1636{ 1637 /* XXX: No idea what the actual wrap limit is here. */ 1638 BFROM (561, 5, 0x1000), 1639 BFROM_STUB, 1640}; 1641static const struct bfrom bf59x_roms[] = 1642{ 1643 BFROM (59x, 1, 0x1000000), 1644 BFROM (59x, 0, 0x1000000), 1645 BFROMA (0xffa10000, 59x_l1, 1, 0x10000), 1646 BFROM_STUB, 1647}; 1648 1649static void 1650bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu) 1651{ 1652 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); 1653 const struct bfin_board_data *board = STATE_BOARD_DATA (sd); 1654 int mnum = mdata->model_num; 1655 const struct bfrom *bfrom; 1656 unsigned int sirev; 1657 1658 if (mnum >= 500 && mnum <= 509) 1659 bfrom = bf50x_roms; 1660 else if (mnum >= 510 && mnum <= 519) 1661 bfrom = bf51x_roms; 1662 else if (mnum >= 520 && mnum <= 529) 1663 bfrom = (mnum & 1) ? bf527_roms : bf526_roms; 1664 else if (mnum >= 531 && mnum <= 533) 1665 bfrom = bf533_roms; 1666 else if (mnum == 535) 1667 return; /* Stub. */ 1668 else if (mnum >= 534 && mnum <= 537) 1669 bfrom = bf537_roms; 1670 else if (mnum >= 538 && mnum <= 539) 1671 bfrom = bf538_roms; 1672 else if (mnum >= 540 && mnum <= 549) 1673 bfrom = bf54x_roms; 1674 else if (mnum == 561) 1675 bfrom = bf561_roms; 1676 else if (mnum >= 590 && mnum <= 599) 1677 bfrom = bf59x_roms; 1678 else 1679 return; 1680 1681 if (board->sirev_valid) 1682 sirev = board->sirev; 1683 else 1684 sirev = bfrom->sirev; 1685 while (bfrom->buf) 1686 { 1687 /* Map all the ranges for this model/sirev. */ 1688 if (bfrom->sirev == sirev) 1689 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr, 1690 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL, 1691 (char *)bfrom->buf); 1692 ++bfrom; 1693 } 1694} 1695 1696void 1697bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu) 1698{ 1699 const SIM_MODEL *model = CPU_MODEL (cpu); 1700 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); 1701 int mnum = MODEL_NUM (model); 1702 size_t idx; 1703 1704 /* These memory maps are supposed to be cpu-specific, but the common sim 1705 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */ 1706 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH, 1707 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL); 1708 1709 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT) 1710 return; 1711 1712 if (mnum == MODEL_BF000) 1713 goto core_only; 1714 1715 /* Map in the on-chip memories (SRAMs). */ 1716 mdata = &bfin_model_data[MODEL_NUM (model)]; 1717 for (idx = 0; idx < mdata->mem_count; ++idx) 1718 { 1719 const struct bfin_memory_layout *mem = &mdata->mem[idx]; 1720 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr, 1721 mem->len, 0, NULL, NULL); 1722 } 1723 1724 /* Map the on-chip ROMs. */ 1725 bfin_model_map_bfrom (sd, cpu); 1726 1727 core_only: 1728 /* Finally, build up the tree for this cpu model. */ 1729 bfin_model_hw_tree_init (sd, cpu); 1730} 1731 1732bu32 1733bfin_model_get_chipid (SIM_DESC sd) 1734{ 1735 SIM_CPU *cpu = STATE_CPU (sd, 0); 1736 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu); 1737 const struct bfin_board_data *board = STATE_BOARD_DATA (sd); 1738 return 1739 (board->sirev << 28) | 1740 (mdata->chipid << 12) | 1741 (((0xE5 << 1) | 1) & 0xFF); 1742} 1743 1744bu32 1745bfin_model_get_dspid (SIM_DESC sd) 1746{ 1747 const struct bfin_board_data *board = STATE_BOARD_DATA (sd); 1748 return 1749 (0xE5 << 24) | 1750 (0x04 << 16) | 1751 (board->sirev); 1752} 1753 1754static void 1755bfin_model_init (SIM_CPU *cpu) 1756{ 1757 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))]; 1758} 1759 1760static bu32 1761bfin_extract_unsigned_integer (const unsigned char *addr, int len) 1762{ 1763 bu32 retval; 1764 unsigned char * p; 1765 unsigned char * startaddr = (unsigned char *)addr; 1766 unsigned char * endaddr = startaddr + len; 1767 1768 retval = 0; 1769 1770 for (p = endaddr; p > startaddr;) 1771 retval = (retval << 8) | *--p; 1772 1773 return retval; 1774} 1775 1776static void 1777bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val) 1778{ 1779 unsigned char *p; 1780 unsigned char *startaddr = addr; 1781 unsigned char *endaddr = startaddr + len; 1782 1783 for (p = startaddr; p < endaddr;) 1784 { 1785 *p++ = val & 0xff; 1786 val >>= 8; 1787 } 1788} 1789 1790static bu32 * 1791bfin_get_reg (SIM_CPU *cpu, int rn) 1792{ 1793 switch (rn) 1794 { 1795 case SIM_BFIN_R0_REGNUM: return &DREG (0); 1796 case SIM_BFIN_R1_REGNUM: return &DREG (1); 1797 case SIM_BFIN_R2_REGNUM: return &DREG (2); 1798 case SIM_BFIN_R3_REGNUM: return &DREG (3); 1799 case SIM_BFIN_R4_REGNUM: return &DREG (4); 1800 case SIM_BFIN_R5_REGNUM: return &DREG (5); 1801 case SIM_BFIN_R6_REGNUM: return &DREG (6); 1802 case SIM_BFIN_R7_REGNUM: return &DREG (7); 1803 case SIM_BFIN_P0_REGNUM: return &PREG (0); 1804 case SIM_BFIN_P1_REGNUM: return &PREG (1); 1805 case SIM_BFIN_P2_REGNUM: return &PREG (2); 1806 case SIM_BFIN_P3_REGNUM: return &PREG (3); 1807 case SIM_BFIN_P4_REGNUM: return &PREG (4); 1808 case SIM_BFIN_P5_REGNUM: return &PREG (5); 1809 case SIM_BFIN_SP_REGNUM: return &SPREG; 1810 case SIM_BFIN_FP_REGNUM: return &FPREG; 1811 case SIM_BFIN_I0_REGNUM: return &IREG (0); 1812 case SIM_BFIN_I1_REGNUM: return &IREG (1); 1813 case SIM_BFIN_I2_REGNUM: return &IREG (2); 1814 case SIM_BFIN_I3_REGNUM: return &IREG (3); 1815 case SIM_BFIN_M0_REGNUM: return &MREG (0); 1816 case SIM_BFIN_M1_REGNUM: return &MREG (1); 1817 case SIM_BFIN_M2_REGNUM: return &MREG (2); 1818 case SIM_BFIN_M3_REGNUM: return &MREG (3); 1819 case SIM_BFIN_B0_REGNUM: return &BREG (0); 1820 case SIM_BFIN_B1_REGNUM: return &BREG (1); 1821 case SIM_BFIN_B2_REGNUM: return &BREG (2); 1822 case SIM_BFIN_B3_REGNUM: return &BREG (3); 1823 case SIM_BFIN_L0_REGNUM: return &LREG (0); 1824 case SIM_BFIN_L1_REGNUM: return &LREG (1); 1825 case SIM_BFIN_L2_REGNUM: return &LREG (2); 1826 case SIM_BFIN_L3_REGNUM: return &LREG (3); 1827 case SIM_BFIN_RETS_REGNUM: return &RETSREG; 1828 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0); 1829 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0); 1830 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1); 1831 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1); 1832 case SIM_BFIN_LC0_REGNUM: return &LCREG (0); 1833 case SIM_BFIN_LT0_REGNUM: return <REG (0); 1834 case SIM_BFIN_LB0_REGNUM: return &LBREG (0); 1835 case SIM_BFIN_LC1_REGNUM: return &LCREG (1); 1836 case SIM_BFIN_LT1_REGNUM: return <REG (1); 1837 case SIM_BFIN_LB1_REGNUM: return &LBREG (1); 1838 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG; 1839 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG; 1840 case SIM_BFIN_USP_REGNUM: return &USPREG; 1841 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG; 1842 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG; 1843 case SIM_BFIN_RETI_REGNUM: return &RETIREG; 1844 case SIM_BFIN_RETX_REGNUM: return &RETXREG; 1845 case SIM_BFIN_RETN_REGNUM: return &RETNREG; 1846 case SIM_BFIN_RETE_REGNUM: return &RETEREG; 1847 case SIM_BFIN_PC_REGNUM: return &PCREG; 1848 default: return NULL; 1849 } 1850} 1851 1852static int 1853bfin_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int len) 1854{ 1855 bu32 value, *reg; 1856 1857 reg = bfin_get_reg (cpu, rn); 1858 if (reg) 1859 value = *reg; 1860 else if (rn == SIM_BFIN_ASTAT_REGNUM) 1861 value = ASTAT; 1862 else if (rn == SIM_BFIN_CC_REGNUM) 1863 value = CCREG; 1864 else 1865 return -1; 1866 1867 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we 1868 have the normal SP/USP behavior. User mode is tricky though. */ 1869 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT 1870 && cec_is_user_mode (cpu)) 1871 { 1872 if (rn == SIM_BFIN_SP_REGNUM) 1873 value = KSPREG; 1874 else if (rn == SIM_BFIN_USP_REGNUM) 1875 value = SPREG; 1876 } 1877 1878 bfin_store_unsigned_integer (buf, 4, value); 1879 1880 return 4; 1881} 1882 1883static int 1884bfin_reg_store (SIM_CPU *cpu, int rn, const void *buf, int len) 1885{ 1886 bu32 value, *reg; 1887 1888 value = bfin_extract_unsigned_integer (buf, 4); 1889 reg = bfin_get_reg (cpu, rn); 1890 1891 if (reg) 1892 /* XXX: Need register trace ? */ 1893 *reg = value; 1894 else if (rn == SIM_BFIN_ASTAT_REGNUM) 1895 SET_ASTAT (value); 1896 else if (rn == SIM_BFIN_CC_REGNUM) 1897 SET_CCREG (value); 1898 else 1899 return -1; 1900 1901 return 4; 1902} 1903 1904static sim_cia 1905bfin_pc_get (SIM_CPU *cpu) 1906{ 1907 return PCREG; 1908} 1909 1910static void 1911bfin_pc_set (SIM_CPU *cpu, sim_cia newpc) 1912{ 1913 SET_PCREG (newpc); 1914} 1915 1916static const char * 1917bfin_insn_name (SIM_CPU *cpu, int i) 1918{ 1919 static const char * const insn_name[] = { 1920#define I(insn) #insn, 1921#include "insn_list.def" 1922#undef I 1923 }; 1924 return insn_name[i]; 1925} 1926 1927static void 1928bfin_init_cpu (SIM_CPU *cpu) 1929{ 1930 CPU_REG_FETCH (cpu) = bfin_reg_fetch; 1931 CPU_REG_STORE (cpu) = bfin_reg_store; 1932 CPU_PC_FETCH (cpu) = bfin_pc_get; 1933 CPU_PC_STORE (cpu) = bfin_pc_set; 1934 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX; 1935 CPU_INSN_NAME (cpu) = bfin_insn_name; 1936} 1937 1938static void 1939bfin_prepare_run (SIM_CPU *cpu) 1940{ 1941} 1942 1943static const SIM_MODEL bfin_models[] = 1944{ 1945#define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init }, 1946#include "proc_list.def" 1947#undef P 1948 { 0, NULL, 0, NULL, NULL, } 1949}; 1950 1951static const SIM_MACH_IMP_PROPERTIES bfin_imp_properties = 1952{ 1953 sizeof (SIM_CPU), 1954 0, 1955}; 1956 1957static const SIM_MACH bfin_mach = 1958{ 1959 "bfin", "bfin", MACH_BFIN, 1960 32, 32, & bfin_models[0], & bfin_imp_properties, 1961 bfin_init_cpu, 1962 bfin_prepare_run 1963}; 1964 1965const SIM_MACH * const bfin_sim_machs[] = 1966{ 1967 & bfin_mach, 1968 NULL 1969}; 1970 1971/* Device option parsing. */ 1972 1973static DECLARE_OPTION_HANDLER (bfin_mach_option_handler); 1974 1975enum { 1976 OPTION_MACH_SIREV = OPTION_START, 1977 OPTION_MACH_HW_BOARD_FILE, 1978}; 1979 1980static const OPTION bfin_mach_options[] = 1981{ 1982 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV }, 1983 '\0', "NUMBER", "Set CPU silicon revision", 1984 bfin_mach_option_handler, NULL }, 1985 1986 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE }, 1987 '\0', "FILE", "Add the supplemental devices listed in the file", 1988 bfin_mach_option_handler, NULL }, 1989 1990 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL } 1991}; 1992 1993static SIM_RC 1994bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt, 1995 char *arg, int is_command) 1996{ 1997 struct bfin_board_data *board = STATE_BOARD_DATA (sd); 1998 1999 switch (opt) 2000 { 2001 case OPTION_MACH_SIREV: 2002 board->sirev_valid = 1; 2003 /* Accept (and throw away) a leading "0." in the version. */ 2004 if (!strncmp (arg, "0.", 2)) 2005 arg += 2; 2006 board->sirev = atoi (arg); 2007 if (board->sirev > 0xf) 2008 { 2009 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg); 2010 return SIM_RC_FAIL; 2011 } 2012 return SIM_RC_OK; 2013 2014 case OPTION_MACH_HW_BOARD_FILE: 2015 board->hw_file = xstrdup (arg); 2016 return SIM_RC_OK; 2017 2018 default: 2019 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt); 2020 return SIM_RC_FAIL; 2021 } 2022} 2023 2024/* Provide a prototype to silence -Wmissing-prototypes. */ 2025extern MODULE_INIT_FN sim_install_bfin_mach; 2026 2027SIM_RC 2028sim_install_bfin_mach (SIM_DESC sd) 2029{ 2030 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 2031 return sim_add_option_table (sd, NULL, bfin_mach_options); 2032} 2033