1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 3 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 16 17/* This must come before any other includes. */ 18#include "defs.h" 19 20#include <string.h> 21 22#include "armdefs.h" 23#include "armemu.h" 24#include "dbg_rdi.h" 25 26/***************************************************************************\ 27* Definitions for the emulator architecture * 28\***************************************************************************/ 29 30void ARMul_EmulateInit (void); 31ARMul_State *ARMul_NewState (void); 32void ARMul_Reset (ARMul_State * state); 33ARMword ARMul_DoCycle (ARMul_State * state); 34unsigned ARMul_DoCoPro (ARMul_State * state); 35ARMword ARMul_DoProg (ARMul_State * state); 36ARMword ARMul_DoInstr (ARMul_State * state); 37void ARMul_Abort (ARMul_State * state, ARMword address); 38 39unsigned ARMul_MultTable[32] = 40 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 41 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 42}; 43ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 44char ARMul_BitList[256]; /* number of bits in a byte table */ 45 46/* The PC pipeline value depends on whether ARM 47 or Thumb instructions are being executed. */ 48ARMword isize; 49 50/***************************************************************************\ 51* Call this routine once to set up the emulator's tables. * 52\***************************************************************************/ 53 54void 55ARMul_EmulateInit (void) 56{ 57 unsigned long i, j; 58 59 for (i = 0; i < 4096; i++) 60 { /* the values of 12 bit dp rhs's */ 61 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); 62 } 63 64 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ 65 for (j = 1; j < 256; j <<= 1) 66 for (i = 0; i < 256; i++) 67 if ((i & j) > 0) 68 ARMul_BitList[i]++; 69 70 for (i = 0; i < 256; i++) 71 ARMul_BitList[i] *= 4; /* you always need 4 times these values */ 72 73} 74 75/***************************************************************************\ 76* Returns a new instantiation of the ARMulator's state * 77\***************************************************************************/ 78 79ARMul_State * 80ARMul_NewState (void) 81{ 82 ARMul_State *state; 83 unsigned i, j; 84 85 state = (ARMul_State *) malloc (sizeof (ARMul_State)); 86 memset (state, 0, sizeof (ARMul_State)); 87 88 state->Emulate = RUN; 89 for (i = 0; i < 16; i++) 90 { 91 state->Reg[i] = 0; 92 for (j = 0; j < 7; j++) 93 state->RegBank[j][i] = 0; 94 } 95 for (i = 0; i < 7; i++) 96 state->Spsr[i] = 0; 97 98 /* state->Mode = USER26MODE; */ 99 state->Mode = USER32MODE; 100 101 state->CallDebug = FALSE; 102 state->Debug = FALSE; 103 state->VectorCatch = 0; 104 state->Aborted = FALSE; 105 state->Reseted = FALSE; 106 state->Inted = 3; 107 state->LastInted = 3; 108 109 state->MemDataPtr = NULL; 110 state->MemInPtr = NULL; 111 state->MemOutPtr = NULL; 112 state->MemSparePtr = NULL; 113 state->MemSize = 0; 114 115 state->OSptr = NULL; 116 state->CommandLine = NULL; 117 118 state->CP14R0_CCD = -1; 119 state->LastTime = 0; 120 121 state->EventSet = 0; 122 state->Now = 0; 123 state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * 124 sizeof (struct EventNode 125 *)); 126 for (i = 0; i < EVENTLISTSIZE; i++) 127 *(state->EventPtr + i) = NULL; 128 129 state->prog32Sig = HIGH; 130 state->data32Sig = HIGH; 131 132 state->lateabtSig = LOW; 133 state->bigendSig = LOW; 134 135 state->is_v4 = LOW; 136 state->is_v5 = LOW; 137 state->is_v5e = LOW; 138 state->is_XScale = LOW; 139 state->is_iWMMXt = LOW; 140 state->is_v6 = LOW; 141 142 ARMul_Reset (state); 143 144 return state; 145} 146 147/***************************************************************************\ 148 Call this routine to set ARMulator to model certain processor properities 149\***************************************************************************/ 150 151void 152ARMul_SelectProcessor (ARMul_State * state, unsigned properties) 153{ 154 if (properties & ARM_Fix26_Prop) 155 { 156 state->prog32Sig = LOW; 157 state->data32Sig = LOW; 158 } 159 else 160 { 161 state->prog32Sig = HIGH; 162 state->data32Sig = HIGH; 163 } 164 165 state->lateabtSig = LOW; 166 167 state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; 168 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; 169 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; 170 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; 171 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; 172 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; 173 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; 174 175 /* Only initialse the coprocessor support once we 176 know what kind of chip we are dealing with. */ 177 ARMul_CoProInit (state); 178} 179 180/***************************************************************************\ 181* Call this routine to set up the initial machine state (or perform a RESET * 182\***************************************************************************/ 183 184void 185ARMul_Reset (ARMul_State * state) 186{ 187 state->NextInstr = 0; 188 189 if (state->prog32Sig) 190 { 191 state->Reg[15] = 0; 192 state->Cpsr = INTBITS | SVC32MODE; 193 state->Mode = SVC32MODE; 194 } 195 else 196 { 197 state->Reg[15] = R15INTBITS | SVC26MODE; 198 state->Cpsr = INTBITS | SVC26MODE; 199 state->Mode = SVC26MODE; 200 } 201 202 ARMul_CPSRAltered (state); 203 state->Bank = SVCBANK; 204 205 FLUSHPIPE; 206 207 state->EndCondition = 0; 208 209 state->Exception = FALSE; 210 state->NresetSig = HIGH; 211 state->NfiqSig = HIGH; 212 state->NirqSig = HIGH; 213 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 214 state->abortSig = LOW; 215 state->AbortAddr = 1; 216 217 state->NumInstrs = 0; 218 state->NumNcycles = 0; 219 state->NumScycles = 0; 220 state->NumIcycles = 0; 221 state->NumCcycles = 0; 222 state->NumFcycles = 0; 223#ifdef ASIM 224 (void) ARMul_MemoryInit (); 225 ARMul_OSInit (state); 226#endif 227} 228 229 230/***************************************************************************\ 231* Emulate the execution of an entire program. Start the correct emulator * 232* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 233* address of the last instruction that is executed. * 234\***************************************************************************/ 235 236ARMword 237ARMul_DoProg (ARMul_State * state) 238{ 239 ARMword pc = 0; 240 241 state->Emulate = RUN; 242 while (state->Emulate != STOP) 243 { 244 state->Emulate = RUN; 245 if (state->prog32Sig && ARMul_MODE32BIT) 246 pc = ARMul_Emulate32 (state); 247 else 248 pc = ARMul_Emulate26 (state); 249 } 250 return (pc); 251} 252 253/***************************************************************************\ 254* Emulate the execution of one instruction. Start the correct emulator * 255* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 256* address of the instruction that is executed. * 257\***************************************************************************/ 258 259ARMword 260ARMul_DoInstr (ARMul_State * state) 261{ 262 ARMword pc = 0; 263 264 state->Emulate = ONCE; 265 if (state->prog32Sig && ARMul_MODE32BIT) 266 pc = ARMul_Emulate32 (state); 267 else 268 pc = ARMul_Emulate26 (state); 269 270 return (pc); 271} 272 273/***************************************************************************\ 274* This routine causes an Abort to occur, including selecting the correct * 275* mode, register bank, and the saving of registers. Call with the * 276* appropriate vector's memory address (0,4,8 ....) * 277\***************************************************************************/ 278 279void 280ARMul_Abort (ARMul_State * state, ARMword vector) 281{ 282 ARMword temp; 283 int isize = INSN_SIZE; 284 int esize = (TFLAG ? 0 : 4); 285 int e2size = (TFLAG ? -4 : 0); 286 287 state->Aborted = FALSE; 288 289 if (state->prog32Sig) 290 if (ARMul_MODE26BIT) 291 temp = R15PC; 292 else 293 temp = state->Reg[15]; 294 else 295 temp = R15PC | ECC | ER15INT | EMODE; 296 297 switch (vector) 298 { 299 case ARMul_ResetV: /* RESET */ 300 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); 301 break; 302 case ARMul_UndefinedInstrV: /* Undefined Instruction */ 303 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); 304 break; 305 case ARMul_SWIV: /* Software Interrupt */ 306 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); 307 break; 308 case ARMul_PrefetchAbortV: /* Prefetch Abort */ 309 state->AbortAddr = 1; 310 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); 311 break; 312 case ARMul_DataAbortV: /* Data Abort */ 313 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); 314 break; 315 case ARMul_AddrExceptnV: /* Address Exception */ 316 SETABORT (IBIT, SVC26MODE, isize); 317 break; 318 case ARMul_IRQV: /* IRQ */ 319 if ( ! state->is_XScale 320 || ! state->CPRead[13] (state, 0, & temp) 321 || (temp & ARMul_CP13_R0_IRQ)) 322 SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); 323 break; 324 case ARMul_FIQV: /* FIQ */ 325 if ( ! state->is_XScale 326 || ! state->CPRead[13] (state, 0, & temp) 327 || (temp & ARMul_CP13_R0_FIQ)) 328 SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); 329 break; 330 } 331 if (ARMul_MODE32BIT) 332 ARMul_SetR15 (state, vector); 333 else 334 ARMul_SetR15 (state, R15CCINTMODE | vector); 335 336 if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) 337 { 338 /* No vector has been installed. Rather than simulating whatever 339 random bits might happen to be at address 0x20 onwards we elect 340 to stop. */ 341 switch (vector) 342 { 343 case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; 344 case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; 345 case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; 346 case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; 347 case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; 348 case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; 349 case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; 350 case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; 351 default: break; 352 } 353 state->Emulate = FALSE; 354 } 355} 356