1/*  armdefs.h -- ARMulator common definitions:  ARM6 Instruction Emulator.
2    Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4    This program is free software; you can redistribute it and/or modify
5    it under the terms of the GNU General Public License as published by
6    the Free Software Foundation; either version 3 of the License, or
7    (at your option) any later version.
8
9    This program is distributed in the hope that it will be useful,
10    but WITHOUT ANY WARRANTY; without even the implied warranty of
11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12    GNU General Public License for more details.
13
14    You should have received a copy of the GNU General Public License
15    along with this program; if not, see <http://www.gnu.org/licenses/>. */
16
17#include <stdio.h>
18#include <stdlib.h>
19#include <stdint.h>
20#include <ansidecl.h>
21
22#define FALSE 0
23#define TRUE 1
24#define LOW 0
25#define HIGH 1
26#define LOWHIGH 1
27#define HIGHLOW 2
28
29typedef uint32_t ARMword;
30typedef int32_t ARMsword;
31typedef uint64_t ARMdword;
32typedef int64_t ARMsdword;
33typedef struct ARMul_State ARMul_State;
34
35typedef unsigned ARMul_CPInits (ARMul_State * state);
36typedef unsigned ARMul_CPExits (ARMul_State * state);
37typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
38			     ARMword instr, ARMword value);
39typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
40			     ARMword instr, ARMword * value);
41typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
42			     ARMword instr, ARMword * value);
43typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
44			     ARMword instr, ARMword value);
45typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
46			     ARMword instr);
47typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
48				ARMword * value);
49typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
50				 ARMword value);
51
52typedef double ARMdval;	/* FIXME: Must be a 64-bit floating point type.  */
53typedef float  ARMfval;	/* FIXME: Must be a 32-bit floating point type.  */
54
55typedef union
56{
57  ARMword  uword[2];
58  ARMsword sword[2];
59  ARMfval  fval[2];
60  ARMdword dword;
61  ARMdval  dval;
62} ARM_VFP_reg;
63
64#define VFP_fval(N)  (state->VFP_Reg[(N)>> 1].fval[(N) & 1])
65#define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1])
66#define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1])
67
68#define VFP_dval(N)  (state->VFP_Reg[(N)].dval)
69#define VFP_dword(N) (state->VFP_Reg[(N)].dword)
70
71struct ARMul_State
72{
73  ARMword Emulate;		/* to start and stop emulation */
74  unsigned EndCondition;	/* reason for stopping */
75  ARMword Reg[16];		/* the current register file */
76  ARMword RegBank[7][16];	/* all the registers */
77  /* 40 bit accumulator.  We always keep this 64 bits wide,
78     and move only 40 bits out of it in an MRA insn.  */
79  ARMdword Accumulator;
80  ARMword Cpsr;			/* the current psr */
81  ARMword Spsr[7];		/* the exception psr's */
82  ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags;	/* dummy flags for speed */
83  ARMword SFlag;
84#ifdef MODET
85  ARMword TFlag;		/* Thumb state */
86#endif
87  ARMword Bank;			/* the current register bank */
88  ARMword Mode;			/* the current mode */
89  ARMword instr, pc, temp;	/* saved register state */
90  ARMword loaded, decoded;	/* saved pipeline state */
91  unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles;	/* emulated cycles used */
92  unsigned long NumInstrs;	/* the number of instructions executed */
93  unsigned NextInstr;
94  unsigned VectorCatch;		/* caught exception mask */
95  unsigned CallDebug;		/* set to call the debugger */
96  unsigned CanWatch;		/* set by memory interface if its willing to suffer the
97				   overhead of checking for watchpoints on each memory
98				   access */
99  unsigned MemReadDebug, MemWriteDebug;
100  unsigned long StopHandle;
101
102  unsigned char *MemDataPtr;	/* admin data */
103  unsigned char *MemInPtr;	/* the Data In bus */
104  unsigned char *MemOutPtr;	/* the Data Out bus (which you may not need */
105  unsigned char *MemSparePtr;	/* extra space */
106  ARMword MemSize;
107
108  unsigned char *OSptr;		/* OS Handle */
109  char *CommandLine;		/* Command Line from ARMsd */
110
111  ARMul_CPInits *CPInit[16];	/* coprocessor initialisers */
112  ARMul_CPExits *CPExit[16];	/* coprocessor finalisers */
113  ARMul_LDCs *LDC[16];		/* LDC instruction */
114  ARMul_STCs *STC[16];		/* STC instruction */
115  ARMul_MRCs *MRC[16];		/* MRC instruction */
116  ARMul_MCRs *MCR[16];		/* MCR instruction */
117  ARMul_CDPs *CDP[16];		/* CDP instruction */
118  ARMul_CPReads *CPRead[16];	/* Read CP register */
119  ARMul_CPWrites *CPWrite[16];	/* Write CP register */
120  unsigned char *CPData[16];	/* Coprocessor data */
121  unsigned char const *CPRegWords[16];	/* map of coprocessor register sizes */
122  unsigned long LastTime;	/* Value of last call to ARMul_Time() */
123  ARMword CP14R0_CCD;		/* used to count 64 clock cycles with CP14 R0 bit
124				   3 set */
125
126  unsigned EventSet;		/* the number of events in the queue */
127  unsigned long Now;		/* time to the nearest cycle */
128  struct EventNode **EventPtr;	/* the event list */
129
130  unsigned Exception;		/* enable the next four values */
131  unsigned Debug;		/* show instructions as they are executed */
132  unsigned NresetSig;		/* reset the processor */
133  unsigned NfiqSig;
134  unsigned NirqSig;
135
136  unsigned abortSig;
137  unsigned NtransSig;
138  unsigned bigendSig;
139  unsigned prog32Sig;
140  unsigned data32Sig;
141  unsigned lateabtSig;
142  ARMword Vector;		/* synthesize aborts in cycle modes */
143  ARMword Aborted;		/* sticky flag for aborts */
144  ARMword Reseted;		/* sticky flag for Reset */
145  ARMword Inted, LastInted;	/* sticky flags for interrupts */
146  ARMword Base;			/* extra hand for base writeback */
147  ARMword AbortAddr;		/* to keep track of Prefetch aborts */
148
149  const struct Dbg_HostosInterface *hostif;
150
151  unsigned is_v4;		/* Are we emulating a v4 architecture (or higher) ?  */
152  unsigned is_v5;		/* Are we emulating a v5 architecture ?  */
153  unsigned is_v5e;		/* Are we emulating a v5e architecture ?  */
154  unsigned is_v6;		/* Are we emulating a v6 architecture ?  */
155  unsigned is_XScale;		/* Are we emulating an XScale architecture ?  */
156  unsigned is_iWMMXt;		/* Are we emulating an iWMMXt co-processor ?  */
157  unsigned is_ep9312;		/* Are we emulating a Cirrus Maverick co-processor ?  */
158  unsigned verbose;		/* Print various messages like the banner */
159
160  ARM_VFP_reg  VFP_Reg[32];     /* Advanced SIMD registers.  */
161  ARMword      FPSCR;		/* Floating Point Status Register.  */
162};
163
164/***************************************************************************\
165*                        Properties of ARM we know about                    *
166\***************************************************************************/
167
168/* The bitflags */
169#define ARM_Fix26_Prop   0x01
170#define ARM_Nexec_Prop   0x02
171#define ARM_Debug_Prop   0x10
172#define ARM_Isync_Prop   ARM_Debug_Prop
173#define ARM_Lock_Prop    0x20
174#define ARM_v4_Prop      0x40
175#define ARM_v5_Prop      0x80
176#define ARM_v5e_Prop     0x100
177#define ARM_XScale_Prop  0x200
178#define ARM_ep9312_Prop  0x400
179#define ARM_iWMMXt_Prop  0x800
180#define ARM_v6_Prop      0x1000
181
182/***************************************************************************\
183*                   Macros to extract instruction fields                    *
184\***************************************************************************/
185
186#define BIT(n) ( (ARMword)(instr>>(n))&1)	/* bit n of instruction */
187#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) )	/* bits m to n of instr */
188#define TOPBITS(n) (instr >> (n))	/* bits 31 to n of instr */
189
190/***************************************************************************\
191*                      The hardware vector addresses                        *
192\***************************************************************************/
193
194#define ARMResetV 0L
195#define ARMUndefinedInstrV 4L
196#define ARMSWIV 8L
197#define ARMPrefetchAbortV 12L
198#define ARMDataAbortV 16L
199#define ARMAddrExceptnV 20L
200#define ARMIRQV 24L
201#define ARMFIQV 28L
202#define ARMErrorV 32L		/* This is an offset, not an address ! */
203
204#define ARMul_ResetV ARMResetV
205#define ARMul_UndefinedInstrV ARMUndefinedInstrV
206#define ARMul_SWIV ARMSWIV
207#define ARMul_PrefetchAbortV ARMPrefetchAbortV
208#define ARMul_DataAbortV ARMDataAbortV
209#define ARMul_AddrExceptnV ARMAddrExceptnV
210#define ARMul_IRQV ARMIRQV
211#define ARMul_FIQV ARMFIQV
212
213/***************************************************************************\
214*                          Mode and Bank Constants                          *
215\***************************************************************************/
216
217#define USER26MODE   0L
218#define FIQ26MODE    1L
219#define IRQ26MODE    2L
220#define SVC26MODE    3L
221#define USER32MODE  16L
222#define FIQ32MODE   17L
223#define IRQ32MODE   18L
224#define SVC32MODE   19L
225#define ABORT32MODE 23L
226#define UNDEF32MODE 27L
227#define SYSTEMMODE  31L
228
229#define ARM32BITMODE (state->Mode > 3)
230#define ARM26BITMODE (state->Mode <= 3)
231#define ARMMODE (state->Mode)
232#define ARMul_MODEBITS 0x1fL
233#define ARMul_MODE32BIT ARM32BITMODE
234#define ARMul_MODE26BIT ARM26BITMODE
235
236#define USERBANK 0
237#define FIQBANK 1
238#define IRQBANK 2
239#define SVCBANK 3
240#define ABORTBANK 4
241#define UNDEFBANK 5
242#define DUMMYBANK 6
243#define SYSTEMBANK USERBANK
244
245#define BANK_CAN_ACCESS_SPSR(bank)  \
246  ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
247
248/***************************************************************************\
249*                  Definitons of things in the emulator                     *
250\***************************************************************************/
251
252extern void ARMul_EmulateInit (void);
253extern ARMul_State *ARMul_NewState (void);
254extern void ARMul_Reset (ARMul_State * state);
255extern ARMword ARMul_DoProg (ARMul_State * state);
256extern ARMword ARMul_DoInstr (ARMul_State * state);
257
258/***************************************************************************\
259*                Definitons of things for event handling                    *
260\***************************************************************************/
261
262extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
263				 unsigned (*func) ());
264extern void ARMul_EnvokeEvent (ARMul_State * state);
265extern unsigned long ARMul_Time (ARMul_State * state);
266
267/***************************************************************************\
268*                          Useful support routines                          *
269\***************************************************************************/
270
271extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
272			     unsigned reg);
273extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
274			  ARMword value);
275extern ARMword ARMul_GetPC (ARMul_State * state);
276extern ARMword ARMul_GetNextPC (ARMul_State * state);
277extern void ARMul_SetPC (ARMul_State * state, ARMword value);
278extern ARMword ARMul_GetR15 (ARMul_State * state);
279extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
280
281extern ARMword ARMul_GetCPSR (ARMul_State * state);
282extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
283extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
284extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
285
286/***************************************************************************\
287*                  Definitons of things to handle aborts                    *
288\***************************************************************************/
289
290extern void ARMul_Abort (ARMul_State * state, ARMword address);
291#define ARMul_ABORTWORD 0xefffffff	/* SWI -1 */
292#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
293                                        state->AbortAddr = (address & ~3L)
294#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
295                                 state->Aborted = ARMul_DataAbortV ;
296#define ARMul_CLEARABORT state->abortSig = LOW
297
298/***************************************************************************\
299*              Definitons of things in the memory interface                 *
300\***************************************************************************/
301
302extern unsigned ARMul_MemoryInit (ARMul_State * state,
303				  unsigned long initmemsize);
304extern void ARMul_MemoryExit (ARMul_State * state);
305
306extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
307				 ARMword isize);
308extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
309				 ARMword isize);
310extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
311				  ARMword isize);
312
313extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
314extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
315extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
316extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
317
318extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
319			      ARMword data);
320extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
321			      ARMword data);
322extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
323				 ARMword data);
324extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
325			     ARMword data);
326
327extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
328			       ARMword data);
329extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
330			       ARMword data);
331
332extern void ARMul_Icycles (ARMul_State * state, unsigned number,
333			   ARMword address);
334extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
335			   ARMword address);
336
337extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
338extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
339extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
340extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
341			     ARMword data);
342extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
343			     ARMword data);
344extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
345			     ARMword data);
346
347extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
348				ARMword, ARMword, ARMword, ARMword, ARMword,
349				ARMword, ARMword, ARMword);
350
351/***************************************************************************\
352*            Definitons of things in the co-processor interface             *
353\***************************************************************************/
354
355#define ARMul_FIRST 0
356#define ARMul_TRANSFER 1
357#define ARMul_BUSY 2
358#define ARMul_DATA 3
359#define ARMul_INTERRUPT 4
360#define ARMul_DONE 0
361#define ARMul_CANT 1
362#define ARMul_INC 3
363
364#define ARMul_CP13_R0_FIQ	0x1
365#define ARMul_CP13_R0_IRQ	0x2
366#define ARMul_CP13_R8_PMUS	0x1
367
368#define ARMul_CP14_R0_ENABLE	0x0001
369#define ARMul_CP14_R0_CLKRST	0x0004
370#define ARMul_CP14_R0_CCD	0x0008
371#define ARMul_CP14_R0_INTEN0	0x0010
372#define ARMul_CP14_R0_INTEN1	0x0020
373#define ARMul_CP14_R0_INTEN2	0x0040
374#define ARMul_CP14_R0_FLAG0	0x0100
375#define ARMul_CP14_R0_FLAG1	0x0200
376#define ARMul_CP14_R0_FLAG2	0x0400
377#define ARMul_CP14_R10_MOE_IB	0x0004
378#define ARMul_CP14_R10_MOE_DB	0x0008
379#define ARMul_CP14_R10_MOE_BT	0x000c
380#define ARMul_CP15_R1_ENDIAN	0x0080
381#define ARMul_CP15_R1_ALIGN	0x0002
382#define ARMul_CP15_R5_X		0x0400
383#define ARMul_CP15_R5_ST_ALIGN	0x0001
384#define ARMul_CP15_R5_IMPRE	0x0406
385#define ARMul_CP15_R5_MMU_EXCPT	0x0400
386#define ARMul_CP15_DBCON_M	0x0100
387#define ARMul_CP15_DBCON_E1	0x000c
388#define ARMul_CP15_DBCON_E0	0x0003
389
390extern unsigned ARMul_CoProInit (ARMul_State * state);
391extern void ARMul_CoProExit (ARMul_State * state);
392extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
393			       ARMul_CPInits * init, ARMul_CPExits * exit,
394			       ARMul_LDCs * ldc, ARMul_STCs * stc,
395			       ARMul_MRCs * mrc, ARMul_MCRs * mcr,
396			       ARMul_CDPs * cdp,
397			       ARMul_CPReads * read, ARMul_CPWrites * write);
398extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
399extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
400				 int store);
401extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
402extern int XScale_debug_moe (ARMul_State * state, int moe);
403
404/***************************************************************************\
405*               Definitons of things in the host environment                *
406\***************************************************************************/
407
408extern unsigned ARMul_OSInit (ARMul_State * state);
409extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
410
411/***************************************************************************\
412*                            Host-dependent stuff                           *
413\***************************************************************************/
414
415extern void ARMul_UndefInstr      (ARMul_State *, ARMword);
416extern void ARMul_FixCPSR         (ARMul_State *, ARMword, ARMword);
417extern void ARMul_FixSPSR         (ARMul_State *, ARMword, ARMword);
418extern void ARMul_ConsolePrint    (ARMul_State *, const char *, ...)
419    ATTRIBUTE_PRINTF (2, 3);
420extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
421