1/* CPU data for cris. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright (C) 1996-2022 Free Software Foundation, Inc. 6 7This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#include "sysdep.h" 26#include <stdio.h> 27#include <stdarg.h> 28#include <stdlib.h> 29#include "ansidecl.h" 30#include "bfd.h" 31#include "symcat.h" 32#include "cris-desc.h" 33#include "cris-opc.h" 34#include "opintl.h" 35#include "libiberty.h" 36#include "xregex.h" 37 38/* Attributes. */ 39 40static const CGEN_ATTR_ENTRY bool_attr[] = 41{ 42 { "#f", 0 }, 43 { "#t", 1 }, 44 { 0, 0 } 45}; 46 47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 48{ 49 { "base", MACH_BASE }, 50 { "crisv0", MACH_CRISV0 }, 51 { "crisv3", MACH_CRISV3 }, 52 { "crisv8", MACH_CRISV8 }, 53 { "crisv10", MACH_CRISV10 }, 54 { "crisv32", MACH_CRISV32 }, 55 { "max", MACH_MAX }, 56 { 0, 0 } 57}; 58 59static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 60{ 61 { "cris", ISA_CRIS }, 62 { "max", ISA_MAX }, 63 { 0, 0 } 64}; 65 66const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] = 67{ 68 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 69 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 70 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 71 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 72 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 73 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 74 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 75 { 0, 0, 0 } 76}; 77 78const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] = 79{ 80 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 81 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 82 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 83 { "PC", &bool_attr[0], &bool_attr[0] }, 84 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 85 { 0, 0, 0 } 86}; 87 88const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] = 89{ 90 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 92 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 93 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 94 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 95 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 96 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 97 { "RELAX", &bool_attr[0], &bool_attr[0] }, 98 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 99 { 0, 0, 0 } 100}; 101 102const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] = 103{ 104 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 105 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 106 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 107 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 108 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 109 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 110 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 111 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 112 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 113 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 114 { "PBB", &bool_attr[0], &bool_attr[0] }, 115 { 0, 0, 0 } 116}; 117 118/* Instruction set variants. */ 119 120static const CGEN_ISA cris_cgen_isa_table[] = { 121 { "cris", 16, 16, 16, 48 }, 122 { 0, 0, 0, 0, 0 } 123}; 124 125/* Machine variants. */ 126 127static const CGEN_MACH cris_cgen_mach_table[] = { 128 { "crisv0", "cris", MACH_CRISV0, 0 }, 129 { "crisv3", "cris", MACH_CRISV3, 0 }, 130 { "crisv8", "cris", MACH_CRISV8, 0 }, 131 { "crisv10", "cris", MACH_CRISV10, 0 }, 132 { "crisv32", "crisv32", MACH_CRISV32, 0 }, 133 { 0, 0, 0, 0 } 134}; 135 136static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] = 137{ 138 { "PC", 15, {0, {{{0, 0}}}}, 0, 0 }, 139 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, 140 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, 141 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, 142 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, 143 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, 144 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, 145 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, 146 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, 147 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, 148 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, 149 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, 150 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, 151 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, 152 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, 153 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, 154 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } 155}; 156 157CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg = 158{ 159 & cris_cgen_opval_gr_names_pcreg_entries[0], 160 17, 161 0, 0, 0, 0, "" 162}; 163 164static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] = 165{ 166 { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, 167 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, 168 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, 169 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, 170 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, 171 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, 172 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, 173 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, 174 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, 175 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, 176 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, 177 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, 178 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, 179 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, 180 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, 181 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, 182 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } 183}; 184 185CGEN_KEYWORD cris_cgen_opval_gr_names_acr = 186{ 187 & cris_cgen_opval_gr_names_acr_entries[0], 188 17, 189 0, 0, 0, 0, "" 190}; 191 192static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] = 193{ 194 { "ACR", 15, {0, {{{0, 0}}}}, 0, 0 }, 195 { "SP", 14, {0, {{{0, 0}}}}, 0, 0 }, 196 { "R0", 0, {0, {{{0, 0}}}}, 0, 0 }, 197 { "R1", 1, {0, {{{0, 0}}}}, 0, 0 }, 198 { "R2", 2, {0, {{{0, 0}}}}, 0, 0 }, 199 { "R3", 3, {0, {{{0, 0}}}}, 0, 0 }, 200 { "R4", 4, {0, {{{0, 0}}}}, 0, 0 }, 201 { "R5", 5, {0, {{{0, 0}}}}, 0, 0 }, 202 { "R6", 6, {0, {{{0, 0}}}}, 0, 0 }, 203 { "R7", 7, {0, {{{0, 0}}}}, 0, 0 }, 204 { "R8", 8, {0, {{{0, 0}}}}, 0, 0 }, 205 { "R9", 9, {0, {{{0, 0}}}}, 0, 0 }, 206 { "R10", 10, {0, {{{0, 0}}}}, 0, 0 }, 207 { "R11", 11, {0, {{{0, 0}}}}, 0, 0 }, 208 { "R12", 12, {0, {{{0, 0}}}}, 0, 0 }, 209 { "R13", 13, {0, {{{0, 0}}}}, 0, 0 }, 210 { "R14", 14, {0, {{{0, 0}}}}, 0, 0 } 211}; 212 213CGEN_KEYWORD cris_cgen_opval_gr_names_v32 = 214{ 215 & cris_cgen_opval_gr_names_v32_entries[0], 216 17, 217 0, 0, 0, 0, "" 218}; 219 220static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] = 221{ 222 { "CCR", 5, {0, {{{0, 0}}}}, 0, 0 }, 223 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, 224 { "IBR", 9, {0, {{{0, 0}}}}, 0, 0 }, 225 { "IRP", 10, {0, {{{0, 0}}}}, 0, 0 }, 226 { "BAR", 12, {0, {{{0, 0}}}}, 0, 0 }, 227 { "DCCR", 13, {0, {{{0, 0}}}}, 0, 0 }, 228 { "BRP", 14, {0, {{{0, 0}}}}, 0, 0 }, 229 { "USP", 15, {0, {{{0, 0}}}}, 0, 0 }, 230 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, 231 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, 232 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, 233 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, 234 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, 235 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, 236 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, 237 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, 238 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, 239 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, 240 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, 241 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, 242 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, 243 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, 244 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, 245 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, 246 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } 247}; 248 249CGEN_KEYWORD cris_cgen_opval_p_names_v10 = 250{ 251 & cris_cgen_opval_p_names_v10_entries[0], 252 25, 253 0, 0, 0, 0, "" 254}; 255 256static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] = 257{ 258 { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, 259 { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, 260 { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, 261 { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, 262 { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, 263 { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, 264 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, 265 { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, 266 { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, 267 { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, 268 { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, 269 { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, 270 { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, 271 { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, 272 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, 273 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, 274 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, 275 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, 276 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, 277 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, 278 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, 279 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, 280 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, 281 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, 282 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, 283 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, 284 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, 285 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, 286 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, 287 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, 288 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } 289}; 290 291CGEN_KEYWORD cris_cgen_opval_p_names_v32 = 292{ 293 & cris_cgen_opval_p_names_v32_entries[0], 294 31, 295 0, 0, 0, 0, "" 296}; 297 298static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] = 299{ 300 { "BZ", 0, {0, {{{0, 0}}}}, 0, 0 }, 301 { "PID", 2, {0, {{{0, 0}}}}, 0, 0 }, 302 { "SRS", 3, {0, {{{0, 0}}}}, 0, 0 }, 303 { "WZ", 4, {0, {{{0, 0}}}}, 0, 0 }, 304 { "EXS", 5, {0, {{{0, 0}}}}, 0, 0 }, 305 { "EDA", 6, {0, {{{0, 0}}}}, 0, 0 }, 306 { "MOF", 7, {0, {{{0, 0}}}}, 0, 0 }, 307 { "DZ", 8, {0, {{{0, 0}}}}, 0, 0 }, 308 { "EBP", 9, {0, {{{0, 0}}}}, 0, 0 }, 309 { "ERP", 10, {0, {{{0, 0}}}}, 0, 0 }, 310 { "NRP", 12, {0, {{{0, 0}}}}, 0, 0 }, 311 { "CCS", 13, {0, {{{0, 0}}}}, 0, 0 }, 312 { "USP", 14, {0, {{{0, 0}}}}, 0, 0 }, 313 { "SPC", 15, {0, {{{0, 0}}}}, 0, 0 }, 314 { "VR", 1, {0, {{{0, 0}}}}, 0, 0 }, 315 { "SRP", 11, {0, {{{0, 0}}}}, 0, 0 }, 316 { "P0", 0, {0, {{{0, 0}}}}, 0, 0 }, 317 { "P1", 1, {0, {{{0, 0}}}}, 0, 0 }, 318 { "P2", 2, {0, {{{0, 0}}}}, 0, 0 }, 319 { "P3", 3, {0, {{{0, 0}}}}, 0, 0 }, 320 { "P4", 4, {0, {{{0, 0}}}}, 0, 0 }, 321 { "P5", 5, {0, {{{0, 0}}}}, 0, 0 }, 322 { "P6", 6, {0, {{{0, 0}}}}, 0, 0 }, 323 { "P7", 7, {0, {{{0, 0}}}}, 0, 0 }, 324 { "P8", 8, {0, {{{0, 0}}}}, 0, 0 }, 325 { "P9", 9, {0, {{{0, 0}}}}, 0, 0 }, 326 { "P10", 10, {0, {{{0, 0}}}}, 0, 0 }, 327 { "P11", 11, {0, {{{0, 0}}}}, 0, 0 }, 328 { "P12", 12, {0, {{{0, 0}}}}, 0, 0 }, 329 { "P13", 13, {0, {{{0, 0}}}}, 0, 0 }, 330 { "P14", 14, {0, {{{0, 0}}}}, 0, 0 } 331}; 332 333CGEN_KEYWORD cris_cgen_opval_p_names_v32_x = 334{ 335 & cris_cgen_opval_p_names_v32_x_entries[0], 336 31, 337 0, 0, 0, 0, "" 338}; 339 340static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] = 341{ 342 { "", 0, {0, {{{0, 0}}}}, 0, 0 }, 343 { "+", 1, {0, {{{0, 0}}}}, 0, 0 } 344}; 345 346CGEN_KEYWORD cris_cgen_opval_h_inc = 347{ 348 & cris_cgen_opval_h_inc_entries[0], 349 2, 350 0, 0, 0, 0, "" 351}; 352 353static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] = 354{ 355 { "cc", 0, {0, {{{0, 0}}}}, 0, 0 }, 356 { "cs", 1, {0, {{{0, 0}}}}, 0, 0 }, 357 { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, 358 { "eq", 3, {0, {{{0, 0}}}}, 0, 0 }, 359 { "vc", 4, {0, {{{0, 0}}}}, 0, 0 }, 360 { "vs", 5, {0, {{{0, 0}}}}, 0, 0 }, 361 { "pl", 6, {0, {{{0, 0}}}}, 0, 0 }, 362 { "mi", 7, {0, {{{0, 0}}}}, 0, 0 }, 363 { "ls", 8, {0, {{{0, 0}}}}, 0, 0 }, 364 { "hi", 9, {0, {{{0, 0}}}}, 0, 0 }, 365 { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, 366 { "lt", 11, {0, {{{0, 0}}}}, 0, 0 }, 367 { "gt", 12, {0, {{{0, 0}}}}, 0, 0 }, 368 { "le", 13, {0, {{{0, 0}}}}, 0, 0 }, 369 { "a", 14, {0, {{{0, 0}}}}, 0, 0 }, 370 { "wf", 15, {0, {{{0, 0}}}}, 0, 0 } 371}; 372 373CGEN_KEYWORD cris_cgen_opval_h_ccode = 374{ 375 & cris_cgen_opval_h_ccode_entries[0], 376 16, 377 0, 0, 0, 0, "" 378}; 379 380static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] = 381{ 382 { " ", 0, {0, {{{0, 0}}}}, 0, 0 }, 383 { "r", 1, {0, {{{0, 0}}}}, 0, 0 }, 384 { "b", 2, {0, {{{0, 0}}}}, 0, 0 }, 385 { "br", 3, {0, {{{0, 0}}}}, 0, 0 }, 386 { "w", 4, {0, {{{0, 0}}}}, 0, 0 }, 387 { "wr", 5, {0, {{{0, 0}}}}, 0, 0 }, 388 { "wb", 6, {0, {{{0, 0}}}}, 0, 0 }, 389 { "wbr", 7, {0, {{{0, 0}}}}, 0, 0 }, 390 { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, 391 { "nr", 9, {0, {{{0, 0}}}}, 0, 0 }, 392 { "nb", 10, {0, {{{0, 0}}}}, 0, 0 }, 393 { "nbr", 11, {0, {{{0, 0}}}}, 0, 0 }, 394 { "nw", 12, {0, {{{0, 0}}}}, 0, 0 }, 395 { "nwr", 13, {0, {{{0, 0}}}}, 0, 0 }, 396 { "nwb", 14, {0, {{{0, 0}}}}, 0, 0 }, 397 { "nwbr", 15, {0, {{{0, 0}}}}, 0, 0 } 398}; 399 400CGEN_KEYWORD cris_cgen_opval_h_swap = 401{ 402 & cris_cgen_opval_h_swap_entries[0], 403 16, 404 0, 0, 0, 0, "" 405}; 406 407static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] = 408{ 409 { "_", 0, {0, {{{0, 0}}}}, 0, 0 }, 410 { "c", 1, {0, {{{0, 0}}}}, 0, 0 }, 411 { "v", 2, {0, {{{0, 0}}}}, 0, 0 }, 412 { "cv", 3, {0, {{{0, 0}}}}, 0, 0 }, 413 { "z", 4, {0, {{{0, 0}}}}, 0, 0 }, 414 { "cz", 5, {0, {{{0, 0}}}}, 0, 0 }, 415 { "vz", 6, {0, {{{0, 0}}}}, 0, 0 }, 416 { "cvz", 7, {0, {{{0, 0}}}}, 0, 0 }, 417 { "n", 8, {0, {{{0, 0}}}}, 0, 0 }, 418 { "cn", 9, {0, {{{0, 0}}}}, 0, 0 }, 419 { "vn", 10, {0, {{{0, 0}}}}, 0, 0 }, 420 { "cvn", 11, {0, {{{0, 0}}}}, 0, 0 }, 421 { "zn", 12, {0, {{{0, 0}}}}, 0, 0 }, 422 { "czn", 13, {0, {{{0, 0}}}}, 0, 0 }, 423 { "vzn", 14, {0, {{{0, 0}}}}, 0, 0 }, 424 { "cvzn", 15, {0, {{{0, 0}}}}, 0, 0 }, 425 { "x", 16, {0, {{{0, 0}}}}, 0, 0 }, 426 { "cx", 17, {0, {{{0, 0}}}}, 0, 0 }, 427 { "vx", 18, {0, {{{0, 0}}}}, 0, 0 }, 428 { "cvx", 19, {0, {{{0, 0}}}}, 0, 0 }, 429 { "zx", 20, {0, {{{0, 0}}}}, 0, 0 }, 430 { "czx", 21, {0, {{{0, 0}}}}, 0, 0 }, 431 { "vzx", 22, {0, {{{0, 0}}}}, 0, 0 }, 432 { "cvzx", 23, {0, {{{0, 0}}}}, 0, 0 }, 433 { "nx", 24, {0, {{{0, 0}}}}, 0, 0 }, 434 { "cnx", 25, {0, {{{0, 0}}}}, 0, 0 }, 435 { "vnx", 26, {0, {{{0, 0}}}}, 0, 0 }, 436 { "cvnx", 27, {0, {{{0, 0}}}}, 0, 0 }, 437 { "znx", 28, {0, {{{0, 0}}}}, 0, 0 }, 438 { "cznx", 29, {0, {{{0, 0}}}}, 0, 0 }, 439 { "vznx", 30, {0, {{{0, 0}}}}, 0, 0 }, 440 { "cvznx", 31, {0, {{{0, 0}}}}, 0, 0 }, 441 { "i", 32, {0, {{{0, 0}}}}, 0, 0 }, 442 { "ci", 33, {0, {{{0, 0}}}}, 0, 0 }, 443 { "vi", 34, {0, {{{0, 0}}}}, 0, 0 }, 444 { "cvi", 35, {0, {{{0, 0}}}}, 0, 0 }, 445 { "zi", 36, {0, {{{0, 0}}}}, 0, 0 }, 446 { "czi", 37, {0, {{{0, 0}}}}, 0, 0 }, 447 { "vzi", 38, {0, {{{0, 0}}}}, 0, 0 }, 448 { "cvzi", 39, {0, {{{0, 0}}}}, 0, 0 }, 449 { "ni", 40, {0, {{{0, 0}}}}, 0, 0 }, 450 { "cni", 41, {0, {{{0, 0}}}}, 0, 0 }, 451 { "vni", 42, {0, {{{0, 0}}}}, 0, 0 }, 452 { "cvni", 43, {0, {{{0, 0}}}}, 0, 0 }, 453 { "zni", 44, {0, {{{0, 0}}}}, 0, 0 }, 454 { "czni", 45, {0, {{{0, 0}}}}, 0, 0 }, 455 { "vzni", 46, {0, {{{0, 0}}}}, 0, 0 }, 456 { "cvzni", 47, {0, {{{0, 0}}}}, 0, 0 }, 457 { "xi", 48, {0, {{{0, 0}}}}, 0, 0 }, 458 { "cxi", 49, {0, {{{0, 0}}}}, 0, 0 }, 459 { "vxi", 50, {0, {{{0, 0}}}}, 0, 0 }, 460 { "cvxi", 51, {0, {{{0, 0}}}}, 0, 0 }, 461 { "zxi", 52, {0, {{{0, 0}}}}, 0, 0 }, 462 { "czxi", 53, {0, {{{0, 0}}}}, 0, 0 }, 463 { "vzxi", 54, {0, {{{0, 0}}}}, 0, 0 }, 464 { "cvzxi", 55, {0, {{{0, 0}}}}, 0, 0 }, 465 { "nxi", 56, {0, {{{0, 0}}}}, 0, 0 }, 466 { "cnxi", 57, {0, {{{0, 0}}}}, 0, 0 }, 467 { "vnxi", 58, {0, {{{0, 0}}}}, 0, 0 }, 468 { "cvnxi", 59, {0, {{{0, 0}}}}, 0, 0 }, 469 { "znxi", 60, {0, {{{0, 0}}}}, 0, 0 }, 470 { "cznxi", 61, {0, {{{0, 0}}}}, 0, 0 }, 471 { "vznxi", 62, {0, {{{0, 0}}}}, 0, 0 }, 472 { "cvznxi", 63, {0, {{{0, 0}}}}, 0, 0 }, 473 { "u", 64, {0, {{{0, 0}}}}, 0, 0 }, 474 { "cu", 65, {0, {{{0, 0}}}}, 0, 0 }, 475 { "vu", 66, {0, {{{0, 0}}}}, 0, 0 }, 476 { "cvu", 67, {0, {{{0, 0}}}}, 0, 0 }, 477 { "zu", 68, {0, {{{0, 0}}}}, 0, 0 }, 478 { "czu", 69, {0, {{{0, 0}}}}, 0, 0 }, 479 { "vzu", 70, {0, {{{0, 0}}}}, 0, 0 }, 480 { "cvzu", 71, {0, {{{0, 0}}}}, 0, 0 }, 481 { "nu", 72, {0, {{{0, 0}}}}, 0, 0 }, 482 { "cnu", 73, {0, {{{0, 0}}}}, 0, 0 }, 483 { "vnu", 74, {0, {{{0, 0}}}}, 0, 0 }, 484 { "cvnu", 75, {0, {{{0, 0}}}}, 0, 0 }, 485 { "znu", 76, {0, {{{0, 0}}}}, 0, 0 }, 486 { "cznu", 77, {0, {{{0, 0}}}}, 0, 0 }, 487 { "vznu", 78, {0, {{{0, 0}}}}, 0, 0 }, 488 { "cvznu", 79, {0, {{{0, 0}}}}, 0, 0 }, 489 { "xu", 80, {0, {{{0, 0}}}}, 0, 0 }, 490 { "cxu", 81, {0, {{{0, 0}}}}, 0, 0 }, 491 { "vxu", 82, {0, {{{0, 0}}}}, 0, 0 }, 492 { "cvxu", 83, {0, {{{0, 0}}}}, 0, 0 }, 493 { "zxu", 84, {0, {{{0, 0}}}}, 0, 0 }, 494 { "czxu", 85, {0, {{{0, 0}}}}, 0, 0 }, 495 { "vzxu", 86, {0, {{{0, 0}}}}, 0, 0 }, 496 { "cvzxu", 87, {0, {{{0, 0}}}}, 0, 0 }, 497 { "nxu", 88, {0, {{{0, 0}}}}, 0, 0 }, 498 { "cnxu", 89, {0, {{{0, 0}}}}, 0, 0 }, 499 { "vnxu", 90, {0, {{{0, 0}}}}, 0, 0 }, 500 { "cvnxu", 91, {0, {{{0, 0}}}}, 0, 0 }, 501 { "znxu", 92, {0, {{{0, 0}}}}, 0, 0 }, 502 { "cznxu", 93, {0, {{{0, 0}}}}, 0, 0 }, 503 { "vznxu", 94, {0, {{{0, 0}}}}, 0, 0 }, 504 { "cvznxu", 95, {0, {{{0, 0}}}}, 0, 0 }, 505 { "iu", 96, {0, {{{0, 0}}}}, 0, 0 }, 506 { "ciu", 97, {0, {{{0, 0}}}}, 0, 0 }, 507 { "viu", 98, {0, {{{0, 0}}}}, 0, 0 }, 508 { "cviu", 99, {0, {{{0, 0}}}}, 0, 0 }, 509 { "ziu", 100, {0, {{{0, 0}}}}, 0, 0 }, 510 { "cziu", 101, {0, {{{0, 0}}}}, 0, 0 }, 511 { "vziu", 102, {0, {{{0, 0}}}}, 0, 0 }, 512 { "cvziu", 103, {0, {{{0, 0}}}}, 0, 0 }, 513 { "niu", 104, {0, {{{0, 0}}}}, 0, 0 }, 514 { "cniu", 105, {0, {{{0, 0}}}}, 0, 0 }, 515 { "vniu", 106, {0, {{{0, 0}}}}, 0, 0 }, 516 { "cvniu", 107, {0, {{{0, 0}}}}, 0, 0 }, 517 { "zniu", 108, {0, {{{0, 0}}}}, 0, 0 }, 518 { "czniu", 109, {0, {{{0, 0}}}}, 0, 0 }, 519 { "vzniu", 110, {0, {{{0, 0}}}}, 0, 0 }, 520 { "cvzniu", 111, {0, {{{0, 0}}}}, 0, 0 }, 521 { "xiu", 112, {0, {{{0, 0}}}}, 0, 0 }, 522 { "cxiu", 113, {0, {{{0, 0}}}}, 0, 0 }, 523 { "vxiu", 114, {0, {{{0, 0}}}}, 0, 0 }, 524 { "cvxiu", 115, {0, {{{0, 0}}}}, 0, 0 }, 525 { "zxiu", 116, {0, {{{0, 0}}}}, 0, 0 }, 526 { "czxiu", 117, {0, {{{0, 0}}}}, 0, 0 }, 527 { "vzxiu", 118, {0, {{{0, 0}}}}, 0, 0 }, 528 { "cvzxiu", 119, {0, {{{0, 0}}}}, 0, 0 }, 529 { "nxiu", 120, {0, {{{0, 0}}}}, 0, 0 }, 530 { "cnxiu", 121, {0, {{{0, 0}}}}, 0, 0 }, 531 { "vnxiu", 122, {0, {{{0, 0}}}}, 0, 0 }, 532 { "cvnxiu", 123, {0, {{{0, 0}}}}, 0, 0 }, 533 { "znxiu", 124, {0, {{{0, 0}}}}, 0, 0 }, 534 { "cznxiu", 125, {0, {{{0, 0}}}}, 0, 0 }, 535 { "vznxiu", 126, {0, {{{0, 0}}}}, 0, 0 }, 536 { "cvznxiu", 127, {0, {{{0, 0}}}}, 0, 0 }, 537 { "p", 128, {0, {{{0, 0}}}}, 0, 0 }, 538 { "cp", 129, {0, {{{0, 0}}}}, 0, 0 }, 539 { "vp", 130, {0, {{{0, 0}}}}, 0, 0 }, 540 { "cvp", 131, {0, {{{0, 0}}}}, 0, 0 }, 541 { "zp", 132, {0, {{{0, 0}}}}, 0, 0 }, 542 { "czp", 133, {0, {{{0, 0}}}}, 0, 0 }, 543 { "vzp", 134, {0, {{{0, 0}}}}, 0, 0 }, 544 { "cvzp", 135, {0, {{{0, 0}}}}, 0, 0 }, 545 { "np", 136, {0, {{{0, 0}}}}, 0, 0 }, 546 { "cnp", 137, {0, {{{0, 0}}}}, 0, 0 }, 547 { "vnp", 138, {0, {{{0, 0}}}}, 0, 0 }, 548 { "cvnp", 139, {0, {{{0, 0}}}}, 0, 0 }, 549 { "znp", 140, {0, {{{0, 0}}}}, 0, 0 }, 550 { "cznp", 141, {0, {{{0, 0}}}}, 0, 0 }, 551 { "vznp", 142, {0, {{{0, 0}}}}, 0, 0 }, 552 { "cvznp", 143, {0, {{{0, 0}}}}, 0, 0 }, 553 { "xp", 144, {0, {{{0, 0}}}}, 0, 0 }, 554 { "cxp", 145, {0, {{{0, 0}}}}, 0, 0 }, 555 { "vxp", 146, {0, {{{0, 0}}}}, 0, 0 }, 556 { "cvxp", 147, {0, {{{0, 0}}}}, 0, 0 }, 557 { "zxp", 148, {0, {{{0, 0}}}}, 0, 0 }, 558 { "czxp", 149, {0, {{{0, 0}}}}, 0, 0 }, 559 { "vzxp", 150, {0, {{{0, 0}}}}, 0, 0 }, 560 { "cvzxp", 151, {0, {{{0, 0}}}}, 0, 0 }, 561 { "nxp", 152, {0, {{{0, 0}}}}, 0, 0 }, 562 { "cnxp", 153, {0, {{{0, 0}}}}, 0, 0 }, 563 { "vnxp", 154, {0, {{{0, 0}}}}, 0, 0 }, 564 { "cvnxp", 155, {0, {{{0, 0}}}}, 0, 0 }, 565 { "znxp", 156, {0, {{{0, 0}}}}, 0, 0 }, 566 { "cznxp", 157, {0, {{{0, 0}}}}, 0, 0 }, 567 { "vznxp", 158, {0, {{{0, 0}}}}, 0, 0 }, 568 { "cvznxp", 159, {0, {{{0, 0}}}}, 0, 0 }, 569 { "ip", 160, {0, {{{0, 0}}}}, 0, 0 }, 570 { "cip", 161, {0, {{{0, 0}}}}, 0, 0 }, 571 { "vip", 162, {0, {{{0, 0}}}}, 0, 0 }, 572 { "cvip", 163, {0, {{{0, 0}}}}, 0, 0 }, 573 { "zip", 164, {0, {{{0, 0}}}}, 0, 0 }, 574 { "czip", 165, {0, {{{0, 0}}}}, 0, 0 }, 575 { "vzip", 166, {0, {{{0, 0}}}}, 0, 0 }, 576 { "cvzip", 167, {0, {{{0, 0}}}}, 0, 0 }, 577 { "nip", 168, {0, {{{0, 0}}}}, 0, 0 }, 578 { "cnip", 169, {0, {{{0, 0}}}}, 0, 0 }, 579 { "vnip", 170, {0, {{{0, 0}}}}, 0, 0 }, 580 { "cvnip", 171, {0, {{{0, 0}}}}, 0, 0 }, 581 { "znip", 172, {0, {{{0, 0}}}}, 0, 0 }, 582 { "cznip", 173, {0, {{{0, 0}}}}, 0, 0 }, 583 { "vznip", 174, {0, {{{0, 0}}}}, 0, 0 }, 584 { "cvznip", 175, {0, {{{0, 0}}}}, 0, 0 }, 585 { "xip", 176, {0, {{{0, 0}}}}, 0, 0 }, 586 { "cxip", 177, {0, {{{0, 0}}}}, 0, 0 }, 587 { "vxip", 178, {0, {{{0, 0}}}}, 0, 0 }, 588 { "cvxip", 179, {0, {{{0, 0}}}}, 0, 0 }, 589 { "zxip", 180, {0, {{{0, 0}}}}, 0, 0 }, 590 { "czxip", 181, {0, {{{0, 0}}}}, 0, 0 }, 591 { "vzxip", 182, {0, {{{0, 0}}}}, 0, 0 }, 592 { "cvzxip", 183, {0, {{{0, 0}}}}, 0, 0 }, 593 { "nxip", 184, {0, {{{0, 0}}}}, 0, 0 }, 594 { "cnxip", 185, {0, {{{0, 0}}}}, 0, 0 }, 595 { "vnxip", 186, {0, {{{0, 0}}}}, 0, 0 }, 596 { "cvnxip", 187, {0, {{{0, 0}}}}, 0, 0 }, 597 { "znxip", 188, {0, {{{0, 0}}}}, 0, 0 }, 598 { "cznxip", 189, {0, {{{0, 0}}}}, 0, 0 }, 599 { "vznxip", 190, {0, {{{0, 0}}}}, 0, 0 }, 600 { "cvznxip", 191, {0, {{{0, 0}}}}, 0, 0 }, 601 { "up", 192, {0, {{{0, 0}}}}, 0, 0 }, 602 { "cup", 193, {0, {{{0, 0}}}}, 0, 0 }, 603 { "vup", 194, {0, {{{0, 0}}}}, 0, 0 }, 604 { "cvup", 195, {0, {{{0, 0}}}}, 0, 0 }, 605 { "zup", 196, {0, {{{0, 0}}}}, 0, 0 }, 606 { "czup", 197, {0, {{{0, 0}}}}, 0, 0 }, 607 { "vzup", 198, {0, {{{0, 0}}}}, 0, 0 }, 608 { "cvzup", 199, {0, {{{0, 0}}}}, 0, 0 }, 609 { "nup", 200, {0, {{{0, 0}}}}, 0, 0 }, 610 { "cnup", 201, {0, {{{0, 0}}}}, 0, 0 }, 611 { "vnup", 202, {0, {{{0, 0}}}}, 0, 0 }, 612 { "cvnup", 203, {0, {{{0, 0}}}}, 0, 0 }, 613 { "znup", 204, {0, {{{0, 0}}}}, 0, 0 }, 614 { "cznup", 205, {0, {{{0, 0}}}}, 0, 0 }, 615 { "vznup", 206, {0, {{{0, 0}}}}, 0, 0 }, 616 { "cvznup", 207, {0, {{{0, 0}}}}, 0, 0 }, 617 { "xup", 208, {0, {{{0, 0}}}}, 0, 0 }, 618 { "cxup", 209, {0, {{{0, 0}}}}, 0, 0 }, 619 { "vxup", 210, {0, {{{0, 0}}}}, 0, 0 }, 620 { "cvxup", 211, {0, {{{0, 0}}}}, 0, 0 }, 621 { "zxup", 212, {0, {{{0, 0}}}}, 0, 0 }, 622 { "czxup", 213, {0, {{{0, 0}}}}, 0, 0 }, 623 { "vzxup", 214, {0, {{{0, 0}}}}, 0, 0 }, 624 { "cvzxup", 215, {0, {{{0, 0}}}}, 0, 0 }, 625 { "nxup", 216, {0, {{{0, 0}}}}, 0, 0 }, 626 { "cnxup", 217, {0, {{{0, 0}}}}, 0, 0 }, 627 { "vnxup", 218, {0, {{{0, 0}}}}, 0, 0 }, 628 { "cvnxup", 219, {0, {{{0, 0}}}}, 0, 0 }, 629 { "znxup", 220, {0, {{{0, 0}}}}, 0, 0 }, 630 { "cznxup", 221, {0, {{{0, 0}}}}, 0, 0 }, 631 { "vznxup", 222, {0, {{{0, 0}}}}, 0, 0 }, 632 { "cvznxup", 223, {0, {{{0, 0}}}}, 0, 0 }, 633 { "iup", 224, {0, {{{0, 0}}}}, 0, 0 }, 634 { "ciup", 225, {0, {{{0, 0}}}}, 0, 0 }, 635 { "viup", 226, {0, {{{0, 0}}}}, 0, 0 }, 636 { "cviup", 227, {0, {{{0, 0}}}}, 0, 0 }, 637 { "ziup", 228, {0, {{{0, 0}}}}, 0, 0 }, 638 { "cziup", 229, {0, {{{0, 0}}}}, 0, 0 }, 639 { "vziup", 230, {0, {{{0, 0}}}}, 0, 0 }, 640 { "cvziup", 231, {0, {{{0, 0}}}}, 0, 0 }, 641 { "niup", 232, {0, {{{0, 0}}}}, 0, 0 }, 642 { "cniup", 233, {0, {{{0, 0}}}}, 0, 0 }, 643 { "vniup", 234, {0, {{{0, 0}}}}, 0, 0 }, 644 { "cvniup", 235, {0, {{{0, 0}}}}, 0, 0 }, 645 { "zniup", 236, {0, {{{0, 0}}}}, 0, 0 }, 646 { "czniup", 237, {0, {{{0, 0}}}}, 0, 0 }, 647 { "vzniup", 238, {0, {{{0, 0}}}}, 0, 0 }, 648 { "cvzniup", 239, {0, {{{0, 0}}}}, 0, 0 }, 649 { "xiup", 240, {0, {{{0, 0}}}}, 0, 0 }, 650 { "cxiup", 241, {0, {{{0, 0}}}}, 0, 0 }, 651 { "vxiup", 242, {0, {{{0, 0}}}}, 0, 0 }, 652 { "cvxiup", 243, {0, {{{0, 0}}}}, 0, 0 }, 653 { "zxiup", 244, {0, {{{0, 0}}}}, 0, 0 }, 654 { "czxiup", 245, {0, {{{0, 0}}}}, 0, 0 }, 655 { "vzxiup", 246, {0, {{{0, 0}}}}, 0, 0 }, 656 { "cvzxiup", 247, {0, {{{0, 0}}}}, 0, 0 }, 657 { "nxiup", 248, {0, {{{0, 0}}}}, 0, 0 }, 658 { "cnxiup", 249, {0, {{{0, 0}}}}, 0, 0 }, 659 { "vnxiup", 250, {0, {{{0, 0}}}}, 0, 0 }, 660 { "cvnxiup", 251, {0, {{{0, 0}}}}, 0, 0 }, 661 { "znxiup", 252, {0, {{{0, 0}}}}, 0, 0 }, 662 { "cznxiup", 253, {0, {{{0, 0}}}}, 0, 0 }, 663 { "vznxiup", 254, {0, {{{0, 0}}}}, 0, 0 }, 664 { "cvznxiup", 255, {0, {{{0, 0}}}}, 0, 0 } 665}; 666 667CGEN_KEYWORD cris_cgen_opval_h_flagbits = 668{ 669 & cris_cgen_opval_h_flagbits_entries[0], 670 256, 671 0, 0, 0, 0, "" 672}; 673 674static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] = 675{ 676 { "S0", 0, {0, {{{0, 0}}}}, 0, 0 }, 677 { "S1", 1, {0, {{{0, 0}}}}, 0, 0 }, 678 { "S2", 2, {0, {{{0, 0}}}}, 0, 0 }, 679 { "S3", 3, {0, {{{0, 0}}}}, 0, 0 }, 680 { "S4", 4, {0, {{{0, 0}}}}, 0, 0 }, 681 { "S5", 5, {0, {{{0, 0}}}}, 0, 0 }, 682 { "S6", 6, {0, {{{0, 0}}}}, 0, 0 }, 683 { "S7", 7, {0, {{{0, 0}}}}, 0, 0 }, 684 { "S8", 8, {0, {{{0, 0}}}}, 0, 0 }, 685 { "S9", 9, {0, {{{0, 0}}}}, 0, 0 }, 686 { "S10", 10, {0, {{{0, 0}}}}, 0, 0 }, 687 { "S11", 11, {0, {{{0, 0}}}}, 0, 0 }, 688 { "S12", 12, {0, {{{0, 0}}}}, 0, 0 }, 689 { "S13", 13, {0, {{{0, 0}}}}, 0, 0 }, 690 { "S14", 14, {0, {{{0, 0}}}}, 0, 0 }, 691 { "S15", 15, {0, {{{0, 0}}}}, 0, 0 } 692}; 693 694CGEN_KEYWORD cris_cgen_opval_h_supr = 695{ 696 & cris_cgen_opval_h_supr_entries[0], 697 16, 698 0, 0, 0, 0, "" 699}; 700 701 702/* The hardware table. */ 703 704#define A(a) (1 << CGEN_HW_##a) 705 706const CGEN_HW_ENTRY cris_cgen_hw_table[] = 707{ 708 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 709 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 710 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 711 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 712 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 713 { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 714 { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 715 { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 716 { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 717 { "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 718 { "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 719 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 720 { "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 721 { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 722 { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 723 { "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 724 { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 725 { "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 726 { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 727 { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } }, 728 { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } }, 729 { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } }, 730 { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } }, 731 { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 732 { "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 733 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 734 { "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 735 { "h-cbit-move-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 736 { "h-cbit-move-pre-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 737 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 738 { "h-vbit-move", HW_H_VBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 739 { "h-vbit-move-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 740 { "h-vbit-move-pre-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 741 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 742 { "h-zbit-move", HW_H_ZBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 743 { "h-zbit-move-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 744 { "h-zbit-move-pre-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 745 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 746 { "h-nbit-move", HW_H_NBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 747 { "h-nbit-move-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 748 { "h-nbit-move-pre-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 749 { "h-xbit", HW_H_XBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 750 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 751 { "h-ibit-pre-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 752 { "h-pbit", HW_H_PBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } }, 753 { "h-rbit", HW_H_RBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 754 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 755 { "h-ubit-pre-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV10), 0 } } } } }, 756 { "h-gbit", HW_H_GBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 757 { "h-kernel-sp", HW_H_KERNEL_SP, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 758 { "h-ubit-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 759 { "h-ibit-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 760 { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 761 { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 762 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 763 { "h-insn-prefixed-p", HW_H_INSN_PREFIXED_P, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 764 { "h-insn-prefixed-p-pre-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 765 { "h-insn-prefixed-p-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 766 { "h-prefixreg-pre-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } }, 767 { "h-prefixreg-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } }, 768 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 769}; 770 771#undef A 772 773 774/* The instruction field table. */ 775 776#define A(a) (1 << CGEN_IFLD_##a) 777 778const CGEN_IFLD cris_cgen_ifld_table[] = 779{ 780 { CRIS_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 781 { CRIS_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 782 { CRIS_F_OPERAND1, "f-operand1", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 783 { CRIS_F_SIZE, "f-size", 0, 16, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 784 { CRIS_F_OPCODE, "f-opcode", 0, 16, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 785 { CRIS_F_MODE, "f-mode", 0, 16, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 786 { CRIS_F_OPERAND2, "f-operand2", 0, 16, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 787 { CRIS_F_MEMMODE, "f-memmode", 0, 16, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 788 { CRIS_F_MEMBIT, "f-membit", 0, 16, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 789 { CRIS_F_B5, "f-b5", 0, 16, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 790 { CRIS_F_OPCODE_HI, "f-opcode-hi", 0, 16, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 791 { CRIS_F_DSTSRC, "f-dstsrc", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 792 { CRIS_F_U6, "f-u6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 793 { CRIS_F_S6, "f-s6", 0, 16, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 794 { CRIS_F_U5, "f-u5", 0, 16, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 795 { CRIS_F_U4, "f-u4", 0, 16, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 796 { CRIS_F_S8, "f-s8", 0, 16, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 797 { CRIS_F_DISP9_HI, "f-disp9-hi", 0, 16, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 798 { CRIS_F_DISP9_LO, "f-disp9-lo", 0, 16, 7, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 799 { CRIS_F_DISP9, "f-disp9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 800 { CRIS_F_QO, "f-qo", 0, 16, 3, 4, { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } }, 801 { CRIS_F_INDIR_PC__BYTE, "f-indir-pc+-byte", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 802 { CRIS_F_INDIR_PC__WORD, "f-indir-pc+-word", 16, 16, 15, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 803 { CRIS_F_INDIR_PC__WORD_PCREL, "f-indir-pc+-word-pcrel", 16, 16, 15, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 804 { CRIS_F_INDIR_PC__DWORD, "f-indir-pc+-dword", 16, 32, 31, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 805 { CRIS_F_INDIR_PC__DWORD_PCREL, "f-indir-pc+-dword-pcrel", 16, 32, 31, 32, { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } }, 806 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 807}; 808 809#undef A 810 811 812 813/* multi ifield declarations */ 814 815const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD []; 816const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD []; 817 818 819/* multi ifield definitions */ 820 821const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] = 822{ 823 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 824 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } }, 825 { 0, { 0 } } 826}; 827const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] = 828{ 829 { 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } }, 830 { 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } }, 831 { 0, { 0 } } 832}; 833 834/* The operand table. */ 835 836#define A(a) (1 << CGEN_OPERAND_##a) 837#define OPERAND(op) CRIS_OPERAND_##op 838 839const CGEN_OPERAND cris_cgen_operand_table[] = 840{ 841/* pc: program counter */ 842 { "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0, 843 { 0, { &cris_cgen_ifld_table[CRIS_F_NIL] } }, 844 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 845/* cbit: */ 846 { "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0, 847 { 0, { 0 } }, 848 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 849/* cbit-move: cbit for pre-V32, nothing for newer */ 850 { "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0, 851 { 0, { 0 } }, 852 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 853/* vbit: */ 854 { "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0, 855 { 0, { 0 } }, 856 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 857/* vbit-move: vbit for pre-V32, nothing for newer */ 858 { "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0, 859 { 0, { 0 } }, 860 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 861/* zbit: */ 862 { "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, 863 { 0, { 0 } }, 864 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 865/* zbit-move: zbit for pre-V32, nothing for newer */ 866 { "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0, 867 { 0, { 0 } }, 868 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 869/* nbit: */ 870 { "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0, 871 { 0, { 0 } }, 872 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 873/* nbit-move: nbit for pre-V32, nothing for newer */ 874 { "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0, 875 { 0, { 0 } }, 876 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 877/* xbit: */ 878 { "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0, 879 { 0, { 0 } }, 880 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 881/* ibit: */ 882 { "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0, 883 { 0, { 0 } }, 884 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 885/* ubit: */ 886 { "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0, 887 { 0, { 0 } }, 888 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } }, 889/* pbit: */ 890 { "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0, 891 { 0, { 0 } }, 892 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } }, 893/* rbit: carry bit for MCP+restore-P flag bit */ 894 { "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0, 895 { 0, { 0 } }, 896 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } }, 897/* sbit: */ 898 { "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0, 899 { 0, { 0 } }, 900 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } }, 901/* mbit: */ 902 { "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0, 903 { 0, { 0 } }, 904 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } }, 905/* qbit: */ 906 { "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0, 907 { 0, { 0 } }, 908 { 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } }, 909/* prefix-set: Instruction-prefixed flag */ 910 { "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0, 911 { 0, { 0 } }, 912 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 913/* prefixreg: Prefix address */ 914 { "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0, 915 { 0, { 0 } }, 916 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 917/* Rs: Source general register */ 918 { "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4, 919 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } }, 920 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 921/* inc: Incrementness of indirect operand */ 922 { "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1, 923 { 0, { &cris_cgen_ifld_table[CRIS_F_MEMMODE] } }, 924 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 925/* Ps: Source special register */ 926 { "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4, 927 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 928 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 929/* Ss: Source support register */ 930 { "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4, 931 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 932 { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 933/* Sd: Destination support register */ 934 { "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4, 935 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 936 { 0, { { { (1<<MACH_CRISV32), 0 } } } } }, 937/* i: Quick signed 6-bit */ 938 { "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6, 939 { 0, { &cris_cgen_ifld_table[CRIS_F_S6] } }, 940 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 941/* j: Quick unsigned 6-bit */ 942 { "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6, 943 { 0, { &cris_cgen_ifld_table[CRIS_F_U6] } }, 944 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 945/* c: Quick unsigned 5-bit */ 946 { "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5, 947 { 0, { &cris_cgen_ifld_table[CRIS_F_U5] } }, 948 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 949/* qo: Quick unsigned 4-bit, PC-relative */ 950 { "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4, 951 { 0, { &cris_cgen_ifld_table[CRIS_F_QO] } }, 952 { 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } }, 953/* Rd: Destination general register */ 954 { "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4, 955 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 956 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 957/* sconst8: Signed byte [PC+] */ 958 { "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16, 959 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } }, 960 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 961/* uconst8: Unsigned byte [PC+] */ 962 { "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16, 963 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } }, 964 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 965/* sconst16: Signed word [PC+] */ 966 { "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16, 967 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } }, 968 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 969/* uconst16: Unsigned word [PC+] */ 970 { "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16, 971 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } }, 972 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 973/* const32: Dword [PC+] */ 974 { "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32, 975 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } }, 976 { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } }, 977/* const32-pcrel: Dword [PC+] */ 978 { "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32, 979 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } }, 980 { 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } }, 981/* Pd: Destination special register */ 982 { "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4, 983 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 984 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 985/* o: Signed 8-bit */ 986 { "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8, 987 { 0, { &cris_cgen_ifld_table[CRIS_F_S8] } }, 988 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 989/* o-pcrel: 9-bit signed immediate PC-rel */ 990 { "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8, 991 { 2, { &CRIS_F_DISP9_MULTI_IFIELD[0] } }, 992 { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 993/* o-word-pcrel: 16-bit signed immediate PC-rel */ 994 { "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16, 995 { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } }, 996 { 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 997/* cc: Condition codes */ 998 { "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4, 999 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 1000 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 1001/* n: Quick unsigned 4-bit */ 1002 { "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4, 1003 { 0, { &cris_cgen_ifld_table[CRIS_F_U4] } }, 1004 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 1005/* swapoption: Swap option */ 1006 { "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4, 1007 { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } }, 1008 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 1009/* list-of-flags: Flag bits as operand */ 1010 { "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8, 1011 { 2, { &CRIS_F_DSTSRC_MULTI_IFIELD[0] } }, 1012 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 1013/* sentinel */ 1014 { 0, 0, 0, 0, 0, 1015 { 0, { 0 } }, 1016 { 0, { { { (1<<MACH_BASE), 0 } } } } } 1017}; 1018 1019#undef A 1020 1021 1022/* The instruction table. */ 1023 1024#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 1025#define A(a) (1 << CGEN_INSN_##a) 1026 1027static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] = 1028{ 1029 /* Special null first entry. 1030 A `num' value of zero is thus invalid. 1031 Also, the special `invalid' insn resides here. */ 1032 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 1033/* nop */ 1034 { 1035 CRIS_INSN_NOP, "nop", "nop", 16, 1036 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1037 }, 1038/* move.b move.m ${Rs},${Rd} */ 1039 { 1040 CRIS_INSN_MOVE_B_R, "move.b-r", "move.b", 16, 1041 { 0, { { { (1<<MACH_BASE), 0 } } } } 1042 }, 1043/* move.w move.m ${Rs},${Rd} */ 1044 { 1045 CRIS_INSN_MOVE_W_R, "move.w-r", "move.w", 16, 1046 { 0, { { { (1<<MACH_BASE), 0 } } } } 1047 }, 1048/* move.d move.m ${Rs},${Rd} */ 1049 { 1050 CRIS_INSN_MOVE_D_R, "move.d-r", "move.d", 16, 1051 { 0, { { { (1<<MACH_BASE), 0 } } } } 1052 }, 1053/* move.d PC,${Rd} */ 1054 { 1055 CRIS_INSN_MOVEPCR, "movepcr", "move.d", 16, 1056 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1057 }, 1058/* moveq $i,$Rd */ 1059 { 1060 CRIS_INSN_MOVEQ, "moveq", "moveq", 16, 1061 { 0, { { { (1<<MACH_BASE), 0 } } } } 1062 }, 1063/* movs.b movs.m ${Rs},${Rd} */ 1064 { 1065 CRIS_INSN_MOVS_B_R, "movs.b-r", "movs.b", 16, 1066 { 0, { { { (1<<MACH_BASE), 0 } } } } 1067 }, 1068/* movs.w movs.m ${Rs},${Rd} */ 1069 { 1070 CRIS_INSN_MOVS_W_R, "movs.w-r", "movs.w", 16, 1071 { 0, { { { (1<<MACH_BASE), 0 } } } } 1072 }, 1073/* movu.b movu.m ${Rs},${Rd} */ 1074 { 1075 CRIS_INSN_MOVU_B_R, "movu.b-r", "movu.b", 16, 1076 { 0, { { { (1<<MACH_BASE), 0 } } } } 1077 }, 1078/* movu.w movu.m ${Rs},${Rd} */ 1079 { 1080 CRIS_INSN_MOVU_W_R, "movu.w-r", "movu.w", 16, 1081 { 0, { { { (1<<MACH_BASE), 0 } } } } 1082 }, 1083/* move.b ${sconst8},${Rd} */ 1084 { 1085 CRIS_INSN_MOVECBR, "movecbr", "move.b", 32, 1086 { 0, { { { (1<<MACH_BASE), 0 } } } } 1087 }, 1088/* move.w ${sconst16},${Rd} */ 1089 { 1090 CRIS_INSN_MOVECWR, "movecwr", "move.w", 32, 1091 { 0, { { { (1<<MACH_BASE), 0 } } } } 1092 }, 1093/* move.d ${const32},${Rd} */ 1094 { 1095 CRIS_INSN_MOVECDR, "movecdr", "move.d", 48, 1096 { 0, { { { (1<<MACH_BASE), 0 } } } } 1097 }, 1098/* movs.b ${sconst8},${Rd} */ 1099 { 1100 CRIS_INSN_MOVSCBR, "movscbr", "movs.b", 32, 1101 { 0, { { { (1<<MACH_BASE), 0 } } } } 1102 }, 1103/* movs.w ${sconst16},${Rd} */ 1104 { 1105 CRIS_INSN_MOVSCWR, "movscwr", "movs.w", 32, 1106 { 0, { { { (1<<MACH_BASE), 0 } } } } 1107 }, 1108/* movu.b ${uconst8},${Rd} */ 1109 { 1110 CRIS_INSN_MOVUCBR, "movucbr", "movu.b", 32, 1111 { 0, { { { (1<<MACH_BASE), 0 } } } } 1112 }, 1113/* movu.w ${uconst16},${Rd} */ 1114 { 1115 CRIS_INSN_MOVUCWR, "movucwr", "movu.w", 32, 1116 { 0, { { { (1<<MACH_BASE), 0 } } } } 1117 }, 1118/* addq $j,$Rd */ 1119 { 1120 CRIS_INSN_ADDQ, "addq", "addq", 16, 1121 { 0, { { { (1<<MACH_BASE), 0 } } } } 1122 }, 1123/* subq $j,$Rd */ 1124 { 1125 CRIS_INSN_SUBQ, "subq", "subq", 16, 1126 { 0, { { { (1<<MACH_BASE), 0 } } } } 1127 }, 1128/* cmp-r.b $Rs,$Rd */ 1129 { 1130 CRIS_INSN_CMP_R_B_R, "cmp-r.b-r", "cmp-r.b", 16, 1131 { 0, { { { (1<<MACH_BASE), 0 } } } } 1132 }, 1133/* cmp-r.w $Rs,$Rd */ 1134 { 1135 CRIS_INSN_CMP_R_W_R, "cmp-r.w-r", "cmp-r.w", 16, 1136 { 0, { { { (1<<MACH_BASE), 0 } } } } 1137 }, 1138/* cmp-r.d $Rs,$Rd */ 1139 { 1140 CRIS_INSN_CMP_R_D_R, "cmp-r.d-r", "cmp-r.d", 16, 1141 { 0, { { { (1<<MACH_BASE), 0 } } } } 1142 }, 1143/* cmp-m.b [${Rs}${inc}],${Rd} */ 1144 { 1145 CRIS_INSN_CMP_M_B_M, "cmp-m.b-m", "cmp-m.b", 16, 1146 { 0, { { { (1<<MACH_BASE), 0 } } } } 1147 }, 1148/* cmp-m.w [${Rs}${inc}],${Rd} */ 1149 { 1150 CRIS_INSN_CMP_M_W_M, "cmp-m.w-m", "cmp-m.w", 16, 1151 { 0, { { { (1<<MACH_BASE), 0 } } } } 1152 }, 1153/* cmp-m.d [${Rs}${inc}],${Rd} */ 1154 { 1155 CRIS_INSN_CMP_M_D_M, "cmp-m.d-m", "cmp-m.d", 16, 1156 { 0, { { { (1<<MACH_BASE), 0 } } } } 1157 }, 1158/* cmp.b $sconst8,$Rd */ 1159 { 1160 CRIS_INSN_CMPCBR, "cmpcbr", "cmp.b", 32, 1161 { 0, { { { (1<<MACH_BASE), 0 } } } } 1162 }, 1163/* cmp.w $sconst16,$Rd */ 1164 { 1165 CRIS_INSN_CMPCWR, "cmpcwr", "cmp.w", 32, 1166 { 0, { { { (1<<MACH_BASE), 0 } } } } 1167 }, 1168/* cmp.d $const32,$Rd */ 1169 { 1170 CRIS_INSN_CMPCDR, "cmpcdr", "cmp.d", 48, 1171 { 0, { { { (1<<MACH_BASE), 0 } } } } 1172 }, 1173/* cmpq $i,$Rd */ 1174 { 1175 CRIS_INSN_CMPQ, "cmpq", "cmpq", 16, 1176 { 0, { { { (1<<MACH_BASE), 0 } } } } 1177 }, 1178/* cmps-m.b [${Rs}${inc}],$Rd */ 1179 { 1180 CRIS_INSN_CMPS_M_B_M, "cmps-m.b-m", "cmps-m.b", 16, 1181 { 0, { { { (1<<MACH_BASE), 0 } } } } 1182 }, 1183/* cmps-m.w [${Rs}${inc}],$Rd */ 1184 { 1185 CRIS_INSN_CMPS_M_W_M, "cmps-m.w-m", "cmps-m.w", 16, 1186 { 0, { { { (1<<MACH_BASE), 0 } } } } 1187 }, 1188/* [${Rs}${inc}],$Rd */ 1189 { 1190 CRIS_INSN_CMPSCBR, "cmpscbr", "[", 32, 1191 { 0, { { { (1<<MACH_BASE), 0 } } } } 1192 }, 1193/* [${Rs}${inc}],$Rd */ 1194 { 1195 CRIS_INSN_CMPSCWR, "cmpscwr", "[", 32, 1196 { 0, { { { (1<<MACH_BASE), 0 } } } } 1197 }, 1198/* cmpu-m.b [${Rs}${inc}],$Rd */ 1199 { 1200 CRIS_INSN_CMPU_M_B_M, "cmpu-m.b-m", "cmpu-m.b", 16, 1201 { 0, { { { (1<<MACH_BASE), 0 } } } } 1202 }, 1203/* cmpu-m.w [${Rs}${inc}],$Rd */ 1204 { 1205 CRIS_INSN_CMPU_M_W_M, "cmpu-m.w-m", "cmpu-m.w", 16, 1206 { 0, { { { (1<<MACH_BASE), 0 } } } } 1207 }, 1208/* [${Rs}${inc}],$Rd */ 1209 { 1210 CRIS_INSN_CMPUCBR, "cmpucbr", "[", 32, 1211 { 0, { { { (1<<MACH_BASE), 0 } } } } 1212 }, 1213/* [${Rs}${inc}],$Rd */ 1214 { 1215 CRIS_INSN_CMPUCWR, "cmpucwr", "[", 32, 1216 { 0, { { { (1<<MACH_BASE), 0 } } } } 1217 }, 1218/* move-m.b [${Rs}${inc}],${Rd} */ 1219 { 1220 CRIS_INSN_MOVE_M_B_M, "move-m.b-m", "move-m.b", 16, 1221 { 0, { { { (1<<MACH_BASE), 0 } } } } 1222 }, 1223/* move-m.w [${Rs}${inc}],${Rd} */ 1224 { 1225 CRIS_INSN_MOVE_M_W_M, "move-m.w-m", "move-m.w", 16, 1226 { 0, { { { (1<<MACH_BASE), 0 } } } } 1227 }, 1228/* move-m.d [${Rs}${inc}],${Rd} */ 1229 { 1230 CRIS_INSN_MOVE_M_D_M, "move-m.d-m", "move-m.d", 16, 1231 { 0, { { { (1<<MACH_BASE), 0 } } } } 1232 }, 1233/* movs-m.b [${Rs}${inc}],${Rd} */ 1234 { 1235 CRIS_INSN_MOVS_M_B_M, "movs-m.b-m", "movs-m.b", 16, 1236 { 0, { { { (1<<MACH_BASE), 0 } } } } 1237 }, 1238/* movs-m.w [${Rs}${inc}],${Rd} */ 1239 { 1240 CRIS_INSN_MOVS_M_W_M, "movs-m.w-m", "movs-m.w", 16, 1241 { 0, { { { (1<<MACH_BASE), 0 } } } } 1242 }, 1243/* movu-m.b [${Rs}${inc}],${Rd} */ 1244 { 1245 CRIS_INSN_MOVU_M_B_M, "movu-m.b-m", "movu-m.b", 16, 1246 { 0, { { { (1<<MACH_BASE), 0 } } } } 1247 }, 1248/* movu-m.w [${Rs}${inc}],${Rd} */ 1249 { 1250 CRIS_INSN_MOVU_M_W_M, "movu-m.w-m", "movu-m.w", 16, 1251 { 0, { { { (1<<MACH_BASE), 0 } } } } 1252 }, 1253/* move ${Rs},${Pd} */ 1254 { 1255 CRIS_INSN_MOVE_R_SPRV0, "move-r-sprv0", "move", 16, 1256 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1257 }, 1258/* move ${Rs},${Pd} */ 1259 { 1260 CRIS_INSN_MOVE_R_SPRV3, "move-r-sprv3", "move", 16, 1261 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1262 }, 1263/* move ${Rs},${Pd} */ 1264 { 1265 CRIS_INSN_MOVE_R_SPRV8, "move-r-sprv8", "move", 16, 1266 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1267 }, 1268/* move ${Rs},${Pd} */ 1269 { 1270 CRIS_INSN_MOVE_R_SPRV10, "move-r-sprv10", "move", 16, 1271 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1272 }, 1273/* move ${Rs},${Pd} */ 1274 { 1275 CRIS_INSN_MOVE_R_SPRV32, "move-r-sprv32", "move", 16, 1276 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1277 }, 1278/* move ${Ps},${Rd-sfield} */ 1279 { 1280 CRIS_INSN_MOVE_SPR_RV0, "move-spr-rv0", "move", 16, 1281 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1282 }, 1283/* move ${Ps},${Rd-sfield} */ 1284 { 1285 CRIS_INSN_MOVE_SPR_RV3, "move-spr-rv3", "move", 16, 1286 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1287 }, 1288/* move ${Ps},${Rd-sfield} */ 1289 { 1290 CRIS_INSN_MOVE_SPR_RV8, "move-spr-rv8", "move", 16, 1291 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1292 }, 1293/* move ${Ps},${Rd-sfield} */ 1294 { 1295 CRIS_INSN_MOVE_SPR_RV10, "move-spr-rv10", "move", 16, 1296 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1297 }, 1298/* move ${Ps},${Rd-sfield} */ 1299 { 1300 CRIS_INSN_MOVE_SPR_RV32, "move-spr-rv32", "move", 16, 1301 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1302 }, 1303/* ret/reti/retb */ 1304 { 1305 CRIS_INSN_RET_TYPE, "ret-type", "ret/reti/retb", 16, 1306 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1307 }, 1308/* move [${Rs}${inc}],${Pd} */ 1309 { 1310 CRIS_INSN_MOVE_M_SPRV0, "move-m-sprv0", "move", 16, 1311 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1312 }, 1313/* move [${Rs}${inc}],${Pd} */ 1314 { 1315 CRIS_INSN_MOVE_M_SPRV3, "move-m-sprv3", "move", 16, 1316 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1317 }, 1318/* move [${Rs}${inc}],${Pd} */ 1319 { 1320 CRIS_INSN_MOVE_M_SPRV8, "move-m-sprv8", "move", 16, 1321 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1322 }, 1323/* move [${Rs}${inc}],${Pd} */ 1324 { 1325 CRIS_INSN_MOVE_M_SPRV10, "move-m-sprv10", "move", 16, 1326 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1327 }, 1328/* move [${Rs}${inc}],${Pd} */ 1329 { 1330 CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16, 1331 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1332 }, 1333/* move ${sconst16},${Pd} */ 1334 { 1335 CRIS_INSN_MOVE_C_SPRV0_P5, "move-c-sprv0-p5", "move", 32, 1336 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1337 }, 1338/* move ${const32},${Pd} */ 1339 { 1340 CRIS_INSN_MOVE_C_SPRV0_P9, "move-c-sprv0-p9", "move", 48, 1341 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1342 }, 1343/* move ${const32},${Pd} */ 1344 { 1345 CRIS_INSN_MOVE_C_SPRV0_P10, "move-c-sprv0-p10", "move", 48, 1346 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1347 }, 1348/* move ${const32},${Pd} */ 1349 { 1350 CRIS_INSN_MOVE_C_SPRV0_P11, "move-c-sprv0-p11", "move", 48, 1351 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1352 }, 1353/* move ${const32},${Pd} */ 1354 { 1355 CRIS_INSN_MOVE_C_SPRV0_P12, "move-c-sprv0-p12", "move", 48, 1356 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1357 }, 1358/* move ${const32},${Pd} */ 1359 { 1360 CRIS_INSN_MOVE_C_SPRV0_P13, "move-c-sprv0-p13", "move", 48, 1361 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1362 }, 1363/* move ${sconst16},${Pd} */ 1364 { 1365 CRIS_INSN_MOVE_C_SPRV0_P6, "move-c-sprv0-p6", "move", 32, 1366 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1367 }, 1368/* move ${sconst16},${Pd} */ 1369 { 1370 CRIS_INSN_MOVE_C_SPRV0_P7, "move-c-sprv0-p7", "move", 32, 1371 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1372 }, 1373/* move ${sconst16},${Pd} */ 1374 { 1375 CRIS_INSN_MOVE_C_SPRV3_P5, "move-c-sprv3-p5", "move", 32, 1376 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1377 }, 1378/* move ${const32},${Pd} */ 1379 { 1380 CRIS_INSN_MOVE_C_SPRV3_P9, "move-c-sprv3-p9", "move", 48, 1381 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1382 }, 1383/* move ${const32},${Pd} */ 1384 { 1385 CRIS_INSN_MOVE_C_SPRV3_P10, "move-c-sprv3-p10", "move", 48, 1386 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1387 }, 1388/* move ${const32},${Pd} */ 1389 { 1390 CRIS_INSN_MOVE_C_SPRV3_P11, "move-c-sprv3-p11", "move", 48, 1391 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1392 }, 1393/* move ${const32},${Pd} */ 1394 { 1395 CRIS_INSN_MOVE_C_SPRV3_P12, "move-c-sprv3-p12", "move", 48, 1396 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1397 }, 1398/* move ${const32},${Pd} */ 1399 { 1400 CRIS_INSN_MOVE_C_SPRV3_P13, "move-c-sprv3-p13", "move", 48, 1401 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1402 }, 1403/* move ${sconst16},${Pd} */ 1404 { 1405 CRIS_INSN_MOVE_C_SPRV3_P6, "move-c-sprv3-p6", "move", 32, 1406 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1407 }, 1408/* move ${sconst16},${Pd} */ 1409 { 1410 CRIS_INSN_MOVE_C_SPRV3_P7, "move-c-sprv3-p7", "move", 32, 1411 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1412 }, 1413/* move ${const32},${Pd} */ 1414 { 1415 CRIS_INSN_MOVE_C_SPRV3_P14, "move-c-sprv3-p14", "move", 48, 1416 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1417 }, 1418/* move ${sconst16},${Pd} */ 1419 { 1420 CRIS_INSN_MOVE_C_SPRV8_P5, "move-c-sprv8-p5", "move", 32, 1421 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1422 }, 1423/* move ${const32},${Pd} */ 1424 { 1425 CRIS_INSN_MOVE_C_SPRV8_P9, "move-c-sprv8-p9", "move", 48, 1426 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1427 }, 1428/* move ${const32},${Pd} */ 1429 { 1430 CRIS_INSN_MOVE_C_SPRV8_P10, "move-c-sprv8-p10", "move", 48, 1431 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1432 }, 1433/* move ${const32},${Pd} */ 1434 { 1435 CRIS_INSN_MOVE_C_SPRV8_P11, "move-c-sprv8-p11", "move", 48, 1436 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1437 }, 1438/* move ${const32},${Pd} */ 1439 { 1440 CRIS_INSN_MOVE_C_SPRV8_P12, "move-c-sprv8-p12", "move", 48, 1441 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1442 }, 1443/* move ${const32},${Pd} */ 1444 { 1445 CRIS_INSN_MOVE_C_SPRV8_P13, "move-c-sprv8-p13", "move", 48, 1446 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1447 }, 1448/* move ${const32},${Pd} */ 1449 { 1450 CRIS_INSN_MOVE_C_SPRV8_P14, "move-c-sprv8-p14", "move", 48, 1451 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1452 }, 1453/* move ${sconst16},${Pd} */ 1454 { 1455 CRIS_INSN_MOVE_C_SPRV10_P5, "move-c-sprv10-p5", "move", 32, 1456 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1457 }, 1458/* move ${const32},${Pd} */ 1459 { 1460 CRIS_INSN_MOVE_C_SPRV10_P9, "move-c-sprv10-p9", "move", 48, 1461 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1462 }, 1463/* move ${const32},${Pd} */ 1464 { 1465 CRIS_INSN_MOVE_C_SPRV10_P10, "move-c-sprv10-p10", "move", 48, 1466 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1467 }, 1468/* move ${const32},${Pd} */ 1469 { 1470 CRIS_INSN_MOVE_C_SPRV10_P11, "move-c-sprv10-p11", "move", 48, 1471 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1472 }, 1473/* move ${const32},${Pd} */ 1474 { 1475 CRIS_INSN_MOVE_C_SPRV10_P12, "move-c-sprv10-p12", "move", 48, 1476 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1477 }, 1478/* move ${const32},${Pd} */ 1479 { 1480 CRIS_INSN_MOVE_C_SPRV10_P13, "move-c-sprv10-p13", "move", 48, 1481 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1482 }, 1483/* move ${const32},${Pd} */ 1484 { 1485 CRIS_INSN_MOVE_C_SPRV10_P7, "move-c-sprv10-p7", "move", 48, 1486 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1487 }, 1488/* move ${const32},${Pd} */ 1489 { 1490 CRIS_INSN_MOVE_C_SPRV10_P14, "move-c-sprv10-p14", "move", 48, 1491 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1492 }, 1493/* move ${const32},${Pd} */ 1494 { 1495 CRIS_INSN_MOVE_C_SPRV10_P15, "move-c-sprv10-p15", "move", 48, 1496 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1497 }, 1498/* move ${const32},${Pd} */ 1499 { 1500 CRIS_INSN_MOVE_C_SPRV32_P2, "move-c-sprv32-p2", "move", 48, 1501 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1502 }, 1503/* move ${const32},${Pd} */ 1504 { 1505 CRIS_INSN_MOVE_C_SPRV32_P3, "move-c-sprv32-p3", "move", 48, 1506 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1507 }, 1508/* move ${const32},${Pd} */ 1509 { 1510 CRIS_INSN_MOVE_C_SPRV32_P5, "move-c-sprv32-p5", "move", 48, 1511 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1512 }, 1513/* move ${const32},${Pd} */ 1514 { 1515 CRIS_INSN_MOVE_C_SPRV32_P6, "move-c-sprv32-p6", "move", 48, 1516 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1517 }, 1518/* move ${const32},${Pd} */ 1519 { 1520 CRIS_INSN_MOVE_C_SPRV32_P7, "move-c-sprv32-p7", "move", 48, 1521 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1522 }, 1523/* move ${const32},${Pd} */ 1524 { 1525 CRIS_INSN_MOVE_C_SPRV32_P9, "move-c-sprv32-p9", "move", 48, 1526 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1527 }, 1528/* move ${const32},${Pd} */ 1529 { 1530 CRIS_INSN_MOVE_C_SPRV32_P10, "move-c-sprv32-p10", "move", 48, 1531 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1532 }, 1533/* move ${const32},${Pd} */ 1534 { 1535 CRIS_INSN_MOVE_C_SPRV32_P11, "move-c-sprv32-p11", "move", 48, 1536 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1537 }, 1538/* move ${const32},${Pd} */ 1539 { 1540 CRIS_INSN_MOVE_C_SPRV32_P12, "move-c-sprv32-p12", "move", 48, 1541 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1542 }, 1543/* move ${const32},${Pd} */ 1544 { 1545 CRIS_INSN_MOVE_C_SPRV32_P13, "move-c-sprv32-p13", "move", 48, 1546 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1547 }, 1548/* move ${const32},${Pd} */ 1549 { 1550 CRIS_INSN_MOVE_C_SPRV32_P14, "move-c-sprv32-p14", "move", 48, 1551 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1552 }, 1553/* move ${const32},${Pd} */ 1554 { 1555 CRIS_INSN_MOVE_C_SPRV32_P15, "move-c-sprv32-p15", "move", 48, 1556 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1557 }, 1558/* move ${Ps},[${Rd-sfield}${inc}] */ 1559 { 1560 CRIS_INSN_MOVE_SPR_MV0, "move-spr-mv0", "move", 16, 1561 { 0, { { { (1<<MACH_CRISV0), 0 } } } } 1562 }, 1563/* move ${Ps},[${Rd-sfield}${inc}] */ 1564 { 1565 CRIS_INSN_MOVE_SPR_MV3, "move-spr-mv3", "move", 16, 1566 { 0, { { { (1<<MACH_CRISV3), 0 } } } } 1567 }, 1568/* move ${Ps},[${Rd-sfield}${inc}] */ 1569 { 1570 CRIS_INSN_MOVE_SPR_MV8, "move-spr-mv8", "move", 16, 1571 { 0, { { { (1<<MACH_CRISV8), 0 } } } } 1572 }, 1573/* move ${Ps},[${Rd-sfield}${inc}] */ 1574 { 1575 CRIS_INSN_MOVE_SPR_MV10, "move-spr-mv10", "move", 16, 1576 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1577 }, 1578/* move ${Ps},[${Rd-sfield}${inc}] */ 1579 { 1580 CRIS_INSN_MOVE_SPR_MV32, "move-spr-mv32", "move", 16, 1581 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1582 }, 1583/* sbfs [${Rd-sfield}${inc}] */ 1584 { 1585 CRIS_INSN_SBFS, "sbfs", "sbfs", 16, 1586 { 0, { { { (1<<MACH_CRISV10), 0 } } } } 1587 }, 1588/* move ${Ss},${Rd-sfield} */ 1589 { 1590 CRIS_INSN_MOVE_SS_R, "move-ss-r", "move", 16, 1591 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1592 }, 1593/* move ${Rs},${Sd} */ 1594 { 1595 CRIS_INSN_MOVE_R_SS, "move-r-ss", "move", 16, 1596 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1597 }, 1598/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */ 1599 { 1600 CRIS_INSN_MOVEM_R_M, "movem-r-m", "movem", 16, 1601 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1602 }, 1603/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */ 1604 { 1605 CRIS_INSN_MOVEM_R_M_V32, "movem-r-m-v32", "movem", 16, 1606 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1607 }, 1608/* movem [${Rs}${inc}],${Rd} */ 1609 { 1610 CRIS_INSN_MOVEM_M_R, "movem-m-r", "movem", 16, 1611 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1612 }, 1613/* movem [${Rs}${inc}],${Rd} */ 1614 { 1615 CRIS_INSN_MOVEM_M_PC, "movem-m-pc", "movem", 16, 1616 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1617 }, 1618/* movem [${Rs}${inc}],${Rd} */ 1619 { 1620 CRIS_INSN_MOVEM_M_R_V32, "movem-m-r-v32", "movem", 16, 1621 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1622 }, 1623/* add.b $Rs,$Rd */ 1624 { 1625 CRIS_INSN_ADD_B_R, "add.b-r", "add.b", 16, 1626 { 0, { { { (1<<MACH_BASE), 0 } } } } 1627 }, 1628/* add.w $Rs,$Rd */ 1629 { 1630 CRIS_INSN_ADD_W_R, "add.w-r", "add.w", 16, 1631 { 0, { { { (1<<MACH_BASE), 0 } } } } 1632 }, 1633/* add.d $Rs,$Rd */ 1634 { 1635 CRIS_INSN_ADD_D_R, "add.d-r", "add.d", 16, 1636 { 0, { { { (1<<MACH_BASE), 0 } } } } 1637 }, 1638/* add-m.b [${Rs}${inc}],${Rd} */ 1639 { 1640 CRIS_INSN_ADD_M_B_M, "add-m.b-m", "add-m.b", 16, 1641 { 0, { { { (1<<MACH_BASE), 0 } } } } 1642 }, 1643/* add-m.w [${Rs}${inc}],${Rd} */ 1644 { 1645 CRIS_INSN_ADD_M_W_M, "add-m.w-m", "add-m.w", 16, 1646 { 0, { { { (1<<MACH_BASE), 0 } } } } 1647 }, 1648/* add-m.d [${Rs}${inc}],${Rd} */ 1649 { 1650 CRIS_INSN_ADD_M_D_M, "add-m.d-m", "add-m.d", 16, 1651 { 0, { { { (1<<MACH_BASE), 0 } } } } 1652 }, 1653/* add.b ${sconst8}],${Rd} */ 1654 { 1655 CRIS_INSN_ADDCBR, "addcbr", "add.b", 32, 1656 { 0, { { { (1<<MACH_BASE), 0 } } } } 1657 }, 1658/* add.w ${sconst16}],${Rd} */ 1659 { 1660 CRIS_INSN_ADDCWR, "addcwr", "add.w", 32, 1661 { 0, { { { (1<<MACH_BASE), 0 } } } } 1662 }, 1663/* add.d ${const32}],${Rd} */ 1664 { 1665 CRIS_INSN_ADDCDR, "addcdr", "add.d", 48, 1666 { 0, { { { (1<<MACH_BASE), 0 } } } } 1667 }, 1668/* add.d ${sconst32},PC */ 1669 { 1670 CRIS_INSN_ADDCPC, "addcpc", "add.d", 48, 1671 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1672 }, 1673/* adds.b $Rs,$Rd */ 1674 { 1675 CRIS_INSN_ADDS_B_R, "adds.b-r", "adds.b", 16, 1676 { 0, { { { (1<<MACH_BASE), 0 } } } } 1677 }, 1678/* adds.w $Rs,$Rd */ 1679 { 1680 CRIS_INSN_ADDS_W_R, "adds.w-r", "adds.w", 16, 1681 { 0, { { { (1<<MACH_BASE), 0 } } } } 1682 }, 1683/* adds-m.b [${Rs}${inc}],$Rd */ 1684 { 1685 CRIS_INSN_ADDS_M_B_M, "adds-m.b-m", "adds-m.b", 16, 1686 { 0, { { { (1<<MACH_BASE), 0 } } } } 1687 }, 1688/* adds-m.w [${Rs}${inc}],$Rd */ 1689 { 1690 CRIS_INSN_ADDS_M_W_M, "adds-m.w-m", "adds-m.w", 16, 1691 { 0, { { { (1<<MACH_BASE), 0 } } } } 1692 }, 1693/* [${Rs}${inc}],$Rd */ 1694 { 1695 CRIS_INSN_ADDSCBR, "addscbr", "[", 32, 1696 { 0, { { { (1<<MACH_BASE), 0 } } } } 1697 }, 1698/* [${Rs}${inc}],$Rd */ 1699 { 1700 CRIS_INSN_ADDSCWR, "addscwr", "[", 32, 1701 { 0, { { { (1<<MACH_BASE), 0 } } } } 1702 }, 1703/* adds.w [PC],PC */ 1704 { 1705 CRIS_INSN_ADDSPCPC, "addspcpc", "adds.w", 16, 1706 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1707 }, 1708/* addu.b $Rs,$Rd */ 1709 { 1710 CRIS_INSN_ADDU_B_R, "addu.b-r", "addu.b", 16, 1711 { 0, { { { (1<<MACH_BASE), 0 } } } } 1712 }, 1713/* addu.w $Rs,$Rd */ 1714 { 1715 CRIS_INSN_ADDU_W_R, "addu.w-r", "addu.w", 16, 1716 { 0, { { { (1<<MACH_BASE), 0 } } } } 1717 }, 1718/* addu-m.b [${Rs}${inc}],$Rd */ 1719 { 1720 CRIS_INSN_ADDU_M_B_M, "addu-m.b-m", "addu-m.b", 16, 1721 { 0, { { { (1<<MACH_BASE), 0 } } } } 1722 }, 1723/* addu-m.w [${Rs}${inc}],$Rd */ 1724 { 1725 CRIS_INSN_ADDU_M_W_M, "addu-m.w-m", "addu-m.w", 16, 1726 { 0, { { { (1<<MACH_BASE), 0 } } } } 1727 }, 1728/* [${Rs}${inc}],$Rd */ 1729 { 1730 CRIS_INSN_ADDUCBR, "adducbr", "[", 32, 1731 { 0, { { { (1<<MACH_BASE), 0 } } } } 1732 }, 1733/* [${Rs}${inc}],$Rd */ 1734 { 1735 CRIS_INSN_ADDUCWR, "adducwr", "[", 32, 1736 { 0, { { { (1<<MACH_BASE), 0 } } } } 1737 }, 1738/* sub.b $Rs,$Rd */ 1739 { 1740 CRIS_INSN_SUB_B_R, "sub.b-r", "sub.b", 16, 1741 { 0, { { { (1<<MACH_BASE), 0 } } } } 1742 }, 1743/* sub.w $Rs,$Rd */ 1744 { 1745 CRIS_INSN_SUB_W_R, "sub.w-r", "sub.w", 16, 1746 { 0, { { { (1<<MACH_BASE), 0 } } } } 1747 }, 1748/* sub.d $Rs,$Rd */ 1749 { 1750 CRIS_INSN_SUB_D_R, "sub.d-r", "sub.d", 16, 1751 { 0, { { { (1<<MACH_BASE), 0 } } } } 1752 }, 1753/* sub-m.b [${Rs}${inc}],${Rd} */ 1754 { 1755 CRIS_INSN_SUB_M_B_M, "sub-m.b-m", "sub-m.b", 16, 1756 { 0, { { { (1<<MACH_BASE), 0 } } } } 1757 }, 1758/* sub-m.w [${Rs}${inc}],${Rd} */ 1759 { 1760 CRIS_INSN_SUB_M_W_M, "sub-m.w-m", "sub-m.w", 16, 1761 { 0, { { { (1<<MACH_BASE), 0 } } } } 1762 }, 1763/* sub-m.d [${Rs}${inc}],${Rd} */ 1764 { 1765 CRIS_INSN_SUB_M_D_M, "sub-m.d-m", "sub-m.d", 16, 1766 { 0, { { { (1<<MACH_BASE), 0 } } } } 1767 }, 1768/* sub.b ${sconst8}],${Rd} */ 1769 { 1770 CRIS_INSN_SUBCBR, "subcbr", "sub.b", 32, 1771 { 0, { { { (1<<MACH_BASE), 0 } } } } 1772 }, 1773/* sub.w ${sconst16}],${Rd} */ 1774 { 1775 CRIS_INSN_SUBCWR, "subcwr", "sub.w", 32, 1776 { 0, { { { (1<<MACH_BASE), 0 } } } } 1777 }, 1778/* sub.d ${const32}],${Rd} */ 1779 { 1780 CRIS_INSN_SUBCDR, "subcdr", "sub.d", 48, 1781 { 0, { { { (1<<MACH_BASE), 0 } } } } 1782 }, 1783/* subs.b $Rs,$Rd */ 1784 { 1785 CRIS_INSN_SUBS_B_R, "subs.b-r", "subs.b", 16, 1786 { 0, { { { (1<<MACH_BASE), 0 } } } } 1787 }, 1788/* subs.w $Rs,$Rd */ 1789 { 1790 CRIS_INSN_SUBS_W_R, "subs.w-r", "subs.w", 16, 1791 { 0, { { { (1<<MACH_BASE), 0 } } } } 1792 }, 1793/* subs-m.b [${Rs}${inc}],$Rd */ 1794 { 1795 CRIS_INSN_SUBS_M_B_M, "subs-m.b-m", "subs-m.b", 16, 1796 { 0, { { { (1<<MACH_BASE), 0 } } } } 1797 }, 1798/* subs-m.w [${Rs}${inc}],$Rd */ 1799 { 1800 CRIS_INSN_SUBS_M_W_M, "subs-m.w-m", "subs-m.w", 16, 1801 { 0, { { { (1<<MACH_BASE), 0 } } } } 1802 }, 1803/* [${Rs}${inc}],$Rd */ 1804 { 1805 CRIS_INSN_SUBSCBR, "subscbr", "[", 32, 1806 { 0, { { { (1<<MACH_BASE), 0 } } } } 1807 }, 1808/* [${Rs}${inc}],$Rd */ 1809 { 1810 CRIS_INSN_SUBSCWR, "subscwr", "[", 32, 1811 { 0, { { { (1<<MACH_BASE), 0 } } } } 1812 }, 1813/* subu.b $Rs,$Rd */ 1814 { 1815 CRIS_INSN_SUBU_B_R, "subu.b-r", "subu.b", 16, 1816 { 0, { { { (1<<MACH_BASE), 0 } } } } 1817 }, 1818/* subu.w $Rs,$Rd */ 1819 { 1820 CRIS_INSN_SUBU_W_R, "subu.w-r", "subu.w", 16, 1821 { 0, { { { (1<<MACH_BASE), 0 } } } } 1822 }, 1823/* subu-m.b [${Rs}${inc}],$Rd */ 1824 { 1825 CRIS_INSN_SUBU_M_B_M, "subu-m.b-m", "subu-m.b", 16, 1826 { 0, { { { (1<<MACH_BASE), 0 } } } } 1827 }, 1828/* subu-m.w [${Rs}${inc}],$Rd */ 1829 { 1830 CRIS_INSN_SUBU_M_W_M, "subu-m.w-m", "subu-m.w", 16, 1831 { 0, { { { (1<<MACH_BASE), 0 } } } } 1832 }, 1833/* [${Rs}${inc}],$Rd */ 1834 { 1835 CRIS_INSN_SUBUCBR, "subucbr", "[", 32, 1836 { 0, { { { (1<<MACH_BASE), 0 } } } } 1837 }, 1838/* [${Rs}${inc}],$Rd */ 1839 { 1840 CRIS_INSN_SUBUCWR, "subucwr", "[", 32, 1841 { 0, { { { (1<<MACH_BASE), 0 } } } } 1842 }, 1843/* addc $Rs,$Rd */ 1844 { 1845 CRIS_INSN_ADDC_R, "addc-r", "addc", 16, 1846 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1847 }, 1848/* addc [${Rs}${inc}],${Rd} */ 1849 { 1850 CRIS_INSN_ADDC_M, "addc-m", "addc", 16, 1851 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1852 }, 1853/* addc ${const32},${Rd} */ 1854 { 1855 CRIS_INSN_ADDC_C, "addc-c", "addc", 48, 1856 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1857 }, 1858/* lapc.d ${const32-pcrel},${Rd} */ 1859 { 1860 CRIS_INSN_LAPC_D, "lapc-d", "lapc.d", 48, 1861 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1862 }, 1863/* lapcq ${qo},${Rd} */ 1864 { 1865 CRIS_INSN_LAPCQ, "lapcq", "lapcq", 16, 1866 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1867 }, 1868/* addi.b ${Rs-dfield}.m,${Rd-sfield} */ 1869 { 1870 CRIS_INSN_ADDI_B_R, "addi.b-r", "addi.b", 16, 1871 { 0, { { { (1<<MACH_BASE), 0 } } } } 1872 }, 1873/* addi.w ${Rs-dfield}.m,${Rd-sfield} */ 1874 { 1875 CRIS_INSN_ADDI_W_R, "addi.w-r", "addi.w", 16, 1876 { 0, { { { (1<<MACH_BASE), 0 } } } } 1877 }, 1878/* addi.d ${Rs-dfield}.m,${Rd-sfield} */ 1879 { 1880 CRIS_INSN_ADDI_D_R, "addi.d-r", "addi.d", 16, 1881 { 0, { { { (1<<MACH_BASE), 0 } } } } 1882 }, 1883/* neg.b $Rs,$Rd */ 1884 { 1885 CRIS_INSN_NEG_B_R, "neg.b-r", "neg.b", 16, 1886 { 0, { { { (1<<MACH_BASE), 0 } } } } 1887 }, 1888/* neg.w $Rs,$Rd */ 1889 { 1890 CRIS_INSN_NEG_W_R, "neg.w-r", "neg.w", 16, 1891 { 0, { { { (1<<MACH_BASE), 0 } } } } 1892 }, 1893/* neg.d $Rs,$Rd */ 1894 { 1895 CRIS_INSN_NEG_D_R, "neg.d-r", "neg.d", 16, 1896 { 0, { { { (1<<MACH_BASE), 0 } } } } 1897 }, 1898/* test-m.b [${Rs}${inc}] */ 1899 { 1900 CRIS_INSN_TEST_M_B_M, "test-m.b-m", "test-m.b", 16, 1901 { 0, { { { (1<<MACH_BASE), 0 } } } } 1902 }, 1903/* test-m.w [${Rs}${inc}] */ 1904 { 1905 CRIS_INSN_TEST_M_W_M, "test-m.w-m", "test-m.w", 16, 1906 { 0, { { { (1<<MACH_BASE), 0 } } } } 1907 }, 1908/* test-m.d [${Rs}${inc}] */ 1909 { 1910 CRIS_INSN_TEST_M_D_M, "test-m.d-m", "test-m.d", 16, 1911 { 0, { { { (1<<MACH_BASE), 0 } } } } 1912 }, 1913/* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */ 1914 { 1915 CRIS_INSN_MOVE_R_M_B_M, "move-r-m.b-m", "move-r-m.b", 16, 1916 { 0, { { { (1<<MACH_BASE), 0 } } } } 1917 }, 1918/* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */ 1919 { 1920 CRIS_INSN_MOVE_R_M_W_M, "move-r-m.w-m", "move-r-m.w", 16, 1921 { 0, { { { (1<<MACH_BASE), 0 } } } } 1922 }, 1923/* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */ 1924 { 1925 CRIS_INSN_MOVE_R_M_D_M, "move-r-m.d-m", "move-r-m.d", 16, 1926 { 0, { { { (1<<MACH_BASE), 0 } } } } 1927 }, 1928/* muls.b $Rs,$Rd */ 1929 { 1930 CRIS_INSN_MULS_B, "muls.b", "muls.b", 16, 1931 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1932 }, 1933/* muls.w $Rs,$Rd */ 1934 { 1935 CRIS_INSN_MULS_W, "muls.w", "muls.w", 16, 1936 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1937 }, 1938/* muls.d $Rs,$Rd */ 1939 { 1940 CRIS_INSN_MULS_D, "muls.d", "muls.d", 16, 1941 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1942 }, 1943/* mulu.b $Rs,$Rd */ 1944 { 1945 CRIS_INSN_MULU_B, "mulu.b", "mulu.b", 16, 1946 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1947 }, 1948/* mulu.w $Rs,$Rd */ 1949 { 1950 CRIS_INSN_MULU_W, "mulu.w", "mulu.w", 16, 1951 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1952 }, 1953/* mulu.d $Rs,$Rd */ 1954 { 1955 CRIS_INSN_MULU_D, "mulu.d", "mulu.d", 16, 1956 { 0, { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 1957 }, 1958/* mcp $Ps,$Rd */ 1959 { 1960 CRIS_INSN_MCP, "mcp", "mcp", 16, 1961 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 1962 }, 1963/* mstep $Rs,$Rd */ 1964 { 1965 CRIS_INSN_MSTEP, "mstep", "mstep", 16, 1966 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 1967 }, 1968/* dstep $Rs,$Rd */ 1969 { 1970 CRIS_INSN_DSTEP, "dstep", "dstep", 16, 1971 { 0, { { { (1<<MACH_BASE), 0 } } } } 1972 }, 1973/* abs $Rs,$Rd */ 1974 { 1975 CRIS_INSN_ABS, "abs", "abs", 16, 1976 { 0, { { { (1<<MACH_BASE), 0 } } } } 1977 }, 1978/* and.b $Rs,$Rd */ 1979 { 1980 CRIS_INSN_AND_B_R, "and.b-r", "and.b", 16, 1981 { 0, { { { (1<<MACH_BASE), 0 } } } } 1982 }, 1983/* and.w $Rs,$Rd */ 1984 { 1985 CRIS_INSN_AND_W_R, "and.w-r", "and.w", 16, 1986 { 0, { { { (1<<MACH_BASE), 0 } } } } 1987 }, 1988/* and.d $Rs,$Rd */ 1989 { 1990 CRIS_INSN_AND_D_R, "and.d-r", "and.d", 16, 1991 { 0, { { { (1<<MACH_BASE), 0 } } } } 1992 }, 1993/* and-m.b [${Rs}${inc}],${Rd} */ 1994 { 1995 CRIS_INSN_AND_M_B_M, "and-m.b-m", "and-m.b", 16, 1996 { 0, { { { (1<<MACH_BASE), 0 } } } } 1997 }, 1998/* and-m.w [${Rs}${inc}],${Rd} */ 1999 { 2000 CRIS_INSN_AND_M_W_M, "and-m.w-m", "and-m.w", 16, 2001 { 0, { { { (1<<MACH_BASE), 0 } } } } 2002 }, 2003/* and-m.d [${Rs}${inc}],${Rd} */ 2004 { 2005 CRIS_INSN_AND_M_D_M, "and-m.d-m", "and-m.d", 16, 2006 { 0, { { { (1<<MACH_BASE), 0 } } } } 2007 }, 2008/* and.b ${sconst8}],${Rd} */ 2009 { 2010 CRIS_INSN_ANDCBR, "andcbr", "and.b", 32, 2011 { 0, { { { (1<<MACH_BASE), 0 } } } } 2012 }, 2013/* and.w ${sconst16}],${Rd} */ 2014 { 2015 CRIS_INSN_ANDCWR, "andcwr", "and.w", 32, 2016 { 0, { { { (1<<MACH_BASE), 0 } } } } 2017 }, 2018/* and.d ${const32}],${Rd} */ 2019 { 2020 CRIS_INSN_ANDCDR, "andcdr", "and.d", 48, 2021 { 0, { { { (1<<MACH_BASE), 0 } } } } 2022 }, 2023/* andq $i,$Rd */ 2024 { 2025 CRIS_INSN_ANDQ, "andq", "andq", 16, 2026 { 0, { { { (1<<MACH_BASE), 0 } } } } 2027 }, 2028/* orr.b $Rs,$Rd */ 2029 { 2030 CRIS_INSN_ORR_B_R, "orr.b-r", "orr.b", 16, 2031 { 0, { { { (1<<MACH_BASE), 0 } } } } 2032 }, 2033/* orr.w $Rs,$Rd */ 2034 { 2035 CRIS_INSN_ORR_W_R, "orr.w-r", "orr.w", 16, 2036 { 0, { { { (1<<MACH_BASE), 0 } } } } 2037 }, 2038/* orr.d $Rs,$Rd */ 2039 { 2040 CRIS_INSN_ORR_D_R, "orr.d-r", "orr.d", 16, 2041 { 0, { { { (1<<MACH_BASE), 0 } } } } 2042 }, 2043/* or-m.b [${Rs}${inc}],${Rd} */ 2044 { 2045 CRIS_INSN_OR_M_B_M, "or-m.b-m", "or-m.b", 16, 2046 { 0, { { { (1<<MACH_BASE), 0 } } } } 2047 }, 2048/* or-m.w [${Rs}${inc}],${Rd} */ 2049 { 2050 CRIS_INSN_OR_M_W_M, "or-m.w-m", "or-m.w", 16, 2051 { 0, { { { (1<<MACH_BASE), 0 } } } } 2052 }, 2053/* or-m.d [${Rs}${inc}],${Rd} */ 2054 { 2055 CRIS_INSN_OR_M_D_M, "or-m.d-m", "or-m.d", 16, 2056 { 0, { { { (1<<MACH_BASE), 0 } } } } 2057 }, 2058/* or.b ${sconst8}],${Rd} */ 2059 { 2060 CRIS_INSN_ORCBR, "orcbr", "or.b", 32, 2061 { 0, { { { (1<<MACH_BASE), 0 } } } } 2062 }, 2063/* or.w ${sconst16}],${Rd} */ 2064 { 2065 CRIS_INSN_ORCWR, "orcwr", "or.w", 32, 2066 { 0, { { { (1<<MACH_BASE), 0 } } } } 2067 }, 2068/* or.d ${const32}],${Rd} */ 2069 { 2070 CRIS_INSN_ORCDR, "orcdr", "or.d", 48, 2071 { 0, { { { (1<<MACH_BASE), 0 } } } } 2072 }, 2073/* orq $i,$Rd */ 2074 { 2075 CRIS_INSN_ORQ, "orq", "orq", 16, 2076 { 0, { { { (1<<MACH_BASE), 0 } } } } 2077 }, 2078/* xor $Rs,$Rd */ 2079 { 2080 CRIS_INSN_XOR, "xor", "xor", 16, 2081 { 0, { { { (1<<MACH_BASE), 0 } } } } 2082 }, 2083/* not ${Rs} */ 2084 { 2085 CRIS_INSN_NOT, "not", "not", 16, 2086 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3), 0 } } } } 2087 }, 2088/* swap${swapoption} ${Rs} */ 2089 { 2090 CRIS_INSN_SWAP, "swap", "swap", 16, 2091 { 0, { { { (1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 2092 }, 2093/* asrr.b $Rs,$Rd */ 2094 { 2095 CRIS_INSN_ASRR_B_R, "asrr.b-r", "asrr.b", 16, 2096 { 0, { { { (1<<MACH_BASE), 0 } } } } 2097 }, 2098/* asrr.w $Rs,$Rd */ 2099 { 2100 CRIS_INSN_ASRR_W_R, "asrr.w-r", "asrr.w", 16, 2101 { 0, { { { (1<<MACH_BASE), 0 } } } } 2102 }, 2103/* asrr.d $Rs,$Rd */ 2104 { 2105 CRIS_INSN_ASRR_D_R, "asrr.d-r", "asrr.d", 16, 2106 { 0, { { { (1<<MACH_BASE), 0 } } } } 2107 }, 2108/* asrq $c,${Rd} */ 2109 { 2110 CRIS_INSN_ASRQ, "asrq", "asrq", 16, 2111 { 0, { { { (1<<MACH_BASE), 0 } } } } 2112 }, 2113/* lsrr.b $Rs,$Rd */ 2114 { 2115 CRIS_INSN_LSRR_B_R, "lsrr.b-r", "lsrr.b", 16, 2116 { 0, { { { (1<<MACH_BASE), 0 } } } } 2117 }, 2118/* lsrr.w $Rs,$Rd */ 2119 { 2120 CRIS_INSN_LSRR_W_R, "lsrr.w-r", "lsrr.w", 16, 2121 { 0, { { { (1<<MACH_BASE), 0 } } } } 2122 }, 2123/* lsrr.d $Rs,$Rd */ 2124 { 2125 CRIS_INSN_LSRR_D_R, "lsrr.d-r", "lsrr.d", 16, 2126 { 0, { { { (1<<MACH_BASE), 0 } } } } 2127 }, 2128/* lsrq $c,${Rd} */ 2129 { 2130 CRIS_INSN_LSRQ, "lsrq", "lsrq", 16, 2131 { 0, { { { (1<<MACH_BASE), 0 } } } } 2132 }, 2133/* lslr.b $Rs,$Rd */ 2134 { 2135 CRIS_INSN_LSLR_B_R, "lslr.b-r", "lslr.b", 16, 2136 { 0, { { { (1<<MACH_BASE), 0 } } } } 2137 }, 2138/* lslr.w $Rs,$Rd */ 2139 { 2140 CRIS_INSN_LSLR_W_R, "lslr.w-r", "lslr.w", 16, 2141 { 0, { { { (1<<MACH_BASE), 0 } } } } 2142 }, 2143/* lslr.d $Rs,$Rd */ 2144 { 2145 CRIS_INSN_LSLR_D_R, "lslr.d-r", "lslr.d", 16, 2146 { 0, { { { (1<<MACH_BASE), 0 } } } } 2147 }, 2148/* lslq $c,${Rd} */ 2149 { 2150 CRIS_INSN_LSLQ, "lslq", "lslq", 16, 2151 { 0, { { { (1<<MACH_BASE), 0 } } } } 2152 }, 2153/* $Rs,$Rd */ 2154 { 2155 CRIS_INSN_BTST, "btst", "", 16, 2156 { 0, { { { (1<<MACH_BASE), 0 } } } } 2157 }, 2158/* btstq $c,${Rd} */ 2159 { 2160 CRIS_INSN_BTSTQ, "btstq", "btstq", 16, 2161 { 0, { { { (1<<MACH_BASE), 0 } } } } 2162 }, 2163/* setf ${list-of-flags} */ 2164 { 2165 CRIS_INSN_SETF, "setf", "setf", 16, 2166 { 0, { { { (1<<MACH_BASE), 0 } } } } 2167 }, 2168/* clearf ${list-of-flags} */ 2169 { 2170 CRIS_INSN_CLEARF, "clearf", "clearf", 16, 2171 { 0, { { { (1<<MACH_BASE), 0 } } } } 2172 }, 2173/* rfe */ 2174 { 2175 CRIS_INSN_RFE, "rfe", "rfe", 16, 2176 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 2177 }, 2178/* sfe */ 2179 { 2180 CRIS_INSN_SFE, "sfe", "sfe", 16, 2181 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 2182 }, 2183/* rfg */ 2184 { 2185 CRIS_INSN_RFG, "rfg", "rfg", 16, 2186 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 2187 }, 2188/* rfn */ 2189 { 2190 CRIS_INSN_RFN, "rfn", "rfn", 16, 2191 { 0, { { { (1<<MACH_CRISV32), 0 } } } } 2192 }, 2193/* halt */ 2194 { 2195 CRIS_INSN_HALT, "halt", "halt", 16, 2196 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } } 2197 }, 2198/* b${cc} ${o-pcrel} */ 2199 { 2200 CRIS_INSN_BCC_B, "bcc-b", "b", 16, 2201 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 2202 }, 2203/* ba ${o-pcrel} */ 2204 { 2205 CRIS_INSN_BA_B, "ba-b", "ba", 16, 2206 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 2207 }, 2208/* b${cc} ${o-word-pcrel} */ 2209 { 2210 CRIS_INSN_BCC_W, "bcc-w", "b", 32, 2211 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 2212 }, 2213/* ba ${o-word-pcrel} */ 2214 { 2215 CRIS_INSN_BA_W, "ba-w", "ba", 32, 2216 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 2217 }, 2218/* jas ${Rs},${Pd} */ 2219 { 2220 CRIS_INSN_JAS_R, "jas-r", "jas", 16, 2221 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2222 }, 2223/* jump/jsr/jir ${Rs} */ 2224 { 2225 CRIS_INSN_JUMP_R, "jump-r", "jump/jsr/jir", 16, 2226 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2227 }, 2228/* jas ${const32},${Pd} */ 2229 { 2230 CRIS_INSN_JAS_C, "jas-c", "jas", 48, 2231 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2232 }, 2233/* jump/jsr/jir [${Rs}${inc}] */ 2234 { 2235 CRIS_INSN_JUMP_M, "jump-m", "jump/jsr/jir", 16, 2236 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2237 }, 2238/* jump/jsr/jir ${const32} */ 2239 { 2240 CRIS_INSN_JUMP_C, "jump-c", "jump/jsr/jir", 48, 2241 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2242 }, 2243/* jump ${Ps} */ 2244 { 2245 CRIS_INSN_JUMP_P, "jump-p", "jump", 16, 2246 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2247 }, 2248/* bas ${const32},${Pd} */ 2249 { 2250 CRIS_INSN_BAS_C, "bas-c", "bas", 48, 2251 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2252 }, 2253/* jasc ${Rs},${Pd} */ 2254 { 2255 CRIS_INSN_JASC_R, "jasc-r", "jasc", 16, 2256 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2257 }, 2258/* jasc ${const32},${Pd} */ 2259 { 2260 CRIS_INSN_JASC_C, "jasc-c", "jasc", 48, 2261 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2262 }, 2263/* basc ${const32},${Pd} */ 2264 { 2265 CRIS_INSN_BASC_C, "basc-c", "basc", 48, 2266 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_CRISV32), 0 } } } } 2267 }, 2268/* break $n */ 2269 { 2270 CRIS_INSN_BREAK, "break", "break", 16, 2271 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } 2272 }, 2273/* bound-r.b ${Rs},${Rd} */ 2274 { 2275 CRIS_INSN_BOUND_R_B_R, "bound-r.b-r", "bound-r.b", 16, 2276 { 0, { { { (1<<MACH_BASE), 0 } } } } 2277 }, 2278/* bound-r.w ${Rs},${Rd} */ 2279 { 2280 CRIS_INSN_BOUND_R_W_R, "bound-r.w-r", "bound-r.w", 16, 2281 { 0, { { { (1<<MACH_BASE), 0 } } } } 2282 }, 2283/* bound-r.d ${Rs},${Rd} */ 2284 { 2285 CRIS_INSN_BOUND_R_D_R, "bound-r.d-r", "bound-r.d", 16, 2286 { 0, { { { (1<<MACH_BASE), 0 } } } } 2287 }, 2288/* bound-m.b [${Rs}${inc}],${Rd} */ 2289 { 2290 CRIS_INSN_BOUND_M_B_M, "bound-m.b-m", "bound-m.b", 16, 2291 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2292 }, 2293/* bound-m.w [${Rs}${inc}],${Rd} */ 2294 { 2295 CRIS_INSN_BOUND_M_W_M, "bound-m.w-m", "bound-m.w", 16, 2296 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2297 }, 2298/* bound-m.d [${Rs}${inc}],${Rd} */ 2299 { 2300 CRIS_INSN_BOUND_M_D_M, "bound-m.d-m", "bound-m.d", 16, 2301 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2302 }, 2303/* bound.b [PC+],${Rd} */ 2304 { 2305 CRIS_INSN_BOUND_CB, "bound-cb", "bound.b", 32, 2306 { 0, { { { (1<<MACH_BASE), 0 } } } } 2307 }, 2308/* bound.w [PC+],${Rd} */ 2309 { 2310 CRIS_INSN_BOUND_CW, "bound-cw", "bound.w", 32, 2311 { 0, { { { (1<<MACH_BASE), 0 } } } } 2312 }, 2313/* bound.d [PC+],${Rd} */ 2314 { 2315 CRIS_INSN_BOUND_CD, "bound-cd", "bound.d", 48, 2316 { 0, { { { (1<<MACH_BASE), 0 } } } } 2317 }, 2318/* s${cc} ${Rd-sfield} */ 2319 { 2320 CRIS_INSN_SCC, "scc", "s", 16, 2321 { 0, { { { (1<<MACH_BASE), 0 } } } } 2322 }, 2323/* lz ${Rs},${Rd} */ 2324 { 2325 CRIS_INSN_LZ, "lz", "lz", 16, 2326 { 0, { { { (1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } 2327 }, 2328/* addoq $o,$Rs,ACR */ 2329 { 2330 CRIS_INSN_ADDOQ, "addoq", "addoq", 16, 2331 { 0, { { { (1<<MACH_BASE), 0 } } } } 2332 }, 2333/* bdapq $o,PC */ 2334 { 2335 CRIS_INSN_BDAPQPC, "bdapqpc", "bdapq", 16, 2336 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2337 }, 2338/* bdap ${sconst32},PC */ 2339 { 2340 CRIS_INSN_BDAP_32_PC, "bdap-32-pc", "bdap", 48, 2341 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2342 }, 2343/* move [PC+],P0 */ 2344 { 2345 CRIS_INSN_MOVE_M_PCPLUS_P0, "move-m-pcplus-p0", "move", 16, 2346 { 0|A(COND_CTI), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2347 }, 2348/* move [SP+],P8 */ 2349 { 2350 CRIS_INSN_MOVE_M_SPPLUS_P8, "move-m-spplus-p8", "move", 16, 2351 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2352 }, 2353/* addo-m.b [${Rs}${inc}],$Rd,ACR */ 2354 { 2355 CRIS_INSN_ADDO_M_B_M, "addo-m.b-m", "addo-m.b", 16, 2356 { 0, { { { (1<<MACH_BASE), 0 } } } } 2357 }, 2358/* addo-m.w [${Rs}${inc}],$Rd,ACR */ 2359 { 2360 CRIS_INSN_ADDO_M_W_M, "addo-m.w-m", "addo-m.w", 16, 2361 { 0, { { { (1<<MACH_BASE), 0 } } } } 2362 }, 2363/* addo-m.d [${Rs}${inc}],$Rd,ACR */ 2364 { 2365 CRIS_INSN_ADDO_M_D_M, "addo-m.d-m", "addo-m.d", 16, 2366 { 0, { { { (1<<MACH_BASE), 0 } } } } 2367 }, 2368/* addo.b [PC+],$Rd,ACR */ 2369 { 2370 CRIS_INSN_ADDO_CB, "addo-cb", "addo.b", 32, 2371 { 0, { { { (1<<MACH_BASE), 0 } } } } 2372 }, 2373/* addo.w [PC+],$Rd,ACR */ 2374 { 2375 CRIS_INSN_ADDO_CW, "addo-cw", "addo.w", 32, 2376 { 0, { { { (1<<MACH_BASE), 0 } } } } 2377 }, 2378/* addo.d [PC+],$Rd,ACR */ 2379 { 2380 CRIS_INSN_ADDO_CD, "addo-cd", "addo.d", 48, 2381 { 0, { { { (1<<MACH_BASE), 0 } } } } 2382 }, 2383/* dip [${Rs}${inc}] */ 2384 { 2385 CRIS_INSN_DIP_M, "dip-m", "dip", 16, 2386 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2387 }, 2388/* dip [PC+] */ 2389 { 2390 CRIS_INSN_DIP_C, "dip-c", "dip", 48, 2391 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2392 }, 2393/* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */ 2394 { 2395 CRIS_INSN_ADDI_ACR_B_R, "addi-acr.b-r", "addi-acr.b", 16, 2396 { 0, { { { (1<<MACH_BASE), 0 } } } } 2397 }, 2398/* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */ 2399 { 2400 CRIS_INSN_ADDI_ACR_W_R, "addi-acr.w-r", "addi-acr.w", 16, 2401 { 0, { { { (1<<MACH_BASE), 0 } } } } 2402 }, 2403/* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */ 2404 { 2405 CRIS_INSN_ADDI_ACR_D_R, "addi-acr.d-r", "addi-acr.d", 16, 2406 { 0, { { { (1<<MACH_BASE), 0 } } } } 2407 }, 2408/* biap-pc.b ${Rs-dfield}.m,PC */ 2409 { 2410 CRIS_INSN_BIAP_PC_B_R, "biap-pc.b-r", "biap-pc.b", 16, 2411 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2412 }, 2413/* biap-pc.w ${Rs-dfield}.m,PC */ 2414 { 2415 CRIS_INSN_BIAP_PC_W_R, "biap-pc.w-r", "biap-pc.w", 16, 2416 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2417 }, 2418/* biap-pc.d ${Rs-dfield}.m,PC */ 2419 { 2420 CRIS_INSN_BIAP_PC_D_R, "biap-pc.d-r", "biap-pc.d", 16, 2421 { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } 2422 }, 2423/* fidxi [$Rs] */ 2424 { 2425 CRIS_INSN_FIDXI, "fidxi", "fidxi", 16, 2426 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } } 2427 }, 2428/* fidxi [$Rs] */ 2429 { 2430 CRIS_INSN_FTAGI, "ftagi", "fidxi", 16, 2431 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } } 2432 }, 2433/* fidxd [$Rs] */ 2434 { 2435 CRIS_INSN_FIDXD, "fidxd", "fidxd", 16, 2436 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } } 2437 }, 2438/* ftagd [$Rs] */ 2439 { 2440 CRIS_INSN_FTAGD, "ftagd", "ftagd", 16, 2441 { 0|A(UNCOND_CTI), { { { (1<<MACH_CRISV32), 0 } } } } 2442 }, 2443}; 2444 2445#undef OP 2446#undef A 2447 2448/* Initialize anything needed to be done once, before any cpu_open call. */ 2449 2450static void 2451init_tables (void) 2452{ 2453} 2454 2455#ifndef opcodes_error_handler 2456#define opcodes_error_handler(...) \ 2457 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) 2458#endif 2459 2460static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 2461static void build_hw_table (CGEN_CPU_TABLE *); 2462static void build_ifield_table (CGEN_CPU_TABLE *); 2463static void build_operand_table (CGEN_CPU_TABLE *); 2464static void build_insn_table (CGEN_CPU_TABLE *); 2465static void cris_cgen_rebuild_tables (CGEN_CPU_TABLE *); 2466 2467/* Subroutine of cris_cgen_cpu_open to look up a mach via its bfd name. */ 2468 2469static const CGEN_MACH * 2470lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 2471{ 2472 while (table->name) 2473 { 2474 if (strcmp (name, table->bfd_name) == 0) 2475 return table; 2476 ++table; 2477 } 2478 return NULL; 2479} 2480 2481/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ 2482 2483static void 2484build_hw_table (CGEN_CPU_TABLE *cd) 2485{ 2486 int i; 2487 int machs = cd->machs; 2488 const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0]; 2489 /* MAX_HW is only an upper bound on the number of selected entries. 2490 However each entry is indexed by it's enum so there can be holes in 2491 the table. */ 2492 const CGEN_HW_ENTRY **selected = 2493 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 2494 2495 cd->hw_table.init_entries = init; 2496 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 2497 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 2498 /* ??? For now we just use machs to determine which ones we want. */ 2499 for (i = 0; init[i].name != NULL; ++i) 2500 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 2501 & machs) 2502 selected[init[i].type] = &init[i]; 2503 cd->hw_table.entries = selected; 2504 cd->hw_table.num_entries = MAX_HW; 2505} 2506 2507/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ 2508 2509static void 2510build_ifield_table (CGEN_CPU_TABLE *cd) 2511{ 2512 cd->ifld_table = & cris_cgen_ifld_table[0]; 2513} 2514 2515/* Subroutine of cris_cgen_cpu_open to build the hardware table. */ 2516 2517static void 2518build_operand_table (CGEN_CPU_TABLE *cd) 2519{ 2520 int i; 2521 int machs = cd->machs; 2522 const CGEN_OPERAND *init = & cris_cgen_operand_table[0]; 2523 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 2524 However each entry is indexed by it's enum so there can be holes in 2525 the table. */ 2526 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 2527 2528 cd->operand_table.init_entries = init; 2529 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 2530 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 2531 /* ??? For now we just use mach to determine which ones we want. */ 2532 for (i = 0; init[i].name != NULL; ++i) 2533 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 2534 & machs) 2535 selected[init[i].type] = &init[i]; 2536 cd->operand_table.entries = selected; 2537 cd->operand_table.num_entries = MAX_OPERANDS; 2538} 2539 2540/* Subroutine of cris_cgen_cpu_open to build the hardware table. 2541 ??? This could leave out insns not supported by the specified mach/isa, 2542 but that would cause errors like "foo only supported by bar" to become 2543 "unknown insn", so for now we include all insns and require the app to 2544 do the checking later. 2545 ??? On the other hand, parsing of such insns may require their hardware or 2546 operand elements to be in the table [which they mightn't be]. */ 2547 2548static void 2549build_insn_table (CGEN_CPU_TABLE *cd) 2550{ 2551 int i; 2552 const CGEN_IBASE *ib = & cris_cgen_insn_table[0]; 2553 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 2554 2555 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 2556 for (i = 0; i < MAX_INSNS; ++i) 2557 insns[i].base = &ib[i]; 2558 cd->insn_table.init_entries = insns; 2559 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 2560 cd->insn_table.num_init_entries = MAX_INSNS; 2561} 2562 2563/* Subroutine of cris_cgen_cpu_open to rebuild the tables. */ 2564 2565static void 2566cris_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 2567{ 2568 int i; 2569 CGEN_BITSET *isas = cd->isas; 2570 unsigned int machs = cd->machs; 2571 2572 cd->int_insn_p = CGEN_INT_INSN_P; 2573 2574 /* Data derived from the isa spec. */ 2575#define UNSET (CGEN_SIZE_UNKNOWN + 1) 2576 cd->default_insn_bitsize = UNSET; 2577 cd->base_insn_bitsize = UNSET; 2578 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 2579 cd->max_insn_bitsize = 0; 2580 for (i = 0; i < MAX_ISAS; ++i) 2581 if (cgen_bitset_contains (isas, i)) 2582 { 2583 const CGEN_ISA *isa = & cris_cgen_isa_table[i]; 2584 2585 /* Default insn sizes of all selected isas must be 2586 equal or we set the result to 0, meaning "unknown". */ 2587 if (cd->default_insn_bitsize == UNSET) 2588 cd->default_insn_bitsize = isa->default_insn_bitsize; 2589 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 2590 ; /* This is ok. */ 2591 else 2592 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 2593 2594 /* Base insn sizes of all selected isas must be equal 2595 or we set the result to 0, meaning "unknown". */ 2596 if (cd->base_insn_bitsize == UNSET) 2597 cd->base_insn_bitsize = isa->base_insn_bitsize; 2598 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 2599 ; /* This is ok. */ 2600 else 2601 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 2602 2603 /* Set min,max insn sizes. */ 2604 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 2605 cd->min_insn_bitsize = isa->min_insn_bitsize; 2606 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 2607 cd->max_insn_bitsize = isa->max_insn_bitsize; 2608 } 2609 2610 /* Data derived from the mach spec. */ 2611 for (i = 0; i < MAX_MACHS; ++i) 2612 if (((1 << i) & machs) != 0) 2613 { 2614 const CGEN_MACH *mach = & cris_cgen_mach_table[i]; 2615 2616 if (mach->insn_chunk_bitsize != 0) 2617 { 2618 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 2619 { 2620 opcodes_error_handler 2621 (/* xgettext:c-format */ 2622 _("internal error: cris_cgen_rebuild_tables: " 2623 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), 2624 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 2625 abort (); 2626 } 2627 2628 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 2629 } 2630 } 2631 2632 /* Determine which hw elements are used by MACH. */ 2633 build_hw_table (cd); 2634 2635 /* Build the ifield table. */ 2636 build_ifield_table (cd); 2637 2638 /* Determine which operands are used by MACH/ISA. */ 2639 build_operand_table (cd); 2640 2641 /* Build the instruction table. */ 2642 build_insn_table (cd); 2643} 2644 2645/* Initialize a cpu table and return a descriptor. 2646 It's much like opening a file, and must be the first function called. 2647 The arguments are a set of (type/value) pairs, terminated with 2648 CGEN_CPU_OPEN_END. 2649 2650 Currently supported values: 2651 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 2652 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 2653 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 2654 CGEN_CPU_OPEN_ENDIAN: specify endian choice 2655 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice 2656 CGEN_CPU_OPEN_END: terminates arguments 2657 2658 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 2659 precluded. */ 2660 2661CGEN_CPU_DESC 2662cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 2663{ 2664 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 2665 static int init_p; 2666 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 2667 unsigned int machs = 0; /* 0 = "unspecified" */ 2668 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 2669 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; 2670 va_list ap; 2671 2672 if (! init_p) 2673 { 2674 init_tables (); 2675 init_p = 1; 2676 } 2677 2678 memset (cd, 0, sizeof (*cd)); 2679 2680 va_start (ap, arg_type); 2681 while (arg_type != CGEN_CPU_OPEN_END) 2682 { 2683 switch (arg_type) 2684 { 2685 case CGEN_CPU_OPEN_ISAS : 2686 isas = va_arg (ap, CGEN_BITSET *); 2687 break; 2688 case CGEN_CPU_OPEN_MACHS : 2689 machs = va_arg (ap, unsigned int); 2690 break; 2691 case CGEN_CPU_OPEN_BFDMACH : 2692 { 2693 const char *name = va_arg (ap, const char *); 2694 const CGEN_MACH *mach = 2695 lookup_mach_via_bfd_name (cris_cgen_mach_table, name); 2696 2697 if (mach != NULL) 2698 machs |= 1 << mach->num; 2699 break; 2700 } 2701 case CGEN_CPU_OPEN_ENDIAN : 2702 endian = va_arg (ap, enum cgen_endian); 2703 break; 2704 case CGEN_CPU_OPEN_INSN_ENDIAN : 2705 insn_endian = va_arg (ap, enum cgen_endian); 2706 break; 2707 default : 2708 opcodes_error_handler 2709 (/* xgettext:c-format */ 2710 _("internal error: cris_cgen_cpu_open: " 2711 "unsupported argument `%d'"), 2712 arg_type); 2713 abort (); /* ??? return NULL? */ 2714 } 2715 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 2716 } 2717 va_end (ap); 2718 2719 /* Mach unspecified means "all". */ 2720 if (machs == 0) 2721 machs = (1 << MAX_MACHS) - 1; 2722 /* Base mach is always selected. */ 2723 machs |= 1; 2724 if (endian == CGEN_ENDIAN_UNKNOWN) 2725 { 2726 /* ??? If target has only one, could have a default. */ 2727 opcodes_error_handler 2728 (/* xgettext:c-format */ 2729 _("internal error: cris_cgen_cpu_open: no endianness specified")); 2730 abort (); 2731 } 2732 2733 cd->isas = cgen_bitset_copy (isas); 2734 cd->machs = machs; 2735 cd->endian = endian; 2736 cd->insn_endian 2737 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); 2738 2739 /* Table (re)builder. */ 2740 cd->rebuild_tables = cris_cgen_rebuild_tables; 2741 cris_cgen_rebuild_tables (cd); 2742 2743 /* Default to not allowing signed overflow. */ 2744 cd->signed_overflow_ok_p = 0; 2745 2746 return (CGEN_CPU_DESC) cd; 2747} 2748 2749/* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 2750 MACH_NAME is the bfd name of the mach. */ 2751 2752CGEN_CPU_DESC 2753cris_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 2754{ 2755 return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 2756 CGEN_CPU_OPEN_ENDIAN, endian, 2757 CGEN_CPU_OPEN_END); 2758} 2759 2760/* Close a cpu table. 2761 ??? This can live in a machine independent file, but there's currently 2762 no place to put this file (there's no libcgen). libopcodes is the wrong 2763 place as some simulator ports use this but they don't use libopcodes. */ 2764 2765void 2766cris_cgen_cpu_close (CGEN_CPU_DESC cd) 2767{ 2768 unsigned int i; 2769 const CGEN_INSN *insns; 2770 2771 if (cd->macro_insn_table.init_entries) 2772 { 2773 insns = cd->macro_insn_table.init_entries; 2774 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 2775 if (CGEN_INSN_RX ((insns))) 2776 regfree (CGEN_INSN_RX (insns)); 2777 } 2778 2779 if (cd->insn_table.init_entries) 2780 { 2781 insns = cd->insn_table.init_entries; 2782 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 2783 if (CGEN_INSN_RX (insns)) 2784 regfree (CGEN_INSN_RX (insns)); 2785 } 2786 2787 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 2788 free ((CGEN_INSN *) cd->insn_table.init_entries); 2789 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 2790 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 2791 free (cd); 2792} 2793 2794