1/* Target-dependent code for NetBSD on RISC-V processors.
2   Copyright (C) 2018-2020 Free Software Foundation, Inc.
3
4   This file is part of GDB.
5
6   This program is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3 of the License, or
9   (at your option) any later version.
10
11   This program is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18
19#include "defs.h"
20#include "netbsd-tdep.h"
21#include "osabi.h"
22#include "riscv-tdep.h"
23#include "riscv-netbsd-tdep.h"
24#include "solib-svr4.h"
25#include "target.h"
26#include "trad-frame.h"
27#include "tramp-frame.h"
28#include "gdbarch.h"
29#include "inferior.h"
30
31/* Register maps.  */
32
33static const struct regcache_map_entry riscv_nbsd_gregmap[] =
34  {
35    { 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */
36    { 1,  RISCV_PC_REGNUM, 0 },
37    { 0 }
38  };
39
40static const struct regcache_map_entry riscv_nbsd_fpregmap[] =
41  {
42    { 32, RISCV_FIRST_FP_REGNUM, 16 },
43    { 1, RISCV_CSR_FCSR_REGNUM, 8 },
44    { 0 }
45  };
46
47/* Supply the general-purpose registers stored in GREGS to REGCACHE.
48   This function only exists to supply the always-zero x0 in addition
49   to the registers in GREGS.  */
50
51static void
52riscv_nbsd_supply_gregset (const struct regset *regset,
53			   struct regcache *regcache, int regnum,
54			   const void *gregs, size_t len)
55{
56  regcache->supply_regset (&riscv_nbsd_gregset, regnum, gregs, len);
57  if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
58    regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
59}
60
61/* Register set definitions.  */
62
63const struct regset riscv_nbsd_gregset =
64  {
65    riscv_nbsd_gregmap,
66    riscv_nbsd_supply_gregset, regcache_collect_regset
67  };
68
69const struct regset riscv_nbsd_fpregset =
70  {
71    riscv_nbsd_fpregmap,
72    regcache_supply_regset, regcache_collect_regset
73  };
74
75/* Implement the "iterate_over_regset_sections" gdbarch method.  */
76
77static void
78riscv_nbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
79					 iterate_over_regset_sections_cb *cb,
80					 void *cb_data,
81					 const struct regcache *regcache)
82{
83  cb (".reg", RISCV_NBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
84      RISCV_NBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
85      &riscv_nbsd_gregset, NULL, cb_data);
86  cb (".reg2", RISCV_NBSD_SIZEOF_FPREGSET, RISCV_NBSD_SIZEOF_FPREGSET,
87      &riscv_nbsd_fpregset, NULL, cb_data);
88}
89
90/* In a signal frame, sp points to a 'struct sigframe' which is
91   defined as:
92
93   struct sigframe {
94	   siginfo_t	sf_si;
95	   ucontext_t	sf_uc;
96   };
97
98   ucontext_t is defined as:
99
100   struct __ucontext {
101	   sigset_t	uc_sigmask;
102	   mcontext_t	uc_mcontext;
103	   ...
104   };
105
106   The mcontext_t contains the general purpose register set followed
107   by the floating point register set.  The floating point register
108   set is only valid if the _MC_FP_VALID flag is set in mc_flags.  */
109
110#define RISCV_SIGFRAME_UCONTEXT_OFFSET 		80
111#define RISCV_UCONTEXT_MCONTEXT_OFFSET		16
112#define RISCV_MCONTEXT_FLAG_FP_VALID		0x1
113
114/* Implement the "init" method of struct tramp_frame.  */
115
116static void
117riscv_nbsd_sigframe_init (const struct tramp_frame *self,
118			  frame_info_ptr this_frame,
119			  struct trad_frame_cache *this_cache,
120			  CORE_ADDR func)
121{
122  struct gdbarch *gdbarch = get_frame_arch (this_frame);
123  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
124  CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
125  CORE_ADDR mcontext_addr
126    = (sp
127       + RISCV_SIGFRAME_UCONTEXT_OFFSET
128       + RISCV_UCONTEXT_MCONTEXT_OFFSET);
129  gdb_byte buf[4];
130
131  trad_frame_set_reg_regmap (this_cache, riscv_nbsd_gregmap, mcontext_addr,
132			     RISCV_NBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));
133
134  CORE_ADDR fpregs_addr
135    = mcontext_addr + RISCV_NBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
136  CORE_ADDR fp_flags_addr
137    = fpregs_addr + RISCV_NBSD_SIZEOF_FPREGSET;
138  if (target_read_memory (fp_flags_addr, buf, 4) == 0
139      && (extract_unsigned_integer (buf, 4, byte_order)
140	  & RISCV_MCONTEXT_FLAG_FP_VALID))
141    trad_frame_set_reg_regmap (this_cache, riscv_nbsd_fpregmap, fpregs_addr,
142			       RISCV_NBSD_SIZEOF_FPREGSET);
143
144  trad_frame_set_id (this_cache, frame_id_build (sp, func));
145}
146
147/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
148   instructions.  The signal trampoline on NetBSD uses a mix of
149   these, but tramp_frame assumes a fixed instruction size.  To cope,
150   claim that all instructions are 16 bits and use two "slots" for
151   32-bit instructions.  */
152
153static const struct tramp_frame riscv_nbsd_sigframe =
154{
155  SIGTRAMP_FRAME,
156  2,
157  {
158    {0x850a, ULONGEST_MAX},		/* mov  a0, sp  */
159    {0x0513, ULONGEST_MAX},		/* addi a0, a0, #SF_UC  */
160    {0x0505, ULONGEST_MAX},
161    {0x0293, ULONGEST_MAX},		/* li   t0, #SYS_sigreturn  */
162    {0x1a10, ULONGEST_MAX},
163    {0x0073, ULONGEST_MAX},		/* ecall  */
164    {0x0000, ULONGEST_MAX},
165    {TRAMP_SENTINEL_INSN, ULONGEST_MAX}
166  },
167  riscv_nbsd_sigframe_init
168};
169
170
171#if 0
172/* Implement the "get_thread_local_address" gdbarch method.  */
173
174static CORE_ADDR
175riscv_nbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
176				     CORE_ADDR lm_addr, CORE_ADDR offset)
177{
178  struct regcache *regcache;
179
180  regcache = get_thread_arch_regcache (current_inferior ()->process_target (),
181				       ptid, gdbarch);
182
183  target_fetch_registers (regcache, RISCV_TP_REGNUM);
184
185  ULONGEST tp;
186  if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
187    error (_("Unable to fetch %%tp"));
188
189  /* %tp points to the end of the TCB which contains two pointers.
190      The first pointer in the TCB points to the DTV array.  */
191  CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
192  return nbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
193}
194#endif
195
196
197/* Implement the 'init_osabi' method of struct gdb_osabi_handler.  */
198
199static void
200riscv_nbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
201{
202  /* Generic NetBSD support.  */
203  nbsd_init_abi (info, gdbarch);
204
205  set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
206
207  set_solib_svr4_fetch_link_map_offsets (gdbarch,
208					 (riscv_isa_xlen (gdbarch) == 4
209					  ? svr4_ilp32_fetch_link_map_offsets
210					  : svr4_lp64_fetch_link_map_offsets));
211
212  tramp_frame_prepend_unwinder (gdbarch, &riscv_nbsd_sigframe);
213
214  set_gdbarch_iterate_over_regset_sections
215    (gdbarch, riscv_nbsd_iterate_over_regset_sections);
216
217  set_gdbarch_fetch_tls_load_module_address (gdbarch,
218					     svr4_fetch_objfile_link_map);
219#if 0
220  set_gdbarch_get_thread_local_address (gdbarch,
221					riscv_nbsd_get_thread_local_address);
222#endif
223}
224
225void _initialize_riscv_nbsd_tdep ();
226void
227_initialize_riscv_nbsd_tdep ()
228{
229  gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_NETBSD,
230			  riscv_nbsd_init_abi);
231}
232