1#ifndef SIM_MAIN_H 2#define SIM_MAIN_H 3 4/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ 5 6#define WITH_TARGET_WORD_MSB 31 7 8#include "config.h" 9#include "sim-basics.h" 10#include "sim-signal.h" 11#include "sim-fpu.h" 12#include "sim-base.h" 13 14#include "simops.h" 15#include "bfd.h" 16 17 18typedef signed8 int8; 19typedef unsigned8 uint8; 20typedef signed16 int16; 21typedef unsigned16 uint16; 22typedef signed32 int32; 23typedef unsigned32 uint32; 24typedef unsigned32 reg_t; 25typedef unsigned64 reg64_t; 26 27 28/* The current state of the processor; registers, memory, etc. */ 29 30typedef struct _v850_regs { 31 reg_t regs[32]; /* general-purpose registers */ 32 reg_t sregs[32]; /* system registers, including psw */ 33 reg_t pc; 34 int dummy_mem; /* where invalid accesses go */ 35 reg_t mpu0_sregs[28]; /* mpu0 system registers */ 36 reg_t mpu1_sregs[28]; /* mpu1 system registers */ 37 reg_t fpu_sregs[28]; /* fpu system registers */ 38 reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */ 39 reg64_t vregs[32]; /* vector registers. */ 40} v850_regs; 41 42struct _sim_cpu 43{ 44 /* ... simulator specific members ... */ 45 v850_regs reg; 46 reg_t psw_mask; /* only allow non-reserved bits to be set */ 47 sim_event *pending_nmi; 48 /* ... base type ... */ 49 sim_cpu_base base; 50}; 51 52struct sim_state { 53 sim_cpu *cpu[MAX_NR_PROCESSORS]; 54#if 0 55 SIM_ADDR rom_size; 56 SIM_ADDR low_end; 57 SIM_ADDR high_start; 58 SIM_ADDR high_base; 59 void *mem; 60#endif 61 sim_state_base base; 62}; 63 64/* For compatibility, until all functions converted to passing 65 SIM_DESC as an argument */ 66extern SIM_DESC simulator; 67 68 69#define V850_ROM_SIZE 0x8000 70#define V850_LOW_END 0x200000 71#define V850_HIGH_START 0xffe000 72 73 74/* Because we are still using the old semantic table, provide compat 75 macro's that store the instruction where the old simops expects 76 it. */ 77 78extern uint32 OP[4]; 79#if 0 80OP[0] = inst & 0x1f; /* RRRRR -> reg1 */ 81OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */ 82OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */ 83OP[3] = inst; 84#endif 85 86#define SAVE_1 \ 87PC = cia; \ 88OP[0] = instruction_0 & 0x1f; \ 89OP[1] = (instruction_0 >> 11) & 0x1f; \ 90OP[2] = 0; \ 91OP[3] = instruction_0 92 93#define COMPAT_1(CALL) \ 94SAVE_1; \ 95PC += (CALL); \ 96nia = PC 97 98#define SAVE_2 \ 99PC = cia; \ 100OP[0] = instruction_0 & 0x1f; \ 101OP[1] = (instruction_0 >> 11) & 0x1f; \ 102OP[2] = instruction_1; \ 103OP[3] = (instruction_1 << 16) | instruction_0 104 105#define COMPAT_2(CALL) \ 106SAVE_2; \ 107PC += (CALL); \ 108nia = PC 109 110 111/* new */ 112#define GR ((CPU)->reg.regs) 113#define SR ((CPU)->reg.sregs) 114#define VR ((CPU)->reg.vregs) 115#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs) 116#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs) 117#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs) 118 119/* old */ 120#define State (STATE_CPU (simulator, 0)->reg) 121#define PC (State.pc) 122#define SP_REGNO 3 123#define SP (State.regs[SP_REGNO]) 124#define EP (State.regs[30]) 125 126#define EIPC (State.sregs[0]) 127#define EIPSW (State.sregs[1]) 128#define FEPC (State.sregs[2]) 129#define FEPSW (State.sregs[3]) 130#define ECR (State.sregs[4]) 131#define PSW (State.sregs[5]) 132#define PSW_REGNO 5 133#define EIIC (State.sregs[13]) 134#define FEIC (State.sregs[14]) 135#define DBIC (SR[15]) 136#define CTPC (SR[16]) 137#define CTPSW (SR[17]) 138#define DBPC (State.sregs[18]) 139#define DBPSW (State.sregs[19]) 140#define CTBP (State.sregs[20]) 141#define DIR (SR[21]) 142#define EIWR (SR[28]) 143#define FEWR (SR[29]) 144#define DBWR (SR[30]) 145#define BSEL (SR[31]) 146 147#define PSW_US BIT32 (8) 148#define PSW_NP 0x80 149#define PSW_EP 0x40 150#define PSW_ID 0x20 151#define PSW_SAT 0x10 152#define PSW_CY 0x8 153#define PSW_OV 0x4 154#define PSW_S 0x2 155#define PSW_Z 0x1 156 157#define PSW_NPV (1<<18) 158#define PSW_DMP (1<<17) 159#define PSW_IMP (1<<16) 160 161#define ECR_EICC 0x0000ffff 162#define ECR_FECC 0xffff0000 163 164/* FPU */ 165 166#define FPSR (FPU_SR[6]) 167#define FPSR_REGNO 6 168#define FPEPC (FPU_SR[7]) 169#define FPST (FPU_SR[8]) 170#define FPST_REGNO 8 171#define FPCC (FPU_SR[9]) 172#define FPCFG (FPU_SR[10]) 173#define FPCFG_REGNO 10 174 175#define FPSR_DEM 0x00200000 176#define FPSR_SEM 0x00100000 177#define FPSR_RM 0x000c0000 178#define FPSR_RN 0x00000000 179#define FPSR_FS 0x00020000 180#define FPSR_PR 0x00010000 181 182#define FPSR_XC 0x0000fc00 183#define FPSR_XCE 0x00008000 184#define FPSR_XCV 0x00004000 185#define FPSR_XCZ 0x00002000 186#define FPSR_XCO 0x00001000 187#define FPSR_XCU 0x00000800 188#define FPSR_XCI 0x00000400 189 190#define FPSR_XE 0x000003e0 191#define FPSR_XEV 0x00000200 192#define FPSR_XEZ 0x00000100 193#define FPSR_XEO 0x00000080 194#define FPSR_XEU 0x00000040 195#define FPSR_XEI 0x00000020 196 197#define FPSR_XP 0x0000001f 198#define FPSR_XPV 0x00000010 199#define FPSR_XPZ 0x00000008 200#define FPSR_XPO 0x00000004 201#define FPSR_XPU 0x00000002 202#define FPSR_XPI 0x00000001 203 204#define FPST_PR 0x00008000 205#define FPST_XCE 0x00002000 206#define FPST_XCV 0x00001000 207#define FPST_XCZ 0x00000800 208#define FPST_XCO 0x00000400 209#define FPST_XCU 0x00000200 210#define FPST_XCI 0x00000100 211 212#define FPST_XPV 0x00000010 213#define FPST_XPZ 0x00000008 214#define FPST_XPO 0x00000004 215#define FPST_XPU 0x00000002 216#define FPST_XPI 0x00000001 217 218#define FPCFG_RM 0x00000180 219#define FPCFG_XEV 0x00000010 220#define FPCFG_XEZ 0x00000008 221#define FPCFG_XEO 0x00000004 222#define FPCFG_XEU 0x00000002 223#define FPCFG_XEI 0x00000001 224 225#define GET_FPCC()\ 226 ((FPSR >> 24) &0xf) 227 228#define CLEAR_FPCC(bbb)\ 229 (FPSR &= ~(1 << (bbb+24))) 230 231#define SET_FPCC(bbb)\ 232 (FPSR |= 1 << (bbb+24)) 233 234#define TEST_FPCC(bbb)\ 235 ((FPSR & (1 << (bbb+24))) != 0) 236 237#define FPSR_GET_ROUND() \ 238 (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \ 239 : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \ 240 : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \ 241 : sim_fpu_round_zero) 242 243 244enum FPU_COMPARE { 245 FPU_CMP_F = 0, 246 FPU_CMP_UN, 247 FPU_CMP_EQ, 248 FPU_CMP_UEQ, 249 FPU_CMP_OLT, 250 FPU_CMP_ULT, 251 FPU_CMP_OLE, 252 FPU_CMP_ULE, 253 FPU_CMP_SF, 254 FPU_CMP_NGLE, 255 FPU_CMP_SEQ, 256 FPU_CMP_NGL, 257 FPU_CMP_LT, 258 FPU_CMP_NGE, 259 FPU_CMP_LE, 260 FPU_CMP_NGT 261}; 262 263 264/* MPU */ 265#define MPM (MPU1_SR[0]) 266#define MPC (MPU1_SR[1]) 267#define MPC_REGNO 1 268#define TID (MPU1_SR[2]) 269#define PPA (MPU1_SR[3]) 270#define PPM (MPU1_SR[4]) 271#define PPC (MPU1_SR[5]) 272#define DCC (MPU1_SR[6]) 273#define DCV0 (MPU1_SR[7]) 274#define DCV1 (MPU1_SR[8]) 275#define SPAL (MPU1_SR[10]) 276#define SPAU (MPU1_SR[11]) 277#define IPA0L (MPU1_SR[12]) 278#define IPA0U (MPU1_SR[13]) 279#define IPA1L (MPU1_SR[14]) 280#define IPA1U (MPU1_SR[15]) 281#define IPA2L (MPU1_SR[16]) 282#define IPA2U (MPU1_SR[17]) 283#define IPA3L (MPU1_SR[18]) 284#define IPA3U (MPU1_SR[19]) 285#define DPA0L (MPU1_SR[20]) 286#define DPA0U (MPU1_SR[21]) 287#define DPA1L (MPU1_SR[22]) 288#define DPA1U (MPU1_SR[23]) 289#define DPA2L (MPU1_SR[24]) 290#define DPA2U (MPU1_SR[25]) 291#define DPA3L (MPU1_SR[26]) 292#define DPA3U (MPU1_SR[27]) 293 294#define PPC_PPE 0x1 295#define SPAL_SPE 0x1 296#define SPAL_SPS 0x10 297 298#define VIP (MPU0_SR[0]) 299#define VMECR (MPU0_SR[4]) 300#define VMTID (MPU0_SR[5]) 301#define VMADR (MPU0_SR[6]) 302#define VPECR (MPU0_SR[8]) 303#define VPTID (MPU0_SR[9]) 304#define VPADR (MPU0_SR[10]) 305#define VDECR (MPU0_SR[12]) 306#define VDTID (MPU0_SR[13]) 307 308#define MPM_AUE 0x2 309#define MPM_MPE 0x1 310 311#define VMECR_VMX 0x2 312#define VMECR_VMR 0x4 313#define VMECR_VMW 0x8 314#define VMECR_VMS 0x10 315#define VMECR_VMRMW 0x20 316#define VMECR_VMMS 0x40 317 318#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80) 319#define IPA_IPE 0x1 320#define IPA_IPX 0x2 321#define IPA_IPR 0x4 322#define IPE0 (IPA0L & IPA_IPE) 323#define IPE1 (IPA1L & IPA_IPE) 324#define IPE2 (IPA2L & IPA_IPE) 325#define IPE3 (IPA3L & IPA_IPE) 326#define IPX0 (IPA0L & IPA_IPX) 327#define IPX1 (IPA1L & IPA_IPX) 328#define IPX2 (IPA2L & IPA_IPX) 329#define IPX3 (IPA3L & IPA_IPX) 330#define IPR0 (IPA0L & IPA_IPR) 331#define IPR1 (IPA1L & IPA_IPR) 332#define IPR2 (IPA2L & IPA_IPR) 333#define IPR3 (IPA3L & IPA_IPR) 334 335#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80) 336#define DPA_DPE 0x1 337#define DPA_DPR 0x4 338#define DPA_DPW 0x8 339#define DPE0 (DPA0L & DPA_DPE) 340#define DPE1 (DPA1L & DPA_DPE) 341#define DPE2 (DPA2L & DPA_DPE) 342#define DPE3 (DPA3L & DPA_DPE) 343#define DPR0 (DPA0L & DPA_DPR) 344#define DPR1 (DPA1L & DPA_DPR) 345#define DPR2 (DPA2L & DPA_DPR) 346#define DPR3 (DPA3L & DPA_DPR) 347#define DPW0 (DPA0L & DPA_DPW) 348#define DPW1 (DPA1L & DPA_DPW) 349#define DPW2 (DPA2L & DPA_DPW) 350#define DPW3 (DPA3L & DPA_DPW) 351 352#define DCC_DCE0 0x1 353#define DCC_DCE1 0x10000 354 355#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80) 356#define PPC_PPC 0xfffffffe 357#define PPC_PPE 0x1 358#define PPC_PPM 0x0000fff8 359 360 361#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) 362 363/* sign-extend a 4-bit number */ 364#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) 365 366/* sign-extend a 5-bit number */ 367#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) 368 369/* sign-extend a 9-bit number */ 370#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) 371 372/* sign-extend a 22-bit number */ 373#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) 374 375/* sign extend a 40 bit number */ 376#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \ 377 ^ (~UNSIGNED64 (0x7fffffffff))) \ 378 + UNSIGNED64 (0x8000000000)) 379 380/* sign extend a 44 bit number */ 381#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \ 382 ^ (~ UNSIGNED64 (0x7ffffffffff))) \ 383 + UNSIGNED64 (0x80000000000)) 384 385/* sign extend a 60 bit number */ 386#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \ 387 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \ 388 + UNSIGNED64 (0x800000000000000)) 389 390/* No sign extension */ 391#define NOP(x) (x) 392 393#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i)) 394 395#define RLW(x) load_mem (x, 4) 396 397/* Function declarations. */ 398 399#define IMEM16(EA) \ 400sim_core_read_aligned_2 (CPU, PC, exec_map, (EA)) 401 402#define IMEM16_IMMED(EA,N) \ 403sim_core_read_aligned_2 (STATE_CPU (sd, 0), \ 404 PC, exec_map, (EA) + (N) * 2) 405 406#define load_mem(ADDR,LEN) \ 407sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \ 408 PC, read_map, (ADDR)) 409 410#define store_mem(ADDR,LEN,DATA) \ 411sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \ 412 PC, write_map, (ADDR), (DATA)) 413 414 415/* compare cccc field against PSW */ 416int condition_met (unsigned code); 417 418 419/* Debug/tracing calls */ 420 421enum op_types 422{ 423 OP_UNKNOWN, 424 OP_NONE, 425 OP_TRAP, 426 OP_REG, 427 OP_REG_REG, 428 OP_REG_REG_CMP, 429 OP_REG_REG_MOVE, 430 OP_IMM_REG, 431 OP_IMM_REG_CMP, 432 OP_IMM_REG_MOVE, 433 OP_COND_BR, 434 OP_LOAD16, 435 OP_STORE16, 436 OP_LOAD32, 437 OP_STORE32, 438 OP_JUMP, 439 OP_IMM_REG_REG, 440 OP_UIMM_REG_REG, 441 OP_IMM16_REG_REG, 442 OP_UIMM16_REG_REG, 443 OP_BIT, 444 OP_EX1, 445 OP_EX2, 446 OP_LDSR, 447 OP_STSR, 448 OP_BIT_CHANGE, 449 OP_REG_REG_REG, 450 OP_REG_REG3, 451 OP_IMM_REG_REG_REG, 452 OP_PUSHPOP1, 453 OP_PUSHPOP2, 454 OP_PUSHPOP3, 455}; 456 457#ifdef DEBUG 458void trace_input (char *name, enum op_types type, int size); 459void trace_output (enum op_types result); 460void trace_result (int has_result, unsigned32 result); 461 462extern int trace_num_values; 463extern unsigned32 trace_values[]; 464extern unsigned32 trace_pc; 465extern const char *trace_name; 466extern int trace_module; 467 468#define TRACE_BRANCH0() \ 469do { \ 470 if (TRACE_BRANCH_P (CPU)) { \ 471 trace_module = TRACE_BRANCH_IDX; \ 472 trace_pc = cia; \ 473 trace_name = itable[MY_INDEX].name; \ 474 trace_num_values = 0; \ 475 trace_result (1, (nia)); \ 476 } \ 477} while (0) 478 479#define TRACE_BRANCH1(IN1) \ 480do { \ 481 if (TRACE_BRANCH_P (CPU)) { \ 482 trace_module = TRACE_BRANCH_IDX; \ 483 trace_pc = cia; \ 484 trace_name = itable[MY_INDEX].name; \ 485 trace_values[0] = (IN1); \ 486 trace_num_values = 1; \ 487 trace_result (1, (nia)); \ 488 } \ 489} while (0) 490 491#define TRACE_BRANCH2(IN1, IN2) \ 492do { \ 493 if (TRACE_BRANCH_P (CPU)) { \ 494 trace_module = TRACE_BRANCH_IDX; \ 495 trace_pc = cia; \ 496 trace_name = itable[MY_INDEX].name; \ 497 trace_values[0] = (IN1); \ 498 trace_values[1] = (IN2); \ 499 trace_num_values = 2; \ 500 trace_result (1, (nia)); \ 501 } \ 502} while (0) 503 504#define TRACE_BRANCH3(IN1, IN2, IN3) \ 505do { \ 506 if (TRACE_BRANCH_P (CPU)) { \ 507 trace_module = TRACE_BRANCH_IDX; \ 508 trace_pc = cia; \ 509 trace_name = itable[MY_INDEX].name; \ 510 trace_values[0] = (IN1); \ 511 trace_values[1] = (IN2); \ 512 trace_values[2] = (IN3); \ 513 trace_num_values = 3; \ 514 trace_result (1, (nia)); \ 515 } \ 516} while (0) 517 518#define TRACE_LD(ADDR,RESULT) \ 519do { \ 520 if (TRACE_MEMORY_P (CPU)) { \ 521 trace_module = TRACE_MEMORY_IDX; \ 522 trace_pc = cia; \ 523 trace_name = itable[MY_INDEX].name; \ 524 trace_values[0] = (ADDR); \ 525 trace_num_values = 1; \ 526 trace_result (1, (RESULT)); \ 527 } \ 528} while (0) 529 530#define TRACE_LD_NAME(NAME, ADDR,RESULT) \ 531do { \ 532 if (TRACE_MEMORY_P (CPU)) { \ 533 trace_module = TRACE_MEMORY_IDX; \ 534 trace_pc = cia; \ 535 trace_name = (NAME); \ 536 trace_values[0] = (ADDR); \ 537 trace_num_values = 1; \ 538 trace_result (1, (RESULT)); \ 539 } \ 540} while (0) 541 542#define TRACE_ST(ADDR,RESULT) \ 543do { \ 544 if (TRACE_MEMORY_P (CPU)) { \ 545 trace_module = TRACE_MEMORY_IDX; \ 546 trace_pc = cia; \ 547 trace_name = itable[MY_INDEX].name; \ 548 trace_values[0] = (ADDR); \ 549 trace_num_values = 1; \ 550 trace_result (1, (RESULT)); \ 551 } \ 552} while (0) 553 554#define TRACE_FP_INPUT_FPU1(V0) \ 555do { \ 556 if (TRACE_FPU_P (CPU)) \ 557 { \ 558 unsigned64 f0; \ 559 sim_fpu_to64 (&f0, (V0)); \ 560 trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ 561 } \ 562} while (0) 563 564#define TRACE_FP_INPUT_FPU2(V0, V1) \ 565do { \ 566 if (TRACE_FPU_P (CPU)) \ 567 { \ 568 unsigned64 f0, f1; \ 569 sim_fpu_to64 (&f0, (V0)); \ 570 sim_fpu_to64 (&f1, (V1)); \ 571 trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \ 572 } \ 573} while (0) 574 575#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \ 576do { \ 577 if (TRACE_FPU_P (CPU)) \ 578 { \ 579 unsigned64 f0, f1, f2; \ 580 sim_fpu_to64 (&f0, (V0)); \ 581 sim_fpu_to64 (&f1, (V1)); \ 582 sim_fpu_to64 (&f2, (V2)); \ 583 trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \ 584 } \ 585} while (0) 586 587#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \ 588do { \ 589 if (TRACE_FPU_P (CPU)) \ 590 { \ 591 int d0 = (V0); \ 592 unsigned64 f1, f2; \ 593 TRACE_DATA *data = CPU_TRACE_DATA (CPU); \ 594 TRACE_IDX (data) = TRACE_FPU_IDX; \ 595 sim_fpu_to64 (&f1, (V1)); \ 596 sim_fpu_to64 (&f2, (V2)); \ 597 save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \ 598 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \ 599 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \ 600 } \ 601} while (0) 602 603#define TRACE_FP_INPUT_WORD2(V0, V1) \ 604do { \ 605 if (TRACE_FPU_P (CPU)) \ 606 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \ 607} while (0) 608 609#define TRACE_FP_RESULT_FPU1(R0) \ 610do { \ 611 if (TRACE_FPU_P (CPU)) \ 612 { \ 613 unsigned64 f0; \ 614 sim_fpu_to64 (&f0, (R0)); \ 615 trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ 616 } \ 617} while (0) 618 619#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0) 620 621#define TRACE_FP_RESULT_WORD2(R0, R1) \ 622do { \ 623 if (TRACE_FPU_P (CPU)) \ 624 trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \ 625} while (0) 626 627#else 628#define trace_input(NAME, IN1, IN2) 629#define trace_output(RESULT) 630#define trace_result(HAS_RESULT, RESULT) 631 632#define TRACE_ALU_INPUT0() 633#define TRACE_ALU_INPUT1(IN0) 634#define TRACE_ALU_INPUT2(IN0, IN1) 635#define TRACE_ALU_INPUT2(IN0, IN1) 636#define TRACE_ALU_INPUT2(IN0, IN1 INS2) 637#define TRACE_ALU_RESULT(RESULT) 638 639#define TRACE_BRANCH0() 640#define TRACE_BRANCH1(IN1) 641#define TRACE_BRANCH2(IN1, IN2) 642#define TRACE_BRANCH2(IN1, IN2, IN3) 643 644#define TRACE_LD(ADDR,RESULT) 645#define TRACE_ST(ADDR,RESULT) 646 647#endif 648 649#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL)) 650#define GPR_CLEAR(N) (State.regs[(N)] = 0) 651 652extern void divun ( unsigned int N, 653 unsigned long int als, 654 unsigned long int sfi, 655 unsigned32 /*unsigned long int*/ * quotient_ptr, 656 unsigned32 /*unsigned long int*/ * remainder_ptr, 657 int *overflow_ptr 658 ); 659extern void divn ( unsigned int N, 660 unsigned long int als, 661 unsigned long int sfi, 662 signed32 /*signed long int*/ * quotient_ptr, 663 signed32 /*signed long int*/ * remainder_ptr, 664 int *overflow_ptr 665 ); 666extern int type1_regs[]; 667extern int type2_regs[]; 668extern int type3_regs[]; 669 670#define SESR_OV (1 << 0) 671#define SESR_SOV (1 << 1) 672 673#define SESR (State.sregs[12]) 674 675#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff) 676#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff) 677#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff) 678#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff) 679 680#define SAT16(X) \ 681 do \ 682 { \ 683 signed64 z = (X); \ 684 if (z > 0x7fff) \ 685 { \ 686 SESR |= SESR_OV | SESR_SOV; \ 687 z = 0x7fff; \ 688 } \ 689 else if (z < -0x8000) \ 690 { \ 691 SESR |= SESR_OV | SESR_SOV; \ 692 z = - 0x8000; \ 693 } \ 694 (X) = z; \ 695 } \ 696 while (0) 697 698#define SAT32(X) \ 699 do \ 700 { \ 701 signed64 z = (X); \ 702 if (z > 0x7fffffff) \ 703 { \ 704 SESR |= SESR_OV | SESR_SOV; \ 705 z = 0x7fffffff; \ 706 } \ 707 else if (z < -0x80000000) \ 708 { \ 709 SESR |= SESR_OV | SESR_SOV; \ 710 z = - 0x80000000; \ 711 } \ 712 (X) = z; \ 713 } \ 714 while (0) 715 716#define ABS16(X) \ 717 do \ 718 { \ 719 signed64 z = (X) & 0xffff; \ 720 if (z == 0x8000) \ 721 { \ 722 SESR |= SESR_OV | SESR_SOV; \ 723 z = 0x7fff; \ 724 } \ 725 else if (z & 0x8000) \ 726 { \ 727 z = (- z) & 0xffff; \ 728 } \ 729 (X) = z; \ 730 } \ 731 while (0) 732 733#define ABS32(X) \ 734 do \ 735 { \ 736 signed64 z = (X) & 0xffffffff; \ 737 if (z == 0x80000000) \ 738 { \ 739 SESR |= SESR_OV | SESR_SOV; \ 740 z = 0x7fffffff; \ 741 } \ 742 else if (z & 0x80000000) \ 743 { \ 744 z = (- z) & 0xffffffff; \ 745 } \ 746 (X) = z; \ 747 } \ 748 while (0) 749 750#endif 751