1//Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp
2# mach: bfin
3
4.include "testutils.inc"
5	start
6
7
8// Spec Reference: dsp32shiftimm lshift: lshift / lshift
9
10
11
12imm32 r0, 0x01230abc;
13imm32 r1, 0x12345678;
14imm32 r2, 0x23456789;
15imm32 r3, 0x3456789a;
16imm32 r4, 0x456789ab;
17imm32 r5, 0x56789abc;
18imm32 r6, 0x6789abcd;
19imm32 r7, 0x789abcde;
20R0 = R0 << 0 (V);
21R1 = R1 << 3 (V);
22R2 = R2 << 5 (V);
23R3 = R3 << 8 (V);
24R4 = R4 << 9 (V);
25R5 = R5 << 15 (V);
26R6 = R6 << 7 (V);
27R7 = R7 << 13 (V);
28CHECKREG r0, 0x01230ABC;
29CHECKREG r1, 0x91A0B3C0;
30CHECKREG r2, 0x68A0F120;
31CHECKREG r3, 0x56009A00;
32CHECKREG r4, 0xCE005600;
33CHECKREG r5, 0x00000000;
34CHECKREG r6, 0xC480E680;
35CHECKREG r7, 0x4000C000;
36
37imm32 r0, 0x01230000;
38imm32 r1, 0x12345678;
39imm32 r2, 0x23456789;
40imm32 r3, 0x3456789a;
41imm32 r4, 0x456789ab;
42imm32 r5, 0x56789abc;
43imm32 r6, 0x6789abcd;
44imm32 r7, 0x789abcde;
45R7 = R0 >> 11 (V);
46R0 = R1 >> 8 (V);
47R1 = R2 >> 14 (V);
48R2 = R3 >> 15 (V);
49R3 = R4 >> 10 (V);
50R4 = R5 >> 2 (V);
51R5 = R6 >> 9 (V);
52R6 = R7 >> 6 (V);
53CHECKREG r0, 0x00120056;
54CHECKREG r1, 0x00000001;
55CHECKREG r2, 0x00000000;
56CHECKREG r3, 0x00110022;
57CHECKREG r4, 0x159E26AF;
58CHECKREG r5, 0x00330055;
59CHECKREG r6, 0x00000000;
60CHECKREG r7, 0x00000000;
61
62
63
64
65pass
66