1//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp 2// Spec Reference: alu2op shadd 1 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10imm32 r0, 0x03417990; 11imm32 r1, 0x12315678; 12imm32 r2, 0x23416789; 13imm32 r3, 0x3451789a; 14imm32 r4, 0x856189ab; 15imm32 r5, 0x96719abc; 16imm32 r6, 0xa781abcd; 17imm32 r7, 0xb891bcde; 18R1 = ( R1 + R0 ) << 1; 19R2 = ( R2 + R0 ) << 1; 20R3 = ( R3 + R0 ) << 1; 21R4 = ( R4 + R0 ) << 1; 22R5 = ( R5 + R0 ) << 1; 23R6 = ( R6 + R0 ) << 1; 24R7 = ( R7 + R0 ) << 1; 25R0 = ( R0 + R0 ) << 1; 26CHECKREG r0, 0x0D05E640; 27CHECKREG r1, 0x2AE5A010; 28CHECKREG r2, 0x4D05C232; 29CHECKREG r3, 0x6F25E454; 30CHECKREG r4, 0x11460676; 31CHECKREG r5, 0x33662898; 32CHECKREG r6, 0x55864ABA; 33CHECKREG r7, 0x77A66CDC; 34 35imm32 r0, 0x03457290; 36imm32 r1, 0x12345278; 37imm32 r2, 0x23456289; 38imm32 r3, 0x3456729a; 39imm32 r4, 0x856782ab; 40imm32 r5, 0x967892bc; 41imm32 r6, 0xa789a2cd; 42imm32 r7, 0xb89ab2de; 43R0 = ( R0 + R1 ) << 1; 44R2 = ( R2 + R1 ) << 1; 45R3 = ( R3 + R1 ) << 1; 46R4 = ( R4 + R1 ) << 1; 47R5 = ( R5 + R1 ) << 1; 48R6 = ( R6 + R1 ) << 1; 49R7 = ( R7 + R1 ) << 1; 50R1 = ( R1 + R1 ) << 1; 51CHECKREG r0, 0x2AF38A10; 52CHECKREG r1, 0x48D149E0; 53CHECKREG r2, 0x6AF36A02; 54CHECKREG r3, 0x8D158A24; 55CHECKREG r4, 0x2F37AA46; 56CHECKREG r5, 0x5159CA68; 57CHECKREG r6, 0x737BEA8A; 58CHECKREG r7, 0x959E0AAC; 59 60imm32 r0, 0x03457930; 61imm32 r1, 0x12345638; 62imm32 r2, 0x23456739; 63imm32 r3, 0x3456783a; 64imm32 r4, 0x8567893b; 65imm32 r5, 0x96789a3c; 66imm32 r6, 0xa789ab3d; 67imm32 r7, 0xb89abc3e; 68R0 = ( R0 + R2 ) << 1; 69R1 = ( R1 + R2 ) << 1; 70R3 = ( R3 + R2 ) << 1; 71R4 = ( R4 + R2 ) << 1; 72R5 = ( R5 + R2 ) << 1; 73R6 = ( R6 + R2 ) << 1; 74R7 = ( R7 + R2 ) << 1; 75R2 = ( R2 + R2 ) << 1; 76CHECKREG r0, 0x4D15C0D2; 77CHECKREG r1, 0x6AF37AE2; 78CHECKREG r2, 0x8D159CE4; 79CHECKREG r3, 0xAF37BEE6; 80CHECKREG r4, 0x5159E0E8; 81CHECKREG r5, 0x737C02EA; 82CHECKREG r6, 0x959E24EC; 83CHECKREG r7, 0xB7C046EE; 84 85imm32 r0, 0x04457990; 86imm32 r1, 0x14345678; 87imm32 r2, 0x24456789; 88imm32 r3, 0x3456789a; 89imm32 r4, 0x846789ab; 90imm32 r5, 0x94789abc; 91imm32 r6, 0xa489abcd; 92imm32 r7, 0xb49abcde; 93R0 = ( R0 + R3 ) << 1; 94R1 = ( R1 + R3 ) << 1; 95R2 = ( R2 + R3 ) << 1; 96R4 = ( R4 + R3 ) << 1; 97R5 = ( R5 + R3 ) << 1; 98R6 = ( R6 + R3 ) << 1; 99R7 = ( R7 + R3 ) << 1; 100R3 = ( R3 + R3 ) << 1; 101CHECKREG r0, 0x7137E454; 102CHECKREG r1, 0x91159E24; 103CHECKREG r2, 0xB137C046; 104CHECKREG r3, 0xD159E268; 105CHECKREG r4, 0x717C048A; 106CHECKREG r5, 0x919E26AC; 107CHECKREG r6, 0xB1C048CE; 108CHECKREG r7, 0xD1E26AF0; 109 110imm32 r0, 0x03417990; 111imm32 r1, 0x12315678; 112imm32 r2, 0x23416789; 113imm32 r3, 0x3451789a; 114imm32 r4, 0x856189ab; 115imm32 r5, 0x96719abc; 116imm32 r6, 0xa781abcd; 117imm32 r7, 0xb891bcde; 118R0 = ( R0 + R4 ) << 1; 119R1 = ( R1 + R4 ) << 1; 120R2 = ( R2 + R4 ) << 1; 121R3 = ( R3 + R4 ) << 1; 122R5 = ( R5 + R4 ) << 1; 123R6 = ( R6 + R4 ) << 1; 124R7 = ( R7 + R4 ) << 1; 125R4 = ( R4 + R4 ) << 1; 126CHECKREG r0, 0x11460676; 127CHECKREG r1, 0x2F25C046; 128CHECKREG r2, 0x5145E268; 129CHECKREG r3, 0x7366048A; 130CHECKREG r4, 0x158626AC; 131CHECKREG r5, 0x37A648CE; 132CHECKREG r6, 0x59C66AF0; 133CHECKREG r7, 0x7BE68D12; 134 135imm32 r0, 0x03457290; 136imm32 r1, 0x12345278; 137imm32 r2, 0x23456289; 138imm32 r3, 0x3456729a; 139imm32 r4, 0x856782ab; 140imm32 r5, 0x967892bc; 141imm32 r6, 0xa789a2cd; 142imm32 r7, 0xb89ab2de; 143R0 = ( R0 + R5 ) << 1; 144R1 = ( R1 + R5 ) << 1; 145R2 = ( R2 + R5 ) << 1; 146R3 = ( R3 + R5 ) << 1; 147R4 = ( R4 + R5 ) << 1; 148R6 = ( R6 + R5 ) << 1; 149R7 = ( R7 + R5 ) << 1; 150R5 = ( R5 + R5 ) << 1; 151CHECKREG r0, 0x337C0A98; 152CHECKREG r1, 0x5159CA68; 153CHECKREG r2, 0x737BEA8A; 154CHECKREG r3, 0x959E0AAC; 155CHECKREG r4, 0x37C02ACE; 156CHECKREG r5, 0x59E24AF0; 157CHECKREG r6, 0x7C046B12; 158CHECKREG r7, 0x9E268B34; 159 160imm32 r0, 0x03457930; 161imm32 r1, 0x12345638; 162imm32 r2, 0x23456739; 163imm32 r3, 0x3456783a; 164imm32 r4, 0x8567893b; 165imm32 r5, 0x96789a3c; 166imm32 r6, 0xa789ab3d; 167imm32 r7, 0xb89abc3e; 168R0 = ( R0 + R6 ) << 1; 169R1 = ( R1 + R6 ) << 1; 170R2 = ( R2 + R6 ) << 1; 171R3 = ( R3 + R6 ) << 1; 172R4 = ( R4 + R6 ) << 1; 173R5 = ( R5 + R6 ) << 1; 174R7 = ( R7 + R6 ) << 1; 175R6 = ( R6 + R6 ) << 1; 176CHECKREG r0, 0x559E48DA; 177CHECKREG r1, 0x737C02EA; 178CHECKREG r2, 0x959E24EC; 179CHECKREG r3, 0xB7C046EE; 180CHECKREG r4, 0x59E268F0; 181CHECKREG r5, 0x7C048AF2; 182CHECKREG r6, 0x9E26ACF4; 183CHECKREG r7, 0xC048CEF6; 184 185imm32 r0, 0x04457990; 186imm32 r1, 0x14345678; 187imm32 r2, 0x24456789; 188imm32 r3, 0x3456789a; 189imm32 r4, 0x846789ab; 190imm32 r5, 0x94789abc; 191imm32 r6, 0xa489abcd; 192imm32 r7, 0xb49abcde; 193R0 = ( R0 + R7 ) << 1; 194R1 = ( R1 + R7 ) << 1; 195R2 = ( R2 + R7 ) << 1; 196R3 = ( R3 + R7 ) << 1; 197R4 = ( R4 + R7 ) << 1; 198R5 = ( R5 + R7 ) << 1; 199R6 = ( R6 + R7 ) << 1; 200R7 = ( R7 + R7 ) << 1; 201CHECKREG r0, 0x71C06CDC; 202CHECKREG r1, 0x919E26AC; 203CHECKREG r2, 0xB1C048CE; 204CHECKREG r3, 0xD1E26AF0; 205CHECKREG r4, 0x72048D12; 206CHECKREG r5, 0x9226AF34; 207CHECKREG r6, 0xB248D156; 208CHECKREG r7, 0xD26AF378; 209pass 210