1# Hitachi H8 testcase 'or.b' 2# mach(): all 3# as(h8300): --defsym sim_cpu=0 4# as(h8300h): --defsym sim_cpu=1 5# as(h8300s): --defsym sim_cpu=2 6# as(h8sx): --defsym sim_cpu=3 7# ld(h8300h): -m h8300helf 8# ld(h8300s): -m h8300self 9# ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 # Instructions tested: 14 # or.b #xx:8, rd ; c rd xxxxxxxx 15 # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx 16 # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx 17 # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx 18 # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx 19 # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx 20 # or.b rs, rd ; 1 4 rs rd 21 # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? 22 # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs 23 # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs 24 # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs 25 # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs 26 # 27 # orc #xx:8, ccr 28 # orc #xx:8, exr 29 30 31 # Coming soon: 32 # ... 33 34.data 35pre_byte: .byte 0 36byte_dest: .byte 0xa5 37post_byte: .byte 0 38 39 start 40 41or_b_imm8_reg8: 42 set_grs_a5a5 ; Fill all general regs with a fixed pattern 43 ;; fixme set ccr 44 45 ;; or.b #xx:8,Rd 46 or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest 47 48 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 49 test_h_gr16 0xa5af r0 ; or result: a5 | aa 50.if (sim_cpu) ; non-zero means h8300h, s, or sx 51 test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa 52.endif 53 test_gr_a5a5 1 ; Make sure other general regs not disturbed 54 test_gr_a5a5 2 55 test_gr_a5a5 3 56 test_gr_a5a5 4 57 test_gr_a5a5 5 58 test_gr_a5a5 6 59 test_gr_a5a5 7 60 61.if (sim_cpu == h8sx) 62or_b_imm8_rdind: 63 mov #byte_dest, er0 64 mov.b #0xa5, r1l 65 mov.b r1l, @er0 66 67 set_grs_a5a5 ; Fill all general regs with a fixed pattern 68 set_ccr_zero 69 70 ;; or.b #xx:8,@eRd 71 mov #byte_dest, er0 72 or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst 73;;; .word 0x7d00 74;;; .word 0xc0aa 75 76 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 77 test_ovf_clear 78 test_zero_clear 79 test_neg_set 80 81 test_h_gr32 byte_dest, er0 ; er0 still contains address 82 test_gr_a5a5 1 ; Make sure other general regs not disturbed 83 test_gr_a5a5 2 84 test_gr_a5a5 3 85 test_gr_a5a5 4 86 test_gr_a5a5 5 87 test_gr_a5a5 6 88 test_gr_a5a5 7 89 90 ;; Now check the result of the or to memory. 91 sub.b r0l, r0l 92 mov.b @byte_dest, r0l 93 cmp.b #0xaf, r0l 94 beq .L1 95 fail 96.L1: 97 98or_b_imm8_rdpostinc: 99 mov #byte_dest, er0 100 mov.b #0xa5, r1l 101 mov.b r1l, @er0 102 103 set_grs_a5a5 ; Fill all general regs with a fixed pattern 104 set_ccr_zero 105 106 ;; or.b #xx:8,@eRd+ 107 mov #byte_dest, er0 108 or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest 109;;; .word 0x0174 110;;; .word 0x6c08 111;;; .word 0xc055 112 113 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 114 test_ovf_clear 115 test_zero_clear 116 test_neg_set 117 118 test_h_gr32 post_byte, er0 ; er0 contains address plus one 119 test_gr_a5a5 1 ; Make sure other general regs not disturbed 120 test_gr_a5a5 2 121 test_gr_a5a5 3 122 test_gr_a5a5 4 123 test_gr_a5a5 5 124 test_gr_a5a5 6 125 test_gr_a5a5 7 126 127 ;; Now check the result of the or to memory. 128 sub.b r0l, r0l 129 mov.b @byte_dest, r0l 130 cmp.b #0xf5, r0l 131 beq .L2 132 fail 133.L2: 134 135or_b_imm8_rdpostdec: 136 mov #byte_dest, er0 137 mov.b #0xa5, r1l 138 mov.b r1l, @er0 139 140 set_grs_a5a5 ; Fill all general regs with a fixed pattern 141 set_ccr_zero 142 143 ;; or.b #xx:8,@eRd- 144 mov #byte_dest, er0 145 or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest 146;;; .word 0x0176 147;;; .word 0x6c08 148;;; .word 0xc0aa 149 150 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 151 test_ovf_clear 152 test_zero_clear 153 test_neg_set 154 155 test_h_gr32 pre_byte, er0 ; er0 contains address minus one 156 test_gr_a5a5 1 ; Make sure other general regs not disturbed 157 test_gr_a5a5 2 158 test_gr_a5a5 3 159 test_gr_a5a5 4 160 test_gr_a5a5 5 161 test_gr_a5a5 6 162 test_gr_a5a5 7 163 164 ;; Now check the result of the or to memory. 165 sub.b r0l, r0l 166 mov.b @byte_dest, r0l 167 cmp.b #0xaf, r0l 168 beq .L3 169 fail 170.L3: 171 172or_b_imm8_rdpreinc: 173 mov #byte_dest, er0 174 mov.b #0xa5, r1l 175 mov.b r1l, @er0 176 177 set_grs_a5a5 ; Fill all general regs with a fixed pattern 178 set_ccr_zero 179 180 ;; or.b #xx:8,@+eRd 181 mov #pre_byte, er0 182 or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest 183;;; .word 0x0175 184;;; .word 0x6c08 185;;; .word 0xc055 186 187 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 188 test_ovf_clear 189 test_zero_clear 190 test_neg_set 191 192 test_h_gr32 byte_dest, er0 ; er0 contains destination address 193 test_gr_a5a5 1 ; Make sure other general regs not disturbed 194 test_gr_a5a5 2 195 test_gr_a5a5 3 196 test_gr_a5a5 4 197 test_gr_a5a5 5 198 test_gr_a5a5 6 199 test_gr_a5a5 7 200 201 ;; Now check the result of the or to memory. 202 sub.b r0l, r0l 203 mov.b @byte_dest, r0l 204 cmp.b #0xf5, r0l 205 beq .L4 206 fail 207.L4: 208 209or_b_imm8_rdpredec: 210 mov #byte_dest, er0 211 mov.b #0xa5, r1l 212 mov.b r1l, @er0 213 214 set_grs_a5a5 ; Fill all general regs with a fixed pattern 215 set_ccr_zero 216 217 ;; or.b #xx:8,@-eRd 218 mov #post_byte, er0 219 or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest 220;;; .word 0x0177 221;;; .word 0x6c08 222;;; .word 0xc0aa 223 224 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 225 test_ovf_clear 226 test_zero_clear 227 test_neg_set 228 229 test_h_gr32 byte_dest, er0 ; er0 contains destination address 230 test_gr_a5a5 1 ; Make sure other general regs not disturbed 231 test_gr_a5a5 2 232 test_gr_a5a5 3 233 test_gr_a5a5 4 234 test_gr_a5a5 5 235 test_gr_a5a5 6 236 test_gr_a5a5 7 237 238 ;; Now check the result of the or to memory. 239 sub.b r0l, r0l 240 mov.b @byte_dest, r0l 241 cmp.b #0xaf, r0l 242 beq .L5 243 fail 244.L5: 245 246.endif 247 248or_b_reg8_reg8: 249 set_grs_a5a5 ; Fill all general regs with a fixed pattern 250 ;; fixme set ccr 251 252 ;; or.b Rs,Rd 253 mov.b #0xaa, r0h 254 or.b r0h, r0l ; Reg8 src, reg8 dest 255 256 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 257 test_h_gr16 0xaaaf r0 ; or result: a5 | aa 258.if (sim_cpu) ; non-zero means h8300h, s, or sx 259 test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa 260.endif 261 test_gr_a5a5 1 ; Make sure other general regs not disturbed 262 test_gr_a5a5 2 263 test_gr_a5a5 3 264 test_gr_a5a5 4 265 test_gr_a5a5 5 266 test_gr_a5a5 6 267 test_gr_a5a5 7 268 269.if (sim_cpu == h8sx) 270or_b_reg8_rdind: 271 mov #byte_dest, er0 272 mov.b #0xa5, r1l 273 mov.b r1l, @er0 274 275 set_grs_a5a5 ; Fill all general regs with a fixed pattern 276 set_ccr_zero 277 278 ;; or.b rs8,@eRd ; or reg8 to register indirect 279 mov #byte_dest, er0 280 mov #0xaa, r1l 281 or.b r1l, @er0 ; reg8 src, reg indirect dest 282;;; .word 0x7d00 283;;; .word 0x1490 284 285 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 286 test_ovf_clear 287 test_zero_clear 288 test_neg_set 289 290 test_h_gr32 byte_dest er0 ; er0 still contains address 291 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load 292 293 test_gr_a5a5 2 ; Make sure other general regs not disturbed 294 test_gr_a5a5 3 295 test_gr_a5a5 4 296 test_gr_a5a5 5 297 test_gr_a5a5 6 298 test_gr_a5a5 7 299 300 ;; Now check the result of the or to memory. 301 sub.b r0l, r0l 302 mov.b @byte_dest, r0l 303 cmp.b #0xaf, r0l 304 beq .L6 305 fail 306.L6: 307 308or_b_reg8_rdpostinc: 309 mov #byte_dest, er0 310 mov.b #0xa5, r1l 311 mov.b r1l, @er0 312 313 set_grs_a5a5 ; Fill all general regs with a fixed pattern 314 set_ccr_zero 315 316 ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment 317 mov #byte_dest, er0 318 mov #0x55, r1l 319 or.b r1l, @er0+ ; reg8 src, reg post-incr dest 320;;; .word 0x0179 321;;; .word 0x8049 322 323 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 324 test_ovf_clear 325 test_zero_clear 326 test_neg_set 327 328 test_h_gr32 post_byte er0 ; er0 contains address plus one 329 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load 330 331 test_gr_a5a5 2 ; Make sure other general regs not disturbed 332 test_gr_a5a5 3 333 test_gr_a5a5 4 334 test_gr_a5a5 5 335 test_gr_a5a5 6 336 test_gr_a5a5 7 337 338 ;; Now check the result of the or to memory. 339 sub.b r0l, r0l 340 mov.b @byte_dest, r0l 341 cmp.b #0xf5, r0l 342 beq .L7 343 fail 344.L7: 345 ;; special case same register 346 mov.l #byte_dest, er0 347 mov.b r0l, r1l 348 mov.b @er0, r1h 349 or.b r0l, @er0+ 350 inc.b r1l 351 or.b r1h, r1l 352 mov.b @byte_dest, r0l 353 cmp.b r1l, r0l 354 beq .L27 355 fail 356.L27: 357 358or_b_reg8_rdpostdec: 359 mov #byte_dest, er0 360 mov.b #0xa5, r1l 361 mov.b r1l, @er0 362 363 set_grs_a5a5 ; Fill all general regs with a fixed pattern 364 set_ccr_zero 365 366 ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement 367 mov #byte_dest, er0 368 mov #0xaa, r1l 369 or.b r1l, @er0- ; reg8 src, reg post-decr dest 370;;; .word 0x0179 371;;; .word 0xa049 372 373 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 374 test_ovf_clear 375 test_zero_clear 376 test_neg_set 377 378 test_h_gr32 pre_byte er0 ; er0 contains address minus one 379 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load 380 381 test_gr_a5a5 2 ; Make sure other general regs not disturbed 382 test_gr_a5a5 3 383 test_gr_a5a5 4 384 test_gr_a5a5 5 385 test_gr_a5a5 6 386 test_gr_a5a5 7 387 388 ;; Now check the result of the or to memory. 389 sub.b r0l, r0l 390 mov.b @byte_dest, r0l 391 cmp.b #0xaf, r0l 392 beq .L8 393 fail 394.L8: 395 ;; special case same register 396 mov.l #byte_dest, er0 397 mov.b r0l, r1l 398 mov.b @er0, r1h 399 or.b r0l, @er0- 400 dec.b r1l 401 or.b r1h, r1l 402 mov.b @byte_dest, r0l 403 cmp.b r1l, r0l 404 beq .L28 405 fail 406.L28: 407 408or_b_reg8_rdpreinc: 409 mov #byte_dest, er0 410 mov.b #0xa5, r1l 411 mov.b r1l, @er0 412 413 set_grs_a5a5 ; Fill all general regs with a fixed pattern 414 set_ccr_zero 415 416 ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment 417 mov #pre_byte, er0 418 mov #0x55, r1l 419 or.b r1l, @+er0 ; reg8 src, reg pre-incr dest 420;;; .word 0x0179 421;;; .word 0x9049 422 423 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 424 test_ovf_clear 425 test_zero_clear 426 test_neg_set 427 428 test_h_gr32 byte_dest er0 ; er0 contains destination address 429 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load 430 431 test_gr_a5a5 2 ; Make sure other general regs not disturbed 432 test_gr_a5a5 3 433 test_gr_a5a5 4 434 test_gr_a5a5 5 435 test_gr_a5a5 6 436 test_gr_a5a5 7 437 438 ;; Now check the result of the or to memory. 439 sub.b r0l, r0l 440 mov.b @byte_dest, r0l 441 cmp.b #0xf5, r0l 442 beq .L9 443 fail 444.L9: 445 ;; special case same register 446 mov.l #pre_byte, er0 447 mov.b r0l, r1l 448 mov.b @byte_dest, r1h 449 or.b r0l, @+er0 450 inc.b r1l 451 or.b r1h, r1l 452 mov.b @byte_dest, r0l 453 cmp.b r1l, r0l 454 beq .L29 455 fail 456.L29: 457 458or_b_reg8_rdpredec: 459 mov #byte_dest, er0 460 mov.b #0xa5, r1l 461 mov.b r1l, @er0 462 463 set_grs_a5a5 ; Fill all general regs with a fixed pattern 464 set_ccr_zero 465 466 ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement 467 mov #post_byte, er0 468 mov #0xaa, r1l 469 or.b r1l, @-er0 ; reg8 src, reg pre-decr dest 470;;; .word 0x0179 471;;; .word 0xb049 472 473 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 474 test_ovf_clear 475 test_zero_clear 476 test_neg_set 477 478 test_h_gr32 byte_dest er0 ; er0 contains destination address 479 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load 480 481 test_gr_a5a5 2 ; Make sure other general regs not disturbed 482 test_gr_a5a5 3 483 test_gr_a5a5 4 484 test_gr_a5a5 5 485 test_gr_a5a5 6 486 test_gr_a5a5 7 487 488 ;; Now check the result of the or to memory. 489 sub.b r0l, r0l 490 mov.b @byte_dest, r0l 491 cmp.b #0xaf, r0l 492 beq .L10 493 fail 494.L10: 495 ;; special case same register 496 mov.l #post_byte, er0 497 mov.b r0l, r1l 498 mov.b @byte_dest, r1h 499 or.b r0l, @-er0 500 dec.b r1l 501 or.b r1h, r1l 502 mov.b @byte_dest, r0l 503 cmp.b r1l, r0l 504 beq .L30 505 fail 506.L30: 507 508.endif 509 510orc_imm8_ccr: 511 set_grs_a5a5 ; Fill all general regs with a fixed pattern 512 set_ccr_zero 513 514 ;; orc #xx:8,ccr 515 516 test_neg_clear 517 orc #0x8, ccr ; Immediate 8-bit operand (neg flag) 518 test_neg_set 519 520 test_zero_clear 521 orc #0x4, ccr ; Immediate 8-bit operand (zero flag) 522 test_zero_set 523 524 test_ovf_clear 525 orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) 526 test_ovf_set 527 528 test_carry_clear 529 orc #0x1, ccr ; Immediate 8-bit operand (carry flag) 530 test_carry_set 531 532 test_gr_a5a5 0 ; Make sure other general regs not disturbed 533 test_gr_a5a5 1 534 test_gr_a5a5 2 535 test_gr_a5a5 3 536 test_gr_a5a5 4 537 test_gr_a5a5 5 538 test_gr_a5a5 6 539 test_gr_a5a5 7 540 541.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr 542orc_imm8_exr: 543 set_grs_a5a5 ; Fill all general regs with a fixed pattern 544 545 ldc #0, exr 546 stc exr, r0l 547 test_h_gr8 0, r0l 548 549 ;; orc #xx:8,exr 550 551 orc #0x1, exr 552 stc exr,r0l 553 test_h_gr8 1, r0l 554 555 orc #0x2, exr 556 stc exr,r0l 557 test_h_gr8 3, r0l 558 559 orc #0x4, exr 560 stc exr,r0l 561 test_h_gr8 7, r0l 562 563 orc #0x80, exr 564 stc exr,r0l 565 test_h_gr8 0x87, r0l 566 567 test_h_gr32 0xa5a5a587 er0 568 test_gr_a5a5 1 ; Make sure other general regs not disturbed 569 test_gr_a5a5 2 570 test_gr_a5a5 3 571 test_gr_a5a5 4 572 test_gr_a5a5 5 573 test_gr_a5a5 6 574 test_gr_a5a5 7 575.endif ; not h8300 or h8300h 576 577 pass 578 579 exit 0 580