1# Hitachi H8 testcase 'mov.l' 2# mach(): h8300h h8300s h8sx 3# as(h8300h): --defsym sim_cpu=1 4# as(h8300s): --defsym sim_cpu=2 5# as(h8sx): --defsym sim_cpu=3 6# ld(h8300h): -m h8300helf 7# ld(h8300s): -m h8300self 8# ld(h8sx): -m h8300sxelf 9 10 .include "testutils.inc" 11 12 start 13 14 .data 15 .align 4 16long_dst_dec: 17 .long 0 18long_src: 19 .long 0x77777777 20long_dst: 21 .long 0 22 23 .text 24 25 ;; 26 ;; Move long from immediate source 27 ;; 28 29.if (sim_cpu == h8sx) 30mov_l_imm3_to_reg32: 31 set_grs_a5a5 ; Fill all general regs with a fixed pattern 32 set_ccr_zero 33 34 ;; mov.l #xx:3, erd 35 mov.l #0x3:3, er0 ; Immediate 3-bit operand 36;;; .word 0x0fb8 37 38 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 39 test_neg_clear 40 test_zero_clear 41 test_ovf_clear 42 test_carry_clear 43 44 test_h_gr32 0x3 er0 45 46 test_gr_a5a5 1 ; Make sure other general regs not disturbed 47 test_gr_a5a5 2 48 test_gr_a5a5 3 49 test_gr_a5a5 4 50 test_gr_a5a5 5 51 test_gr_a5a5 6 52 test_gr_a5a5 7 53 54mov_l_imm16_to_reg32: 55 set_grs_a5a5 ; Fill all general regs with a fixed pattern 56 set_ccr_zero 57 58 ;; mov.l #xx:16, erd 59 mov.l #0x1234, er0 ; Immediate 16-bit operand 60;;; .word 0x7a08 61;;; .word 0x1234 62 63 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 64 test_neg_clear 65 test_zero_clear 66 test_ovf_clear 67 test_carry_clear 68 69 test_h_gr32 0x1234 er0 70 71 test_gr_a5a5 1 ; Make sure other general regs not disturbed 72 test_gr_a5a5 2 73 test_gr_a5a5 3 74 test_gr_a5a5 4 75 test_gr_a5a5 5 76 test_gr_a5a5 6 77 test_gr_a5a5 7 78.endif 79 80mov_l_imm32_to_reg32: 81 set_grs_a5a5 ; Fill all general regs with a fixed pattern 82 set_ccr_zero 83 84 ;; mov.l #xx:32, erd 85 mov.l #0x12345678, er0 ; Immediate 32-bit operand 86;;; .word 0x7a00 87;;; .long 0x12345678 88 89 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 90 test_neg_clear 91 test_zero_clear 92 test_ovf_clear 93 test_carry_clear 94 95 test_h_gr32 0x12345678 er0 96 97 test_gr_a5a5 1 ; Make sure other general regs not disturbed 98 test_gr_a5a5 2 99 test_gr_a5a5 3 100 test_gr_a5a5 4 101 test_gr_a5a5 5 102 test_gr_a5a5 6 103 test_gr_a5a5 7 104 105.if (sim_cpu == h8sx) 106mov_l_imm8_to_indirect: 107 set_grs_a5a5 ; Fill all general regs with a fixed pattern 108 set_ccr_zero 109 110 ;; mov.l #xx:8, @erd 111 mov.l #long_dst, er1 112 mov.l #0xa5:8, @er1 ; Register indirect operand 113;;; .word 0x010d 114;;; .word 0x01a5 115 116 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 117 test_neg_clear 118 test_zero_clear 119 test_ovf_clear 120 test_carry_clear 121 122 test_gr_a5a5 0 ; Make sure other general regs not disturbed 123 test_h_gr32 long_dst, er1 124 test_gr_a5a5 2 125 test_gr_a5a5 3 126 test_gr_a5a5 4 127 test_gr_a5a5 5 128 test_gr_a5a5 6 129 test_gr_a5a5 7 130 131 ;; Now check the result of the move to memory. 132 cmp.l #0xa5, @long_dst 133 beq .Lnext1 134 fail 135.Lnext1: 136 mov.l #0, @long_dst ; zero it again for the next use. 137 138mov_l_imm8_to_postinc: ; post-increment from imm8 to mem 139 set_grs_a5a5 ; Fill all general regs with a fixed pattern 140 set_ccr_zero 141 142 ;; mov.l #xx:8, @erd+ 143 mov.l #long_dst, er1 144 mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. 145;;; .word 0x010d 146;;; .word 0x81a5 147 148 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 149 test_neg_clear 150 test_zero_clear 151 test_ovf_clear 152 test_carry_clear 153 154 test_gr_a5a5 0 ; Make sure other general regs not disturbed 155 test_h_gr32 long_dst+4, er1 156 test_gr_a5a5 2 157 test_gr_a5a5 3 158 test_gr_a5a5 4 159 test_gr_a5a5 5 160 test_gr_a5a5 6 161 test_gr_a5a5 7 162 163 ;; Now check the result of the move to memory. 164 cmp.l #0xa5, @long_dst 165 beq .Lnext2 166 fail 167.Lnext2: 168 mov.l #0, @long_dst ; zero it again for the next use. 169 170mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem 171 set_grs_a5a5 ; Fill all general regs with a fixed pattern 172 set_ccr_zero 173 174 ;; mov.l #xx:8, @erd- 175 mov.l #long_dst, er1 176 mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. 177;;; .word 0x010d 178;;; .word 0xa1a5 179 180 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 181 test_neg_clear 182 test_zero_clear 183 test_ovf_clear 184 test_carry_clear 185 186 test_gr_a5a5 0 ; Make sure other general regs not disturbed 187 test_h_gr32 long_dst-4, er1 188 test_gr_a5a5 2 189 test_gr_a5a5 3 190 test_gr_a5a5 4 191 test_gr_a5a5 5 192 test_gr_a5a5 6 193 test_gr_a5a5 7 194 195 ;; Now check the result of the move to memory. 196 cmp.l #0xa5, @long_dst 197 beq .Lnext3 198 fail 199.Lnext3: 200 mov.l #0, @long_dst ; zero it again for the next use. 201 202mov_l_imm8_to_preinc: ; pre-increment from register to mem 203 set_grs_a5a5 ; Fill all general regs with a fixed pattern 204 set_ccr_zero 205 206 ;; mov.l #xx:8, @+erd 207 mov.l #long_dst-4, er1 208 mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands 209;;; .word 0x010d 210;;; .word 0x91a5 211 212 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 213 test_neg_clear 214 test_zero_clear 215 test_ovf_clear 216 test_carry_clear 217 218 test_gr_a5a5 0 ; Make sure other general regs not disturbed 219 test_h_gr32 long_dst, er1 220 test_gr_a5a5 2 221 test_gr_a5a5 3 222 test_gr_a5a5 4 223 test_gr_a5a5 5 224 test_gr_a5a5 6 225 test_gr_a5a5 7 226 227 ;; Now check the result of the move to memory. 228 cmp.l #0xa5, @long_dst 229 beq .Lnext4 230 fail 231.Lnext4: 232 mov.l #0, @long_dst ; zero it again for the next use. 233 234mov_l_imm8_to_predec: ; pre-decrement from register to mem 235 set_grs_a5a5 ; Fill all general regs with a fixed pattern 236 set_ccr_zero 237 238 ;; mov.l #xx:8, @-erd 239 mov.l #long_dst+4, er1 240 mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands 241;;; .word 0x010d 242;;; .word 0xb1a5 243 244 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 245 test_neg_clear 246 test_zero_clear 247 test_ovf_clear 248 test_carry_clear 249 250 test_gr_a5a5 0 ; Make sure other general regs not disturbed 251 test_h_gr32 long_dst, er1 252 test_gr_a5a5 2 253 test_gr_a5a5 3 254 test_gr_a5a5 4 255 test_gr_a5a5 5 256 test_gr_a5a5 6 257 test_gr_a5a5 7 258 259 ;; Now check the result of the move to memory. 260 cmp.l #0xa5, @long_dst 261 beq .Lnext5 262 fail 263.Lnext5: 264 mov.l #0, @long_dst ; zero it again for the next use. 265 266mov_l_imm8_to_disp2: 267 set_grs_a5a5 ; Fill all general regs with a fixed pattern 268 set_ccr_zero 269 270 ;; mov.l #xx:8, @(dd:2, erd) 271 mov.l #long_dst-12, er1 272 mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand 273;;; .word 0x010d 274;;; .word 0x31a5 275 276 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 277 test_neg_clear 278 test_zero_clear 279 test_ovf_clear 280 test_carry_clear 281 282 test_gr_a5a5 0 ; Make sure other general regs not disturbed 283 test_h_gr32 long_dst-12, er1 284 test_gr_a5a5 2 285 test_gr_a5a5 3 286 test_gr_a5a5 4 287 test_gr_a5a5 5 288 test_gr_a5a5 6 289 test_gr_a5a5 7 290 291 ;; Now check the result of the move to memory. 292 cmp.l #0xa5, @long_dst 293 beq .Lnext6 294 fail 295.Lnext6: 296 mov.l #0, @long_dst ; zero it again for the next use. 297 298mov_l_imm8_to_disp16: 299 set_grs_a5a5 ; Fill all general regs with a fixed pattern 300 set_ccr_zero 301 302 ;; mov.l #xx:8, @(dd:16, erd) 303 mov.l #long_dst-4, er1 304 mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand 305;;; .word 0x010d 306;;; .word 0x6f90 307;;; .word 0x0004 308 309 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 310 test_neg_clear 311 test_zero_clear 312 test_ovf_clear 313 test_carry_clear 314 315 test_gr_a5a5 0 ; Make sure other general regs not disturbed 316 test_h_gr32 long_dst-4, er1 317 test_gr_a5a5 2 318 test_gr_a5a5 3 319 test_gr_a5a5 4 320 test_gr_a5a5 5 321 test_gr_a5a5 6 322 test_gr_a5a5 7 323 324 ;; Now check the result of the move to memory. 325 cmp.l #0xa5, @long_dst 326 beq .Lnext7 327 fail 328.Lnext7: 329 mov.l #0, @long_dst ; zero it again for the next use. 330 331mov_l_imm8_to_disp32: 332 set_grs_a5a5 ; Fill all general regs with a fixed pattern 333 set_ccr_zero 334 335 ;; mov.l #xx:8, @(dd:32, erd) 336 mov.l #long_dst-8, er1 337 mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand 338;;; .word 0x010d 339;;; .word 0xc9a5 340;;; .long 8 341 342 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 343 test_neg_clear 344 test_zero_clear 345 test_ovf_clear 346 test_carry_clear 347 348 test_gr_a5a5 0 ; Make sure other general regs not disturbed 349 test_h_gr32 long_dst-8, er1 350 test_gr_a5a5 2 351 test_gr_a5a5 3 352 test_gr_a5a5 4 353 test_gr_a5a5 5 354 test_gr_a5a5 6 355 test_gr_a5a5 7 356 357 ;; Now check the result of the move to memory. 358 cmp.l #0xa5, @long_dst 359 beq .Lnext8 360 fail 361.Lnext8: 362 mov.l #0, @long_dst ; zero it again for the next use. 363 364mov_l_imm8_to_abs16: 365 set_grs_a5a5 ; Fill all general regs with a fixed pattern 366 set_ccr_zero 367 368 ;; mov.l #xx:8, @aa:16 369 mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand 370;;; .word 0x010d 371;;; .word 0x40a5 372;;; .word @long_dst 373 374 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 375 test_neg_clear 376 test_zero_clear 377 test_ovf_clear 378 test_carry_clear 379 380 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 381 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 382 test_gr_a5a5 2 ; to examine the destination memory). 383 test_gr_a5a5 3 384 test_gr_a5a5 4 385 test_gr_a5a5 5 386 test_gr_a5a5 6 387 test_gr_a5a5 7 388 389 ;; Now check the result of the move to memory. 390 cmp.l #0xa5, @long_dst 391 beq .Lnext9 392 fail 393.Lnext9: 394 mov.l #0, @long_dst ; zero it again for the next use. 395 396mov_l_imm8_to_abs32: 397 set_grs_a5a5 ; Fill all general regs with a fixed pattern 398 set_ccr_zero 399 400 ;; mov.l #xx:8, @aa:32 401 mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand 402;;; .word 0x010d 403;;; .word 0x48a5 404;;; .long @long_dst 405 406 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 407 test_neg_clear 408 test_zero_clear 409 test_ovf_clear 410 test_carry_clear 411 412 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 413 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 414 test_gr_a5a5 2 ; to examine the destination memory). 415 test_gr_a5a5 3 416 test_gr_a5a5 4 417 test_gr_a5a5 5 418 test_gr_a5a5 6 419 test_gr_a5a5 7 420 421 ;; Now check the result of the move to memory. 422 cmp.l #0xa5, @long_dst 423 beq .Lnext10 424 fail 425.Lnext10: 426 mov.l #0, @long_dst ; zero it again for the next use. 427 428mov_l_imm16_to_indirect: 429 set_grs_a5a5 ; Fill all general regs with a fixed pattern 430 set_ccr_zero 431 432 ;; mov.l #xx:16, @erd 433 mov.l #long_dst, er1 434 mov.l #0xdead:16, @er1 ; Register indirect operand 435;;; .word 0x7a7c 436;;; .word 0xdead 437;;; .word 0x0100 438 439 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 440 test_neg_clear 441 test_zero_clear 442 test_ovf_clear 443 test_carry_clear 444 445 test_gr_a5a5 0 ; Make sure other general regs not disturbed 446 test_h_gr32 long_dst, er1 447 test_gr_a5a5 2 448 test_gr_a5a5 3 449 test_gr_a5a5 4 450 test_gr_a5a5 5 451 test_gr_a5a5 6 452 test_gr_a5a5 7 453 454 ;; Now check the result of the move to memory. 455 cmp.l #0xdead, @long_dst 456 beq .Lnext11 457 fail 458.Lnext11: 459 mov.l #0, @long_dst ; zero it again for the next use. 460 461mov_l_imm16_to_postinc: ; post-increment from imm16 to mem 462 set_grs_a5a5 ; Fill all general regs with a fixed pattern 463 set_ccr_zero 464 465 ;; mov.l #xx:16, @erd+ 466 mov.l #long_dst, er1 467 mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. 468;;; .word 0x7a7c 469;;; .word 0xdead 470;;; .word 0x8100 471 472 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 473 test_neg_clear 474 test_zero_clear 475 test_ovf_clear 476 test_carry_clear 477 478 test_gr_a5a5 0 ; Make sure other general regs not disturbed 479 test_h_gr32 long_dst+4, er1 480 test_gr_a5a5 2 481 test_gr_a5a5 3 482 test_gr_a5a5 4 483 test_gr_a5a5 5 484 test_gr_a5a5 6 485 test_gr_a5a5 7 486 487 ;; Now check the result of the move to memory. 488 cmp.l #0xdead, @long_dst 489 beq .Lnext12 490 fail 491.Lnext12: 492 mov.l #0, @long_dst ; zero it again for the next use. 493 494mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem 495 set_grs_a5a5 ; Fill all general regs with a fixed pattern 496 set_ccr_zero 497 498 ;; mov.l #xx:16, @erd- 499 mov.l #long_dst, er1 500 mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. 501;;; .word 0x7a7c 502;;; .word 0xdead 503;;; .word 0xa100 504 505 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 506 test_neg_clear 507 test_zero_clear 508 test_ovf_clear 509 test_carry_clear 510 511 test_gr_a5a5 0 ; Make sure other general regs not disturbed 512 test_h_gr32 long_dst-4, er1 513 test_gr_a5a5 2 514 test_gr_a5a5 3 515 test_gr_a5a5 4 516 test_gr_a5a5 5 517 test_gr_a5a5 6 518 test_gr_a5a5 7 519 520 ;; Now check the result of the move to memory. 521 cmp.l #0xdead, @long_dst 522 beq .Lnext13 523 fail 524.Lnext13: 525 mov.l #0, @long_dst ; zero it again for the next use. 526 527mov_l_imm16_to_preinc: ; pre-increment from register to mem 528 set_grs_a5a5 ; Fill all general regs with a fixed pattern 529 set_ccr_zero 530 531 ;; mov.l #xx:16, @+erd 532 mov.l #long_dst-4, er1 533 mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands 534;;; .word 0x7a7c 535;;; .word 0xdead 536;;; .word 0x9100 537 538 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 539 test_neg_clear 540 test_zero_clear 541 test_ovf_clear 542 test_carry_clear 543 544 test_gr_a5a5 0 ; Make sure other general regs not disturbed 545 test_h_gr32 long_dst, er1 546 test_gr_a5a5 2 547 test_gr_a5a5 3 548 test_gr_a5a5 4 549 test_gr_a5a5 5 550 test_gr_a5a5 6 551 test_gr_a5a5 7 552 553 ;; Now check the result of the move to memory. 554 cmp.l #0xdead, @long_dst 555 beq .Lnext14 556 fail 557.Lnext14: 558 mov.l #0, @long_dst ; zero it again for the next use. 559 560mov_l_imm16_to_predec: ; pre-decrement from register to mem 561 set_grs_a5a5 ; Fill all general regs with a fixed pattern 562 set_ccr_zero 563 564 ;; mov.l #xx:16, @-erd 565 mov.l #long_dst+4, er1 566 mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands 567;;; .word 0x7a7c 568;;; .word 0xdead 569;;; .word 0xb100 570 571 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 572 test_neg_clear 573 test_zero_clear 574 test_ovf_clear 575 test_carry_clear 576 577 test_gr_a5a5 0 ; Make sure other general regs not disturbed 578 test_h_gr32 long_dst, er1 579 test_gr_a5a5 2 580 test_gr_a5a5 3 581 test_gr_a5a5 4 582 test_gr_a5a5 5 583 test_gr_a5a5 6 584 test_gr_a5a5 7 585 586 ;; Now check the result of the move to memory. 587 cmp.l #0xdead, @long_dst 588 beq .Lnext15 589 fail 590.Lnext15: 591 mov.l #0, @long_dst ; zero it again for the next use. 592 593mov_l_imm16_to_disp2: 594 set_grs_a5a5 ; Fill all general regs with a fixed pattern 595 set_ccr_zero 596 597 ;; mov.l #xx:16, @(dd:2, erd) 598 mov.l #long_dst-12, er1 599 mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand 600;;; .word 0x7a7c 601;;; .word 0xdead 602;;; .word 0x3100 603 604 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 605 test_neg_clear 606 test_zero_clear 607 test_ovf_clear 608 test_carry_clear 609 610 test_gr_a5a5 0 ; Make sure other general regs not disturbed 611 test_h_gr32 long_dst-12, er1 612 test_gr_a5a5 2 613 test_gr_a5a5 3 614 test_gr_a5a5 4 615 test_gr_a5a5 5 616 test_gr_a5a5 6 617 test_gr_a5a5 7 618 619 ;; Now check the result of the move to memory. 620 cmp.l #0xdead, @long_dst 621 beq .Lnext16 622 fail 623.Lnext16: 624 mov.l #0, @long_dst ; zero it again for the next use. 625 626mov_l_imm16_to_disp16: 627 set_grs_a5a5 ; Fill all general regs with a fixed pattern 628 set_ccr_zero 629 630 ;; mov.l #xx:16, @(dd:16, erd) 631 mov.l #long_dst-4, er1 632 mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand 633;;; .word 0x7a7c 634;;; .word 0xdead 635;;; .word 0xc100 636;;; .word 0x0004 637 638 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 639 test_neg_clear 640 test_zero_clear 641 test_ovf_clear 642 test_carry_clear 643 644 test_gr_a5a5 0 ; Make sure other general regs not disturbed 645 test_h_gr32 long_dst-4, er1 646 test_gr_a5a5 2 647 test_gr_a5a5 3 648 test_gr_a5a5 4 649 test_gr_a5a5 5 650 test_gr_a5a5 6 651 test_gr_a5a5 7 652 653 ;; Now check the result of the move to memory. 654 cmp.l #0xdead, @long_dst 655 beq .Lnext17 656 fail 657.Lnext17: 658 mov.l #0, @long_dst ; zero it again for the next use. 659 660mov_l_imm16_to_disp32: 661 set_grs_a5a5 ; Fill all general regs with a fixed pattern 662 set_ccr_zero 663 664 ;; mov.l #xx:16, @(dd:32, erd) 665 mov.l #long_dst-8, er1 666 mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand 667;;; .word 0x7a7c 668;;; .word 0xdead 669;;; .word 0xc900 670;;; .long 8 671 672 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 673 test_neg_clear 674 test_zero_clear 675 test_ovf_clear 676 test_carry_clear 677 678 test_gr_a5a5 0 ; Make sure other general regs not disturbed 679 test_h_gr32 long_dst-8, er1 680 test_gr_a5a5 2 681 test_gr_a5a5 3 682 test_gr_a5a5 4 683 test_gr_a5a5 5 684 test_gr_a5a5 6 685 test_gr_a5a5 7 686 687 ;; Now check the result of the move to memory. 688 cmp.l #0xdead, @long_dst 689 beq .Lnext18 690 fail 691.Lnext18: 692 mov.l #0, @long_dst ; zero it again for the next use. 693 694mov_l_imm16_to_abs16: 695 set_grs_a5a5 ; Fill all general regs with a fixed pattern 696 set_ccr_zero 697 698 ;; mov.l #xx:16, @aa:16 699 mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand 700;;; .word 0x7a7c 701;;; .word 0xdead 702;;; .word 0x4000 703;;; .word @long_dst 704 705 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 706 test_neg_clear 707 test_zero_clear 708 test_ovf_clear 709 test_carry_clear 710 711 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 712 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 713 test_gr_a5a5 2 ; to examine the destination memory). 714 test_gr_a5a5 3 715 test_gr_a5a5 4 716 test_gr_a5a5 5 717 test_gr_a5a5 6 718 test_gr_a5a5 7 719 720 ;; Now check the result of the move to memory. 721 cmp.l #0xdead, @long_dst 722 beq .Lnext19 723 fail 724.Lnext19: 725 mov.l #0, @long_dst ; zero it again for the next use. 726 727mov_l_imm16_to_abs32: 728 set_grs_a5a5 ; Fill all general regs with a fixed pattern 729 set_ccr_zero 730 731 ;; mov.l #xx:16, @aa:32 732 mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand 733;;; .word 0x7a7c 734;;; .word 0xdead 735;;; .word 0x4800 736;;; .long @long_dst 737 738 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 739 test_neg_clear 740 test_zero_clear 741 test_ovf_clear 742 test_carry_clear 743 744 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 745 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 746 test_gr_a5a5 2 ; to examine the destination memory). 747 test_gr_a5a5 3 748 test_gr_a5a5 4 749 test_gr_a5a5 5 750 test_gr_a5a5 6 751 test_gr_a5a5 7 752 753 ;; Now check the result of the move to memory. 754 cmp.l #0xdead, @long_dst 755 beq .Lnext20 756 fail 757.Lnext20: 758 mov.l #0, @long_dst ; zero it again for the next use. 759 760mov_l_imm32_to_indirect: 761 set_grs_a5a5 ; Fill all general regs with a fixed pattern 762 set_ccr_zero 763 764 ;; mov.l #xx:32, @erd 765 mov.l #long_dst, er1 766 mov.l #0xcafedead:32, @er1 ; Register indirect operand 767;;; .word 0x7a74 768;;; .long 0xcafedead 769;;; .word 0x0100 770 771 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 772 test_neg_set 773 test_zero_clear 774 test_ovf_clear 775 test_carry_clear 776 777 test_gr_a5a5 0 ; Make sure other general regs not disturbed 778 test_h_gr32 long_dst, er1 779 test_gr_a5a5 2 780 test_gr_a5a5 3 781 test_gr_a5a5 4 782 test_gr_a5a5 5 783 test_gr_a5a5 6 784 test_gr_a5a5 7 785 786 ;; Now check the result of the move to memory. 787 cmp.l #0xcafedead, @long_dst 788 beq .Lnext21 789 fail 790.Lnext21: 791 mov.l #0, @long_dst ; zero it again for the next use. 792 793mov_l_imm32_to_postinc: ; post-increment from imm32 to mem 794 set_grs_a5a5 ; Fill all general regs with a fixed pattern 795 set_ccr_zero 796 797 ;; mov.l #xx:32, @erd+ 798 mov.l #long_dst, er1 799 mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. 800;;; .word 0x7a74 801;;; .long 0xcafedead 802;;; .word 0x8100 803 804 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 805 test_neg_set 806 test_zero_clear 807 test_ovf_clear 808 test_carry_clear 809 810 test_gr_a5a5 0 ; Make sure other general regs not disturbed 811 test_h_gr32 long_dst+4, er1 812 test_gr_a5a5 2 813 test_gr_a5a5 3 814 test_gr_a5a5 4 815 test_gr_a5a5 5 816 test_gr_a5a5 6 817 test_gr_a5a5 7 818 819 ;; Now check the result of the move to memory. 820 cmp.l #0xcafedead, @long_dst 821 beq .Lnext22 822 fail 823.Lnext22: 824 mov.l #0, @long_dst ; zero it again for the next use. 825 826mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem 827 set_grs_a5a5 ; Fill all general regs with a fixed pattern 828 set_ccr_zero 829 830 ;; mov.l #xx:32, @erd- 831 mov.l #long_dst, er1 832 mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. 833;;; .word 0x7a74 834;;; .long 0xcafedead 835;;; .word 0xa100 836 837 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 838 test_neg_set 839 test_zero_clear 840 test_ovf_clear 841 test_carry_clear 842 843 test_gr_a5a5 0 ; Make sure other general regs not disturbed 844 test_h_gr32 long_dst-4, er1 845 test_gr_a5a5 2 846 test_gr_a5a5 3 847 test_gr_a5a5 4 848 test_gr_a5a5 5 849 test_gr_a5a5 6 850 test_gr_a5a5 7 851 852 ;; Now check the result of the move to memory. 853 cmp.l #0xcafedead, @long_dst 854 beq .Lnext23 855 fail 856.Lnext23: 857 mov.l #0, @long_dst ; zero it again for the next use. 858 859mov_l_imm32_to_preinc: ; pre-increment from register to mem 860 set_grs_a5a5 ; Fill all general regs with a fixed pattern 861 set_ccr_zero 862 863 ;; mov.l #xx:32, @+erd 864 mov.l #long_dst-4, er1 865 mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands 866;;; .word 0x7a74 867;;; .long 0xcafedead 868;;; .word 0x9100 869 870 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 871 test_neg_set 872 test_zero_clear 873 test_ovf_clear 874 test_carry_clear 875 876 test_gr_a5a5 0 ; Make sure other general regs not disturbed 877 test_h_gr32 long_dst, er1 878 test_gr_a5a5 2 879 test_gr_a5a5 3 880 test_gr_a5a5 4 881 test_gr_a5a5 5 882 test_gr_a5a5 6 883 test_gr_a5a5 7 884 885 ;; Now check the result of the move to memory. 886 cmp.l #0xcafedead, @long_dst 887 beq .Lnext24 888 fail 889.Lnext24: 890 mov.l #0, @long_dst ; zero it again for the next use. 891 892mov_l_imm32_to_predec: ; pre-decrement from register to mem 893 set_grs_a5a5 ; Fill all general regs with a fixed pattern 894 set_ccr_zero 895 896 ;; mov.l #xx:32, @-erd 897 mov.l #long_dst+4, er1 898 mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands 899;;; .word 0x7a74 900;;; .long 0xcafedead 901;;; .word 0xb100 902 903 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 904 test_neg_set 905 test_zero_clear 906 test_ovf_clear 907 test_carry_clear 908 909 test_gr_a5a5 0 ; Make sure other general regs not disturbed 910 test_h_gr32 long_dst, er1 911 test_gr_a5a5 2 912 test_gr_a5a5 3 913 test_gr_a5a5 4 914 test_gr_a5a5 5 915 test_gr_a5a5 6 916 test_gr_a5a5 7 917 918 ;; Now check the result of the move to memory. 919 cmp.l #0xcafedead, @long_dst 920 beq .Lnext25 921 fail 922.Lnext25: 923 mov.l #0, @long_dst ; zero it again for the next use. 924 925mov_l_imm32_to_disp2: 926 set_grs_a5a5 ; Fill all general regs with a fixed pattern 927 set_ccr_zero 928 929 ;; mov.l #xx:32, @(dd:2, erd) 930 mov.l #long_dst-12, er1 931 mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand 932;;; .word 0x7a74 933;;; .long 0xcafedead 934;;; .word 0x3100 935 936 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 937 test_neg_set 938 test_zero_clear 939 test_ovf_clear 940 test_carry_clear 941 942 test_gr_a5a5 0 ; Make sure other general regs not disturbed 943 test_h_gr32 long_dst-12, er1 944 test_gr_a5a5 2 945 test_gr_a5a5 3 946 test_gr_a5a5 4 947 test_gr_a5a5 5 948 test_gr_a5a5 6 949 test_gr_a5a5 7 950 951 ;; Now check the result of the move to memory. 952 cmp.l #0xcafedead, @long_dst 953 beq .Lnext26 954 fail 955.Lnext26: 956 mov.l #0, @long_dst ; zero it again for the next use. 957 958mov_l_imm32_to_disp16: 959 set_grs_a5a5 ; Fill all general regs with a fixed pattern 960 set_ccr_zero 961 962 ;; mov.l #xx:32, @(dd:16, erd) 963 mov.l #long_dst-4, er1 964 mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand 965;;; .word 0x7a74 966;;; .long 0xcafedead 967;;; .word 0xc100 968;;; .word 0x0004 969 970 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 971 test_neg_set 972 test_zero_clear 973 test_ovf_clear 974 test_carry_clear 975 976 test_gr_a5a5 0 ; Make sure other general regs not disturbed 977 test_h_gr32 long_dst-4, er1 978 test_gr_a5a5 2 979 test_gr_a5a5 3 980 test_gr_a5a5 4 981 test_gr_a5a5 5 982 test_gr_a5a5 6 983 test_gr_a5a5 7 984 985 ;; Now check the result of the move to memory. 986 cmp.l #0xcafedead, @long_dst 987 beq .Lnext27 988 fail 989.Lnext27: 990 mov.l #0, @long_dst ; zero it again for the next use. 991 992mov_l_imm32_to_disp32: 993 set_grs_a5a5 ; Fill all general regs with a fixed pattern 994 set_ccr_zero 995 996 ;; mov.l #xx:32, @(dd:32, erd) 997 mov.l #long_dst-8, er1 998 mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand 999;;; .word 0x7a74 1000;;; .long 0xcafedead 1001;;; .word 0xc900 1002;;; .long 8 1003 1004 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1005 test_neg_set 1006 test_zero_clear 1007 test_ovf_clear 1008 test_carry_clear 1009 1010 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1011 test_h_gr32 long_dst-8, er1 1012 test_gr_a5a5 2 1013 test_gr_a5a5 3 1014 test_gr_a5a5 4 1015 test_gr_a5a5 5 1016 test_gr_a5a5 6 1017 test_gr_a5a5 7 1018 1019 ;; Now check the result of the move to memory. 1020 cmp.l #0xcafedead, @long_dst 1021 beq .Lnext28 1022 fail 1023.Lnext28: 1024 mov.l #0, @long_dst ; zero it again for the next use. 1025 1026mov_l_imm32_to_abs16: 1027 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1028 set_ccr_zero 1029 1030 ;; mov.l #xx:32, @aa:16 1031 mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand 1032;;; .word 0x7a74 1033;;; .long 0xcafedead 1034;;; .word 0x4000 1035;;; .word @long_dst 1036 1037 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1038 test_neg_set 1039 test_zero_clear 1040 test_ovf_clear 1041 test_carry_clear 1042 1043 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1044 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1045 test_gr_a5a5 2 ; to examine the destination memory). 1046 test_gr_a5a5 3 1047 test_gr_a5a5 4 1048 test_gr_a5a5 5 1049 test_gr_a5a5 6 1050 test_gr_a5a5 7 1051 1052 ;; Now check the result of the move to memory. 1053 cmp.l #0xcafedead, @long_dst 1054 beq .Lnext29 1055 fail 1056.Lnext29: 1057 mov.l #0, @long_dst ; zero it again for the next use. 1058 1059mov_l_imm32_to_abs32: 1060 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1061 set_ccr_zero 1062 1063 ;; mov.l #xx:32, @aa:32 1064 mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand 1065;;; .word 0x7a74 1066;;; .long 0xcafedead 1067;;; .word 0x4800 1068;;; .long @long_dst 1069 1070 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1071 test_neg_set 1072 test_zero_clear 1073 test_ovf_clear 1074 test_carry_clear 1075 1076 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1077 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1078 test_gr_a5a5 2 ; to examine the destination memory). 1079 test_gr_a5a5 3 1080 test_gr_a5a5 4 1081 test_gr_a5a5 5 1082 test_gr_a5a5 6 1083 test_gr_a5a5 7 1084 1085 ;; Now check the result of the move to memory. 1086 cmp.l #0xcafedead, @long_dst 1087 beq .Lnext30 1088 fail 1089.Lnext30: 1090 mov.l #0, @long_dst ; zero it again for the next use. 1091 1092.endif 1093 1094 ;; 1095 ;; Move long from register source 1096 ;; 1097 1098mov_l_reg32_to_reg32: 1099 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1100 set_ccr_zero 1101 1102 ;; mov.l ers, erd 1103 mov.l #0x12345678, er1 1104 mov.l er1, er0 ; Register 32-bit operand 1105;;; .word 0x0f90 1106 1107 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1108 test_neg_clear 1109 test_zero_clear 1110 test_ovf_clear 1111 test_carry_clear 1112 test_h_gr32 0x12345678 er0 1113 test_h_gr32 0x12345678 er1 ; mov src unchanged 1114 1115 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1116 test_gr_a5a5 3 1117 test_gr_a5a5 4 1118 test_gr_a5a5 5 1119 test_gr_a5a5 6 1120 test_gr_a5a5 7 1121 1122mov_l_reg32_to_indirect: 1123 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1124 set_ccr_zero 1125 1126 ;; mov.l ers, @erd 1127 mov.l #long_dst, er1 1128 mov.l er0, @er1 ; Register indirect operand 1129;;; .word 0x0100 1130;;; .word 0x6990 1131 1132 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1133 test_neg_set 1134 test_zero_clear 1135 test_ovf_clear 1136 test_carry_clear 1137 1138 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1139 test_h_gr32 long_dst, er1 1140 test_gr_a5a5 2 1141 test_gr_a5a5 3 1142 test_gr_a5a5 4 1143 test_gr_a5a5 5 1144 test_gr_a5a5 6 1145 test_gr_a5a5 7 1146 1147 ;; Now check the result of the move to memory. 1148 mov.l #0, er0 1149 mov.l @long_dst, er0 1150 cmp.l er2, er0 1151 beq .Lnext44 1152 fail 1153.Lnext44: 1154 mov.l #0, er0 1155 mov.l er0, @long_dst ; zero it again for the next use. 1156 1157.if (sim_cpu == h8sx) 1158mov_l_reg32_to_postinc: ; post-increment from register to mem 1159 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1160 set_ccr_zero 1161 1162 ;; mov.l ers, @erd+ 1163 mov.l #long_dst, er1 1164 mov.l er0, @er1+ ; Register post-incr operand 1165;;; .word 0x0103 1166;;; .word 0x6d90 1167 1168 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1169 test_neg_set 1170 test_zero_clear 1171 test_ovf_clear 1172 test_carry_clear 1173 1174 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1175 test_h_gr32 long_dst+4, er1 1176 test_gr_a5a5 2 1177 test_gr_a5a5 3 1178 test_gr_a5a5 4 1179 test_gr_a5a5 5 1180 test_gr_a5a5 6 1181 test_gr_a5a5 7 1182 1183 ;; Now check the result of the move to memory. 1184 cmp.l er2, @long_dst 1185 beq .Lnext49 1186 fail 1187.Lnext49: 1188 mov.l #0, @long_dst ; zero it again for the next use. 1189 1190mov_l_reg32_to_postdec: ; post-decrement from register to mem 1191 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1192 set_ccr_zero 1193 1194 ;; mov.l ers, @erd- 1195 mov.l #long_dst, er1 1196 mov.l er0, @er1- ; Register post-decr operand 1197;;; .word 0x0101 1198;;; .word 0x6d90 1199 1200 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1201 test_neg_set 1202 test_zero_clear 1203 test_ovf_clear 1204 test_carry_clear 1205 1206 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1207 test_h_gr32 long_dst-4, er1 1208 test_gr_a5a5 2 1209 test_gr_a5a5 3 1210 test_gr_a5a5 4 1211 test_gr_a5a5 5 1212 test_gr_a5a5 6 1213 test_gr_a5a5 7 1214 1215 ;; Now check the result of the move to memory. 1216 cmp.l er2, @long_dst 1217 beq .Lnext50 1218 fail 1219.Lnext50: 1220 ;; special case same register 1221 mov.l #long_dst, er0 1222 mov.l er0, er1 1223 subs #4, er1 1224 mov.l er0, @er0- 1225 mov.l @long_dst, er0 1226 cmp.l er0, er1 1227 beq .Lnext54 1228 fail 1229.Lnext54: 1230 mov.l #0, @long_dst ; zero it again for the next use. 1231 1232mov_l_reg32_to_preinc: ; pre-increment from register to mem 1233 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1234 set_ccr_zero 1235 1236 ;; mov.l ers, @+erd 1237 mov.l #long_dst-4, er1 1238 mov.l er0, @+er1 ; Register pre-incr operand 1239;;; .word 0x0102 1240;;; .word 0x6d90 1241 1242 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1243 test_neg_set 1244 test_zero_clear 1245 test_ovf_clear 1246 test_carry_clear 1247 1248 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1249 test_h_gr32 long_dst, er1 1250 test_gr_a5a5 2 1251 test_gr_a5a5 3 1252 test_gr_a5a5 4 1253 test_gr_a5a5 5 1254 test_gr_a5a5 6 1255 test_gr_a5a5 7 1256 1257 ;; Now check the result of the move to memory. 1258 cmp.l er2, @long_dst 1259 beq .Lnext51 1260 fail 1261.Lnext51: 1262 mov.l #0, @long_dst ; zero it again for the next use. 1263.endif ; h8sx 1264 1265mov_l_reg32_to_predec: ; pre-decrement from register to mem 1266 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1267 set_ccr_zero 1268 1269 ;; mov.l ers, @-erd 1270 mov.l #long_dst+4, er1 1271 mov.l er0, @-er1 ; Register pre-decr operand 1272;;; .word 0x0100 1273;;; .word 0x6d90 1274 1275 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1276 test_neg_set 1277 test_zero_clear 1278 test_ovf_clear 1279 test_carry_clear 1280 1281 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1282 test_h_gr32 long_dst, er1 1283 test_gr_a5a5 2 1284 test_gr_a5a5 3 1285 test_gr_a5a5 4 1286 test_gr_a5a5 5 1287 test_gr_a5a5 6 1288 test_gr_a5a5 7 1289 1290 ;; Now check the result of the move to memory. 1291 mov.l #0, er0 1292 mov.l @long_dst, er0 1293 cmp.l er2, er0 1294 beq .Lnext48 1295 fail 1296.Lnext48: 1297 ;; Special case in same register 1298 ;; CCR confirmation omitted 1299 mov.l #long_dst+4, er1 1300 mov.l er1, er0 1301 subs #4, er1 1302 mov.l er0, @-er0 1303 mov.l @long_dst, er0 1304 cmp.l er1, er0 1305 beq .Lnext47 1306 fail 1307.Lnext47: 1308 mov.l #0, er0 1309 mov.l er0, @long_dst ; zero it again for the next use. 1310 1311.if (sim_cpu == h8sx) 1312mov_l_reg32_to_disp2: 1313 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1314 set_ccr_zero 1315 1316 ;; mov.l ers, @(dd:2, erd) 1317 mov.l #long_dst-12, er1 1318 mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand 1319;;; .word 0x0103 1320;;; .word 0x6990 1321 1322 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1323 test_neg_set 1324 test_zero_clear 1325 test_ovf_clear 1326 test_carry_clear 1327 1328 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1329 test_h_gr32 long_dst-12, er1 1330 test_gr_a5a5 2 1331 test_gr_a5a5 3 1332 test_gr_a5a5 4 1333 test_gr_a5a5 5 1334 test_gr_a5a5 6 1335 test_gr_a5a5 7 1336 1337 ;; Now check the result of the move to memory. 1338 cmp.l er2, @long_dst 1339 beq .Lnext52 1340 fail 1341.Lnext52: 1342 mov.l #0, @long_dst ; zero it again for the next use. 1343.endif ; h8sx 1344 1345mov_l_reg32_to_disp16: 1346 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1347 set_ccr_zero 1348 1349 ;; mov.l ers, @(dd:16, erd) 1350 mov.l #long_dst-4, er1 1351 mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand 1352;;; .word 0x0100 1353;;; .word 0x6f90 1354;;; .word 0x0004 1355 1356 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1357 test_neg_set 1358 test_zero_clear 1359 test_ovf_clear 1360 test_carry_clear 1361 1362 test_h_gr32 long_dst-4, er1 1363 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1364 test_gr_a5a5 2 1365 test_gr_a5a5 3 1366 test_gr_a5a5 4 1367 test_gr_a5a5 5 1368 test_gr_a5a5 6 1369 test_gr_a5a5 7 1370 1371 ;; Now check the result of the move to memory. 1372 mov.l #0, er0 1373 mov.l @long_dst, er0 1374 cmp.l er2, er0 1375 beq .Lnext45 1376 fail 1377.Lnext45: 1378 mov.l #0, er0 1379 mov.l er0, @long_dst ; zero it again for the next use. 1380 1381mov_l_reg32_to_disp32: 1382 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1383 set_ccr_zero 1384 1385 ;; mov.l ers, @(dd:32, erd) 1386 mov.l #long_dst-8, er1 1387 mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand 1388;;; .word 0x7890 1389;;; .word 0x6ba0 1390;;; .long 8 1391 1392 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1393 test_neg_set 1394 test_zero_clear 1395 test_ovf_clear 1396 test_carry_clear 1397 1398 test_h_gr32 long_dst-8, er1 1399 test_gr_a5a5 0 ; Make sure other general regs not disturbed 1400 test_gr_a5a5 2 1401 test_gr_a5a5 3 1402 test_gr_a5a5 4 1403 test_gr_a5a5 5 1404 test_gr_a5a5 6 1405 test_gr_a5a5 7 1406 1407 ;; Now check the result of the move to memory. 1408 mov.l #0, er0 1409 mov.l @long_dst, er0 1410 cmp.l er2, er0 1411 beq .Lnext46 1412 fail 1413.Lnext46: 1414 mov.l #0, er0 1415 mov.l er0, @long_dst ; zero it again for the next use. 1416 1417mov_l_reg32_to_abs16: 1418 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1419 set_ccr_zero 1420 1421 ;; mov.l ers, @aa:16 1422 mov.l er0, @long_dst:16 ; 16-bit address-direct operand 1423;;; .word 0x0100 1424;;; .word 0x6b80 1425;;; .word @long_dst 1426 1427 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1428 test_neg_set 1429 test_zero_clear 1430 test_ovf_clear 1431 test_carry_clear 1432 1433 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1434 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1435 test_gr_a5a5 2 ; to examine the destination memory). 1436 test_gr_a5a5 3 1437 test_gr_a5a5 4 1438 test_gr_a5a5 5 1439 test_gr_a5a5 6 1440 test_gr_a5a5 7 1441 1442 ;; Now check the result of the move to memory. 1443 mov.l #0, er0 1444 mov.l @long_dst, er0 1445 cmp.l er0, er1 1446 beq .Lnext41 1447 fail 1448.Lnext41: 1449 mov.l #0, er0 1450 mov.l er0, @long_dst ; zero it again for the next use. 1451 1452mov_l_reg32_to_abs32: 1453 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1454 set_ccr_zero 1455 1456 ;; mov.l ers, @aa:32 1457 mov.l er0, @long_dst:32 ; 32-bit address-direct operand 1458;;; .word 0x0100 1459;;; .word 0x6ba0 1460;;; .long @long_dst 1461 1462 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 1463 test_neg_set 1464 test_zero_clear 1465 test_ovf_clear 1466 test_carry_clear 1467 1468 test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed 1469 test_gr_a5a5 1 ; (first, because on h8/300 we must use one 1470 test_gr_a5a5 2 ; to examine the destination memory). 1471 test_gr_a5a5 3 1472 test_gr_a5a5 4 1473 test_gr_a5a5 5 1474 test_gr_a5a5 6 1475 test_gr_a5a5 7 1476 1477 ;; Now check the result of the move to memory. 1478 mov.l #0, er0 1479 mov.l @long_dst, er0 1480 cmp.l er0, er1 1481 beq .Lnext42 1482 fail 1483.Lnext42: 1484 mov.l #0, er0 1485 mov.l er0, @long_dst ; zero it again for the next use. 1486 1487 ;; 1488 ;; Move long to register destination. 1489 ;; 1490 1491mov_l_indirect_to_reg32: 1492 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1493 set_ccr_zero 1494 1495 ;; mov.l @ers, erd 1496 mov.l #long_src, er1 1497 mov.l @er1, er0 ; Register indirect operand 1498;;; .word 0x0100 1499;;; .word 0x6910 1500 1501 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1502 test_neg_clear 1503 test_zero_clear 1504 test_ovf_clear 1505 test_carry_clear 1506 1507 test_h_gr32 0x77777777 er0 1508 1509 test_h_gr32 long_src, er1 1510 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1511 test_gr_a5a5 3 1512 test_gr_a5a5 4 1513 test_gr_a5a5 5 1514 test_gr_a5a5 6 1515 test_gr_a5a5 7 1516 1517mov_l_postinc_to_reg32: ; post-increment from mem to register 1518 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1519 set_ccr_zero 1520 1521 ;; mov.l @ers+, erd 1522 1523 mov.l #long_src, er1 1524 mov.l @er1+, er0 ; Register post-incr operand 1525;;; .word 0x0100 1526;;; .word 0x6d10 1527 1528 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1529 test_neg_clear 1530 test_zero_clear 1531 test_ovf_clear 1532 test_carry_clear 1533 1534 test_h_gr32 0x77777777 er0 1535 1536 test_h_gr32 long_src+4, er1 1537 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1538 test_gr_a5a5 3 1539 test_gr_a5a5 4 1540 test_gr_a5a5 5 1541 test_gr_a5a5 6 1542 test_gr_a5a5 7 1543 1544.if (sim_cpu == h8sx) 1545mov_l_postdec_to_reg32: ; post-decrement from mem to register 1546 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1547 set_ccr_zero 1548 1549 ;; mov.l @ers-, erd 1550 1551 mov.l #long_src, er1 1552 mov.l @er1-, er0 ; Register post-decr operand 1553;;; .word 0x0102 1554;;; .word 0x6d10 1555 1556 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1557 test_neg_clear 1558 test_zero_clear 1559 test_ovf_clear 1560 test_carry_clear 1561 1562 test_h_gr32 0x77777777 er0 1563 1564 test_h_gr32 long_src-4, er1 1565 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1566 test_gr_a5a5 3 1567 test_gr_a5a5 4 1568 test_gr_a5a5 5 1569 test_gr_a5a5 6 1570 test_gr_a5a5 7 1571 1572mov_l_preinc_to_reg32: ; pre-increment from mem to register 1573 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1574 set_ccr_zero 1575 1576 ;; mov.l @+ers, erd 1577 1578 mov.l #long_src-4, er1 1579 mov.l @+er1, er0 ; Register pre-incr operand 1580;;; .word 0x0101 1581;;; .word 0x6d10 1582 1583 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1584 test_neg_clear 1585 test_zero_clear 1586 test_ovf_clear 1587 test_carry_clear 1588 1589 test_h_gr32 0x77777777 er0 1590 1591 test_h_gr32 long_src, er1 1592 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1593 test_gr_a5a5 3 1594 test_gr_a5a5 4 1595 test_gr_a5a5 5 1596 test_gr_a5a5 6 1597 test_gr_a5a5 7 1598 1599mov_l_predec_to_reg32: ; pre-decrement from mem to register 1600 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1601 set_ccr_zero 1602 1603 ;; mov.l @-ers, erd 1604 1605 mov.l #long_src+4, er1 1606 mov.l @-er1, er0 ; Register pre-decr operand 1607;;; .word 0x0103 1608;;; .word 0x6d10 1609 1610 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1611 test_neg_clear 1612 test_zero_clear 1613 test_ovf_clear 1614 test_carry_clear 1615 1616 test_h_gr32 0x77777777 er0 1617 1618 test_h_gr32 long_src, er1 1619 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1620 test_gr_a5a5 3 1621 test_gr_a5a5 4 1622 test_gr_a5a5 5 1623 test_gr_a5a5 6 1624 test_gr_a5a5 7 1625 1626 1627mov_l_disp2_to_reg32: 1628 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1629 set_ccr_zero 1630 1631 ;; mov.l @(dd:2, ers), erd 1632 mov.l #long_src-4, er1 1633 mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand 1634;;; .word 0x0101 1635;;; .word 0x6910 1636 1637 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1638 test_neg_clear 1639 test_zero_clear 1640 test_ovf_clear 1641 test_carry_clear 1642 1643 test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 1644 1645 test_h_gr32 long_src-4, er1 1646 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1647 test_gr_a5a5 3 1648 test_gr_a5a5 4 1649 test_gr_a5a5 5 1650 test_gr_a5a5 6 1651 test_gr_a5a5 7 1652.endif ; h8sx 1653 1654mov_l_disp16_to_reg32: 1655 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1656 set_ccr_zero 1657 1658 ;; mov.l @(dd:16, ers), erd 1659 mov.l #long_src+0x1234, er1 1660 mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand 1661;;; .word 0x0100 1662;;; .word 0x6f10 1663;;; .word -0x1234 1664 1665 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1666 test_neg_clear 1667 test_zero_clear 1668 test_ovf_clear 1669 test_carry_clear 1670 1671 test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 1672 1673 test_h_gr32 long_src+0x1234, er1 1674 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1675 test_gr_a5a5 3 1676 test_gr_a5a5 4 1677 test_gr_a5a5 5 1678 test_gr_a5a5 6 1679 test_gr_a5a5 7 1680 1681mov_l_disp32_to_reg32: 1682 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1683 set_ccr_zero 1684 1685 ;; mov.l @(dd:32, ers), erd 1686 mov.l #long_src+65536, er1 1687 mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand 1688;;; .word 0x7890 1689;;; .word 0x6b20 1690;;; .long -65536 1691 1692 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1693 test_neg_clear 1694 test_zero_clear 1695 test_ovf_clear 1696 test_carry_clear 1697 1698 test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 1699 1700 test_h_gr32 long_src+65536, er1 1701 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1702 test_gr_a5a5 3 1703 test_gr_a5a5 4 1704 test_gr_a5a5 5 1705 test_gr_a5a5 6 1706 test_gr_a5a5 7 1707 1708mov_l_abs16_to_reg32: 1709 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1710 set_ccr_zero 1711 1712 ;; mov.l @aa:16, erd 1713 mov.l @long_src:16, er0 ; 16-bit address-direct operand 1714;;; .word 0x0100 1715;;; .word 0x6b00 1716;;; .word @long_src 1717 1718 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1719 test_neg_clear 1720 test_zero_clear 1721 test_ovf_clear 1722 test_carry_clear 1723 1724 test_h_gr32 0x77777777 er0 1725 1726 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1727 test_gr_a5a5 2 1728 test_gr_a5a5 3 1729 test_gr_a5a5 4 1730 test_gr_a5a5 5 1731 test_gr_a5a5 6 1732 test_gr_a5a5 7 1733 1734mov_l_abs32_to_reg32: 1735 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1736 set_ccr_zero 1737 1738 ;; mov.l @aa:32, erd 1739 mov.l @long_src:32, er0 ; 32-bit address-direct operand 1740;;; .word 0x0100 1741;;; .word 0x6b20 1742;;; .long @long_src 1743 1744 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1745 test_neg_clear 1746 test_zero_clear 1747 test_ovf_clear 1748 test_carry_clear 1749 1750 test_h_gr32 0x77777777 er0 1751 1752 test_gr_a5a5 1 ; Make sure other general regs not disturbed 1753 test_gr_a5a5 2 1754 test_gr_a5a5 3 1755 test_gr_a5a5 4 1756 test_gr_a5a5 5 1757 test_gr_a5a5 6 1758 test_gr_a5a5 7 1759 1760 1761.if (sim_cpu == h8sx) 1762 1763 ;; 1764 ;; Move long from memory to memory 1765 ;; 1766 1767mov_l_indirect_to_indirect: ; reg indirect, memory to memory 1768 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1769 set_ccr_zero 1770 1771 ;; mov.l @ers, @erd 1772 1773 mov.l #long_src, er1 1774 mov.l #long_dst, er0 1775 mov.l @er1, @er0 1776;;; .word 0x0108 1777;;; .word 0x0100 1778 1779 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1780 test_neg_clear 1781 test_zero_clear 1782 test_ovf_clear 1783 test_carry_clear 1784 1785 ;; Verify the affected registers. 1786 1787 test_h_gr32 long_dst er0 1788 test_h_gr32 long_src er1 1789 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1790 test_gr_a5a5 3 1791 test_gr_a5a5 4 1792 test_gr_a5a5 5 1793 test_gr_a5a5 6 1794 test_gr_a5a5 7 1795 1796 ;; Now check the result of the move to memory. 1797 cmp.l @long_src, @long_dst 1798 beq .Lnext56 1799 fail 1800.Lnext56: 1801 ;; Now clear the destination location, and verify that. 1802 mov.l #0, @long_dst 1803 cmp.l @long_src, @long_dst 1804 bne .Lnext57 1805 fail 1806.Lnext57: ; OK, pass on. 1807 1808mov_l_postinc_to_postinc: ; reg post-increment, memory to memory 1809 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1810 set_ccr_zero 1811 1812 ;; mov.l @ers+, @erd+ 1813 1814 mov.l #long_src, er1 1815 mov.l #long_dst, er0 1816 mov.l @er1+, @er0+ 1817;;; .word 0x0108 1818;;; .word 0x8180 1819 1820 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1821 test_neg_clear 1822 test_zero_clear 1823 test_ovf_clear 1824 test_carry_clear 1825 1826 ;; Verify the affected registers. 1827 1828 test_h_gr32 long_dst+4 er0 1829 test_h_gr32 long_src+4 er1 1830 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1831 test_gr_a5a5 3 1832 test_gr_a5a5 4 1833 test_gr_a5a5 5 1834 test_gr_a5a5 6 1835 test_gr_a5a5 7 1836 1837 ;; Now check the result of the move to memory. 1838 cmp.l @long_src, @long_dst 1839 beq .Lnext65 1840 fail 1841.Lnext65: 1842 ;; Now clear the destination location, and verify that. 1843 mov.l #0, @long_dst 1844 cmp.l @long_src, @long_dst 1845 bne .Lnext66 1846 fail 1847.Lnext66: ; OK, pass on. 1848 ;; special case same register 1849 mov.l #long_src, er0 1850 mov.l @er0+, @er0+ ; copying long_src to long_dst 1851 test_h_gr32 long_src+8 er0 1852 cmp.b @long_src, @long_dst 1853 beq .Lnext67 1854 fail 1855.Lnext67: 1856 ;; Now clear the destination location, and verify that. 1857 mov.l #0, @long_dst 1858 cmp.l @long_src, @long_dst 1859 bne .Lnext68 1860 fail 1861.Lnext68: 1862 1863mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory 1864 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1865 set_ccr_zero 1866 1867 ;; mov.l @ers-, @erd- 1868 1869 mov.l #long_src, er1 1870 mov.l #long_dst, er0 1871 mov.l @er1-, @er0- 1872;;; .word 0x0108 1873;;; .word 0xa1a0 1874 1875 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1876 test_neg_clear 1877 test_zero_clear 1878 test_ovf_clear 1879 test_carry_clear 1880 1881 ;; Verify the affected registers. 1882 1883 test_h_gr32 long_dst-4 er0 1884 test_h_gr32 long_src-4 er1 1885 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1886 test_gr_a5a5 3 1887 test_gr_a5a5 4 1888 test_gr_a5a5 5 1889 test_gr_a5a5 6 1890 test_gr_a5a5 7 1891 1892 ;; Now check the result of the move to memory. 1893 cmp.l @long_src, @long_dst 1894 beq .Lnext75 1895 fail 1896.Lnext75: 1897 ;; Now clear the destination location, and verify that. 1898 mov.l #0, @long_dst 1899 cmp.l @long_src, @long_dst 1900 bne .Lnext76 1901 fail 1902.Lnext76: ; OK, pass on. 1903 ;; special case same register 1904 mov.l #long_src, er0 1905 mov.l @er0-, @er0- ; copying long_src to long_dst_dec 1906 test_h_gr32 long_src-8 er0 1907 cmp.l @long_src, @long_dst_dec 1908 beq .Lnext77 1909 fail 1910.Lnext77: 1911 ;; Now clear the destination location, and verify that. 1912 mov.l #0, @long_dst_dec 1913 cmp.l @long_src, @long_dst_dec 1914 bne .Lnext78 1915 fail 1916.Lnext78: 1917 1918mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory 1919 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1920 set_ccr_zero 1921 1922 ;; mov.l @+ers, @+erd 1923 1924 mov.l #long_src-4, er1 1925 mov.l #long_dst-4, er0 1926 mov.l @+er1, @+er0 1927;;; .word 0x0108 1928;;; .word 0x9190 1929 1930 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1931 test_neg_clear 1932 test_zero_clear 1933 test_ovf_clear 1934 test_carry_clear 1935 1936 ;; Verify the affected registers. 1937 1938 test_h_gr32 long_dst er0 1939 test_h_gr32 long_src er1 1940 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1941 test_gr_a5a5 3 1942 test_gr_a5a5 4 1943 test_gr_a5a5 5 1944 test_gr_a5a5 6 1945 test_gr_a5a5 7 1946 1947 ;; Now check the result of the move to memory. 1948 cmp.l @long_src, @long_dst 1949 beq .Lnext85 1950 fail 1951.Lnext85: 1952 ;; Now clear the destination location, and verify that. 1953 mov.l #0, @long_dst 1954 cmp.l @long_src, @long_dst 1955 bne .Lnext86 1956 fail 1957.Lnext86: ; OK, pass on. 1958 ;; special case same register 1959 mov.l #long_src-4, er0 1960 mov.l @+er0, @+er0 ; copying long_src to long_dst 1961 test_h_gr32 long_src+4 er0 1962 cmp.b @long_src, @long_dst 1963 beq .Lnext87 1964 fail 1965.Lnext87: 1966 ;; Now clear the destination location, and verify that. 1967 mov.b #0, @long_dst 1968 cmp.b @long_src, @long_dst 1969 bne .Lnext88 1970 fail 1971.Lnext88: 1972 1973mov_l_predec_to_predec: ; reg pre-decrement, memory to memory 1974 set_grs_a5a5 ; Fill all general regs with a fixed pattern 1975 set_ccr_zero 1976 1977 ;; mov.l @-ers, @-erd 1978 1979 mov.l #long_src+4, er1 1980 mov.l #long_dst+4, er0 1981 mov.l @-er1, @-er0 1982;;; .word 0x0108 1983;;; .word 0xb1b0 1984 1985 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 1986 test_neg_clear 1987 test_zero_clear 1988 test_ovf_clear 1989 test_carry_clear 1990 1991 ;; Verify the affected registers. 1992 1993 test_h_gr32 long_dst er0 1994 test_h_gr32 long_src er1 1995 test_gr_a5a5 2 ; Make sure other general regs not disturbed 1996 test_gr_a5a5 3 1997 test_gr_a5a5 4 1998 test_gr_a5a5 5 1999 test_gr_a5a5 6 2000 test_gr_a5a5 7 2001 2002 ;; Now check the result of the move to memory. 2003 cmp.l @long_src, @long_dst 2004 beq .Lnext95 2005 fail 2006.Lnext95: 2007 ;; Now clear the destination location, and verify that. 2008 mov.l #0, @long_dst 2009 cmp.l @long_src, @long_dst 2010 bne .Lnext96 2011 fail 2012.Lnext96: ; OK, pass on. 2013 ;; special case same register 2014 mov.l #long_src+4, er0 2015 mov.l @-er0, @-er0 ; copying long_src to long_dst_dec 2016 test_h_gr32 long_src-4 er0 2017 cmp.l @long_src, @long_dst_dec 2018 beq .Lnext97 2019 fail 2020.Lnext97: 2021 ;; Now clear the destination location, and verify that. 2022 mov.l #0, @long_dst_dec 2023 cmp.l @long_src, @long_dst_dec 2024 bne .Lnext98 2025 fail 2026.Lnext98: 2027 2028mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory 2029 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2030 set_ccr_zero 2031 2032 ;; mov.l @(dd:2, ers), @(dd:2, erd) 2033 2034 mov.l #long_src-4, er1 2035 mov.l #long_dst-8, er0 2036 mov.l @(4:2, er1), @(8:2, er0) 2037;;; .word 0x0108 2038;;; .word 0x1120 2039 2040 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2041 test_neg_clear 2042 test_zero_clear 2043 test_ovf_clear 2044 test_carry_clear 2045 2046 ;; Verify the affected registers. 2047 2048 test_h_gr32 long_dst-8 er0 2049 test_h_gr32 long_src-4 er1 2050 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2051 test_gr_a5a5 3 2052 test_gr_a5a5 4 2053 test_gr_a5a5 5 2054 test_gr_a5a5 6 2055 test_gr_a5a5 7 2056 2057 ;; Now check the result of the move to memory. 2058 cmp.l @long_src, @long_dst 2059 beq .Lnext105 2060 fail 2061.Lnext105: 2062 ;; Now clear the destination location, and verify that. 2063 mov.l #0, @long_dst 2064 cmp.l @long_src, @long_dst 2065 bne .Lnext106 2066 fail 2067.Lnext106: ; OK, pass on. 2068 2069mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory 2070 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2071 set_ccr_zero 2072 2073 ;; mov.l @(dd:16, ers), @(dd:16, erd) 2074 2075 mov.l #long_src-1, er1 2076 mov.l #long_dst-2, er0 2077 mov.l @(1:16, er1), @(2:16, er0) 2078;;; .word 0x0108 2079;;; .word 0xc1c0 2080;;; .word 0x0001 2081;;; .word 0x0002 2082 2083 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2084 test_neg_clear 2085 test_zero_clear 2086 test_ovf_clear 2087 test_carry_clear 2088 2089 ;; Verify the affected registers. 2090 2091 test_h_gr32 long_dst-2 er0 2092 test_h_gr32 long_src-1 er1 2093 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2094 test_gr_a5a5 3 2095 test_gr_a5a5 4 2096 test_gr_a5a5 5 2097 test_gr_a5a5 6 2098 test_gr_a5a5 7 2099 2100 ;; Now check the result of the move to memory. 2101 cmp.l @long_src, @long_dst 2102 beq .Lnext115 2103 fail 2104.Lnext115: 2105 ;; Now clear the destination location, and verify that. 2106 mov.l #0, @long_dst 2107 cmp.l @long_src, @long_dst 2108 bne .Lnext116 2109 fail 2110.Lnext116: ; OK, pass on. 2111 2112mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory 2113 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2114 set_ccr_zero 2115 2116 ;; mov.l @(dd:32, ers), @(dd:32, erd) 2117 2118 mov.l #long_src-1, er1 2119 mov.l #long_dst-2, er0 2120 mov.l @(1:32, er1), @(2:32, er0) 2121;;; .word 0x0108 2122;;; .word 0xc9c8 2123;;; .long 1 2124;;; .long 2 2125 2126 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2127 test_neg_clear 2128 test_zero_clear 2129 test_ovf_clear 2130 test_carry_clear 2131 2132 ;; Verify the affected registers. 2133 2134 test_h_gr32 long_dst-2 er0 2135 test_h_gr32 long_src-1 er1 2136 test_gr_a5a5 2 ; Make sure other general regs not disturbed 2137 test_gr_a5a5 3 2138 test_gr_a5a5 4 2139 test_gr_a5a5 5 2140 test_gr_a5a5 6 2141 test_gr_a5a5 7 2142 2143 ;; Now check the result of the move to memory. 2144 cmp.l @long_src, @long_dst 2145 beq .Lnext125 2146 fail 2147.Lnext125: 2148 ;; Now clear the destination location, and verify that. 2149 mov.l #0, @long_dst 2150 cmp.l @long_src, @long_dst 2151 bne .Lnext126 2152 fail 2153.Lnext126: ; OK, pass on. 2154 2155mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory 2156 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2157 set_ccr_zero 2158 2159 ;; mov.l @aa:16, @aa:16 2160 2161 mov.l @long_src:16, @long_dst:16 2162;;; .word 0x0108 2163;;; .word 0x4040 2164;;; .word @long_src 2165;;; .word @long_dst 2166 2167 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2168 test_neg_clear 2169 test_zero_clear 2170 test_ovf_clear 2171 test_carry_clear 2172 2173 2174 test_gr_a5a5 0 ; Make sure *NO* general registers are changed 2175 test_gr_a5a5 1 2176 test_gr_a5a5 2 2177 test_gr_a5a5 3 2178 test_gr_a5a5 4 2179 test_gr_a5a5 5 2180 test_gr_a5a5 6 2181 test_gr_a5a5 7 2182 2183 ;; Now check the result of the move to memory. 2184 cmp.l @long_src, @long_dst 2185 beq .Lnext135 2186 fail 2187.Lnext135: 2188 ;; Now clear the destination location, and verify that. 2189 mov.l #0, @long_dst 2190 cmp.l @long_src, @long_dst 2191 bne .Lnext136 2192 fail 2193.Lnext136: ; OK, pass on. 2194 2195mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory 2196 set_grs_a5a5 ; Fill all general regs with a fixed pattern 2197 set_ccr_zero 2198 2199 ;; mov.l @aa:32, @aa:32 2200 2201 mov.l @long_src:32, @long_dst:32 2202;;; .word 0x0108 2203;;; .word 0x4848 2204;;; .long @long_src 2205;;; .long @long_dst 2206 2207 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 2208 test_neg_clear 2209 test_zero_clear 2210 test_ovf_clear 2211 test_carry_clear 2212 2213 test_gr_a5a5 0 ; Make sure *NO* general registers are changed 2214 test_gr_a5a5 1 2215 test_gr_a5a5 2 2216 test_gr_a5a5 3 2217 test_gr_a5a5 4 2218 test_gr_a5a5 5 2219 test_gr_a5a5 6 2220 test_gr_a5a5 7 2221 2222 ;; Now check the result of the move to memory. 2223 cmp.l @long_src, @long_dst 2224 beq .Lnext145 2225 fail 2226.Lnext145: 2227 ;; Now clear the destination location, and verify that. 2228 mov.l #0, @long_dst 2229 cmp.l @long_src, @long_dst 2230 bne .Lnext146 2231 fail 2232.Lnext146: ; OK, pass on. 2233 2234 2235.endif 2236 2237 pass 2238 2239 exit 0 2240