1//Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp 2// Spec Reference: dsp32mac dr_a1 iu (unsigned integer) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A1 , and stored to a reg half 14imm32 r0, 0x93545abd; 15imm32 r1, 0x7890afc7; 16imm32 r2, 0x52248679; 17imm32 r3, 0xd5069007; 18imm32 r4, 0xef5c4569; 19imm32 r5, 0xcd35500b; 20imm32 r6, 0xe00c500d; 21imm32 r7, 0xf78e950f; 22R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU); 23R1 = A1.w; 24R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU); 25R3 = A1.w; 26R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU); 27R5 = A1.w; 28R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU); 29R7 = A1.w; 30CHECKREG r0, 0xFFFF5ABD; 31CHECKREG r1, 0x3E4DBBEB; 32CHECKREG r2, 0xFFFF8679; 33CHECKREG r3, 0xAE338FC1; 34CHECKREG r4, 0xFFFF4569; 35CHECKREG r5, 0xF90A98B5; 36CHECKREG r6, 0xFFFF500D; 37CHECKREG r7, 0x2062BE0D; 38 39// The result accumulated in A1, and stored to a reg half (MNOP) 40imm32 r0, 0xd3548abd; 41imm32 r1, 0x9dbcfec7; 42imm32 r2, 0xa9d45679; 43imm32 r3, 0xb09d9007; 44imm32 r4, 0xcfb9d569; 45imm32 r5, 0xd2359d0b; 46imm32 r6, 0xe00ca90d; 47imm32 r7, 0x678e709f; 48R0.H = ( A1 += R1.L * R0.L ) (IU); 49R1 = A1.w; 50R2.H = ( A1 -= R2.L * R3.H ) (IU); 51R3 = A1.w; 52R4.H = ( A1 = R4.H * R5.L ) (IU); 53R5 = A1.w; 54R6.H = ( A1 -= R6.H * R7.H ) (IU); 55R7 = A1.w; 56CHECKREG r0, 0xFFFF8ABD; 57CHECKREG r1, 0xAA761CF8; 58CHECKREG r2, 0xFFFF5679; 59CHECKREG r3, 0x6ECDE4C3; 60CHECKREG r4, 0xFFFFD569; 61CHECKREG r5, 0x7F6D61F3; 62CHECKREG r6, 0xFFFFA90D; 63CHECKREG r7, 0x24CC474B; 64 65// The result accumulated in A1 , and stored to a reg half (MNOP) 66imm32 r0, 0xa354babd; 67imm32 r1, 0x9abcdec7; 68imm32 r2, 0x77a4e679; 69imm32 r3, 0x805a7007; 70imm32 r4, 0x9fb3a569; 71imm32 r5, 0xa2352a0b; 72imm32 r6, 0xb00c10ad; 73imm32 r7, 0x9876a10a; 74 R0.H = A1 , A0 -= R1.L * R0.L (IU); 75R1 = A1.w; 76 R2.H = A1 , A0 += R2.H * R3.L (IU); 77R3 = A1.w; 78 R4.H = A1 , A0 = R4.H * R5.H (IU); 79R5 = A1.w; 80 R6.H = A1 , A0 -= R6.L * R7.H (IU); 81R7 = A1.w; 82CHECKREG r0, 0xFFFFBABD; 83CHECKREG r1, 0x24CC474B; 84CHECKREG r2, 0xFFFFE679; 85CHECKREG r3, 0x24CC474B; 86CHECKREG r4, 0xFFFFA569; 87CHECKREG r5, 0x24CC474B; 88CHECKREG r6, 0xFFFF10AD; 89CHECKREG r7, 0x24CC474B; 90 91// The result accumulated in A1 , and stored to a reg half 92imm32 r0, 0x33545abd; 93imm32 r1, 0x9dbcfec7; 94imm32 r2, 0x81245679; 95imm32 r3, 0x97060007; 96imm32 r4, 0xaf6c4569; 97imm32 r5, 0xd235900b; 98imm32 r6, 0xc00c400d; 99imm32 r7, 0x678ed30f; 100R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU); 101R1 = A1.w; 102R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU); 103R3 = A1.w; 104R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU); 105R5 = A1.w; 106R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU); 107R7 = A1.w; 108CHECKREG r0, 0x80005ABD; 109CHECKREG r1, 0xFF910EEB; 110CHECKREG r2, 0x80005679; 111CHECKREG r3, 0xCC8DA915; 112CHECKREG r4, 0x80004569; 113CHECKREG r5, 0xD2A949A4; 114CHECKREG r6, 0x8000400D; 115CHECKREG r7, 0xB8CAA44C; 116 117// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) 118imm32 r0, 0xe2005ABD; 119imm32 r1, 0x0e300000; 120imm32 r2, 0x56e49679; 121imm32 r3, 0x30Ae5000; 122imm32 r4, 0xa000e669; 123imm32 r5, 0x01000e70; 124imm32 r6, 0xdf4560eD; 125imm32 r7, 0x1234567e; 126R0.H = ( A1 -= R1.L * R0.L ) (M,IU); 127R1 = A1.w; 128R2.H = ( A1 += R2.L * R3.H ) (M,IU); 129R3 = A1.w; 130R4.H = ( A1 -= R4.H * R5.L ) (M,IU); 131R5 = A1.w; 132R6.H = ( A1 -= R6.H * R7.H ) (M,IU); 133R7 = A1.w; 134CHECKREG r0, 0x80005ABD; 135CHECKREG r1, 0xB8CAA44C; 136CHECKREG r2, 0x80009679; 137CHECKREG r3, 0xA4B99A8A; 138CHECKREG r4, 0x8000E669; 139CHECKREG r5, 0xAA239A8A; 140CHECKREG r6, 0x800060ED; 141CHECKREG r7, 0xAC776686; 142 143 144 145pass 146