1//Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp
2// Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round)
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10
11A1 = A0 = 0;
12
13// The result accumulated in A , and stored to a reg half
14imm32 r0, 0x83545abd;
15imm32 r1, 0x98bcfec7;
16imm32 r2, 0xc9948679;
17imm32 r3, 0xd0999007;
18imm32 r4, 0xefb99569;
19imm32 r5, 0xcd35900b;
20imm32 r6, 0xe00c89ad;
21imm32 r7, 0xf78e909a;
22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND);
23R1 = A0.w;
24A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND);
25R3 = A0.w;
26A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND);
27R5 = A0.w;
28A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND);
29R7 = A0.w;
30CHECKREG r0, 0x8354FE44;
31CHECKREG r1, 0xFF221DD6;
32CHECKREG r2, 0xC9945F37;
33CHECKREG r3, 0x2F9B8618;
34CHECKREG r4, 0xEFB96C22;
35CHECKREG r5, 0x361112B2;
36CHECKREG r6, 0xE00C7BBF;
37CHECKREG r7, 0x3DDFA49E;
38
39// The result accumulated in A , and stored to a reg half (MNOP)
40imm32 r0, 0xc8548abd;
41imm32 r1, 0x7bccfec7;
42imm32 r2, 0xa1bc5679;
43imm32 r3, 0xb00bc007;
44imm32 r4, 0xcfbcb8c9;
45imm32 r5, 0x5235cb8c;
46imm32 r6, 0xe50ca0b8;
47imm32 r7, 0x675e700b;
48R0.L = ( A0 = R1.L * R0.L ) (S2RND);
49R1 = A0.w;
50R2.L = ( A0 += R2.L * R3.H ) (S2RND);
51R3 = A0.w;
52R4.L = ( A0 -= R4.H * R5.L ) (S2RND);
53R5 = A0.w;
54R6.L = ( A0 = R6.H * R7.H ) (S2RND);
55R7 = A0.w;
56CHECKREG r0, 0xC854023D;
57CHECKREG r1, 0x011EBDD6;
58CHECKREG r2, 0xA1BC9635;
59CHECKREG r3, 0xCB1A8C3C;
60CHECKREG r4, 0xCFBC8000;
61CHECKREG r5, 0xB7532E9C;
62CHECKREG r6, 0xE50CD478;
63CHECKREG r7, 0xEA3BDCD0;
64
65// The result accumulated in A , and stored to a reg half (MNOP)
66imm32 r0, 0x7b54babd;
67imm32 r1, 0xbabcdec7;
68imm32 r2, 0xabbbe679;
69imm32 r3, 0x8abdb007;
70imm32 r4, 0x9fab7b69;
71imm32 r5, 0xa23a87bb;
72imm32 r6, 0xb00ca88b;
73imm32 r7, 0xc78eaab8;
74R0.L = ( A0 = R1.L * R0.L ) (S2RND);
75R1 = A0.w;
76R2.L = ( A0 -= R2.H * R3.L ) (S2RND);
77R3 = A0.w;
78R4.L = ( A0 = R4.H * R5.H ) (S2RND);
79R5 = A0.w;
80R6.L = ( A0 += R6.L * R7.H ) (S2RND);
81R7 = A0.w;
82CHECKREG r0, 0x7B5423F4;
83CHECKREG r1, 0x11FA1DD6;
84CHECKREG r2, 0xABBBBAA7;
85CHECKREG r3, 0xDD53999C;
86CHECKREG r4, 0x9FAB7FFF;
87CHECKREG r5, 0x4692C57C;
88CHECKREG r6, 0xB00C7FFF;
89CHECKREG r7, 0x6D23D9B0;
90
91// The result accumulated in A , and stored to a reg half
92imm32 r0, 0xfa545abd;
93imm32 r1, 0x5ffcfec7;
94imm32 r2, 0xc1ef5679;
95imm32 r3, 0x9c0ef007;
96imm32 r4, 0xafccec69;
97imm32 r5, 0xd23c9e1b;
98imm32 r6, 0xc00cc0e2;
99imm32 r7, 0x678edc0e;
100A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND);
101R3 = A0.w;
102A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND);
103R7 = A0.w;
104A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND);
105R5 = A0.w;
106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND);
107R1 = A0.w;
108CHECKREG r0, 0xFA54CF65;
109CHECKREG r1, 0xE7B2ACD4;
110CHECKREG r2, 0xC1EF7FFF;
111CHECKREG r3, 0x6C45F786;
112CHECKREG r4, 0xAFCCCEDE;
113CHECKREG r5, 0xE76F2094;
114CHECKREG r6, 0xC00C0838;
115CHECKREG r7, 0x041C3834;
116
117
118
119pass
120