1//Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp 2// Spec Reference: dsp32mac dr a0 i (signed int) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A , and stored to a reg half 14imm32 r0, 0xa3545abd; 15imm32 r1, 0x9dbcfec7; 16imm32 r2, 0xc9248679; 17imm32 r3, 0xd0969007; 18imm32 r4, 0xefb94569; 19imm32 r5, 0xcd35900b; 20imm32 r6, 0xe00c890d; 21imm32 r7, 0xf78e909f; 22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS); 23R1 = A0.w; 24A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS); 25R3 = A0.w; 26A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS); 27R5 = A0.w; 28A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS); 29R7 = A0.w; 30CHECKREG r0, 0xA3548000; 31CHECKREG r1, 0xFF910EEB; 32CHECKREG r2, 0xC9247FFF; 33CHECKREG r3, 0x17FEBFFC; 34CHECKREG r4, 0xEFB97FFF; 35CHECKREG r5, 0x1B398649; 36CHECKREG r6, 0xE00C7FFF; 37CHECKREG r7, 0x174CF613; 38 39// The result accumulated in A , and stored to a reg half (MNOP) 40imm32 r0, 0x68548abd; 41imm32 r1, 0x7d8cfec7; 42imm32 r2, 0xa1285679; 43imm32 r3, 0xb0068007; 44imm32 r4, 0xcfbc4869; 45imm32 r5, 0xd235c08b; 46imm32 r6, 0xe00ca008; 47imm32 r7, 0x678e700f; 48R0.L = ( A0 -= R1.L * R0.L ) (IS); 49R1 = A0.w; 50R2.L = ( A0 += R2.L * R3.H ) (IS); 51R3 = A0.w; 52R4.L = ( A0 = R4.H * R5.L ) (IS); 53R5 = A0.w; 54R6.L = ( A0 -= R6.H * R7.H ) (IS); 55R7 = A0.w; 56CHECKREG r0, 0x68547FFF; 57CHECKREG r1, 0x16BD9728; 58CHECKREG r2, 0xA1288000; 59CHECKREG r3, 0xFBB9CDFE; 60CHECKREG r4, 0xCFBC7FFF; 61CHECKREG r5, 0x0BF6CB14; 62CHECKREG r6, 0xE00C7FFF; 63CHECKREG r7, 0x18E3B06C; 64 65// The result accumulated in A , and stored to a reg half (MNOP) 66imm32 r0, 0x7b54babd; 67imm32 r1, 0xb7bcdec7; 68imm32 r2, 0x7b7be679; 69imm32 r3, 0x80b77007; 70imm32 r4, 0x9fbb7569; 71imm32 r5, 0xa235b70b; 72imm32 r6, 0xb00c3b7d; 73imm32 r7, 0xc78ea0b7; 74R0.L = ( A0 = R1.L * R0.L ) (IS); 75R1 = A0.w; 76R2.L = ( A0 -= R2.H * R3.L ) (IS); 77R3 = A0.w; 78R4.L = ( A0 = R4.H * R5.H ) (IS); 79R5 = A0.w; 80R6.L = ( A0 += R6.L * R7.H ) (IS); 81R7 = A0.w; 82CHECKREG r0, 0x7B547FFF; 83CHECKREG r1, 0x08FD0EEB; 84CHECKREG r2, 0x7B7B8000; 85CHECKREG r3, 0xD2F3DE8E; 86CHECKREG r4, 0x9FBB7FFF; 87CHECKREG r5, 0x234567B7; 88CHECKREG r6, 0xB00C7FFF; 89CHECKREG r7, 0x1627920D; 90 91// The result accumulated in A , and stored to a reg half 92imm32 r0, 0xe3545abd; 93imm32 r1, 0x5ebcfec7; 94imm32 r2, 0x71e45679; 95imm32 r3, 0x900e0007; 96imm32 r4, 0xafbce569; 97imm32 r5, 0xd2359e0b; 98imm32 r6, 0xc00ca0ed; 99imm32 r7, 0x678ed00e; 100A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS); 101R3 = A0.w; 102A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS); 103R7 = A0.w; 104A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS); 105R5 = A0.w; 106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS); 107R1 = A0.w; 108CHECKREG r0, 0xE3547FFF; 109CHECKREG r1, 0x2E5AD9ED; 110CHECKREG r2, 0x71E47FFF; 111CHECKREG r3, 0x15B8A0F8; 112CHECKREG r4, 0xAFBC7FFF; 113CHECKREG r5, 0x0E5B99EC; 114CHECKREG r6, 0xC00C7FFF; 115CHECKREG r7, 0x3FFFCC18; 116 117 118 119pass 120