1/* Moxie Simulator definition. 2 Copyright (C) 2009-2020 Free Software Foundation, Inc. 3 4This file is part of GDB, the GNU debugger. 5 6This program is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 3 of the License, or 9(at your option) any later version. 10 11This program is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19#ifndef SIM_MAIN_H 20#define SIM_MAIN_H 21 22#include "sim-basics.h" 23#include "sim-base.h" 24 25typedef struct 26{ 27 int regs[20]; 28} regstacktype; 29 30typedef union 31{ 32 33 struct 34 { 35 int regs[16]; 36 int pc; 37 38 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1 39 which are located in fregs, i.e. strictly speaking, these are 40 out-of-bounds accesses of sregs.i . This wart of the code could be 41 fixed by making fregs part of sregs, and including pc too - to avoid 42 alignment repercussions - but this would cause very onerous union / 43 structure nesting, which would only be managable with anonymous 44 unions and structs. */ 45 union 46 { 47 struct 48 { 49 int mach; 50 int macl; 51 int pr; 52 int dummy3, dummy4; 53 int fpul; /* A1 for sh-dsp - but only for movs etc. */ 54 int fpscr; /* dsr for sh-dsp */ 55 } named; 56 int i[7]; 57 } sregs; 58 59 /* sh3e / sh-dsp */ 60 union fregs_u 61 { 62 float f[16]; 63 double d[8]; 64 int i[16]; 65 } 66 fregs[2]; 67 68 /* Control registers; on the SH4, ldc / stc is privileged, except when 69 accessing gbr. */ 70 union 71 { 72 struct 73 { 74 int sr; 75 int gbr; 76 int vbr; 77 int ssr; 78 int spc; 79 int mod; 80 /* sh-dsp */ 81 int rs; 82 int re; 83 /* sh3 */ 84 int bank[8]; 85 int dbr; /* debug base register */ 86 int sgr; /* saved gr15 */ 87 int ldst; /* load/store flag (boolean) */ 88 int tbr; 89 int ibcr; /* sh2a bank control register */ 90 int ibnr; /* sh2a bank number register */ 91 } named; 92 int i[16]; 93 } cregs; 94 95 unsigned char *insn_end; 96 97 int ticks; 98 int stalls; 99 int memstalls; 100 int cycles; 101 int insts; 102 103 int prevlock; 104 int thislock; 105 int exception; 106 107 int end_of_registers; 108 109 int msize; 110#define PROFILE_FREQ 1 111#define PROFILE_SHIFT 2 112 int profile; 113 unsigned short *profile_hist; 114 unsigned char *memory; 115 int xyram_select, xram_start, yram_start; 116 unsigned char *xmem; 117 unsigned char *ymem; 118 unsigned char *xmem_offset; 119 unsigned char *ymem_offset; 120 unsigned long bfd_mach; 121 regstacktype *regstack; 122 } asregs; 123 int asints[40]; 124} saved_state_type; 125 126/* TODO: Move into sim_cpu. */ 127extern saved_state_type saved_state; 128 129struct _sim_cpu { 130 131 sim_cpu_base base; 132}; 133 134struct sim_state { 135 136 sim_cpu *cpu[MAX_NR_PROCESSORS]; 137 138 sim_state_base base; 139}; 140 141#endif 142