1#include <stdio.h> 2#include <ctype.h> 3#include "ansidecl.h" 4#include "gdb/callback.h" 5#include "opcode/mn10300.h" 6#include <limits.h> 7#include "gdb/remote-sim.h" 8#include "bfd.h" 9#include "sim-fpu.h" 10 11extern SIM_DESC simulator; 12 13typedef unsigned8 uint8; 14typedef signed8 int8; 15typedef unsigned16 uint16; 16typedef signed16 int16; 17typedef unsigned32 uint32; 18typedef signed32 int32; 19 20typedef struct 21{ 22 uint32 low, high; 23} dword; 24typedef uint32 reg_t; 25 26struct simops 27{ 28 long opcode; 29 long mask; 30 void (*func)(); 31 int length; 32 int format; 33 int numops; 34 int operands[16]; 35}; 36 37/* The current state of the processor; registers, memory, etc. */ 38 39struct _state 40{ 41 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw, 42 lir, lar, mdrq, plus some room for processor 43 specific regs. */ 44 union 45 { 46 reg_t fs[32]; /* FS0-31 */ 47 dword fd[16]; /* FD0,2,...,30 */ 48 } fpregs; 49 50 /* All internal state modified by signal_exception() that may need to be 51 rolled back for passing moment-of-exception image back to gdb. */ 52 reg_t exc_trigger_regs[32]; 53 reg_t exc_suspend_regs[32]; 54 int exc_suspended; 55 56#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA) 57#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC) 58#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC) 59}; 60 61extern struct _state State; 62 63#define PC (State.regs[REG_PC]) 64#define SP (State.regs[REG_SP]) 65 66#define PSW (State.regs[11]) 67#define PSW_Z 0x1 68#define PSW_N 0x2 69#define PSW_C 0x4 70#define PSW_V 0x8 71#define PSW_IE LSBIT (11) 72#define PSW_LM LSMASK (10, 8) 73 74#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8) 75#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8) 76 77#define REG_D0 0 78#define REG_A0 4 79#define REG_SP 8 80#define REG_PC 9 81#define REG_MDR 10 82#define REG_PSW 11 83#define REG_LIR 12 84#define REG_LAR 13 85#define REG_MDRQ 14 86#define REG_E0 15 87#define REG_SSP 23 88#define REG_MSP 24 89#define REG_USP 25 90#define REG_MCRH 26 91#define REG_MCRL 27 92#define REG_MCVF 28 93 94#define REG_FPCR 29 95 96#define FPCR (State.regs[REG_FPCR]) 97 98#define FCC_MASK LSMASK (21, 18) 99#define RM_MASK LSMASK (17, 16) /* Must always be zero. */ 100#define EC_MASK LSMASK (14, 10) 101#define EE_MASK LSMASK ( 9, 5) 102#define EF_MASK LSMASK ( 4, 0) 103#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK) 104 105#define FCC_L LSBIT (21) 106#define FCC_G LSBIT (20) 107#define FCC_E LSBIT (19) 108#define FCC_U LSBIT (18) 109 110#define EC_V LSBIT (14) 111#define EC_Z LSBIT (13) 112#define EC_O LSBIT (12) 113#define EC_U LSBIT (11) 114#define EC_I LSBIT (10) 115 116#define EE_V LSBIT (9) 117#define EE_Z LSBIT (8) 118#define EE_O LSBIT (7) 119#define EE_U LSBIT (6) 120#define EE_I LSBIT (5) 121 122#define EF_V LSBIT (4) 123#define EF_Z LSBIT (3) 124#define EF_O LSBIT (2) 125#define EF_U LSBIT (1) 126#define EF_I LSBIT (0) 127 128#define PSW_FE LSBIT(20) 129#define FPU_DISABLED !(PSW & PSW_FE) 130 131#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))] 132#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))] 133#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))] 134 135#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS)) 136#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low)) 137#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F)) 138#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F)) 139 140#define FETCH32(a,b,c,d) \ 141 ((a)+((b)<<8)+((c)<<16)+((d)<<24)) 142 143#define FETCH24(a,b,c) \ 144 ((a)+((b)<<8)+((c)<<16)) 145 146#define FETCH16(a,b) ((a)+((b)<<8)) 147 148#define load_byte(ADDR) \ 149sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 150 151#define load_half(ADDR) \ 152sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 153 154#define load_word(ADDR) \ 155sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) 156 157#define load_dword(ADDR) \ 158u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \ 159 PC, read_map, (ADDR))) 160 161static INLINE dword 162u642dw (unsigned64 dw) 163{ 164 dword r; 165 166 r.low = (unsigned32)dw; 167 r.high = (unsigned32)(dw >> 32); 168 return r; 169} 170 171#define store_byte(ADDR, DATA) \ 172sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \ 173 PC, write_map, (ADDR), (DATA)) 174 175 176#define store_half(ADDR, DATA) \ 177sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \ 178 PC, write_map, (ADDR), (DATA)) 179 180 181#define store_word(ADDR, DATA) \ 182sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \ 183 PC, write_map, (ADDR), (DATA)) 184#define store_dword(ADDR, DATA) \ 185sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \ 186 PC, write_map, (ADDR), dw2u64 (DATA)) 187 188static INLINE unsigned64 189dw2u64 (dword data) 190{ 191 return data.low | (((unsigned64)data.high) << 32); 192} 193 194/* Function declarations. */ 195 196INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg); 197INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg); 198INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd); 199INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg); 200INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg); 201INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd); 202INLINE_SIM_MAIN (void) do_syscall (void); 203void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig); 204 205void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 206void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 207void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 208 209void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word); 210void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word); 211void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word); 212 213extern const struct fp_prec_t 214{ 215 void (* reg2val) (const void *, sim_fpu *); 216 int (* round) (sim_fpu *); 217 void (* val2reg) (const sim_fpu *, void *); 218} fp_single_prec, fp_double_prec; 219 220#define FP_SINGLE (&fp_single_prec) 221#define FP_DOUBLE (&fp_double_prec) 222 223void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *); 224void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *); 225void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *); 226void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 227void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 228void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 229void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *); 230void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 231void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 232void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 233void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *); 234