1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* Disassembler interface for targets using CGEN. -*- C -*- 3 CGEN: Cpu tools GENerator 4 5 THIS FILE IS MACHINE GENERATED WITH CGEN. 6 - the resultant file is machine generated, cgen-dis.in isn't 7 8 Copyright (C) 1996-2020 Free Software Foundation, Inc. 9 10 This file is part of libopcodes. 11 12 This library is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 3, or (at your option) 15 any later version. 16 17 It is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software Foundation, Inc., 24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 25 26/* ??? Eventually more and more of this stuff can go to cpu-independent files. 27 Keep that in mind. */ 28 29#include "sysdep.h" 30#include <stdio.h> 31#include "ansidecl.h" 32#include "disassemble.h" 33#include "bfd.h" 34#include "symcat.h" 35#include "libiberty.h" 36#include "fr30-desc.h" 37#include "fr30-opc.h" 38#include "opintl.h" 39 40/* Default text to print if an instruction isn't recognized. */ 41#define UNKNOWN_INSN_MSG _("*unknown*") 42 43static void print_normal 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 45static void print_address 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 47static void print_keyword 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 49static void print_insn_normal 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 51static int print_insn 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 53static int default_print_insn 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 55static int read_insn 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 57 unsigned long *); 58 59/* -- disassembler routines inserted here. */ 60 61/* -- dis.c */ 62static void 63print_register_list (void * dis_info, 64 long value, 65 long offset, 66 int load_store) /* 0 == load, 1 == store. */ 67{ 68 disassemble_info *info = dis_info; 69 int mask; 70 int reg_index = 0; 71 char * comma = ""; 72 73 if (load_store) 74 mask = 0x80; 75 else 76 mask = 1; 77 78 if (value & mask) 79 { 80 (*info->fprintf_func) (info->stream, "r%li", reg_index + offset); 81 comma = ","; 82 } 83 84 for (reg_index = 1; reg_index <= 7; ++reg_index) 85 { 86 if (load_store) 87 mask >>= 1; 88 else 89 mask <<= 1; 90 91 if (value & mask) 92 { 93 (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset); 94 comma = ","; 95 } 96 } 97} 98 99static void 100print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 101 void * dis_info, 102 long value, 103 unsigned int attrs ATTRIBUTE_UNUSED, 104 bfd_vma pc ATTRIBUTE_UNUSED, 105 int length ATTRIBUTE_UNUSED) 106{ 107 print_register_list (dis_info, value, 8, 0 /* Load. */); 108} 109 110static void 111print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 112 void * dis_info, 113 long value, 114 unsigned int attrs ATTRIBUTE_UNUSED, 115 bfd_vma pc ATTRIBUTE_UNUSED, 116 int length ATTRIBUTE_UNUSED) 117{ 118 print_register_list (dis_info, value, 0, 0 /* Load. */); 119} 120 121static void 122print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 123 void * dis_info, 124 long value, 125 unsigned int attrs ATTRIBUTE_UNUSED, 126 bfd_vma pc ATTRIBUTE_UNUSED, 127 int length ATTRIBUTE_UNUSED) 128{ 129 print_register_list (dis_info, value, 8, 1 /* Store. */); 130} 131 132static void 133print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 134 void * dis_info, 135 long value, 136 unsigned int attrs ATTRIBUTE_UNUSED, 137 bfd_vma pc ATTRIBUTE_UNUSED, 138 int length ATTRIBUTE_UNUSED) 139{ 140 print_register_list (dis_info, value, 0, 1 /* Store. */); 141} 142 143static void 144print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 145 void * dis_info, 146 long value, 147 unsigned int attrs ATTRIBUTE_UNUSED, 148 bfd_vma pc ATTRIBUTE_UNUSED, 149 int length ATTRIBUTE_UNUSED) 150{ 151 disassemble_info *info = (disassemble_info *) dis_info; 152 153 (*info->fprintf_func) (info->stream, "%ld", value); 154} 155/* -- */ 156 157void fr30_cgen_print_operand 158 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 159 160/* Main entry point for printing operands. 161 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 162 of dis-asm.h on cgen.h. 163 164 This function is basically just a big switch statement. Earlier versions 165 used tables to look up the function to use, but 166 - if the table contains both assembler and disassembler functions then 167 the disassembler contains much of the assembler and vice-versa, 168 - there's a lot of inlining possibilities as things grow, 169 - using a switch statement avoids the function call overhead. 170 171 This function could be moved into `print_insn_normal', but keeping it 172 separate makes clear the interface between `print_insn_normal' and each of 173 the handlers. */ 174 175void 176fr30_cgen_print_operand (CGEN_CPU_DESC cd, 177 int opindex, 178 void * xinfo, 179 CGEN_FIELDS *fields, 180 void const *attrs ATTRIBUTE_UNUSED, 181 bfd_vma pc, 182 int length) 183{ 184 disassemble_info *info = (disassemble_info *) xinfo; 185 186 switch (opindex) 187 { 188 case FR30_OPERAND_CRI : 189 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0); 190 break; 191 case FR30_OPERAND_CRJ : 192 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0); 193 break; 194 case FR30_OPERAND_R13 : 195 print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0); 196 break; 197 case FR30_OPERAND_R14 : 198 print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0); 199 break; 200 case FR30_OPERAND_R15 : 201 print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0); 202 break; 203 case FR30_OPERAND_RI : 204 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0); 205 break; 206 case FR30_OPERAND_RIC : 207 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0); 208 break; 209 case FR30_OPERAND_RJ : 210 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0); 211 break; 212 case FR30_OPERAND_RJC : 213 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0); 214 break; 215 case FR30_OPERAND_RS1 : 216 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0); 217 break; 218 case FR30_OPERAND_RS2 : 219 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0); 220 break; 221 case FR30_OPERAND_CC : 222 print_normal (cd, info, fields->f_cc, 0, pc, length); 223 break; 224 case FR30_OPERAND_CCC : 225 print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 226 break; 227 case FR30_OPERAND_DIR10 : 228 print_normal (cd, info, fields->f_dir10, 0, pc, length); 229 break; 230 case FR30_OPERAND_DIR8 : 231 print_normal (cd, info, fields->f_dir8, 0, pc, length); 232 break; 233 case FR30_OPERAND_DIR9 : 234 print_normal (cd, info, fields->f_dir9, 0, pc, length); 235 break; 236 case FR30_OPERAND_DISP10 : 237 print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 238 break; 239 case FR30_OPERAND_DISP8 : 240 print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 241 break; 242 case FR30_OPERAND_DISP9 : 243 print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 244 break; 245 case FR30_OPERAND_I20 : 246 print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 247 break; 248 case FR30_OPERAND_I32 : 249 print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 250 break; 251 case FR30_OPERAND_I8 : 252 print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 253 break; 254 case FR30_OPERAND_LABEL12 : 255 print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 256 break; 257 case FR30_OPERAND_LABEL9 : 258 print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 259 break; 260 case FR30_OPERAND_M4 : 261 print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 262 break; 263 case FR30_OPERAND_PS : 264 print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0); 265 break; 266 case FR30_OPERAND_REGLIST_HI_LD : 267 print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length); 268 break; 269 case FR30_OPERAND_REGLIST_HI_ST : 270 print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length); 271 break; 272 case FR30_OPERAND_REGLIST_LOW_LD : 273 print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length); 274 break; 275 case FR30_OPERAND_REGLIST_LOW_ST : 276 print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length); 277 break; 278 case FR30_OPERAND_S10 : 279 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 280 break; 281 case FR30_OPERAND_U10 : 282 print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 283 break; 284 case FR30_OPERAND_U4 : 285 print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 286 break; 287 case FR30_OPERAND_U4C : 288 print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 289 break; 290 case FR30_OPERAND_U8 : 291 print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 292 break; 293 case FR30_OPERAND_UDISP6 : 294 print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); 295 break; 296 297 default : 298 /* xgettext:c-format */ 299 opcodes_error_handler 300 (_("internal error: unrecognized field %d while printing insn"), 301 opindex); 302 abort (); 303 } 304} 305 306cgen_print_fn * const fr30_cgen_print_handlers[] = 307{ 308 print_insn_normal, 309}; 310 311 312void 313fr30_cgen_init_dis (CGEN_CPU_DESC cd) 314{ 315 fr30_cgen_init_opcode_table (cd); 316 fr30_cgen_init_ibld_table (cd); 317 cd->print_handlers = & fr30_cgen_print_handlers[0]; 318 cd->print_operand = fr30_cgen_print_operand; 319} 320 321 322/* Default print handler. */ 323 324static void 325print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 326 void *dis_info, 327 long value, 328 unsigned int attrs, 329 bfd_vma pc ATTRIBUTE_UNUSED, 330 int length ATTRIBUTE_UNUSED) 331{ 332 disassemble_info *info = (disassemble_info *) dis_info; 333 334 /* Print the operand as directed by the attributes. */ 335 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 336 ; /* nothing to do */ 337 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 338 (*info->fprintf_func) (info->stream, "%ld", value); 339 else 340 (*info->fprintf_func) (info->stream, "0x%lx", value); 341} 342 343/* Default address handler. */ 344 345static void 346print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 347 void *dis_info, 348 bfd_vma value, 349 unsigned int attrs, 350 bfd_vma pc ATTRIBUTE_UNUSED, 351 int length ATTRIBUTE_UNUSED) 352{ 353 disassemble_info *info = (disassemble_info *) dis_info; 354 355 /* Print the operand as directed by the attributes. */ 356 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 357 ; /* Nothing to do. */ 358 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 359 (*info->print_address_func) (value, info); 360 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 361 (*info->print_address_func) (value, info); 362 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 363 (*info->fprintf_func) (info->stream, "%ld", (long) value); 364 else 365 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 366} 367 368/* Keyword print handler. */ 369 370static void 371print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 372 void *dis_info, 373 CGEN_KEYWORD *keyword_table, 374 long value, 375 unsigned int attrs ATTRIBUTE_UNUSED) 376{ 377 disassemble_info *info = (disassemble_info *) dis_info; 378 const CGEN_KEYWORD_ENTRY *ke; 379 380 ke = cgen_keyword_lookup_value (keyword_table, value); 381 if (ke != NULL) 382 (*info->fprintf_func) (info->stream, "%s", ke->name); 383 else 384 (*info->fprintf_func) (info->stream, "???"); 385} 386 387/* Default insn printer. 388 389 DIS_INFO is defined as `void *' so the disassembler needn't know anything 390 about disassemble_info. */ 391 392static void 393print_insn_normal (CGEN_CPU_DESC cd, 394 void *dis_info, 395 const CGEN_INSN *insn, 396 CGEN_FIELDS *fields, 397 bfd_vma pc, 398 int length) 399{ 400 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 401 disassemble_info *info = (disassemble_info *) dis_info; 402 const CGEN_SYNTAX_CHAR_TYPE *syn; 403 404 CGEN_INIT_PRINT (cd); 405 406 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 407 { 408 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 409 { 410 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 411 continue; 412 } 413 if (CGEN_SYNTAX_CHAR_P (*syn)) 414 { 415 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 416 continue; 417 } 418 419 /* We have an operand. */ 420 fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 421 fields, CGEN_INSN_ATTRS (insn), pc, length); 422 } 423} 424 425/* Subroutine of print_insn. Reads an insn into the given buffers and updates 426 the extract info. 427 Returns 0 if all is well, non-zero otherwise. */ 428 429static int 430read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 431 bfd_vma pc, 432 disassemble_info *info, 433 bfd_byte *buf, 434 int buflen, 435 CGEN_EXTRACT_INFO *ex_info, 436 unsigned long *insn_value) 437{ 438 int status = (*info->read_memory_func) (pc, buf, buflen, info); 439 440 if (status != 0) 441 { 442 (*info->memory_error_func) (status, pc, info); 443 return -1; 444 } 445 446 ex_info->dis_info = info; 447 ex_info->valid = (1 << buflen) - 1; 448 ex_info->insn_bytes = buf; 449 450 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 451 return 0; 452} 453 454/* Utility to print an insn. 455 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 456 The result is the size of the insn in bytes or zero for an unknown insn 457 or -1 if an error occurs fetching data (memory_error_func will have 458 been called). */ 459 460static int 461print_insn (CGEN_CPU_DESC cd, 462 bfd_vma pc, 463 disassemble_info *info, 464 bfd_byte *buf, 465 unsigned int buflen) 466{ 467 CGEN_INSN_INT insn_value; 468 const CGEN_INSN_LIST *insn_list; 469 CGEN_EXTRACT_INFO ex_info; 470 int basesize; 471 472 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 473 basesize = cd->base_insn_bitsize < buflen * 8 ? 474 cd->base_insn_bitsize : buflen * 8; 475 insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); 476 477 478 /* Fill in ex_info fields like read_insn would. Don't actually call 479 read_insn, since the incoming buffer is already read (and possibly 480 modified a la m32r). */ 481 ex_info.valid = (1 << buflen) - 1; 482 ex_info.dis_info = info; 483 ex_info.insn_bytes = buf; 484 485 /* The instructions are stored in hash lists. 486 Pick the first one and keep trying until we find the right one. */ 487 488 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 489 while (insn_list != NULL) 490 { 491 const CGEN_INSN *insn = insn_list->insn; 492 CGEN_FIELDS fields; 493 int length; 494 unsigned long insn_value_cropped; 495 496#ifdef CGEN_VALIDATE_INSN_SUPPORTED 497 /* Not needed as insn shouldn't be in hash lists if not supported. */ 498 /* Supported by this cpu? */ 499 if (! fr30_cgen_insn_supported (cd, insn)) 500 { 501 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 502 continue; 503 } 504#endif 505 506 /* Basic bit mask must be correct. */ 507 /* ??? May wish to allow target to defer this check until the extract 508 handler. */ 509 510 /* Base size may exceed this instruction's size. Extract the 511 relevant part from the buffer. */ 512 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 513 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 514 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 515 info->endian == BFD_ENDIAN_BIG); 516 else 517 insn_value_cropped = insn_value; 518 519 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 520 == CGEN_INSN_BASE_VALUE (insn)) 521 { 522 /* Printing is handled in two passes. The first pass parses the 523 machine insn and extracts the fields. The second pass prints 524 them. */ 525 526 /* Make sure the entire insn is loaded into insn_value, if it 527 can fit. */ 528 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 529 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 530 { 531 unsigned long full_insn_value; 532 int rc = read_insn (cd, pc, info, buf, 533 CGEN_INSN_BITSIZE (insn) / 8, 534 & ex_info, & full_insn_value); 535 if (rc != 0) 536 return rc; 537 length = CGEN_EXTRACT_FN (cd, insn) 538 (cd, insn, &ex_info, full_insn_value, &fields, pc); 539 } 540 else 541 length = CGEN_EXTRACT_FN (cd, insn) 542 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 543 544 /* Length < 0 -> error. */ 545 if (length < 0) 546 return length; 547 if (length > 0) 548 { 549 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 550 /* Length is in bits, result is in bytes. */ 551 return length / 8; 552 } 553 } 554 555 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 556 } 557 558 return 0; 559} 560 561/* Default value for CGEN_PRINT_INSN. 562 The result is the size of the insn in bytes or zero for an unknown insn 563 or -1 if an error occured fetching bytes. */ 564 565#ifndef CGEN_PRINT_INSN 566#define CGEN_PRINT_INSN default_print_insn 567#endif 568 569static int 570default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 571{ 572 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 573 int buflen; 574 int status; 575 576 /* Attempt to read the base part of the insn. */ 577 buflen = cd->base_insn_bitsize / 8; 578 status = (*info->read_memory_func) (pc, buf, buflen, info); 579 580 /* Try again with the minimum part, if min < base. */ 581 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 582 { 583 buflen = cd->min_insn_bitsize / 8; 584 status = (*info->read_memory_func) (pc, buf, buflen, info); 585 } 586 587 if (status != 0) 588 { 589 (*info->memory_error_func) (status, pc, info); 590 return -1; 591 } 592 593 return print_insn (cd, pc, info, buf, buflen); 594} 595 596/* Main entry point. 597 Print one instruction from PC on INFO->STREAM. 598 Return the size of the instruction (in bytes). */ 599 600typedef struct cpu_desc_list 601{ 602 struct cpu_desc_list *next; 603 CGEN_BITSET *isa; 604 int mach; 605 int endian; 606 int insn_endian; 607 CGEN_CPU_DESC cd; 608} cpu_desc_list; 609 610int 611print_insn_fr30 (bfd_vma pc, disassemble_info *info) 612{ 613 static cpu_desc_list *cd_list = 0; 614 cpu_desc_list *cl = 0; 615 static CGEN_CPU_DESC cd = 0; 616 static CGEN_BITSET *prev_isa; 617 static int prev_mach; 618 static int prev_endian; 619 static int prev_insn_endian; 620 int length; 621 CGEN_BITSET *isa; 622 int mach; 623 int endian = (info->endian == BFD_ENDIAN_BIG 624 ? CGEN_ENDIAN_BIG 625 : CGEN_ENDIAN_LITTLE); 626 int insn_endian = (info->endian_code == BFD_ENDIAN_BIG 627 ? CGEN_ENDIAN_BIG 628 : CGEN_ENDIAN_LITTLE); 629 enum bfd_architecture arch; 630 631 /* ??? gdb will set mach but leave the architecture as "unknown" */ 632#ifndef CGEN_BFD_ARCH 633#define CGEN_BFD_ARCH bfd_arch_fr30 634#endif 635 arch = info->arch; 636 if (arch == bfd_arch_unknown) 637 arch = CGEN_BFD_ARCH; 638 639 /* There's no standard way to compute the machine or isa number 640 so we leave it to the target. */ 641#ifdef CGEN_COMPUTE_MACH 642 mach = CGEN_COMPUTE_MACH (info); 643#else 644 mach = info->mach; 645#endif 646 647#ifdef CGEN_COMPUTE_ISA 648 { 649 static CGEN_BITSET *permanent_isa; 650 651 if (!permanent_isa) 652 permanent_isa = cgen_bitset_create (MAX_ISAS); 653 isa = permanent_isa; 654 cgen_bitset_clear (isa); 655 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 656 } 657#else 658 isa = info->private_data; 659#endif 660 661 /* If we've switched cpu's, try to find a handle we've used before */ 662 if (cd 663 && (cgen_bitset_compare (isa, prev_isa) != 0 664 || mach != prev_mach 665 || endian != prev_endian)) 666 { 667 cd = 0; 668 for (cl = cd_list; cl; cl = cl->next) 669 { 670 if (cgen_bitset_compare (cl->isa, isa) == 0 && 671 cl->mach == mach && 672 cl->endian == endian) 673 { 674 cd = cl->cd; 675 prev_isa = cd->isas; 676 break; 677 } 678 } 679 } 680 681 /* If we haven't initialized yet, initialize the opcode table. */ 682 if (! cd) 683 { 684 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 685 const char *mach_name; 686 687 if (!arch_type) 688 abort (); 689 mach_name = arch_type->printable_name; 690 691 prev_isa = cgen_bitset_copy (isa); 692 prev_mach = mach; 693 prev_endian = endian; 694 prev_insn_endian = insn_endian; 695 cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 696 CGEN_CPU_OPEN_BFDMACH, mach_name, 697 CGEN_CPU_OPEN_ENDIAN, prev_endian, 698 CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian, 699 CGEN_CPU_OPEN_END); 700 if (!cd) 701 abort (); 702 703 /* Save this away for future reference. */ 704 cl = xmalloc (sizeof (struct cpu_desc_list)); 705 cl->cd = cd; 706 cl->isa = prev_isa; 707 cl->mach = mach; 708 cl->endian = endian; 709 cl->next = cd_list; 710 cd_list = cl; 711 712 fr30_cgen_init_dis (cd); 713 } 714 715 /* We try to have as much common code as possible. 716 But at this point some targets need to take over. */ 717 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 718 but if not possible try to move this hook elsewhere rather than 719 have two hooks. */ 720 length = CGEN_PRINT_INSN (cd, pc, info); 721 if (length > 0) 722 return length; 723 if (length < 0) 724 return -1; 725 726 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 727 return cd->default_insn_bitsize / 8; 728} 729