1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* CPU data for bpf. 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6Copyright (C) 1996-2020 Free Software Foundation, Inc. 7 8This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24*/ 25 26#include "sysdep.h" 27#include <stdio.h> 28#include <stdarg.h> 29#include "ansidecl.h" 30#include "bfd.h" 31#include "symcat.h" 32#include "bpf-desc.h" 33#include "bpf-opc.h" 34#include "opintl.h" 35#include "libiberty.h" 36#include "xregex.h" 37 38/* Attributes. */ 39 40static const CGEN_ATTR_ENTRY bool_attr[] = 41{ 42 { "#f", 0 }, 43 { "#t", 1 }, 44 { 0, 0 } 45}; 46 47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 48{ 49 { "base", MACH_BASE }, 50 { "bpf", MACH_BPF }, 51 { "xbpf", MACH_XBPF }, 52 { "max", MACH_MAX }, 53 { 0, 0 } 54}; 55 56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 57{ 58 { "ebpfle", ISA_EBPFLE }, 59 { "ebpfbe", ISA_EBPFBE }, 60 { "xbpfle", ISA_XBPFLE }, 61 { "xbpfbe", ISA_XBPFBE }, 62 { "max", ISA_MAX }, 63 { 0, 0 } 64}; 65 66const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] = 67{ 68 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 69 { "ISA", & ISA_attr[0], & ISA_attr[0] }, 70 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 71 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 72 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 73 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 74 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 75 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 76 { 0, 0, 0 } 77}; 78 79const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] = 80{ 81 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 82 { "ISA", & ISA_attr[0], & ISA_attr[0] }, 83 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 84 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 85 { "PC", &bool_attr[0], &bool_attr[0] }, 86 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 87 { 0, 0, 0 } 88}; 89 90const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] = 91{ 92 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 93 { "ISA", & ISA_attr[0], & ISA_attr[0] }, 94 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 95 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 96 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 97 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 98 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 99 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 100 { "RELAX", &bool_attr[0], &bool_attr[0] }, 101 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 102 { 0, 0, 0 } 103}; 104 105const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] = 106{ 107 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 108 { "ISA", & ISA_attr[0], & ISA_attr[0] }, 109 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 110 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 111 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 112 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 113 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 114 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 115 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 116 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 117 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 118 { "PBB", &bool_attr[0], &bool_attr[0] }, 119 { 0, 0, 0 } 120}; 121 122/* Instruction set variants. */ 123 124static const CGEN_ISA bpf_cgen_isa_table[] = { 125 { "ebpfle", 64, 64, 64, 128 }, 126 { "ebpfbe", 64, 64, 64, 128 }, 127 { "xbpfle", 64, 64, 64, 128 }, 128 { "xbpfbe", 64, 64, 64, 128 }, 129 { 0, 0, 0, 0, 0 } 130}; 131 132/* Machine variants. */ 133 134static const CGEN_MACH bpf_cgen_mach_table[] = { 135 { "bpf", "bpf", MACH_BPF, 0 }, 136 { "xbpf", "xbpf", MACH_XBPF, 0 }, 137 { 0, 0, 0, 0 } 138}; 139 140static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] = 141{ 142 { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 143 { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 144 { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 145 { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 146 { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 147 { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 148 { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 149 { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 150 { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 151 { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 152 { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 }, 153 { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 154 { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 155 { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 } 156}; 157 158CGEN_KEYWORD bpf_cgen_opval_h_gpr = 159{ 160 & bpf_cgen_opval_h_gpr_entries[0], 161 14, 162 0, 0, 0, 0, "" 163}; 164 165 166/* The hardware table. */ 167 168#define A(a) (1 << CGEN_HW_##a) 169 170const CGEN_HW_ENTRY bpf_cgen_hw_table[] = 171{ 172 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 173 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 174 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 175 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 176 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 177 { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } }, 178 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 179 { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 180 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } 181}; 182 183#undef A 184 185 186/* The instruction field table. */ 187 188#define A(a) (1 << CGEN_IFLD_##a) 189 190const CGEN_IFLD bpf_cgen_ifld_table[] = 191{ 192 { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 193 { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 194 { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 195 { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 196 { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 197 { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 198 { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 199 { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, 200 { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, 201 { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, 202 { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, 203 { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 204 { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 205 { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 206 { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 207 { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 208 { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 209 { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 210 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } 211}; 212 213#undef A 214 215 216 217/* multi ifield declarations */ 218 219const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD []; 220 221 222/* multi ifield definitions */ 223 224const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] = 225{ 226 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_A] } }, 227 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_B] } }, 228 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM64_C] } }, 229 { 0, { (const PTR) 0 } } 230}; 231 232/* The operand table. */ 233 234#define A(a) (1 << CGEN_OPERAND_##a) 235#define OPERAND(op) BPF_OPERAND_##op 236 237const CGEN_OPERAND bpf_cgen_operand_table[] = 238{ 239/* pc: program counter */ 240 { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0, 241 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } }, 242 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 243/* dstle: destination register */ 244 { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4, 245 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } }, 246 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, 247/* srcle: source register */ 248 { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4, 249 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } }, 250 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } }, 251/* dstbe: destination register */ 252 { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4, 253 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } }, 254 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, 255/* srcbe: source register */ 256 { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4, 257 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } }, 258 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } }, 259/* disp16: 16-bit PC-relative address */ 260 { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16, 261 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } }, 262 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 263/* disp32: 32-bit PC-relative address */ 264 { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32, 265 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } }, 266 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 267/* imm32: 32-bit immediate */ 268 { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32, 269 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } }, 270 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 271/* offset16: 16-bit offset */ 272 { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16, 273 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } }, 274 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 275/* imm64: 64-bit immediate */ 276 { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96, 277 { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } }, 278 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 279/* endsize: endianness size immediate: 16, 32 or 64 */ 280 { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32, 281 { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } }, 282 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } }, 283/* sentinel */ 284 { 0, 0, 0, 0, 0, 285 { 0, { (const PTR) 0 } }, 286 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } } 287}; 288 289#undef A 290 291 292/* The instruction table. */ 293 294#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 295#define A(a) (1 << CGEN_INSN_##a) 296 297static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] = 298{ 299 /* Special null first entry. 300 A `num' value of zero is thus invalid. 301 Also, the special `invalid' insn resides here. */ 302 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }, 303/* add $dstle,$imm32 */ 304 { 305 BPF_INSN_ADDILE, "addile", "add", 64, 306 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 307 }, 308/* add $dstle,$srcle */ 309 { 310 BPF_INSN_ADDRLE, "addrle", "add", 64, 311 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 312 }, 313/* add32 $dstle,$imm32 */ 314 { 315 BPF_INSN_ADD32ILE, "add32ile", "add32", 64, 316 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 317 }, 318/* add32 $dstle,$srcle */ 319 { 320 BPF_INSN_ADD32RLE, "add32rle", "add32", 64, 321 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 322 }, 323/* sub $dstle,$imm32 */ 324 { 325 BPF_INSN_SUBILE, "subile", "sub", 64, 326 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 327 }, 328/* sub $dstle,$srcle */ 329 { 330 BPF_INSN_SUBRLE, "subrle", "sub", 64, 331 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 332 }, 333/* sub32 $dstle,$imm32 */ 334 { 335 BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64, 336 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 337 }, 338/* sub32 $dstle,$srcle */ 339 { 340 BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64, 341 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 342 }, 343/* mul $dstle,$imm32 */ 344 { 345 BPF_INSN_MULILE, "mulile", "mul", 64, 346 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 347 }, 348/* mul $dstle,$srcle */ 349 { 350 BPF_INSN_MULRLE, "mulrle", "mul", 64, 351 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 352 }, 353/* mul32 $dstle,$imm32 */ 354 { 355 BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64, 356 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 357 }, 358/* mul32 $dstle,$srcle */ 359 { 360 BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64, 361 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 362 }, 363/* div $dstle,$imm32 */ 364 { 365 BPF_INSN_DIVILE, "divile", "div", 64, 366 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 367 }, 368/* div $dstle,$srcle */ 369 { 370 BPF_INSN_DIVRLE, "divrle", "div", 64, 371 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 372 }, 373/* div32 $dstle,$imm32 */ 374 { 375 BPF_INSN_DIV32ILE, "div32ile", "div32", 64, 376 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 377 }, 378/* div32 $dstle,$srcle */ 379 { 380 BPF_INSN_DIV32RLE, "div32rle", "div32", 64, 381 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 382 }, 383/* or $dstle,$imm32 */ 384 { 385 BPF_INSN_ORILE, "orile", "or", 64, 386 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 387 }, 388/* or $dstle,$srcle */ 389 { 390 BPF_INSN_ORRLE, "orrle", "or", 64, 391 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 392 }, 393/* or32 $dstle,$imm32 */ 394 { 395 BPF_INSN_OR32ILE, "or32ile", "or32", 64, 396 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 397 }, 398/* or32 $dstle,$srcle */ 399 { 400 BPF_INSN_OR32RLE, "or32rle", "or32", 64, 401 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 402 }, 403/* and $dstle,$imm32 */ 404 { 405 BPF_INSN_ANDILE, "andile", "and", 64, 406 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 407 }, 408/* and $dstle,$srcle */ 409 { 410 BPF_INSN_ANDRLE, "andrle", "and", 64, 411 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 412 }, 413/* and32 $dstle,$imm32 */ 414 { 415 BPF_INSN_AND32ILE, "and32ile", "and32", 64, 416 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 417 }, 418/* and32 $dstle,$srcle */ 419 { 420 BPF_INSN_AND32RLE, "and32rle", "and32", 64, 421 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 422 }, 423/* lsh $dstle,$imm32 */ 424 { 425 BPF_INSN_LSHILE, "lshile", "lsh", 64, 426 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 427 }, 428/* lsh $dstle,$srcle */ 429 { 430 BPF_INSN_LSHRLE, "lshrle", "lsh", 64, 431 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 432 }, 433/* lsh32 $dstle,$imm32 */ 434 { 435 BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64, 436 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 437 }, 438/* lsh32 $dstle,$srcle */ 439 { 440 BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64, 441 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 442 }, 443/* rsh $dstle,$imm32 */ 444 { 445 BPF_INSN_RSHILE, "rshile", "rsh", 64, 446 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 447 }, 448/* rsh $dstle,$srcle */ 449 { 450 BPF_INSN_RSHRLE, "rshrle", "rsh", 64, 451 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 452 }, 453/* rsh32 $dstle,$imm32 */ 454 { 455 BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64, 456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 457 }, 458/* rsh32 $dstle,$srcle */ 459 { 460 BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64, 461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 462 }, 463/* mod $dstle,$imm32 */ 464 { 465 BPF_INSN_MODILE, "modile", "mod", 64, 466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 467 }, 468/* mod $dstle,$srcle */ 469 { 470 BPF_INSN_MODRLE, "modrle", "mod", 64, 471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 472 }, 473/* mod32 $dstle,$imm32 */ 474 { 475 BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64, 476 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 477 }, 478/* mod32 $dstle,$srcle */ 479 { 480 BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64, 481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 482 }, 483/* xor $dstle,$imm32 */ 484 { 485 BPF_INSN_XORILE, "xorile", "xor", 64, 486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 487 }, 488/* xor $dstle,$srcle */ 489 { 490 BPF_INSN_XORRLE, "xorrle", "xor", 64, 491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 492 }, 493/* xor32 $dstle,$imm32 */ 494 { 495 BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64, 496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 497 }, 498/* xor32 $dstle,$srcle */ 499 { 500 BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64, 501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 502 }, 503/* arsh $dstle,$imm32 */ 504 { 505 BPF_INSN_ARSHILE, "arshile", "arsh", 64, 506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 507 }, 508/* arsh $dstle,$srcle */ 509 { 510 BPF_INSN_ARSHRLE, "arshrle", "arsh", 64, 511 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 512 }, 513/* arsh32 $dstle,$imm32 */ 514 { 515 BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64, 516 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 517 }, 518/* arsh32 $dstle,$srcle */ 519 { 520 BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64, 521 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 522 }, 523/* neg $dstle */ 524 { 525 BPF_INSN_NEGLE, "negle", "neg", 64, 526 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 527 }, 528/* neg32 $dstle */ 529 { 530 BPF_INSN_NEG32LE, "neg32le", "neg32", 64, 531 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 532 }, 533/* mov $dstle,$imm32 */ 534 { 535 BPF_INSN_MOVILE, "movile", "mov", 64, 536 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 537 }, 538/* mov $dstle,$srcle */ 539 { 540 BPF_INSN_MOVRLE, "movrle", "mov", 64, 541 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 542 }, 543/* mov32 $dstle,$imm32 */ 544 { 545 BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64, 546 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 547 }, 548/* mov32 $dstle,$srcle */ 549 { 550 BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64, 551 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 552 }, 553/* add $dstbe,$imm32 */ 554 { 555 BPF_INSN_ADDIBE, "addibe", "add", 64, 556 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 557 }, 558/* add $dstbe,$srcbe */ 559 { 560 BPF_INSN_ADDRBE, "addrbe", "add", 64, 561 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 562 }, 563/* add32 $dstbe,$imm32 */ 564 { 565 BPF_INSN_ADD32IBE, "add32ibe", "add32", 64, 566 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 567 }, 568/* add32 $dstbe,$srcbe */ 569 { 570 BPF_INSN_ADD32RBE, "add32rbe", "add32", 64, 571 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 572 }, 573/* sub $dstbe,$imm32 */ 574 { 575 BPF_INSN_SUBIBE, "subibe", "sub", 64, 576 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 577 }, 578/* sub $dstbe,$srcbe */ 579 { 580 BPF_INSN_SUBRBE, "subrbe", "sub", 64, 581 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 582 }, 583/* sub32 $dstbe,$imm32 */ 584 { 585 BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64, 586 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 587 }, 588/* sub32 $dstbe,$srcbe */ 589 { 590 BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64, 591 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 592 }, 593/* mul $dstbe,$imm32 */ 594 { 595 BPF_INSN_MULIBE, "mulibe", "mul", 64, 596 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 597 }, 598/* mul $dstbe,$srcbe */ 599 { 600 BPF_INSN_MULRBE, "mulrbe", "mul", 64, 601 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 602 }, 603/* mul32 $dstbe,$imm32 */ 604 { 605 BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64, 606 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 607 }, 608/* mul32 $dstbe,$srcbe */ 609 { 610 BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64, 611 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 612 }, 613/* div $dstbe,$imm32 */ 614 { 615 BPF_INSN_DIVIBE, "divibe", "div", 64, 616 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 617 }, 618/* div $dstbe,$srcbe */ 619 { 620 BPF_INSN_DIVRBE, "divrbe", "div", 64, 621 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 622 }, 623/* div32 $dstbe,$imm32 */ 624 { 625 BPF_INSN_DIV32IBE, "div32ibe", "div32", 64, 626 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 627 }, 628/* div32 $dstbe,$srcbe */ 629 { 630 BPF_INSN_DIV32RBE, "div32rbe", "div32", 64, 631 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 632 }, 633/* or $dstbe,$imm32 */ 634 { 635 BPF_INSN_ORIBE, "oribe", "or", 64, 636 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 637 }, 638/* or $dstbe,$srcbe */ 639 { 640 BPF_INSN_ORRBE, "orrbe", "or", 64, 641 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 642 }, 643/* or32 $dstbe,$imm32 */ 644 { 645 BPF_INSN_OR32IBE, "or32ibe", "or32", 64, 646 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 647 }, 648/* or32 $dstbe,$srcbe */ 649 { 650 BPF_INSN_OR32RBE, "or32rbe", "or32", 64, 651 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 652 }, 653/* and $dstbe,$imm32 */ 654 { 655 BPF_INSN_ANDIBE, "andibe", "and", 64, 656 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 657 }, 658/* and $dstbe,$srcbe */ 659 { 660 BPF_INSN_ANDRBE, "andrbe", "and", 64, 661 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 662 }, 663/* and32 $dstbe,$imm32 */ 664 { 665 BPF_INSN_AND32IBE, "and32ibe", "and32", 64, 666 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 667 }, 668/* and32 $dstbe,$srcbe */ 669 { 670 BPF_INSN_AND32RBE, "and32rbe", "and32", 64, 671 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 672 }, 673/* lsh $dstbe,$imm32 */ 674 { 675 BPF_INSN_LSHIBE, "lshibe", "lsh", 64, 676 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 677 }, 678/* lsh $dstbe,$srcbe */ 679 { 680 BPF_INSN_LSHRBE, "lshrbe", "lsh", 64, 681 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 682 }, 683/* lsh32 $dstbe,$imm32 */ 684 { 685 BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64, 686 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 687 }, 688/* lsh32 $dstbe,$srcbe */ 689 { 690 BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64, 691 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 692 }, 693/* rsh $dstbe,$imm32 */ 694 { 695 BPF_INSN_RSHIBE, "rshibe", "rsh", 64, 696 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 697 }, 698/* rsh $dstbe,$srcbe */ 699 { 700 BPF_INSN_RSHRBE, "rshrbe", "rsh", 64, 701 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 702 }, 703/* rsh32 $dstbe,$imm32 */ 704 { 705 BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64, 706 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 707 }, 708/* rsh32 $dstbe,$srcbe */ 709 { 710 BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64, 711 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 712 }, 713/* mod $dstbe,$imm32 */ 714 { 715 BPF_INSN_MODIBE, "modibe", "mod", 64, 716 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 717 }, 718/* mod $dstbe,$srcbe */ 719 { 720 BPF_INSN_MODRBE, "modrbe", "mod", 64, 721 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 722 }, 723/* mod32 $dstbe,$imm32 */ 724 { 725 BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64, 726 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 727 }, 728/* mod32 $dstbe,$srcbe */ 729 { 730 BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64, 731 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 732 }, 733/* xor $dstbe,$imm32 */ 734 { 735 BPF_INSN_XORIBE, "xoribe", "xor", 64, 736 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 737 }, 738/* xor $dstbe,$srcbe */ 739 { 740 BPF_INSN_XORRBE, "xorrbe", "xor", 64, 741 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 742 }, 743/* xor32 $dstbe,$imm32 */ 744 { 745 BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64, 746 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 747 }, 748/* xor32 $dstbe,$srcbe */ 749 { 750 BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64, 751 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 752 }, 753/* arsh $dstbe,$imm32 */ 754 { 755 BPF_INSN_ARSHIBE, "arshibe", "arsh", 64, 756 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 757 }, 758/* arsh $dstbe,$srcbe */ 759 { 760 BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64, 761 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 762 }, 763/* arsh32 $dstbe,$imm32 */ 764 { 765 BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64, 766 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 767 }, 768/* arsh32 $dstbe,$srcbe */ 769 { 770 BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64, 771 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 772 }, 773/* neg $dstbe */ 774 { 775 BPF_INSN_NEGBE, "negbe", "neg", 64, 776 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 777 }, 778/* neg32 $dstbe */ 779 { 780 BPF_INSN_NEG32BE, "neg32be", "neg32", 64, 781 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 782 }, 783/* mov $dstbe,$imm32 */ 784 { 785 BPF_INSN_MOVIBE, "movibe", "mov", 64, 786 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 787 }, 788/* mov $dstbe,$srcbe */ 789 { 790 BPF_INSN_MOVRBE, "movrbe", "mov", 64, 791 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 792 }, 793/* mov32 $dstbe,$imm32 */ 794 { 795 BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64, 796 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 797 }, 798/* mov32 $dstbe,$srcbe */ 799 { 800 BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64, 801 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 802 }, 803/* endle $dstle,$endsize */ 804 { 805 BPF_INSN_ENDLELE, "endlele", "endle", 64, 806 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 807 }, 808/* endbe $dstle,$endsize */ 809 { 810 BPF_INSN_ENDBELE, "endbele", "endbe", 64, 811 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 812 }, 813/* endle $dstbe,$endsize */ 814 { 815 BPF_INSN_ENDLEBE, "endlebe", "endle", 64, 816 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 817 }, 818/* endbe $dstbe,$endsize */ 819 { 820 BPF_INSN_ENDBEBE, "endbebe", "endbe", 64, 821 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 822 }, 823/* lddw $dstle,$imm64 */ 824 { 825 BPF_INSN_LDDWLE, "lddwle", "lddw", 128, 826 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 827 }, 828/* lddw $dstbe,$imm64 */ 829 { 830 BPF_INSN_LDDWBE, "lddwbe", "lddw", 128, 831 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 832 }, 833/* ldabsw $imm32 */ 834 { 835 BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64, 836 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 837 }, 838/* ldabsh $imm32 */ 839 { 840 BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64, 841 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 842 }, 843/* ldabsb $imm32 */ 844 { 845 BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64, 846 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 847 }, 848/* ldabsdw $imm32 */ 849 { 850 BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64, 851 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 852 }, 853/* ldindw $srcle,$imm32 */ 854 { 855 BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64, 856 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 857 }, 858/* ldindh $srcle,$imm32 */ 859 { 860 BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64, 861 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 862 }, 863/* ldindb $srcle,$imm32 */ 864 { 865 BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64, 866 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 867 }, 868/* ldinddw $srcle,$imm32 */ 869 { 870 BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64, 871 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 872 }, 873/* ldindw $srcbe,$imm32 */ 874 { 875 BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64, 876 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 877 }, 878/* ldindh $srcbe,$imm32 */ 879 { 880 BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64, 881 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 882 }, 883/* ldindb $srcbe,$imm32 */ 884 { 885 BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64, 886 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 887 }, 888/* ldinddw $srcbe,$imm32 */ 889 { 890 BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64, 891 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 892 }, 893/* ldxw $dstle,[$srcle+$offset16] */ 894 { 895 BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64, 896 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 897 }, 898/* ldxh $dstle,[$srcle+$offset16] */ 899 { 900 BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64, 901 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 902 }, 903/* ldxb $dstle,[$srcle+$offset16] */ 904 { 905 BPF_INSN_LDXBLE, "ldxble", "ldxb", 64, 906 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 907 }, 908/* ldxdw $dstle,[$srcle+$offset16] */ 909 { 910 BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64, 911 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 912 }, 913/* stxw [$dstle+$offset16],$srcle */ 914 { 915 BPF_INSN_STXWLE, "stxwle", "stxw", 64, 916 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 917 }, 918/* stxh [$dstle+$offset16],$srcle */ 919 { 920 BPF_INSN_STXHLE, "stxhle", "stxh", 64, 921 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 922 }, 923/* stxb [$dstle+$offset16],$srcle */ 924 { 925 BPF_INSN_STXBLE, "stxble", "stxb", 64, 926 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 927 }, 928/* stxdw [$dstle+$offset16],$srcle */ 929 { 930 BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64, 931 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 932 }, 933/* ldxw $dstbe,[$srcbe+$offset16] */ 934 { 935 BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64, 936 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 937 }, 938/* ldxh $dstbe,[$srcbe+$offset16] */ 939 { 940 BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64, 941 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 942 }, 943/* ldxb $dstbe,[$srcbe+$offset16] */ 944 { 945 BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64, 946 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 947 }, 948/* ldxdw $dstbe,[$srcbe+$offset16] */ 949 { 950 BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64, 951 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 952 }, 953/* stxw [$dstbe+$offset16],$srcbe */ 954 { 955 BPF_INSN_STXWBE, "stxwbe", "stxw", 64, 956 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 957 }, 958/* stxh [$dstbe+$offset16],$srcbe */ 959 { 960 BPF_INSN_STXHBE, "stxhbe", "stxh", 64, 961 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 962 }, 963/* stxb [$dstbe+$offset16],$srcbe */ 964 { 965 BPF_INSN_STXBBE, "stxbbe", "stxb", 64, 966 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 967 }, 968/* stxdw [$dstbe+$offset16],$srcbe */ 969 { 970 BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64, 971 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 972 }, 973/* stb [$dstle+$offset16],$imm32 */ 974 { 975 BPF_INSN_STBLE, "stble", "stb", 64, 976 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 977 }, 978/* sth [$dstle+$offset16],$imm32 */ 979 { 980 BPF_INSN_STHLE, "sthle", "sth", 64, 981 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 982 }, 983/* stw [$dstle+$offset16],$imm32 */ 984 { 985 BPF_INSN_STWLE, "stwle", "stw", 64, 986 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 987 }, 988/* stdw [$dstle+$offset16],$imm32 */ 989 { 990 BPF_INSN_STDWLE, "stdwle", "stdw", 64, 991 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 992 }, 993/* stb [$dstbe+$offset16],$imm32 */ 994 { 995 BPF_INSN_STBBE, "stbbe", "stb", 64, 996 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 997 }, 998/* sth [$dstbe+$offset16],$imm32 */ 999 { 1000 BPF_INSN_STHBE, "sthbe", "sth", 64, 1001 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1002 }, 1003/* stw [$dstbe+$offset16],$imm32 */ 1004 { 1005 BPF_INSN_STWBE, "stwbe", "stw", 64, 1006 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1007 }, 1008/* stdw [$dstbe+$offset16],$imm32 */ 1009 { 1010 BPF_INSN_STDWBE, "stdwbe", "stdw", 64, 1011 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1012 }, 1013/* jeq $dstle,$imm32,$disp16 */ 1014 { 1015 BPF_INSN_JEQILE, "jeqile", "jeq", 64, 1016 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1017 }, 1018/* jeq $dstle,$srcle,$disp16 */ 1019 { 1020 BPF_INSN_JEQRLE, "jeqrle", "jeq", 64, 1021 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1022 }, 1023/* jeq32 $dstle,$imm32,$disp16 */ 1024 { 1025 BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64, 1026 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1027 }, 1028/* jeq32 $dstle,$srcle,$disp16 */ 1029 { 1030 BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64, 1031 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1032 }, 1033/* jgt $dstle,$imm32,$disp16 */ 1034 { 1035 BPF_INSN_JGTILE, "jgtile", "jgt", 64, 1036 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1037 }, 1038/* jgt $dstle,$srcle,$disp16 */ 1039 { 1040 BPF_INSN_JGTRLE, "jgtrle", "jgt", 64, 1041 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1042 }, 1043/* jgt32 $dstle,$imm32,$disp16 */ 1044 { 1045 BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64, 1046 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1047 }, 1048/* jgt32 $dstle,$srcle,$disp16 */ 1049 { 1050 BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64, 1051 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1052 }, 1053/* jge $dstle,$imm32,$disp16 */ 1054 { 1055 BPF_INSN_JGEILE, "jgeile", "jge", 64, 1056 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1057 }, 1058/* jge $dstle,$srcle,$disp16 */ 1059 { 1060 BPF_INSN_JGERLE, "jgerle", "jge", 64, 1061 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1062 }, 1063/* jge32 $dstle,$imm32,$disp16 */ 1064 { 1065 BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64, 1066 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1067 }, 1068/* jge32 $dstle,$srcle,$disp16 */ 1069 { 1070 BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64, 1071 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1072 }, 1073/* jlt $dstle,$imm32,$disp16 */ 1074 { 1075 BPF_INSN_JLTILE, "jltile", "jlt", 64, 1076 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1077 }, 1078/* jlt $dstle,$srcle,$disp16 */ 1079 { 1080 BPF_INSN_JLTRLE, "jltrle", "jlt", 64, 1081 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1082 }, 1083/* jlt32 $dstle,$imm32,$disp16 */ 1084 { 1085 BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64, 1086 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1087 }, 1088/* jlt32 $dstle,$srcle,$disp16 */ 1089 { 1090 BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64, 1091 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1092 }, 1093/* jle $dstle,$imm32,$disp16 */ 1094 { 1095 BPF_INSN_JLEILE, "jleile", "jle", 64, 1096 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1097 }, 1098/* jle $dstle,$srcle,$disp16 */ 1099 { 1100 BPF_INSN_JLERLE, "jlerle", "jle", 64, 1101 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1102 }, 1103/* jle32 $dstle,$imm32,$disp16 */ 1104 { 1105 BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64, 1106 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1107 }, 1108/* jle32 $dstle,$srcle,$disp16 */ 1109 { 1110 BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64, 1111 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1112 }, 1113/* jset $dstle,$imm32,$disp16 */ 1114 { 1115 BPF_INSN_JSETILE, "jsetile", "jset", 64, 1116 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1117 }, 1118/* jset $dstle,$srcle,$disp16 */ 1119 { 1120 BPF_INSN_JSETRLE, "jsetrle", "jset", 64, 1121 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1122 }, 1123/* jset32 $dstle,$imm32,$disp16 */ 1124 { 1125 BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64, 1126 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1127 }, 1128/* jset32 $dstle,$srcle,$disp16 */ 1129 { 1130 BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64, 1131 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1132 }, 1133/* jne $dstle,$imm32,$disp16 */ 1134 { 1135 BPF_INSN_JNEILE, "jneile", "jne", 64, 1136 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1137 }, 1138/* jne $dstle,$srcle,$disp16 */ 1139 { 1140 BPF_INSN_JNERLE, "jnerle", "jne", 64, 1141 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1142 }, 1143/* jne32 $dstle,$imm32,$disp16 */ 1144 { 1145 BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64, 1146 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1147 }, 1148/* jne32 $dstle,$srcle,$disp16 */ 1149 { 1150 BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64, 1151 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1152 }, 1153/* jsgt $dstle,$imm32,$disp16 */ 1154 { 1155 BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64, 1156 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1157 }, 1158/* jsgt $dstle,$srcle,$disp16 */ 1159 { 1160 BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64, 1161 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1162 }, 1163/* jsgt32 $dstle,$imm32,$disp16 */ 1164 { 1165 BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64, 1166 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1167 }, 1168/* jsgt32 $dstle,$srcle,$disp16 */ 1169 { 1170 BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64, 1171 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1172 }, 1173/* jsge $dstle,$imm32,$disp16 */ 1174 { 1175 BPF_INSN_JSGEILE, "jsgeile", "jsge", 64, 1176 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1177 }, 1178/* jsge $dstle,$srcle,$disp16 */ 1179 { 1180 BPF_INSN_JSGERLE, "jsgerle", "jsge", 64, 1181 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1182 }, 1183/* jsge32 $dstle,$imm32,$disp16 */ 1184 { 1185 BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64, 1186 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1187 }, 1188/* jsge32 $dstle,$srcle,$disp16 */ 1189 { 1190 BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64, 1191 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1192 }, 1193/* jslt $dstle,$imm32,$disp16 */ 1194 { 1195 BPF_INSN_JSLTILE, "jsltile", "jslt", 64, 1196 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1197 }, 1198/* jslt $dstle,$srcle,$disp16 */ 1199 { 1200 BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64, 1201 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1202 }, 1203/* jslt32 $dstle,$imm32,$disp16 */ 1204 { 1205 BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64, 1206 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1207 }, 1208/* jslt32 $dstle,$srcle,$disp16 */ 1209 { 1210 BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64, 1211 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1212 }, 1213/* jsle $dstle,$imm32,$disp16 */ 1214 { 1215 BPF_INSN_JSLEILE, "jsleile", "jsle", 64, 1216 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1217 }, 1218/* jsle $dstle,$srcle,$disp16 */ 1219 { 1220 BPF_INSN_JSLERLE, "jslerle", "jsle", 64, 1221 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1222 }, 1223/* jsle32 $dstle,$imm32,$disp16 */ 1224 { 1225 BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64, 1226 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1227 }, 1228/* jsle32 $dstle,$srcle,$disp16 */ 1229 { 1230 BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64, 1231 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1232 }, 1233/* jeq $dstbe,$imm32,$disp16 */ 1234 { 1235 BPF_INSN_JEQIBE, "jeqibe", "jeq", 64, 1236 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1237 }, 1238/* jeq $dstbe,$srcbe,$disp16 */ 1239 { 1240 BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64, 1241 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1242 }, 1243/* jeq32 $dstbe,$imm32,$disp16 */ 1244 { 1245 BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64, 1246 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1247 }, 1248/* jeq32 $dstbe,$srcbe,$disp16 */ 1249 { 1250 BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64, 1251 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1252 }, 1253/* jgt $dstbe,$imm32,$disp16 */ 1254 { 1255 BPF_INSN_JGTIBE, "jgtibe", "jgt", 64, 1256 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1257 }, 1258/* jgt $dstbe,$srcbe,$disp16 */ 1259 { 1260 BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64, 1261 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1262 }, 1263/* jgt32 $dstbe,$imm32,$disp16 */ 1264 { 1265 BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64, 1266 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1267 }, 1268/* jgt32 $dstbe,$srcbe,$disp16 */ 1269 { 1270 BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64, 1271 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1272 }, 1273/* jge $dstbe,$imm32,$disp16 */ 1274 { 1275 BPF_INSN_JGEIBE, "jgeibe", "jge", 64, 1276 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1277 }, 1278/* jge $dstbe,$srcbe,$disp16 */ 1279 { 1280 BPF_INSN_JGERBE, "jgerbe", "jge", 64, 1281 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1282 }, 1283/* jge32 $dstbe,$imm32,$disp16 */ 1284 { 1285 BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64, 1286 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1287 }, 1288/* jge32 $dstbe,$srcbe,$disp16 */ 1289 { 1290 BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64, 1291 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1292 }, 1293/* jlt $dstbe,$imm32,$disp16 */ 1294 { 1295 BPF_INSN_JLTIBE, "jltibe", "jlt", 64, 1296 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1297 }, 1298/* jlt $dstbe,$srcbe,$disp16 */ 1299 { 1300 BPF_INSN_JLTRBE, "jltrbe", "jlt", 64, 1301 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1302 }, 1303/* jlt32 $dstbe,$imm32,$disp16 */ 1304 { 1305 BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64, 1306 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1307 }, 1308/* jlt32 $dstbe,$srcbe,$disp16 */ 1309 { 1310 BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64, 1311 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1312 }, 1313/* jle $dstbe,$imm32,$disp16 */ 1314 { 1315 BPF_INSN_JLEIBE, "jleibe", "jle", 64, 1316 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1317 }, 1318/* jle $dstbe,$srcbe,$disp16 */ 1319 { 1320 BPF_INSN_JLERBE, "jlerbe", "jle", 64, 1321 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1322 }, 1323/* jle32 $dstbe,$imm32,$disp16 */ 1324 { 1325 BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64, 1326 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1327 }, 1328/* jle32 $dstbe,$srcbe,$disp16 */ 1329 { 1330 BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64, 1331 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1332 }, 1333/* jset $dstbe,$imm32,$disp16 */ 1334 { 1335 BPF_INSN_JSETIBE, "jsetibe", "jset", 64, 1336 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1337 }, 1338/* jset $dstbe,$srcbe,$disp16 */ 1339 { 1340 BPF_INSN_JSETRBE, "jsetrbe", "jset", 64, 1341 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1342 }, 1343/* jset32 $dstbe,$imm32,$disp16 */ 1344 { 1345 BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64, 1346 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1347 }, 1348/* jset32 $dstbe,$srcbe,$disp16 */ 1349 { 1350 BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64, 1351 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1352 }, 1353/* jne $dstbe,$imm32,$disp16 */ 1354 { 1355 BPF_INSN_JNEIBE, "jneibe", "jne", 64, 1356 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1357 }, 1358/* jne $dstbe,$srcbe,$disp16 */ 1359 { 1360 BPF_INSN_JNERBE, "jnerbe", "jne", 64, 1361 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1362 }, 1363/* jne32 $dstbe,$imm32,$disp16 */ 1364 { 1365 BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64, 1366 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1367 }, 1368/* jne32 $dstbe,$srcbe,$disp16 */ 1369 { 1370 BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64, 1371 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1372 }, 1373/* jsgt $dstbe,$imm32,$disp16 */ 1374 { 1375 BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64, 1376 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1377 }, 1378/* jsgt $dstbe,$srcbe,$disp16 */ 1379 { 1380 BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64, 1381 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1382 }, 1383/* jsgt32 $dstbe,$imm32,$disp16 */ 1384 { 1385 BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64, 1386 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1387 }, 1388/* jsgt32 $dstbe,$srcbe,$disp16 */ 1389 { 1390 BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64, 1391 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1392 }, 1393/* jsge $dstbe,$imm32,$disp16 */ 1394 { 1395 BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64, 1396 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1397 }, 1398/* jsge $dstbe,$srcbe,$disp16 */ 1399 { 1400 BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64, 1401 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1402 }, 1403/* jsge32 $dstbe,$imm32,$disp16 */ 1404 { 1405 BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64, 1406 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1407 }, 1408/* jsge32 $dstbe,$srcbe,$disp16 */ 1409 { 1410 BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64, 1411 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1412 }, 1413/* jslt $dstbe,$imm32,$disp16 */ 1414 { 1415 BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64, 1416 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1417 }, 1418/* jslt $dstbe,$srcbe,$disp16 */ 1419 { 1420 BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64, 1421 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1422 }, 1423/* jslt32 $dstbe,$imm32,$disp16 */ 1424 { 1425 BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64, 1426 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1427 }, 1428/* jslt32 $dstbe,$srcbe,$disp16 */ 1429 { 1430 BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64, 1431 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1432 }, 1433/* jsle $dstbe,$imm32,$disp16 */ 1434 { 1435 BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64, 1436 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1437 }, 1438/* jsle $dstbe,$srcbe,$disp16 */ 1439 { 1440 BPF_INSN_JSLERBE, "jslerbe", "jsle", 64, 1441 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1442 }, 1443/* jsle32 $dstbe,$imm32,$disp16 */ 1444 { 1445 BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64, 1446 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1447 }, 1448/* jsle32 $dstbe,$srcbe,$disp16 */ 1449 { 1450 BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64, 1451 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1452 }, 1453/* call $disp32 */ 1454 { 1455 BPF_INSN_CALLLE, "callle", "call", 64, 1456 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1457 }, 1458/* call $disp32 */ 1459 { 1460 BPF_INSN_CALLBE, "callbe", "call", 64, 1461 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1462 }, 1463/* call $dstle */ 1464 { 1465 BPF_INSN_CALLRLE, "callrle", "call", 64, 1466 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } } 1467 }, 1468/* call $dstbe */ 1469 { 1470 BPF_INSN_CALLRBE, "callrbe", "call", 64, 1471 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } } 1472 }, 1473/* ja $disp16 */ 1474 { 1475 BPF_INSN_JA, "ja", "ja", 64, 1476 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 1477 }, 1478/* exit */ 1479 { 1480 BPF_INSN_EXIT, "exit", "exit", 64, 1481 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 1482 }, 1483/* xadddw [$dstle+$offset16],$srcle */ 1484 { 1485 BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64, 1486 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1487 }, 1488/* xaddw [$dstle+$offset16],$srcle */ 1489 { 1490 BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64, 1491 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } } 1492 }, 1493/* xadddw [$dstbe+$offset16],$srcbe */ 1494 { 1495 BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64, 1496 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1497 }, 1498/* xaddw [$dstbe+$offset16],$srcbe */ 1499 { 1500 BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64, 1501 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } } 1502 }, 1503/* brkpt */ 1504 { 1505 BPF_INSN_BRKPT, "brkpt", "brkpt", 64, 1506 { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } 1507 }, 1508}; 1509 1510#undef OP 1511#undef A 1512 1513/* Initialize anything needed to be done once, before any cpu_open call. */ 1514 1515static void 1516init_tables (void) 1517{ 1518} 1519 1520#ifndef opcodes_error_handler 1521#define opcodes_error_handler(...) \ 1522 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) 1523#endif 1524 1525static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 1526static void build_hw_table (CGEN_CPU_TABLE *); 1527static void build_ifield_table (CGEN_CPU_TABLE *); 1528static void build_operand_table (CGEN_CPU_TABLE *); 1529static void build_insn_table (CGEN_CPU_TABLE *); 1530static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *); 1531 1532/* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name. */ 1533 1534static const CGEN_MACH * 1535lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 1536{ 1537 while (table->name) 1538 { 1539 if (strcmp (name, table->bfd_name) == 0) 1540 return table; 1541 ++table; 1542 } 1543 return NULL; 1544} 1545 1546/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */ 1547 1548static void 1549build_hw_table (CGEN_CPU_TABLE *cd) 1550{ 1551 int i; 1552 int machs = cd->machs; 1553 const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0]; 1554 /* MAX_HW is only an upper bound on the number of selected entries. 1555 However each entry is indexed by it's enum so there can be holes in 1556 the table. */ 1557 const CGEN_HW_ENTRY **selected = 1558 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1559 1560 cd->hw_table.init_entries = init; 1561 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 1562 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1563 /* ??? For now we just use machs to determine which ones we want. */ 1564 for (i = 0; init[i].name != NULL; ++i) 1565 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 1566 & machs) 1567 selected[init[i].type] = &init[i]; 1568 cd->hw_table.entries = selected; 1569 cd->hw_table.num_entries = MAX_HW; 1570} 1571 1572/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */ 1573 1574static void 1575build_ifield_table (CGEN_CPU_TABLE *cd) 1576{ 1577 cd->ifld_table = & bpf_cgen_ifld_table[0]; 1578} 1579 1580/* Subroutine of bpf_cgen_cpu_open to build the hardware table. */ 1581 1582static void 1583build_operand_table (CGEN_CPU_TABLE *cd) 1584{ 1585 int i; 1586 int machs = cd->machs; 1587 const CGEN_OPERAND *init = & bpf_cgen_operand_table[0]; 1588 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 1589 However each entry is indexed by it's enum so there can be holes in 1590 the table. */ 1591 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 1592 1593 cd->operand_table.init_entries = init; 1594 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 1595 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 1596 /* ??? For now we just use mach to determine which ones we want. */ 1597 for (i = 0; init[i].name != NULL; ++i) 1598 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 1599 & machs) 1600 selected[init[i].type] = &init[i]; 1601 cd->operand_table.entries = selected; 1602 cd->operand_table.num_entries = MAX_OPERANDS; 1603} 1604 1605/* Subroutine of bpf_cgen_cpu_open to build the hardware table. 1606 ??? This could leave out insns not supported by the specified mach/isa, 1607 but that would cause errors like "foo only supported by bar" to become 1608 "unknown insn", so for now we include all insns and require the app to 1609 do the checking later. 1610 ??? On the other hand, parsing of such insns may require their hardware or 1611 operand elements to be in the table [which they mightn't be]. */ 1612 1613static void 1614build_insn_table (CGEN_CPU_TABLE *cd) 1615{ 1616 int i; 1617 const CGEN_IBASE *ib = & bpf_cgen_insn_table[0]; 1618 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 1619 1620 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 1621 for (i = 0; i < MAX_INSNS; ++i) 1622 insns[i].base = &ib[i]; 1623 cd->insn_table.init_entries = insns; 1624 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 1625 cd->insn_table.num_init_entries = MAX_INSNS; 1626} 1627 1628/* Subroutine of bpf_cgen_cpu_open to rebuild the tables. */ 1629 1630static void 1631bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 1632{ 1633 int i; 1634 CGEN_BITSET *isas = cd->isas; 1635 unsigned int machs = cd->machs; 1636 1637 cd->int_insn_p = CGEN_INT_INSN_P; 1638 1639 /* Data derived from the isa spec. */ 1640#define UNSET (CGEN_SIZE_UNKNOWN + 1) 1641 cd->default_insn_bitsize = UNSET; 1642 cd->base_insn_bitsize = UNSET; 1643 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 1644 cd->max_insn_bitsize = 0; 1645 for (i = 0; i < MAX_ISAS; ++i) 1646 if (cgen_bitset_contains (isas, i)) 1647 { 1648 const CGEN_ISA *isa = & bpf_cgen_isa_table[i]; 1649 1650 /* Default insn sizes of all selected isas must be 1651 equal or we set the result to 0, meaning "unknown". */ 1652 if (cd->default_insn_bitsize == UNSET) 1653 cd->default_insn_bitsize = isa->default_insn_bitsize; 1654 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 1655 ; /* This is ok. */ 1656 else 1657 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 1658 1659 /* Base insn sizes of all selected isas must be equal 1660 or we set the result to 0, meaning "unknown". */ 1661 if (cd->base_insn_bitsize == UNSET) 1662 cd->base_insn_bitsize = isa->base_insn_bitsize; 1663 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 1664 ; /* This is ok. */ 1665 else 1666 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 1667 1668 /* Set min,max insn sizes. */ 1669 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 1670 cd->min_insn_bitsize = isa->min_insn_bitsize; 1671 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 1672 cd->max_insn_bitsize = isa->max_insn_bitsize; 1673 } 1674 1675 /* Data derived from the mach spec. */ 1676 for (i = 0; i < MAX_MACHS; ++i) 1677 if (((1 << i) & machs) != 0) 1678 { 1679 const CGEN_MACH *mach = & bpf_cgen_mach_table[i]; 1680 1681 if (mach->insn_chunk_bitsize != 0) 1682 { 1683 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 1684 { 1685 opcodes_error_handler 1686 (/* xgettext:c-format */ 1687 _("internal error: bpf_cgen_rebuild_tables: " 1688 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), 1689 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 1690 abort (); 1691 } 1692 1693 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 1694 } 1695 } 1696 1697 /* Determine which hw elements are used by MACH. */ 1698 build_hw_table (cd); 1699 1700 /* Build the ifield table. */ 1701 build_ifield_table (cd); 1702 1703 /* Determine which operands are used by MACH/ISA. */ 1704 build_operand_table (cd); 1705 1706 /* Build the instruction table. */ 1707 build_insn_table (cd); 1708} 1709 1710/* Initialize a cpu table and return a descriptor. 1711 It's much like opening a file, and must be the first function called. 1712 The arguments are a set of (type/value) pairs, terminated with 1713 CGEN_CPU_OPEN_END. 1714 1715 Currently supported values: 1716 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 1717 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 1718 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 1719 CGEN_CPU_OPEN_ENDIAN: specify endian choice 1720 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice 1721 CGEN_CPU_OPEN_END: terminates arguments 1722 1723 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 1724 precluded. */ 1725 1726CGEN_CPU_DESC 1727bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 1728{ 1729 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 1730 static int init_p; 1731 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 1732 unsigned int machs = 0; /* 0 = "unspecified" */ 1733 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 1734 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; 1735 va_list ap; 1736 1737 if (! init_p) 1738 { 1739 init_tables (); 1740 init_p = 1; 1741 } 1742 1743 memset (cd, 0, sizeof (*cd)); 1744 1745 va_start (ap, arg_type); 1746 while (arg_type != CGEN_CPU_OPEN_END) 1747 { 1748 switch (arg_type) 1749 { 1750 case CGEN_CPU_OPEN_ISAS : 1751 isas = va_arg (ap, CGEN_BITSET *); 1752 break; 1753 case CGEN_CPU_OPEN_MACHS : 1754 machs = va_arg (ap, unsigned int); 1755 break; 1756 case CGEN_CPU_OPEN_BFDMACH : 1757 { 1758 const char *name = va_arg (ap, const char *); 1759 const CGEN_MACH *mach = 1760 lookup_mach_via_bfd_name (bpf_cgen_mach_table, name); 1761 1762 if (mach != NULL) 1763 machs |= 1 << mach->num; 1764 break; 1765 } 1766 case CGEN_CPU_OPEN_ENDIAN : 1767 endian = va_arg (ap, enum cgen_endian); 1768 break; 1769 case CGEN_CPU_OPEN_INSN_ENDIAN : 1770 insn_endian = va_arg (ap, enum cgen_endian); 1771 break; 1772 default : 1773 opcodes_error_handler 1774 (/* xgettext:c-format */ 1775 _("internal error: bpf_cgen_cpu_open: " 1776 "unsupported argument `%d'"), 1777 arg_type); 1778 abort (); /* ??? return NULL? */ 1779 } 1780 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 1781 } 1782 va_end (ap); 1783 1784 /* Mach unspecified means "all". */ 1785 if (machs == 0) 1786 machs = (1 << MAX_MACHS) - 1; 1787 /* Base mach is always selected. */ 1788 machs |= 1; 1789 if (endian == CGEN_ENDIAN_UNKNOWN) 1790 { 1791 /* ??? If target has only one, could have a default. */ 1792 opcodes_error_handler 1793 (/* xgettext:c-format */ 1794 _("internal error: bpf_cgen_cpu_open: no endianness specified")); 1795 abort (); 1796 } 1797 1798 cd->isas = cgen_bitset_copy (isas); 1799 cd->machs = machs; 1800 cd->endian = endian; 1801 cd->insn_endian 1802 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); 1803 1804 /* Table (re)builder. */ 1805 cd->rebuild_tables = bpf_cgen_rebuild_tables; 1806 bpf_cgen_rebuild_tables (cd); 1807 1808 /* Default to not allowing signed overflow. */ 1809 cd->signed_overflow_ok_p = 0; 1810 1811 return (CGEN_CPU_DESC) cd; 1812} 1813 1814/* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 1815 MACH_NAME is the bfd name of the mach. */ 1816 1817CGEN_CPU_DESC 1818bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 1819{ 1820 return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 1821 CGEN_CPU_OPEN_ENDIAN, endian, 1822 CGEN_CPU_OPEN_END); 1823} 1824 1825/* Close a cpu table. 1826 ??? This can live in a machine independent file, but there's currently 1827 no place to put this file (there's no libcgen). libopcodes is the wrong 1828 place as some simulator ports use this but they don't use libopcodes. */ 1829 1830void 1831bpf_cgen_cpu_close (CGEN_CPU_DESC cd) 1832{ 1833 unsigned int i; 1834 const CGEN_INSN *insns; 1835 1836 if (cd->macro_insn_table.init_entries) 1837 { 1838 insns = cd->macro_insn_table.init_entries; 1839 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 1840 if (CGEN_INSN_RX ((insns))) 1841 regfree (CGEN_INSN_RX (insns)); 1842 } 1843 1844 if (cd->insn_table.init_entries) 1845 { 1846 insns = cd->insn_table.init_entries; 1847 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 1848 if (CGEN_INSN_RX (insns)) 1849 regfree (CGEN_INSN_RX (insns)); 1850 } 1851 1852 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 1853 free ((CGEN_INSN *) cd->insn_table.init_entries); 1854 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 1855 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 1856 free (cd); 1857} 1858 1859