1/* Target-dependent code for SPARC. 2 3 Copyright (C) 2003-2020 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#include "defs.h" 21#include "arch-utils.h" 22#include "dis-asm.h" 23#include "dwarf2.h" 24#include "dwarf2/frame.h" 25#include "frame.h" 26#include "frame-base.h" 27#include "frame-unwind.h" 28#include "gdbcore.h" 29#include "gdbtypes.h" 30#include "inferior.h" 31#include "symtab.h" 32#include "objfiles.h" 33#include "osabi.h" 34#include "regcache.h" 35#include "target.h" 36#include "target-descriptions.h" 37#include "value.h" 38 39#include "sparc-tdep.h" 40#include "sparc-ravenscar-thread.h" 41#include <algorithm> 42 43struct regset; 44 45/* This file implements the SPARC 32-bit ABI as defined by the section 46 "Low-Level System Information" of the SPARC Compliance Definition 47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD 48 lists changes with respect to the original 32-bit psABI as defined 49 in the "System V ABI, SPARC Processor Supplement". 50 51 Note that if we talk about SunOS, we mean SunOS 4.x, which was 52 BSD-based, which is sometimes (retroactively?) referred to as 53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and 54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 55 suffering from severe version number inflation). Solaris 2.x is 56 also known as SunOS 5.x, since that's what uname(1) says. Solaris 57 2.x is SVR4-based. */ 58 59/* Please use the sparc32_-prefix for 32-bit specific code, the 60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for 61 code that can handle both. The 64-bit specific code lives in 62 sparc64-tdep.c; don't add any here. */ 63 64/* The SPARC Floating-Point Quad-Precision format is similar to 65 big-endian IA-64 Quad-Precision format. */ 66#define floatformats_sparc_quad floatformats_ia64_quad 67 68/* The stack pointer is offset from the stack frame by a BIAS of 2047 69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC 70 hosts, so undefine it first. */ 71#undef BIAS 72#define BIAS 2047 73 74/* Macros to extract fields from SPARC instructions. */ 75#define X_OP(i) (((i) >> 30) & 0x3) 76#define X_RD(i) (((i) >> 25) & 0x1f) 77#define X_A(i) (((i) >> 29) & 1) 78#define X_COND(i) (((i) >> 25) & 0xf) 79#define X_OP2(i) (((i) >> 22) & 0x7) 80#define X_IMM22(i) ((i) & 0x3fffff) 81#define X_OP3(i) (((i) >> 19) & 0x3f) 82#define X_RS1(i) (((i) >> 14) & 0x1f) 83#define X_RS2(i) ((i) & 0x1f) 84#define X_I(i) (((i) >> 13) & 1) 85/* Sign extension macros. */ 86#define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) 87#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) 88#define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) 89#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) 90/* Macros to identify some instructions. */ 91/* RETURN (RETT in V8) */ 92#define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) 93 94/* Fetch the instruction at PC. Instructions are always big-endian 95 even if the processor operates in little-endian mode. */ 96 97unsigned long 98sparc_fetch_instruction (CORE_ADDR pc) 99{ 100 gdb_byte buf[4]; 101 unsigned long insn; 102 int i; 103 104 /* If we can't read the instruction at PC, return zero. */ 105 if (target_read_memory (pc, buf, sizeof (buf))) 106 return 0; 107 108 insn = 0; 109 for (i = 0; i < sizeof (buf); i++) 110 insn = (insn << 8) | buf[i]; 111 return insn; 112} 113 114 115/* Return non-zero if the instruction corresponding to PC is an "unimp" 116 instruction. */ 117 118static int 119sparc_is_unimp_insn (CORE_ADDR pc) 120{ 121 const unsigned long insn = sparc_fetch_instruction (pc); 122 123 return ((insn & 0xc1c00000) == 0); 124} 125 126/* Return non-zero if the instruction corresponding to PC is an 127 "annulled" branch, i.e. the annul bit is set. */ 128 129int 130sparc_is_annulled_branch_insn (CORE_ADDR pc) 131{ 132 /* The branch instructions featuring an annul bit can be identified 133 by the following bit patterns: 134 135 OP=0 136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc). 137 OP2=2: Branch on Integer Condition Codes (Bcc). 138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc). 139 OP2=6: Branch on FP Condition Codes (FBcc). 140 OP2=3 && Bit28=0: 141 Branch on Integer Register with Prediction (BPr). 142 143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8 144 coprocessor branch instructions (Op2=7). */ 145 146 const unsigned long insn = sparc_fetch_instruction (pc); 147 const unsigned op2 = X_OP2 (insn); 148 149 if ((X_OP (insn) == 0) 150 && ((op2 == 1) || (op2 == 2) || (op2 == 5) || (op2 == 6) 151 || ((op2 == 3) && ((insn & 0x10000000) == 0)))) 152 return X_A (insn); 153 else 154 return 0; 155} 156 157/* OpenBSD/sparc includes StackGhost, which according to the author's 158 website http://stackghost.cerias.purdue.edu "... transparently and 159 automatically protects applications' stack frames; more 160 specifically, it guards the return pointers. The protection 161 mechanisms require no application source or binary modification and 162 imposes only a negligible performance penalty." 163 164 The same website provides the following description of how 165 StackGhost works: 166 167 "StackGhost interfaces with the kernel trap handler that would 168 normally write out registers to the stack and the handler that 169 would read them back in. By XORing a cookie into the 170 return-address saved in the user stack when it is actually written 171 to the stack, and then XOR it out when the return-address is pulled 172 from the stack, StackGhost can cause attacker corrupted return 173 pointers to behave in a manner the attacker cannot predict. 174 StackGhost can also use several unused bits in the return pointer 175 to detect a smashed return pointer and abort the process." 176 177 For GDB this means that whenever we're reading %i7 from a stack 178 frame's window save area, we'll have to XOR the cookie. 179 180 More information on StackGuard can be found on in: 181 182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated 183 Stack Protection." 2001. Published in USENIX Security Symposium 184 '01. */ 185 186/* Fetch StackGhost Per-Process XOR cookie. */ 187 188ULONGEST 189sparc_fetch_wcookie (struct gdbarch *gdbarch) 190{ 191 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 192 struct target_ops *ops = current_top_target (); 193 gdb_byte buf[8]; 194 int len; 195 196 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); 197 if (len == -1) 198 return 0; 199 200 /* We should have either an 32-bit or an 64-bit cookie. */ 201 gdb_assert (len == 4 || len == 8); 202 203 return extract_unsigned_integer (buf, len, byte_order); 204} 205 206 207/* The functions on this page are intended to be used to classify 208 function arguments. */ 209 210/* Check whether TYPE is "Integral or Pointer". */ 211 212static int 213sparc_integral_or_pointer_p (const struct type *type) 214{ 215 int len = TYPE_LENGTH (type); 216 217 switch (type->code ()) 218 { 219 case TYPE_CODE_INT: 220 case TYPE_CODE_BOOL: 221 case TYPE_CODE_CHAR: 222 case TYPE_CODE_ENUM: 223 case TYPE_CODE_RANGE: 224 /* We have byte, half-word, word and extended-word/doubleword 225 integral types. The doubleword is an extension to the 226 original 32-bit ABI by the SCD 2.4.x. */ 227 return (len == 1 || len == 2 || len == 4 || len == 8); 228 case TYPE_CODE_PTR: 229 case TYPE_CODE_REF: 230 case TYPE_CODE_RVALUE_REF: 231 /* Allow either 32-bit or 64-bit pointers. */ 232 return (len == 4 || len == 8); 233 default: 234 break; 235 } 236 237 return 0; 238} 239 240/* Check whether TYPE is "Floating". */ 241 242static int 243sparc_floating_p (const struct type *type) 244{ 245 switch (type->code ()) 246 { 247 case TYPE_CODE_FLT: 248 { 249 int len = TYPE_LENGTH (type); 250 return (len == 4 || len == 8 || len == 16); 251 } 252 default: 253 break; 254 } 255 256 return 0; 257} 258 259/* Check whether TYPE is "Complex Floating". */ 260 261static int 262sparc_complex_floating_p (const struct type *type) 263{ 264 switch (type->code ()) 265 { 266 case TYPE_CODE_COMPLEX: 267 { 268 int len = TYPE_LENGTH (type); 269 return (len == 8 || len == 16 || len == 32); 270 } 271 default: 272 break; 273 } 274 275 return 0; 276} 277 278/* Check whether TYPE is "Structure or Union". 279 280 In terms of Ada subprogram calls, arrays are treated the same as 281 struct and union types. So this function also returns non-zero 282 for array types. */ 283 284static int 285sparc_structure_or_union_p (const struct type *type) 286{ 287 switch (type->code ()) 288 { 289 case TYPE_CODE_STRUCT: 290 case TYPE_CODE_UNION: 291 case TYPE_CODE_ARRAY: 292 return 1; 293 default: 294 break; 295 } 296 297 return 0; 298} 299 300/* Return true if TYPE is returned by memory, false if returned by 301 register. */ 302 303static bool 304sparc_structure_return_p (const struct type *type) 305{ 306 if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) 307 { 308 /* Float vectors are always returned by memory. */ 309 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) 310 return true; 311 /* Integer vectors are returned by memory if the vector size 312 is greater than 8 bytes long. */ 313 return (TYPE_LENGTH (type) > 8); 314 } 315 316 if (sparc_floating_p (type)) 317 { 318 /* Floating point types are passed by register for size 4 and 319 8 bytes, and by memory for size 16 bytes. */ 320 return (TYPE_LENGTH (type) == 16); 321 } 322 323 /* Other than that, only aggregates of all sizes get returned by 324 memory. */ 325 return sparc_structure_or_union_p (type); 326} 327 328/* Return true if arguments of the given TYPE are passed by 329 memory; false if returned by register. */ 330 331static bool 332sparc_arg_by_memory_p (const struct type *type) 333{ 334 if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type)) 335 { 336 /* Float vectors are always passed by memory. */ 337 if (sparc_floating_p (check_typedef (TYPE_TARGET_TYPE (type)))) 338 return true; 339 /* Integer vectors are passed by memory if the vector size 340 is greater than 8 bytes long. */ 341 return (TYPE_LENGTH (type) > 8); 342 } 343 344 /* Floats are passed by register for size 4 and 8 bytes, and by memory 345 for size 16 bytes. */ 346 if (sparc_floating_p (type)) 347 return (TYPE_LENGTH (type) == 16); 348 349 /* Complex floats and aggregates of all sizes are passed by memory. */ 350 if (sparc_complex_floating_p (type) || sparc_structure_or_union_p (type)) 351 return true; 352 353 /* Everything else gets passed by register. */ 354 return false; 355} 356 357/* Register information. */ 358#define SPARC32_FPU_REGISTERS \ 359 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 360 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 361 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ 362 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 363#define SPARC32_CP0_REGISTERS \ 364 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" 365 366static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; 367static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; 368static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; 369 370static const char *sparc32_register_names[] = 371{ 372 SPARC_CORE_REGISTERS, 373 SPARC32_FPU_REGISTERS, 374 SPARC32_CP0_REGISTERS 375}; 376 377/* Total number of registers. */ 378#define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) 379 380/* We provide the aliases %d0..%d30 for the floating registers as 381 "psuedo" registers. */ 382 383static const char *sparc32_pseudo_register_names[] = 384{ 385 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", 386 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" 387}; 388 389/* Total number of pseudo registers. */ 390#define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) 391 392/* Return the name of pseudo register REGNUM. */ 393 394static const char * 395sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 396{ 397 regnum -= gdbarch_num_regs (gdbarch); 398 399 if (regnum < SPARC32_NUM_PSEUDO_REGS) 400 return sparc32_pseudo_register_names[regnum]; 401 402 internal_error (__FILE__, __LINE__, 403 _("sparc32_pseudo_register_name: bad register number %d"), 404 regnum); 405} 406 407/* Return the name of register REGNUM. */ 408 409static const char * 410sparc32_register_name (struct gdbarch *gdbarch, int regnum) 411{ 412 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 413 return tdesc_register_name (gdbarch, regnum); 414 415 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) 416 return sparc32_register_names[regnum]; 417 418 return sparc32_pseudo_register_name (gdbarch, regnum); 419} 420 421/* Construct types for ISA-specific registers. */ 422 423static struct type * 424sparc_psr_type (struct gdbarch *gdbarch) 425{ 426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 427 428 if (!tdep->sparc_psr_type) 429 { 430 struct type *type; 431 432 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 32); 433 append_flags_type_flag (type, 5, "ET"); 434 append_flags_type_flag (type, 6, "PS"); 435 append_flags_type_flag (type, 7, "S"); 436 append_flags_type_flag (type, 12, "EF"); 437 append_flags_type_flag (type, 13, "EC"); 438 439 tdep->sparc_psr_type = type; 440 } 441 442 return tdep->sparc_psr_type; 443} 444 445static struct type * 446sparc_fsr_type (struct gdbarch *gdbarch) 447{ 448 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 449 450 if (!tdep->sparc_fsr_type) 451 { 452 struct type *type; 453 454 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 32); 455 append_flags_type_flag (type, 0, "NXA"); 456 append_flags_type_flag (type, 1, "DZA"); 457 append_flags_type_flag (type, 2, "UFA"); 458 append_flags_type_flag (type, 3, "OFA"); 459 append_flags_type_flag (type, 4, "NVA"); 460 append_flags_type_flag (type, 5, "NXC"); 461 append_flags_type_flag (type, 6, "DZC"); 462 append_flags_type_flag (type, 7, "UFC"); 463 append_flags_type_flag (type, 8, "OFC"); 464 append_flags_type_flag (type, 9, "NVC"); 465 append_flags_type_flag (type, 22, "NS"); 466 append_flags_type_flag (type, 23, "NXM"); 467 append_flags_type_flag (type, 24, "DZM"); 468 append_flags_type_flag (type, 25, "UFM"); 469 append_flags_type_flag (type, 26, "OFM"); 470 append_flags_type_flag (type, 27, "NVM"); 471 472 tdep->sparc_fsr_type = type; 473 } 474 475 return tdep->sparc_fsr_type; 476} 477 478/* Return the GDB type object for the "standard" data type of data in 479 pseudo register REGNUM. */ 480 481static struct type * 482sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 483{ 484 regnum -= gdbarch_num_regs (gdbarch); 485 486 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) 487 return builtin_type (gdbarch)->builtin_double; 488 489 internal_error (__FILE__, __LINE__, 490 _("sparc32_pseudo_register_type: bad register number %d"), 491 regnum); 492} 493 494/* Return the GDB type object for the "standard" data type of data in 495 register REGNUM. */ 496 497static struct type * 498sparc32_register_type (struct gdbarch *gdbarch, int regnum) 499{ 500 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 501 return tdesc_register_type (gdbarch, regnum); 502 503 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) 504 return builtin_type (gdbarch)->builtin_float; 505 506 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) 507 return builtin_type (gdbarch)->builtin_data_ptr; 508 509 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 510 return builtin_type (gdbarch)->builtin_func_ptr; 511 512 if (regnum == SPARC32_PSR_REGNUM) 513 return sparc_psr_type (gdbarch); 514 515 if (regnum == SPARC32_FSR_REGNUM) 516 return sparc_fsr_type (gdbarch); 517 518 if (regnum >= gdbarch_num_regs (gdbarch)) 519 return sparc32_pseudo_register_type (gdbarch, regnum); 520 521 return builtin_type (gdbarch)->builtin_int32; 522} 523 524static enum register_status 525sparc32_pseudo_register_read (struct gdbarch *gdbarch, 526 readable_regcache *regcache, 527 int regnum, gdb_byte *buf) 528{ 529 enum register_status status; 530 531 regnum -= gdbarch_num_regs (gdbarch); 532 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 533 534 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 535 status = regcache->raw_read (regnum, buf); 536 if (status == REG_VALID) 537 status = regcache->raw_read (regnum + 1, buf + 4); 538 return status; 539} 540 541static void 542sparc32_pseudo_register_write (struct gdbarch *gdbarch, 543 struct regcache *regcache, 544 int regnum, const gdb_byte *buf) 545{ 546 regnum -= gdbarch_num_regs (gdbarch); 547 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); 548 549 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); 550 regcache->raw_write (regnum, buf); 551 regcache->raw_write (regnum + 1, buf + 4); 552} 553 554/* Implement the stack_frame_destroyed_p gdbarch method. */ 555 556int 557sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 558{ 559 /* This function must return true if we are one instruction after an 560 instruction that destroyed the stack frame of the current 561 function. The SPARC instructions used to restore the callers 562 stack frame are RESTORE and RETURN/RETT. 563 564 Of these RETURN/RETT is a branch instruction and thus we return 565 true if we are in its delay slot. 566 567 RESTORE is almost always found in the delay slot of a branch 568 instruction that transfers control to the caller, such as JMPL. 569 Thus the next instruction is in the caller frame and we don't 570 need to do anything about it. */ 571 572 unsigned int insn = sparc_fetch_instruction (pc - 4); 573 574 return X_RETTURN (insn); 575} 576 577 578static CORE_ADDR 579sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) 580{ 581 /* The ABI requires double-word alignment. */ 582 return address & ~0x7; 583} 584 585static CORE_ADDR 586sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 587 CORE_ADDR funcaddr, 588 struct value **args, int nargs, 589 struct type *value_type, 590 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 591 struct regcache *regcache) 592{ 593 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 594 595 *bp_addr = sp - 4; 596 *real_pc = funcaddr; 597 598 if (using_struct_return (gdbarch, NULL, value_type)) 599 { 600 gdb_byte buf[4]; 601 602 /* This is an UNIMP instruction. */ 603 store_unsigned_integer (buf, 4, byte_order, 604 TYPE_LENGTH (value_type) & 0x1fff); 605 write_memory (sp - 8, buf, 4); 606 return sp - 8; 607 } 608 609 return sp - 4; 610} 611 612static CORE_ADDR 613sparc32_store_arguments (struct regcache *regcache, int nargs, 614 struct value **args, CORE_ADDR sp, 615 function_call_return_method return_method, 616 CORE_ADDR struct_addr) 617{ 618 struct gdbarch *gdbarch = regcache->arch (); 619 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 620 /* Number of words in the "parameter array". */ 621 int num_elements = 0; 622 int element = 0; 623 int i; 624 625 for (i = 0; i < nargs; i++) 626 { 627 struct type *type = value_type (args[i]); 628 int len = TYPE_LENGTH (type); 629 630 if (sparc_arg_by_memory_p (type)) 631 { 632 /* Structure, Union and Quad-Precision Arguments. */ 633 sp -= len; 634 635 /* Use doubleword alignment for these values. That's always 636 correct, and wasting a few bytes shouldn't be a problem. */ 637 sp &= ~0x7; 638 639 write_memory (sp, value_contents (args[i]), len); 640 args[i] = value_from_pointer (lookup_pointer_type (type), sp); 641 num_elements++; 642 } 643 else if (sparc_floating_p (type)) 644 { 645 /* Floating arguments. */ 646 gdb_assert (len == 4 || len == 8); 647 num_elements += (len / 4); 648 } 649 else 650 { 651 /* Arguments passed via the General Purpose Registers. */ 652 num_elements += ((len + 3) / 4); 653 } 654 } 655 656 /* Always allocate at least six words. */ 657 sp -= std::max (6, num_elements) * 4; 658 659 /* The psABI says that "Software convention requires space for the 660 struct/union return value pointer, even if the word is unused." */ 661 sp -= 4; 662 663 /* The psABI says that "Although software convention and the 664 operating system require every stack frame to be doubleword 665 aligned." */ 666 sp &= ~0x7; 667 668 for (i = 0; i < nargs; i++) 669 { 670 const bfd_byte *valbuf = value_contents (args[i]); 671 struct type *type = value_type (args[i]); 672 int len = TYPE_LENGTH (type); 673 gdb_byte buf[4]; 674 675 if (len < 4) 676 { 677 memset (buf, 0, 4 - len); 678 memcpy (buf + 4 - len, valbuf, len); 679 valbuf = buf; 680 len = 4; 681 } 682 683 gdb_assert (len == 4 || len == 8); 684 685 if (element < 6) 686 { 687 int regnum = SPARC_O0_REGNUM + element; 688 689 regcache->cooked_write (regnum, valbuf); 690 if (len > 4 && element < 5) 691 regcache->cooked_write (regnum + 1, valbuf + 4); 692 } 693 694 /* Always store the argument in memory. */ 695 write_memory (sp + 4 + element * 4, valbuf, len); 696 element += len / 4; 697 } 698 699 gdb_assert (element == num_elements); 700 701 if (return_method == return_method_struct) 702 { 703 gdb_byte buf[4]; 704 705 store_unsigned_integer (buf, 4, byte_order, struct_addr); 706 write_memory (sp, buf, 4); 707 } 708 709 return sp; 710} 711 712static CORE_ADDR 713sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 714 struct regcache *regcache, CORE_ADDR bp_addr, 715 int nargs, struct value **args, CORE_ADDR sp, 716 function_call_return_method return_method, 717 CORE_ADDR struct_addr) 718{ 719 CORE_ADDR call_pc = (return_method == return_method_struct 720 ? (bp_addr - 12) : (bp_addr - 8)); 721 722 /* Set return address. */ 723 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); 724 725 /* Set up function arguments. */ 726 sp = sparc32_store_arguments (regcache, nargs, args, sp, return_method, 727 struct_addr); 728 729 /* Allocate the 16-word window save area. */ 730 sp -= 16 * 4; 731 732 /* Stack should be doubleword aligned at this point. */ 733 gdb_assert (sp % 8 == 0); 734 735 /* Finally, update the stack pointer. */ 736 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); 737 738 return sp; 739} 740 741 742/* Use the program counter to determine the contents and size of a 743 breakpoint instruction. Return a pointer to a string of bytes that 744 encode a breakpoint instruction, store the length of the string in 745 *LEN and optionally adjust *PC to point to the correct memory 746 location for inserting the breakpoint. */ 747constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; 748 749typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; 750 751 752/* Allocate and initialize a frame cache. */ 753 754static struct sparc_frame_cache * 755sparc_alloc_frame_cache (void) 756{ 757 struct sparc_frame_cache *cache; 758 759 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); 760 761 /* Base address. */ 762 cache->base = 0; 763 cache->pc = 0; 764 765 /* Frameless until proven otherwise. */ 766 cache->frameless_p = 1; 767 cache->frame_offset = 0; 768 cache->saved_regs_mask = 0; 769 cache->copied_regs_mask = 0; 770 cache->struct_return_p = 0; 771 772 return cache; 773} 774 775/* GCC generates several well-known sequences of instructions at the begining 776 of each function prologue when compiling with -fstack-check. If one of 777 such sequences starts at START_PC, then return the address of the 778 instruction immediately past this sequence. Otherwise, return START_PC. */ 779 780static CORE_ADDR 781sparc_skip_stack_check (const CORE_ADDR start_pc) 782{ 783 CORE_ADDR pc = start_pc; 784 unsigned long insn; 785 int probing_loop = 0; 786 787 /* With GCC, all stack checking sequences begin with the same two 788 instructions, plus an optional one in the case of a probing loop: 789 790 sethi <some immediate>, %g1 791 sub %sp, %g1, %g1 792 793 or: 794 795 sethi <some immediate>, %g1 796 sethi <some immediate>, %g4 797 sub %sp, %g1, %g1 798 799 or: 800 801 sethi <some immediate>, %g1 802 sub %sp, %g1, %g1 803 sethi <some immediate>, %g4 804 805 If the optional instruction is found (setting g4), assume that a 806 probing loop will follow. */ 807 808 /* sethi <some immediate>, %g1 */ 809 insn = sparc_fetch_instruction (pc); 810 pc = pc + 4; 811 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) 812 return start_pc; 813 814 /* optional: sethi <some immediate>, %g4 */ 815 insn = sparc_fetch_instruction (pc); 816 pc = pc + 4; 817 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 818 { 819 probing_loop = 1; 820 insn = sparc_fetch_instruction (pc); 821 pc = pc + 4; 822 } 823 824 /* sub %sp, %g1, %g1 */ 825 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 826 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) 827 return start_pc; 828 829 insn = sparc_fetch_instruction (pc); 830 pc = pc + 4; 831 832 /* optional: sethi <some immediate>, %g4 */ 833 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) 834 { 835 probing_loop = 1; 836 insn = sparc_fetch_instruction (pc); 837 pc = pc + 4; 838 } 839 840 /* First possible sequence: 841 [first two instructions above] 842 clr [%g1 - some immediate] */ 843 844 /* clr [%g1 - some immediate] */ 845 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 846 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 847 { 848 /* Valid stack-check sequence, return the new PC. */ 849 return pc; 850 } 851 852 /* Second possible sequence: A small number of probes. 853 [first two instructions above] 854 clr [%g1] 855 add %g1, -<some immediate>, %g1 856 clr [%g1] 857 [repeat the two instructions above any (small) number of times] 858 clr [%g1 - some immediate] */ 859 860 /* clr [%g1] */ 861 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 862 && X_RS1 (insn) == 1 && X_RD (insn) == 0) 863 { 864 while (1) 865 { 866 /* add %g1, -<some immediate>, %g1 */ 867 insn = sparc_fetch_instruction (pc); 868 pc = pc + 4; 869 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 870 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 871 break; 872 873 /* clr [%g1] */ 874 insn = sparc_fetch_instruction (pc); 875 pc = pc + 4; 876 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) 877 && X_RD (insn) == 0 && X_RS1 (insn) == 1)) 878 return start_pc; 879 } 880 881 /* clr [%g1 - some immediate] */ 882 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 883 && X_RS1 (insn) == 1 && X_RD (insn) == 0)) 884 return start_pc; 885 886 /* We found a valid stack-check sequence, return the new PC. */ 887 return pc; 888 } 889 890 /* Third sequence: A probing loop. 891 [first three instructions above] 892 sub %g1, %g4, %g4 893 cmp %g1, %g4 894 be <disp> 895 add %g1, -<some immediate>, %g1 896 ba <disp> 897 clr [%g1] 898 899 And an optional last probe for the remainder: 900 901 clr [%g4 - some immediate] */ 902 903 if (probing_loop) 904 { 905 /* sub %g1, %g4, %g4 */ 906 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) 907 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 908 return start_pc; 909 910 /* cmp %g1, %g4 */ 911 insn = sparc_fetch_instruction (pc); 912 pc = pc + 4; 913 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) 914 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) 915 return start_pc; 916 917 /* be <disp> */ 918 insn = sparc_fetch_instruction (pc); 919 pc = pc + 4; 920 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) 921 return start_pc; 922 923 /* add %g1, -<some immediate>, %g1 */ 924 insn = sparc_fetch_instruction (pc); 925 pc = pc + 4; 926 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) 927 && X_RS1 (insn) == 1 && X_RD (insn) == 1)) 928 return start_pc; 929 930 /* ba <disp> */ 931 insn = sparc_fetch_instruction (pc); 932 pc = pc + 4; 933 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) 934 return start_pc; 935 936 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ 937 insn = sparc_fetch_instruction (pc); 938 pc = pc + 4; 939 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 940 && X_RD (insn) == 0 && X_RS1 (insn) == 1 941 && (!X_I(insn) || X_SIMM13 (insn) == 0))) 942 return start_pc; 943 944 /* We found a valid stack-check sequence, return the new PC. */ 945 946 /* optional: clr [%g4 - some immediate] */ 947 insn = sparc_fetch_instruction (pc); 948 pc = pc + 4; 949 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) 950 && X_RS1 (insn) == 4 && X_RD (insn) == 0)) 951 return pc - 4; 952 else 953 return pc; 954 } 955 956 /* No stack check code in our prologue, return the start_pc. */ 957 return start_pc; 958} 959 960/* Record the effect of a SAVE instruction on CACHE. */ 961 962void 963sparc_record_save_insn (struct sparc_frame_cache *cache) 964{ 965 /* The frame is set up. */ 966 cache->frameless_p = 0; 967 968 /* The frame pointer contains the CFA. */ 969 cache->frame_offset = 0; 970 971 /* The `local' and `in' registers are all saved. */ 972 cache->saved_regs_mask = 0xffff; 973 974 /* The `out' registers are all renamed. */ 975 cache->copied_regs_mask = 0xff; 976} 977 978/* Do a full analysis of the prologue at PC and update CACHE accordingly. 979 Bail out early if CURRENT_PC is reached. Return the address where 980 the analysis stopped. 981 982 We handle both the traditional register window model and the single 983 register window (aka flat) model. */ 984 985CORE_ADDR 986sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, 987 CORE_ADDR current_pc, struct sparc_frame_cache *cache) 988{ 989 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 990 unsigned long insn; 991 int offset = 0; 992 int dest = -1; 993 994 pc = sparc_skip_stack_check (pc); 995 996 if (current_pc <= pc) 997 return current_pc; 998 999 /* We have to handle to "Procedure Linkage Table" (PLT) special. On 1000 SPARC the linker usually defines a symbol (typically 1001 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. 1002 This symbol makes us end up here with PC pointing at the start of 1003 the PLT and CURRENT_PC probably pointing at a PLT entry. If we 1004 would do our normal prologue analysis, we would probably conclude 1005 that we've got a frame when in reality we don't, since the 1006 dynamic linker patches up the first PLT with some code that 1007 starts with a SAVE instruction. Patch up PC such that it points 1008 at the start of our PLT entry. */ 1009 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc)) 1010 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); 1011 1012 insn = sparc_fetch_instruction (pc); 1013 1014 /* Recognize store insns and record their sources. */ 1015 while (X_OP (insn) == 3 1016 && (X_OP3 (insn) == 0x4 /* stw */ 1017 || X_OP3 (insn) == 0x7 /* std */ 1018 || X_OP3 (insn) == 0xe) /* stx */ 1019 && X_RS1 (insn) == SPARC_SP_REGNUM) 1020 { 1021 int regnum = X_RD (insn); 1022 1023 /* Recognize stores into the corresponding stack slots. */ 1024 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1025 && ((X_I (insn) 1026 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe 1027 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS 1028 : (regnum - SPARC_L0_REGNUM) * 4)) 1029 || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) 1030 { 1031 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); 1032 if (X_OP3 (insn) == 0x7) 1033 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); 1034 } 1035 1036 offset += 4; 1037 1038 insn = sparc_fetch_instruction (pc + offset); 1039 } 1040 1041 /* Recognize a SETHI insn and record its destination. */ 1042 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) 1043 { 1044 dest = X_RD (insn); 1045 offset += 4; 1046 1047 insn = sparc_fetch_instruction (pc + offset); 1048 } 1049 1050 /* Allow for an arithmetic operation on DEST or %g1. */ 1051 if (X_OP (insn) == 2 && X_I (insn) 1052 && (X_RD (insn) == 1 || X_RD (insn) == dest)) 1053 { 1054 offset += 4; 1055 1056 insn = sparc_fetch_instruction (pc + offset); 1057 } 1058 1059 /* Check for the SAVE instruction that sets up the frame. */ 1060 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) 1061 { 1062 sparc_record_save_insn (cache); 1063 offset += 4; 1064 return pc + offset; 1065 } 1066 1067 /* Check for an arithmetic operation on %sp. */ 1068 if (X_OP (insn) == 2 1069 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1070 && X_RS1 (insn) == SPARC_SP_REGNUM 1071 && X_RD (insn) == SPARC_SP_REGNUM) 1072 { 1073 if (X_I (insn)) 1074 { 1075 cache->frame_offset = X_SIMM13 (insn); 1076 if (X_OP3 (insn) == 0) 1077 cache->frame_offset = -cache->frame_offset; 1078 } 1079 offset += 4; 1080 1081 insn = sparc_fetch_instruction (pc + offset); 1082 1083 /* Check for an arithmetic operation that sets up the frame. */ 1084 if (X_OP (insn) == 2 1085 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) 1086 && X_RS1 (insn) == SPARC_SP_REGNUM 1087 && X_RD (insn) == SPARC_FP_REGNUM) 1088 { 1089 cache->frameless_p = 0; 1090 cache->frame_offset = 0; 1091 /* We could check that the amount subtracted to %sp above is the 1092 same as the one added here, but this seems superfluous. */ 1093 cache->copied_regs_mask |= 0x40; 1094 offset += 4; 1095 1096 insn = sparc_fetch_instruction (pc + offset); 1097 } 1098 1099 /* Check for a move (or) operation that copies the return register. */ 1100 if (X_OP (insn) == 2 1101 && X_OP3 (insn) == 0x2 1102 && !X_I (insn) 1103 && X_RS1 (insn) == SPARC_G0_REGNUM 1104 && X_RS2 (insn) == SPARC_O7_REGNUM 1105 && X_RD (insn) == SPARC_I7_REGNUM) 1106 { 1107 cache->copied_regs_mask |= 0x80; 1108 offset += 4; 1109 } 1110 1111 return pc + offset; 1112 } 1113 1114 return pc; 1115} 1116 1117/* Return PC of first real instruction of the function starting at 1118 START_PC. */ 1119 1120static CORE_ADDR 1121sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1122{ 1123 struct symtab_and_line sal; 1124 CORE_ADDR func_start, func_end; 1125 struct sparc_frame_cache cache; 1126 1127 /* This is the preferred method, find the end of the prologue by 1128 using the debugging information. */ 1129 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) 1130 { 1131 sal = find_pc_line (func_start, 0); 1132 1133 if (sal.end < func_end 1134 && start_pc <= sal.end) 1135 return sal.end; 1136 } 1137 1138 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); 1139 1140 /* The psABI says that "Although the first 6 words of arguments 1141 reside in registers, the standard stack frame reserves space for 1142 them.". It also suggests that a function may use that space to 1143 "write incoming arguments 0 to 5" into that space, and that's 1144 indeed what GCC seems to be doing. In that case GCC will 1145 generate debug information that points to the stack slots instead 1146 of the registers, so we should consider the instructions that 1147 write out these incoming arguments onto the stack. */ 1148 1149 while (1) 1150 { 1151 unsigned long insn = sparc_fetch_instruction (start_pc); 1152 1153 /* Recognize instructions that store incoming arguments into the 1154 corresponding stack slots. */ 1155 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 1156 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) 1157 { 1158 int regnum = X_RD (insn); 1159 1160 /* Case of arguments still in %o[0..5]. */ 1161 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM 1162 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) 1163 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) 1164 { 1165 start_pc += 4; 1166 continue; 1167 } 1168 1169 /* Case of arguments copied into %i[0..5]. */ 1170 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM 1171 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) 1172 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) 1173 { 1174 start_pc += 4; 1175 continue; 1176 } 1177 } 1178 1179 break; 1180 } 1181 1182 return start_pc; 1183} 1184 1185/* Normal frames. */ 1186 1187struct sparc_frame_cache * 1188sparc_frame_cache (struct frame_info *this_frame, void **this_cache) 1189{ 1190 struct sparc_frame_cache *cache; 1191 1192 if (*this_cache) 1193 return (struct sparc_frame_cache *) *this_cache; 1194 1195 cache = sparc_alloc_frame_cache (); 1196 *this_cache = cache; 1197 1198 cache->pc = get_frame_func (this_frame); 1199 if (cache->pc != 0) 1200 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, 1201 get_frame_pc (this_frame), cache); 1202 1203 if (cache->frameless_p) 1204 { 1205 /* This function is frameless, so %fp (%i6) holds the frame 1206 pointer for our calling frame. Use %sp (%o6) as this frame's 1207 base address. */ 1208 cache->base = 1209 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1210 } 1211 else 1212 { 1213 /* For normal frames, %fp (%i6) holds the frame pointer, the 1214 base address for the current stack frame. */ 1215 cache->base = 1216 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); 1217 } 1218 1219 cache->base += cache->frame_offset; 1220 1221 if (cache->base & 1) 1222 cache->base += BIAS; 1223 1224 return cache; 1225} 1226 1227static int 1228sparc32_struct_return_from_sym (struct symbol *sym) 1229{ 1230 struct type *type = check_typedef (SYMBOL_TYPE (sym)); 1231 enum type_code code = type->code (); 1232 1233 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) 1234 { 1235 type = check_typedef (TYPE_TARGET_TYPE (type)); 1236 if (sparc_structure_or_union_p (type) 1237 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) 1238 return 1; 1239 } 1240 1241 return 0; 1242} 1243 1244struct sparc_frame_cache * 1245sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) 1246{ 1247 struct sparc_frame_cache *cache; 1248 struct symbol *sym; 1249 1250 if (*this_cache) 1251 return (struct sparc_frame_cache *) *this_cache; 1252 1253 cache = sparc_frame_cache (this_frame, this_cache); 1254 1255 sym = find_pc_function (cache->pc); 1256 if (sym) 1257 { 1258 cache->struct_return_p = sparc32_struct_return_from_sym (sym); 1259 } 1260 else 1261 { 1262 /* There is no debugging information for this function to 1263 help us determine whether this function returns a struct 1264 or not. So we rely on another heuristic which is to check 1265 the instruction at the return address and see if this is 1266 an "unimp" instruction. If it is, then it is a struct-return 1267 function. */ 1268 CORE_ADDR pc; 1269 int regnum = 1270 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1271 1272 pc = get_frame_register_unsigned (this_frame, regnum) + 8; 1273 if (sparc_is_unimp_insn (pc)) 1274 cache->struct_return_p = 1; 1275 } 1276 1277 return cache; 1278} 1279 1280static void 1281sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, 1282 struct frame_id *this_id) 1283{ 1284 struct sparc_frame_cache *cache = 1285 sparc32_frame_cache (this_frame, this_cache); 1286 1287 /* This marks the outermost frame. */ 1288 if (cache->base == 0) 1289 return; 1290 1291 (*this_id) = frame_id_build (cache->base, cache->pc); 1292} 1293 1294static struct value * 1295sparc32_frame_prev_register (struct frame_info *this_frame, 1296 void **this_cache, int regnum) 1297{ 1298 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1299 struct sparc_frame_cache *cache = 1300 sparc32_frame_cache (this_frame, this_cache); 1301 1302 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) 1303 { 1304 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; 1305 1306 /* If this functions has a Structure, Union or Quad-Precision 1307 return value, we have to skip the UNIMP instruction that encodes 1308 the size of the structure. */ 1309 if (cache->struct_return_p) 1310 pc += 4; 1311 1312 regnum = 1313 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; 1314 pc += get_frame_register_unsigned (this_frame, regnum) + 8; 1315 return frame_unwind_got_constant (this_frame, regnum, pc); 1316 } 1317 1318 /* Handle StackGhost. */ 1319 { 1320 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1321 1322 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) 1323 { 1324 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1325 ULONGEST i7; 1326 1327 /* Read the value in from memory. */ 1328 i7 = get_frame_memory_unsigned (this_frame, addr, 4); 1329 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); 1330 } 1331 } 1332 1333 /* The previous frame's `local' and `in' registers may have been saved 1334 in the register save area. */ 1335 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM 1336 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) 1337 { 1338 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; 1339 1340 return frame_unwind_got_memory (this_frame, regnum, addr); 1341 } 1342 1343 /* The previous frame's `out' registers may be accessible as the current 1344 frame's `in' registers. */ 1345 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM 1346 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) 1347 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); 1348 1349 return frame_unwind_got_register (this_frame, regnum, regnum); 1350} 1351 1352static const struct frame_unwind sparc32_frame_unwind = 1353{ 1354 NORMAL_FRAME, 1355 default_frame_unwind_stop_reason, 1356 sparc32_frame_this_id, 1357 sparc32_frame_prev_register, 1358 NULL, 1359 default_frame_sniffer 1360}; 1361 1362 1363static CORE_ADDR 1364sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) 1365{ 1366 struct sparc_frame_cache *cache = 1367 sparc32_frame_cache (this_frame, this_cache); 1368 1369 return cache->base; 1370} 1371 1372static const struct frame_base sparc32_frame_base = 1373{ 1374 &sparc32_frame_unwind, 1375 sparc32_frame_base_address, 1376 sparc32_frame_base_address, 1377 sparc32_frame_base_address 1378}; 1379 1380static struct frame_id 1381sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1382{ 1383 CORE_ADDR sp; 1384 1385 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); 1386 if (sp & 1) 1387 sp += BIAS; 1388 return frame_id_build (sp, get_frame_pc (this_frame)); 1389} 1390 1391 1392/* Extract a function return value of TYPE from REGCACHE, and copy 1393 that into VALBUF. */ 1394 1395static void 1396sparc32_extract_return_value (struct type *type, struct regcache *regcache, 1397 gdb_byte *valbuf) 1398{ 1399 int len = TYPE_LENGTH (type); 1400 gdb_byte buf[32]; 1401 1402 gdb_assert (!sparc_structure_return_p (type)); 1403 1404 if (sparc_floating_p (type) || sparc_complex_floating_p (type) 1405 || type->code () == TYPE_CODE_ARRAY) 1406 { 1407 /* Floating return values. */ 1408 regcache->cooked_read (SPARC_F0_REGNUM, buf); 1409 if (len > 4) 1410 regcache->cooked_read (SPARC_F1_REGNUM, buf + 4); 1411 if (len > 8) 1412 { 1413 regcache->cooked_read (SPARC_F2_REGNUM, buf + 8); 1414 regcache->cooked_read (SPARC_F3_REGNUM, buf + 12); 1415 } 1416 if (len > 16) 1417 { 1418 regcache->cooked_read (SPARC_F4_REGNUM, buf + 16); 1419 regcache->cooked_read (SPARC_F5_REGNUM, buf + 20); 1420 regcache->cooked_read (SPARC_F6_REGNUM, buf + 24); 1421 regcache->cooked_read (SPARC_F7_REGNUM, buf + 28); 1422 } 1423 memcpy (valbuf, buf, len); 1424 } 1425 else 1426 { 1427 /* Integral and pointer return values. */ 1428 gdb_assert (sparc_integral_or_pointer_p (type)); 1429 1430 regcache->cooked_read (SPARC_O0_REGNUM, buf); 1431 if (len > 4) 1432 { 1433 regcache->cooked_read (SPARC_O1_REGNUM, buf + 4); 1434 gdb_assert (len == 8); 1435 memcpy (valbuf, buf, 8); 1436 } 1437 else 1438 { 1439 /* Just stripping off any unused bytes should preserve the 1440 signed-ness just fine. */ 1441 memcpy (valbuf, buf + 4 - len, len); 1442 } 1443 } 1444} 1445 1446/* Store the function return value of type TYPE from VALBUF into 1447 REGCACHE. */ 1448 1449static void 1450sparc32_store_return_value (struct type *type, struct regcache *regcache, 1451 const gdb_byte *valbuf) 1452{ 1453 int len = TYPE_LENGTH (type); 1454 gdb_byte buf[32]; 1455 1456 gdb_assert (!sparc_structure_return_p (type)); 1457 1458 if (sparc_floating_p (type) || sparc_complex_floating_p (type)) 1459 { 1460 /* Floating return values. */ 1461 memcpy (buf, valbuf, len); 1462 regcache->cooked_write (SPARC_F0_REGNUM, buf); 1463 if (len > 4) 1464 regcache->cooked_write (SPARC_F1_REGNUM, buf + 4); 1465 if (len > 8) 1466 { 1467 regcache->cooked_write (SPARC_F2_REGNUM, buf + 8); 1468 regcache->cooked_write (SPARC_F3_REGNUM, buf + 12); 1469 } 1470 if (len > 16) 1471 { 1472 regcache->cooked_write (SPARC_F4_REGNUM, buf + 16); 1473 regcache->cooked_write (SPARC_F5_REGNUM, buf + 20); 1474 regcache->cooked_write (SPARC_F6_REGNUM, buf + 24); 1475 regcache->cooked_write (SPARC_F7_REGNUM, buf + 28); 1476 } 1477 } 1478 else 1479 { 1480 /* Integral and pointer return values. */ 1481 gdb_assert (sparc_integral_or_pointer_p (type)); 1482 1483 if (len > 4) 1484 { 1485 gdb_assert (len == 8); 1486 memcpy (buf, valbuf, 8); 1487 regcache->cooked_write (SPARC_O1_REGNUM, buf + 4); 1488 } 1489 else 1490 { 1491 /* ??? Do we need to do any sign-extension here? */ 1492 memcpy (buf + 4 - len, valbuf, len); 1493 } 1494 regcache->cooked_write (SPARC_O0_REGNUM, buf); 1495 } 1496} 1497 1498static enum return_value_convention 1499sparc32_return_value (struct gdbarch *gdbarch, struct value *function, 1500 struct type *type, struct regcache *regcache, 1501 gdb_byte *readbuf, const gdb_byte *writebuf) 1502{ 1503 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1504 1505 /* The psABI says that "...every stack frame reserves the word at 1506 %fp+64. If a function returns a structure, union, or 1507 quad-precision value, this word should hold the address of the 1508 object into which the return value should be copied." This 1509 guarantees that we can always find the return value, not just 1510 before the function returns. */ 1511 1512 if (sparc_structure_return_p (type)) 1513 { 1514 ULONGEST sp; 1515 CORE_ADDR addr; 1516 1517 if (readbuf) 1518 { 1519 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1520 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1521 read_memory (addr, readbuf, TYPE_LENGTH (type)); 1522 } 1523 if (writebuf) 1524 { 1525 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 1526 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); 1527 write_memory (addr, writebuf, TYPE_LENGTH (type)); 1528 } 1529 1530 return RETURN_VALUE_ABI_PRESERVES_ADDRESS; 1531 } 1532 1533 if (readbuf) 1534 sparc32_extract_return_value (type, regcache, readbuf); 1535 if (writebuf) 1536 sparc32_store_return_value (type, regcache, writebuf); 1537 1538 return RETURN_VALUE_REGISTER_CONVENTION; 1539} 1540 1541static int 1542sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) 1543{ 1544 return (sparc_structure_or_union_p (type) 1545 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) 1546 || sparc_complex_floating_p (type)); 1547} 1548 1549static int 1550sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) 1551{ 1552 CORE_ADDR pc = get_frame_address_in_block (this_frame); 1553 struct symbol *sym = find_pc_function (pc); 1554 1555 if (sym) 1556 return sparc32_struct_return_from_sym (sym); 1557 return 0; 1558} 1559 1560static void 1561sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 1562 struct dwarf2_frame_state_reg *reg, 1563 struct frame_info *this_frame) 1564{ 1565 int off; 1566 1567 switch (regnum) 1568 { 1569 case SPARC_G0_REGNUM: 1570 /* Since %g0 is always zero, there is no point in saving it, and 1571 people will be inclined omit it from the CFI. Make sure we 1572 don't warn about that. */ 1573 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 1574 break; 1575 case SPARC_SP_REGNUM: 1576 reg->how = DWARF2_FRAME_REG_CFA; 1577 break; 1578 case SPARC32_PC_REGNUM: 1579 case SPARC32_NPC_REGNUM: 1580 reg->how = DWARF2_FRAME_REG_RA_OFFSET; 1581 off = 8; 1582 if (sparc32_dwarf2_struct_return_p (this_frame)) 1583 off += 4; 1584 if (regnum == SPARC32_NPC_REGNUM) 1585 off += 4; 1586 reg->loc.offset = off; 1587 break; 1588 } 1589} 1590 1591/* Implement the execute_dwarf_cfa_vendor_op method. */ 1592 1593static bool 1594sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, 1595 struct dwarf2_frame_state *fs) 1596{ 1597 /* Only DW_CFA_GNU_window_save is expected on SPARC. */ 1598 if (op != DW_CFA_GNU_window_save) 1599 return false; 1600 1601 uint64_t reg; 1602 int size = register_size (gdbarch, 0); 1603 1604 fs->regs.alloc_regs (32); 1605 for (reg = 8; reg < 16; reg++) 1606 { 1607 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_REG; 1608 fs->regs.reg[reg].loc.reg = reg + 16; 1609 } 1610 for (reg = 16; reg < 32; reg++) 1611 { 1612 fs->regs.reg[reg].how = DWARF2_FRAME_REG_SAVED_OFFSET; 1613 fs->regs.reg[reg].loc.offset = (reg - 16) * size; 1614 } 1615 1616 return true; 1617} 1618 1619 1620/* The SPARC Architecture doesn't have hardware single-step support, 1621 and most operating systems don't implement it either, so we provide 1622 software single-step mechanism. */ 1623 1624static CORE_ADDR 1625sparc_analyze_control_transfer (struct regcache *regcache, 1626 CORE_ADDR pc, CORE_ADDR *npc) 1627{ 1628 unsigned long insn = sparc_fetch_instruction (pc); 1629 int conditional_p = X_COND (insn) & 0x7; 1630 int branch_p = 0, fused_p = 0; 1631 long offset = 0; /* Must be signed for sign-extend. */ 1632 1633 if (X_OP (insn) == 0 && X_OP2 (insn) == 3) 1634 { 1635 if ((insn & 0x10000000) == 0) 1636 { 1637 /* Branch on Integer Register with Prediction (BPr). */ 1638 branch_p = 1; 1639 conditional_p = 1; 1640 } 1641 else 1642 { 1643 /* Compare and Branch */ 1644 branch_p = 1; 1645 fused_p = 1; 1646 offset = 4 * X_DISP10 (insn); 1647 } 1648 } 1649 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) 1650 { 1651 /* Branch on Floating-Point Condition Codes (FBfcc). */ 1652 branch_p = 1; 1653 offset = 4 * X_DISP22 (insn); 1654 } 1655 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) 1656 { 1657 /* Branch on Floating-Point Condition Codes with Prediction 1658 (FBPfcc). */ 1659 branch_p = 1; 1660 offset = 4 * X_DISP19 (insn); 1661 } 1662 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) 1663 { 1664 /* Branch on Integer Condition Codes (Bicc). */ 1665 branch_p = 1; 1666 offset = 4 * X_DISP22 (insn); 1667 } 1668 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) 1669 { 1670 /* Branch on Integer Condition Codes with Prediction (BPcc). */ 1671 branch_p = 1; 1672 offset = 4 * X_DISP19 (insn); 1673 } 1674 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) 1675 { 1676 struct frame_info *frame = get_current_frame (); 1677 1678 /* Trap instruction (TRAP). */ 1679 return gdbarch_tdep (regcache->arch ())->step_trap (frame, 1680 insn); 1681 } 1682 1683 /* FIXME: Handle DONE and RETRY instructions. */ 1684 1685 if (branch_p) 1686 { 1687 if (fused_p) 1688 { 1689 /* Fused compare-and-branch instructions are non-delayed, 1690 and do not have an annulling capability. So we need to 1691 always set a breakpoint on both the NPC and the branch 1692 target address. */ 1693 gdb_assert (offset != 0); 1694 return pc + offset; 1695 } 1696 else if (conditional_p) 1697 { 1698 /* For conditional branches, return nPC + 4 iff the annul 1699 bit is 1. */ 1700 return (X_A (insn) ? *npc + 4 : 0); 1701 } 1702 else 1703 { 1704 /* For unconditional branches, return the target if its 1705 specified condition is "always" and return nPC + 4 if the 1706 condition is "never". If the annul bit is 1, set *NPC to 1707 zero. */ 1708 if (X_COND (insn) == 0x0) 1709 pc = *npc, offset = 4; 1710 if (X_A (insn)) 1711 *npc = 0; 1712 1713 return pc + offset; 1714 } 1715 } 1716 1717 return 0; 1718} 1719 1720static CORE_ADDR 1721sparc_step_trap (struct frame_info *frame, unsigned long insn) 1722{ 1723 return 0; 1724} 1725 1726static std::vector<CORE_ADDR> 1727sparc_software_single_step (struct regcache *regcache) 1728{ 1729 struct gdbarch *arch = regcache->arch (); 1730 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 1731 CORE_ADDR npc, nnpc; 1732 1733 CORE_ADDR pc, orig_npc; 1734 std::vector<CORE_ADDR> next_pcs; 1735 1736 pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); 1737 orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); 1738 1739 /* Analyze the instruction at PC. */ 1740 nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); 1741 if (npc != 0) 1742 next_pcs.push_back (npc); 1743 1744 if (nnpc != 0) 1745 next_pcs.push_back (nnpc); 1746 1747 /* Assert that we have set at least one breakpoint, and that 1748 they're not set at the same spot - unless we're going 1749 from here straight to NULL, i.e. a call or jump to 0. */ 1750 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); 1751 gdb_assert (nnpc != npc || orig_npc == 0); 1752 1753 return next_pcs; 1754} 1755 1756static void 1757sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) 1758{ 1759 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); 1760 1761 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); 1762 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); 1763} 1764 1765 1766/* Iterate over core file register note sections. */ 1767 1768static void 1769sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, 1770 iterate_over_regset_sections_cb *cb, 1771 void *cb_data, 1772 const struct regcache *regcache) 1773{ 1774 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1775 1776 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, 1777 cb_data); 1778 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, 1779 NULL, cb_data); 1780} 1781 1782 1783static int 1784validate_tdesc_registers (const struct target_desc *tdesc, 1785 struct tdesc_arch_data *tdesc_data, 1786 const char *feature_name, 1787 const char *register_names[], 1788 unsigned int registers_num, 1789 unsigned int reg_start) 1790{ 1791 int valid_p = 1; 1792 const struct tdesc_feature *feature; 1793 1794 feature = tdesc_find_feature (tdesc, feature_name); 1795 if (feature == NULL) 1796 return 0; 1797 1798 for (unsigned int i = 0; i < registers_num; i++) 1799 valid_p &= tdesc_numbered_register (feature, tdesc_data, 1800 reg_start + i, 1801 register_names[i]); 1802 1803 return valid_p; 1804} 1805 1806static struct gdbarch * 1807sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1808{ 1809 struct gdbarch_tdep *tdep; 1810 const struct target_desc *tdesc = info.target_desc; 1811 struct gdbarch *gdbarch; 1812 int valid_p = 1; 1813 1814 /* If there is already a candidate, use it. */ 1815 arches = gdbarch_list_lookup_by_info (arches, &info); 1816 if (arches != NULL) 1817 return arches->gdbarch; 1818 1819 /* Allocate space for the new architecture. */ 1820 tdep = XCNEW (struct gdbarch_tdep); 1821 gdbarch = gdbarch_alloc (&info, tdep); 1822 1823 tdep->pc_regnum = SPARC32_PC_REGNUM; 1824 tdep->npc_regnum = SPARC32_NPC_REGNUM; 1825 tdep->step_trap = sparc_step_trap; 1826 tdep->fpu_register_names = sparc32_fpu_register_names; 1827 tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); 1828 tdep->cp0_register_names = sparc32_cp0_register_names; 1829 tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); 1830 1831 set_gdbarch_long_double_bit (gdbarch, 128); 1832 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); 1833 1834 set_gdbarch_wchar_bit (gdbarch, 16); 1835 set_gdbarch_wchar_signed (gdbarch, 1); 1836 1837 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); 1838 set_gdbarch_register_name (gdbarch, sparc32_register_name); 1839 set_gdbarch_register_type (gdbarch, sparc32_register_type); 1840 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); 1841 set_tdesc_pseudo_register_name (gdbarch, sparc32_pseudo_register_name); 1842 set_tdesc_pseudo_register_type (gdbarch, sparc32_pseudo_register_type); 1843 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); 1844 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); 1845 1846 /* Register numbers of various important registers. */ 1847 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ 1848 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ 1849 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ 1850 1851 /* Call dummy code. */ 1852 set_gdbarch_frame_align (gdbarch, sparc32_frame_align); 1853 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 1854 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); 1855 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); 1856 1857 set_gdbarch_return_value (gdbarch, sparc32_return_value); 1858 set_gdbarch_stabs_argument_has_addr 1859 (gdbarch, sparc32_stabs_argument_has_addr); 1860 1861 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); 1862 1863 /* Stack grows downward. */ 1864 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1865 1866 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 1867 sparc_breakpoint::kind_from_pc); 1868 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 1869 sparc_breakpoint::bp_from_kind); 1870 1871 set_gdbarch_frame_args_skip (gdbarch, 8); 1872 1873 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); 1874 set_gdbarch_write_pc (gdbarch, sparc_write_pc); 1875 1876 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); 1877 1878 frame_base_set_default (gdbarch, &sparc32_frame_base); 1879 1880 /* Hook in the DWARF CFI frame unwinder. */ 1881 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); 1882 /* Register DWARF vendor CFI handler. */ 1883 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, 1884 sparc_execute_dwarf_cfa_vendor_op); 1885 /* FIXME: kettenis/20050423: Don't enable the unwinder until the 1886 StackGhost issues have been resolved. */ 1887 1888 /* Hook in ABI-specific overrides, if they have been registered. */ 1889 gdbarch_init_osabi (info, gdbarch); 1890 1891 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); 1892 1893 if (tdesc_has_registers (tdesc)) 1894 { 1895 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc (); 1896 1897 /* Validate that the descriptor provides the mandatory registers 1898 and allocate their numbers. */ 1899 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1900 "org.gnu.gdb.sparc.cpu", 1901 sparc_core_register_names, 1902 ARRAY_SIZE (sparc_core_register_names), 1903 SPARC_G0_REGNUM); 1904 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1905 "org.gnu.gdb.sparc.fpu", 1906 tdep->fpu_register_names, 1907 tdep->fpu_registers_num, 1908 SPARC_F0_REGNUM); 1909 valid_p &= validate_tdesc_registers (tdesc, tdesc_data, 1910 "org.gnu.gdb.sparc.cp0", 1911 tdep->cp0_register_names, 1912 tdep->cp0_registers_num, 1913 SPARC_F0_REGNUM 1914 + tdep->fpu_registers_num); 1915 if (!valid_p) 1916 { 1917 tdesc_data_cleanup (tdesc_data); 1918 return NULL; 1919 } 1920 1921 /* Target description may have changed. */ 1922 info.tdesc_data = tdesc_data; 1923 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 1924 } 1925 1926 /* If we have register sets, enable the generic core file support. */ 1927 if (tdep->gregset) 1928 set_gdbarch_iterate_over_regset_sections 1929 (gdbarch, sparc_iterate_over_regset_sections); 1930 1931 register_sparc_ravenscar_ops (gdbarch); 1932 1933 return gdbarch; 1934} 1935 1936/* Helper functions for dealing with register windows. */ 1937 1938void 1939sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) 1940{ 1941 struct gdbarch *gdbarch = regcache->arch (); 1942 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1943 int offset = 0; 1944 gdb_byte buf[8]; 1945 int i; 1946 1947 if (sp & 1) 1948 { 1949 /* Registers are 64-bit. */ 1950 sp += BIAS; 1951 1952 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1953 { 1954 if (regnum == i || regnum == -1) 1955 { 1956 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 1957 1958 /* Handle StackGhost. */ 1959 if (i == SPARC_I7_REGNUM) 1960 { 1961 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1962 ULONGEST i7; 1963 1964 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 1965 store_unsigned_integer (buf + offset, 8, byte_order, 1966 i7 ^ wcookie); 1967 } 1968 1969 regcache->raw_supply (i, buf); 1970 } 1971 } 1972 } 1973 else 1974 { 1975 /* Registers are 32-bit. Toss any sign-extension of the stack 1976 pointer. */ 1977 sp &= 0xffffffffUL; 1978 1979 /* Clear out the top half of the temporary buffer, and put the 1980 register value in the bottom half if we're in 64-bit mode. */ 1981 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 1982 { 1983 memset (buf, 0, 4); 1984 offset = 4; 1985 } 1986 1987 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 1988 { 1989 if (regnum == i || regnum == -1) 1990 { 1991 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 1992 buf + offset, 4); 1993 1994 /* Handle StackGhost. */ 1995 if (i == SPARC_I7_REGNUM) 1996 { 1997 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 1998 ULONGEST i7; 1999 2000 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2001 store_unsigned_integer (buf + offset, 4, byte_order, 2002 i7 ^ wcookie); 2003 } 2004 2005 regcache->raw_supply (i, buf); 2006 } 2007 } 2008 } 2009} 2010 2011void 2012sparc_collect_rwindow (const struct regcache *regcache, 2013 CORE_ADDR sp, int regnum) 2014{ 2015 struct gdbarch *gdbarch = regcache->arch (); 2016 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2017 int offset = 0; 2018 gdb_byte buf[8]; 2019 int i; 2020 2021 if (sp & 1) 2022 { 2023 /* Registers are 64-bit. */ 2024 sp += BIAS; 2025 2026 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2027 { 2028 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2029 { 2030 regcache->raw_collect (i, buf); 2031 2032 /* Handle StackGhost. */ 2033 if (i == SPARC_I7_REGNUM) 2034 { 2035 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2036 ULONGEST i7; 2037 2038 i7 = extract_unsigned_integer (buf + offset, 8, byte_order); 2039 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); 2040 } 2041 2042 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); 2043 } 2044 } 2045 } 2046 else 2047 { 2048 /* Registers are 32-bit. Toss any sign-extension of the stack 2049 pointer. */ 2050 sp &= 0xffffffffUL; 2051 2052 /* Only use the bottom half if we're in 64-bit mode. */ 2053 if (gdbarch_ptr_bit (regcache->arch ()) == 64) 2054 offset = 4; 2055 2056 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2057 { 2058 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) 2059 { 2060 regcache->raw_collect (i, buf); 2061 2062 /* Handle StackGhost. */ 2063 if (i == SPARC_I7_REGNUM) 2064 { 2065 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); 2066 ULONGEST i7; 2067 2068 i7 = extract_unsigned_integer (buf + offset, 4, byte_order); 2069 store_unsigned_integer (buf + offset, 4, byte_order, 2070 i7 ^ wcookie); 2071 } 2072 2073 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), 2074 buf + offset, 4); 2075 } 2076 } 2077 } 2078} 2079 2080/* Helper functions for dealing with register sets. */ 2081 2082void 2083sparc32_supply_gregset (const struct sparc_gregmap *gregmap, 2084 struct regcache *regcache, 2085 int regnum, const void *gregs) 2086{ 2087 const gdb_byte *regs = (const gdb_byte *) gregs; 2088 gdb_byte zero[4] = { 0 }; 2089 int i; 2090 2091 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2092 regcache->raw_supply (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2093 2094 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2095 regcache->raw_supply (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2096 2097 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2098 regcache->raw_supply (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2099 2100 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2101 regcache->raw_supply (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2102 2103 if (regnum == SPARC_G0_REGNUM || regnum == -1) 2104 regcache->raw_supply (SPARC_G0_REGNUM, &zero); 2105 2106 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2107 { 2108 int offset = gregmap->r_g1_offset; 2109 2110 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2111 { 2112 if (regnum == i || regnum == -1) 2113 regcache->raw_supply (i, regs + offset); 2114 offset += 4; 2115 } 2116 } 2117 2118 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2119 { 2120 /* Not all of the register set variants include Locals and 2121 Inputs. For those that don't, we read them off the stack. */ 2122 if (gregmap->r_l0_offset == -1) 2123 { 2124 ULONGEST sp; 2125 2126 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); 2127 sparc_supply_rwindow (regcache, sp, regnum); 2128 } 2129 else 2130 { 2131 int offset = gregmap->r_l0_offset; 2132 2133 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2134 { 2135 if (regnum == i || regnum == -1) 2136 regcache->raw_supply (i, regs + offset); 2137 offset += 4; 2138 } 2139 } 2140 } 2141} 2142 2143void 2144sparc32_collect_gregset (const struct sparc_gregmap *gregmap, 2145 const struct regcache *regcache, 2146 int regnum, void *gregs) 2147{ 2148 gdb_byte *regs = (gdb_byte *) gregs; 2149 int i; 2150 2151 if (regnum == SPARC32_PSR_REGNUM || regnum == -1) 2152 regcache->raw_collect (SPARC32_PSR_REGNUM, regs + gregmap->r_psr_offset); 2153 2154 if (regnum == SPARC32_PC_REGNUM || regnum == -1) 2155 regcache->raw_collect (SPARC32_PC_REGNUM, regs + gregmap->r_pc_offset); 2156 2157 if (regnum == SPARC32_NPC_REGNUM || regnum == -1) 2158 regcache->raw_collect (SPARC32_NPC_REGNUM, regs + gregmap->r_npc_offset); 2159 2160 if (regnum == SPARC32_Y_REGNUM || regnum == -1) 2161 regcache->raw_collect (SPARC32_Y_REGNUM, regs + gregmap->r_y_offset); 2162 2163 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) 2164 { 2165 int offset = gregmap->r_g1_offset; 2166 2167 /* %g0 is always zero. */ 2168 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) 2169 { 2170 if (regnum == i || regnum == -1) 2171 regcache->raw_collect (i, regs + offset); 2172 offset += 4; 2173 } 2174 } 2175 2176 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) 2177 { 2178 /* Not all of the register set variants include Locals and 2179 Inputs. For those that don't, we read them off the stack. */ 2180 if (gregmap->r_l0_offset != -1) 2181 { 2182 int offset = gregmap->r_l0_offset; 2183 2184 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) 2185 { 2186 if (regnum == i || regnum == -1) 2187 regcache->raw_collect (i, regs + offset); 2188 offset += 4; 2189 } 2190 } 2191 } 2192} 2193 2194void 2195sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, 2196 struct regcache *regcache, 2197 int regnum, const void *fpregs) 2198{ 2199 const gdb_byte *regs = (const gdb_byte *) fpregs; 2200 int i; 2201 2202 for (i = 0; i < 32; i++) 2203 { 2204 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2205 regcache->raw_supply (SPARC_F0_REGNUM + i, 2206 regs + fpregmap->r_f0_offset + (i * 4)); 2207 } 2208 2209 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2210 regcache->raw_supply (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); 2211} 2212 2213void 2214sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, 2215 const struct regcache *regcache, 2216 int regnum, void *fpregs) 2217{ 2218 gdb_byte *regs = (gdb_byte *) fpregs; 2219 int i; 2220 2221 for (i = 0; i < 32; i++) 2222 { 2223 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) 2224 regcache->raw_collect (SPARC_F0_REGNUM + i, 2225 regs + fpregmap->r_f0_offset + (i * 4)); 2226 } 2227 2228 if (regnum == SPARC32_FSR_REGNUM || regnum == -1) 2229 regcache->raw_collect (SPARC32_FSR_REGNUM, 2230 regs + fpregmap->r_fsr_offset); 2231} 2232 2233 2234/* SunOS 4. */ 2235 2236/* From <machine/reg.h>. */ 2237const struct sparc_gregmap sparc32_sunos4_gregmap = 2238{ 2239 0 * 4, /* %psr */ 2240 1 * 4, /* %pc */ 2241 2 * 4, /* %npc */ 2242 3 * 4, /* %y */ 2243 -1, /* %wim */ 2244 -1, /* %tbr */ 2245 4 * 4, /* %g1 */ 2246 -1 /* %l0 */ 2247}; 2248 2249const struct sparc_fpregmap sparc32_sunos4_fpregmap = 2250{ 2251 0 * 4, /* %f0 */ 2252 33 * 4, /* %fsr */ 2253}; 2254 2255const struct sparc_fpregmap sparc32_bsd_fpregmap = 2256{ 2257 0 * 4, /* %f0 */ 2258 32 * 4, /* %fsr */ 2259}; 2260 2261void _initialize_sparc_tdep (); 2262void 2263_initialize_sparc_tdep () 2264{ 2265 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); 2266} 2267