aarch64-linux-hw-point.h revision 1.1.1.1 
1/* Copyright (C) 2009-2016 Free Software Foundation, Inc.
2   Contributed by ARM Ltd.
3
4   This file is part of GDB.
5
6   This program is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3 of the License, or
9   (at your option) any later version.
10
11   This program is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18
19#ifndef AARCH64_LINUX_HW_POINT_H
20#define AARCH64_LINUX_HW_POINT_H 1
21
22/* Macro definitions, data structures, and code for the hardware
23   breakpoint and hardware watchpoint support follow.  We use the
24   following abbreviations throughout the code:
25
26   hw - hardware
27   bp - breakpoint
28   wp - watchpoint  */
29
30/* Maximum number of hardware breakpoint and watchpoint registers.
31   Neither of these values may exceed the width of dr_changed_t
32   measured in bits.  */
33
34#define AARCH64_HBP_MAX_NUM 16
35#define AARCH64_HWP_MAX_NUM 16
36
37/* Alignment requirement in bytes for addresses written to
38   hardware breakpoint and watchpoint value registers.
39
40   A ptrace call attempting to set an address that does not meet the
41   alignment criteria will fail.  Limited support has been provided in
42   this port for unaligned watchpoints, such that from a GDB user
43   perspective, an unaligned watchpoint may be requested.
44
45   This is achieved by minimally enlarging the watched area to meet the
46   alignment requirement, and if necessary, splitting the watchpoint
47   over several hardware watchpoint registers.  */
48
49#define AARCH64_HBP_ALIGNMENT 4
50#define AARCH64_HWP_ALIGNMENT 8
51
52/* The maximum length of a memory region that can be watched by one
53   hardware watchpoint register.  */
54
55#define AARCH64_HWP_MAX_LEN_PER_REG 8
56
57/* ptrace hardware breakpoint resource info is formatted as follows:
58
59   31             24             16               8              0
60   +---------------+--------------+---------------+---------------+
61   |   RESERVED    |   RESERVED   |   DEBUG_ARCH  |  NUM_SLOTS    |
62   +---------------+--------------+---------------+---------------+  */
63
64
65/* Macros to extract fields from the hardware debug information word.  */
66#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
67#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
68
69/* Macro for the expected version of the ARMv8-A debug architecture.  */
70#define AARCH64_DEBUG_ARCH_V8 0x6
71#define AARCH64_DEBUG_ARCH_V8_1 0x7
72#define AARCH64_DEBUG_ARCH_V8_2 0x8
73
74/* ptrace expects control registers to be formatted as follows:
75
76   31                             13          5      3      1     0
77   +--------------------------------+----------+------+------+----+
78   |         RESERVED (SBZ)         |  LENGTH  | TYPE | PRIV | EN |
79   +--------------------------------+----------+------+------+----+
80
81   The TYPE field is ignored for breakpoints.  */
82
83#define DR_CONTROL_ENABLED(ctrl)	(((ctrl) & 0x1) == 1)
84#define DR_CONTROL_LENGTH(ctrl)		(((ctrl) >> 5) & 0xff)
85
86/* Each bit of a variable of this type is used to indicate whether a
87   hardware breakpoint or watchpoint setting has been changed since
88   the last update.
89
90   Bit N corresponds to the Nth hardware breakpoint or watchpoint
91   setting which is managed in aarch64_debug_reg_state, where N is
92   valid between 0 and the total number of the hardware breakpoint or
93   watchpoint debug registers minus 1.
94
95   When bit N is 1, the corresponding breakpoint or watchpoint setting
96   has changed, and therefore the corresponding hardware debug
97   register needs to be updated via the ptrace interface.
98
99   In the per-thread arch-specific data area, we define two such
100   variables for per-thread hardware breakpoint and watchpoint
101   settings respectively.
102
103   This type is part of the mechanism which helps reduce the number of
104   ptrace calls to the kernel, i.e. avoid asking the kernel to write
105   to the debug registers with unchanged values.  */
106
107typedef ULONGEST dr_changed_t;
108
109/* Set each of the lower M bits of X to 1; assert X is wide enough.  */
110
111#define DR_MARK_ALL_CHANGED(x, m)					\
112  do									\
113    {									\
114      gdb_assert (sizeof ((x)) * 8 >= (m));				\
115      (x) = (((dr_changed_t)1 << (m)) - 1);				\
116    } while (0)
117
118#define DR_MARK_N_CHANGED(x, n)						\
119  do									\
120    {									\
121      (x) |= ((dr_changed_t)1 << (n));					\
122    } while (0)
123
124#define DR_CLEAR_CHANGED(x)						\
125  do									\
126    {									\
127      (x) = 0;								\
128    } while (0)
129
130#define DR_HAS_CHANGED(x) ((x) != 0)
131#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
132
133/* Structure for managing the hardware breakpoint/watchpoint resources.
134   DR_ADDR_* stores the address, DR_CTRL_* stores the control register
135   content, and DR_REF_COUNT_* counts the numbers of references to the
136   corresponding bp/wp, by which way the limited hardware resources
137   are not wasted on duplicated bp/wp settings (though so far gdb has
138   done a good job by not sending duplicated bp/wp requests).  */
139
140struct aarch64_debug_reg_state
141{
142  /* hardware breakpoint */
143  CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
144  unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
145  unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
146
147  /* hardware watchpoint */
148  CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
149  unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
150  unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
151};
152
153/* Per-thread arch-specific data we want to keep.  */
154
155struct arch_lwp_info
156{
157  /* When bit N is 1, it indicates the Nth hardware breakpoint or
158     watchpoint register pair needs to be updated when the thread is
159     resumed; see aarch64_linux_prepare_to_resume.  */
160  dr_changed_t dr_changed_bp;
161  dr_changed_t dr_changed_wp;
162};
163
164extern int aarch64_num_bp_regs;
165extern int aarch64_num_wp_regs;
166
167unsigned int aarch64_watchpoint_length (unsigned int ctrl);
168
169int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
170			       int len, int is_insert,
171			       struct aarch64_debug_reg_state *state);
172int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
173			       int len, int is_insert,
174			       struct aarch64_debug_reg_state *state);
175
176void aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
177				   int tid, int watchpoint);
178
179void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
180				   const char *func, CORE_ADDR addr,
181				   int len, enum target_hw_bp_type type);
182
183void aarch64_linux_get_debug_reg_capacity (int tid);
184
185struct aarch64_debug_reg_state *aarch64_get_debug_reg_state (pid_t pid);
186
187int aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len);
188
189#endif /* AARCH64_LINUX_HW_POINT_H */
190