1/* Copyright (C) 2009-2020 Free Software Foundation, Inc.
2   Contributed by ARM Ltd.
3
4   This file is part of GDB.
5
6   This program is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3 of the License, or
9   (at your option) any later version.
10
11   This program is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
18
19#ifndef NAT_AARCH64_LINUX_HW_POINT_H
20#define NAT_AARCH64_LINUX_HW_POINT_H
21
22#include "gdbsupport/break-common.h" /* For enum target_hw_bp_type.  */
23
24/* Macro definitions, data structures, and code for the hardware
25   breakpoint and hardware watchpoint support follow.  We use the
26   following abbreviations throughout the code:
27
28   hw - hardware
29   bp - breakpoint
30   wp - watchpoint  */
31
32/* Maximum number of hardware breakpoint and watchpoint registers.
33   Neither of these values may exceed the width of dr_changed_t
34   measured in bits.  */
35
36#define AARCH64_HBP_MAX_NUM 16
37#define AARCH64_HWP_MAX_NUM 16
38
39/* Alignment requirement in bytes for addresses written to
40   hardware breakpoint and watchpoint value registers.
41
42   A ptrace call attempting to set an address that does not meet the
43   alignment criteria will fail.  Limited support has been provided in
44   this port for unaligned watchpoints, such that from a GDB user
45   perspective, an unaligned watchpoint may be requested.
46
47   This is achieved by minimally enlarging the watched area to meet the
48   alignment requirement, and if necessary, splitting the watchpoint
49   over several hardware watchpoint registers.  */
50
51#define AARCH64_HBP_ALIGNMENT 4
52#define AARCH64_HWP_ALIGNMENT 8
53
54/* The maximum length of a memory region that can be watched by one
55   hardware watchpoint register.  */
56
57#define AARCH64_HWP_MAX_LEN_PER_REG 8
58
59/* ptrace hardware breakpoint resource info is formatted as follows:
60
61   31             24             16               8              0
62   +---------------+--------------+---------------+---------------+
63   |   RESERVED    |   RESERVED   |   DEBUG_ARCH  |  NUM_SLOTS    |
64   +---------------+--------------+---------------+---------------+  */
65
66
67/* Macros to extract fields from the hardware debug information word.  */
68#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff)
69#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff)
70
71/* Macro for the expected version of the ARMv8-A debug architecture.  */
72#define AARCH64_DEBUG_ARCH_V8 0x6
73#define AARCH64_DEBUG_ARCH_V8_1 0x7
74#define AARCH64_DEBUG_ARCH_V8_2 0x8
75
76/* ptrace expects control registers to be formatted as follows:
77
78   31                             13          5      3      1     0
79   +--------------------------------+----------+------+------+----+
80   |         RESERVED (SBZ)         |   MASK   | TYPE | PRIV | EN |
81   +--------------------------------+----------+------+------+----+
82
83   The TYPE field is ignored for breakpoints.  */
84
85#define DR_CONTROL_ENABLED(ctrl)	(((ctrl) & 0x1) == 1)
86#define DR_CONTROL_MASK(ctrl)		(((ctrl) >> 5) & 0xff)
87
88/* Each bit of a variable of this type is used to indicate whether a
89   hardware breakpoint or watchpoint setting has been changed since
90   the last update.
91
92   Bit N corresponds to the Nth hardware breakpoint or watchpoint
93   setting which is managed in aarch64_debug_reg_state, where N is
94   valid between 0 and the total number of the hardware breakpoint or
95   watchpoint debug registers minus 1.
96
97   When bit N is 1, the corresponding breakpoint or watchpoint setting
98   has changed, and therefore the corresponding hardware debug
99   register needs to be updated via the ptrace interface.
100
101   In the per-thread arch-specific data area, we define two such
102   variables for per-thread hardware breakpoint and watchpoint
103   settings respectively.
104
105   This type is part of the mechanism which helps reduce the number of
106   ptrace calls to the kernel, i.e. avoid asking the kernel to write
107   to the debug registers with unchanged values.  */
108
109typedef ULONGEST dr_changed_t;
110
111/* Set each of the lower M bits of X to 1; assert X is wide enough.  */
112
113#define DR_MARK_ALL_CHANGED(x, m)					\
114  do									\
115    {									\
116      gdb_assert (sizeof ((x)) * 8 >= (m));				\
117      (x) = (((dr_changed_t)1 << (m)) - 1);				\
118    } while (0)
119
120#define DR_MARK_N_CHANGED(x, n)						\
121  do									\
122    {									\
123      (x) |= ((dr_changed_t)1 << (n));					\
124    } while (0)
125
126#define DR_CLEAR_CHANGED(x)						\
127  do									\
128    {									\
129      (x) = 0;								\
130    } while (0)
131
132#define DR_HAS_CHANGED(x) ((x) != 0)
133#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n)))
134
135/* Structure for managing the hardware breakpoint/watchpoint resources.
136   DR_ADDR_* stores the address, DR_CTRL_* stores the control register
137   content, and DR_REF_COUNT_* counts the numbers of references to the
138   corresponding bp/wp, by which way the limited hardware resources
139   are not wasted on duplicated bp/wp settings (though so far gdb has
140   done a good job by not sending duplicated bp/wp requests).  */
141
142struct aarch64_debug_reg_state
143{
144  /* hardware breakpoint */
145  CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM];
146  unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM];
147  unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM];
148
149  /* hardware watchpoint */
150  /* Address aligned down to AARCH64_HWP_ALIGNMENT.  */
151  CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM];
152  /* Address as entered by user without any forced alignment.  */
153  CORE_ADDR dr_addr_orig_wp[AARCH64_HWP_MAX_NUM];
154  unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM];
155  unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM];
156};
157
158/* Per-thread arch-specific data we want to keep.  */
159
160struct arch_lwp_info
161{
162  /* When bit N is 1, it indicates the Nth hardware breakpoint or
163     watchpoint register pair needs to be updated when the thread is
164     resumed; see aarch64_linux_prepare_to_resume.  */
165  dr_changed_t dr_changed_bp;
166  dr_changed_t dr_changed_wp;
167};
168
169extern int aarch64_num_bp_regs;
170extern int aarch64_num_wp_regs;
171
172unsigned int aarch64_watchpoint_offset (unsigned int ctrl);
173unsigned int aarch64_watchpoint_length (unsigned int ctrl);
174
175int aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
176			       int len, int is_insert,
177			       struct aarch64_debug_reg_state *state);
178int aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
179			       int len, int is_insert,
180			       struct aarch64_debug_reg_state *state);
181
182void aarch64_linux_set_debug_regs (struct aarch64_debug_reg_state *state,
183				   int tid, int watchpoint);
184
185/* Return TRUE if there are any hardware breakpoints.  If WATCHPOINT is TRUE,
186   check hardware watchpoints instead.  */
187bool aarch64_linux_any_set_debug_regs_state (aarch64_debug_reg_state *state,
188					     bool watchpoint);
189
190void aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
191				   const char *func, CORE_ADDR addr,
192				   int len, enum target_hw_bp_type type);
193
194void aarch64_linux_get_debug_reg_capacity (int tid);
195
196struct aarch64_debug_reg_state *aarch64_get_debug_reg_state (pid_t pid);
197
198int aarch64_linux_region_ok_for_watchpoint (CORE_ADDR addr, int len);
199
200#endif /* NAT_AARCH64_LINUX_HW_POINT_H */
201