1/* Target-dependent code for the CSKY architecture, for GDB. 2 3 Copyright (C) 2010-2020 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#ifndef CSKY_TDEP_H 21#define CSKY_TDEP_H 22 23/* How to interpret the contents of the link register. */ 24enum lr_type_t 25{ 26 LR_TYPE_R15, 27 LR_TYPE_EPC, 28 LR_TYPE_FPC 29}; 30 31/* Target-dependent structure in gdbarch. */ 32struct gdbarch_tdep 33{ 34 /* This is Unused. */ 35}; 36 37/* Instruction sizes. */ 38enum csky_insn_size_t 39{ 40 CSKY_INSN_SIZE16 = 2, 41 CSKY_INSN_SIZE32 = 4 42}; 43 44/* CSKY register numbers. */ 45enum csky_regnum 46{ 47 CSKY_R0_REGNUM = 0, /* General registers. */ 48 CSKY_R15_REGNUM = 15, 49 CSKY_PC_REGNUM = 72, 50 CSKY_HI_REGNUM = 20, 51 CSKY_LO_REGNUM = 21, 52 CSKY_CR0_REGNUM = 89, 53 CSKY_VBR_REGNUM = CSKY_CR0_REGNUM + 1, 54 CSKY_EPSR_REGNUM = CSKY_CR0_REGNUM + 2, 55 CSKY_FPSR_REGNUM = CSKY_CR0_REGNUM + 3, 56 CSKY_EPC_REGNUM = CSKY_CR0_REGNUM + 4, 57 CSKY_FPC_REGNUM = CSKY_CR0_REGNUM + 5, 58 59 /* Float register 0. */ 60 CSKY_FR0_REGNUM = 40, 61 CSKY_VCR0_REGNUM = 121, 62 CSKY_MMU_REGNUM = 128, 63 CSKY_PROFCR_REGNUM = 140, 64 CSKY_PROFGR_REGNUM = 144, 65 CSKY_FP_REGNUM = 8, 66 67 /* Vector register 0. */ 68 CSKY_VR0_REGNUM = 56, 69 70 /* m32r calling convention. */ 71 CSKY_SP_REGNUM = CSKY_R0_REGNUM + 14, 72 CSKY_RET_REGNUM = CSKY_R0_REGNUM, 73 74 /* Argument registers. */ 75 CSKY_ABI_A0_REGNUM = 0, 76 CSKY_ABI_LAST_ARG_REGNUM = 3, 77 78 /* Link register, r15. */ 79 CSKY_LR_REGNUM = CSKY_R15_REGNUM, 80 81 /* Processor status register, cr0. */ 82 CSKY_PSR_REGNUM = CSKY_CR0_REGNUM, 83 84 CSKY_MAX_REGISTER_SIZE = 16, 85 CSKY_MAX_REGS = 253 86}; 87 88/* ICE registers. */ 89#define CSKY_CRBANK_NUM_REGS 32 90 91/* Number of processor registers w/o ICE registers. */ 92#define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS) 93 94/* size. */ 95#define CSKY_16_ST_SIZE(insn) (1 << ((insn & 0x1800) >> 11)) 96/* rx. */ 97#define CSKY_16_ST_ADDR_REGNUM(insn) ((insn & 0x700) >> 8) 98/* disp. */ 99#define CSKY_16_ST_OFFSET(insn) ((insn & 0x1f) << ((insn & 0x1800) >> 11)) 100/* ry. */ 101#define CSKY_16_ST_VAL_REGNUM(insn) ((insn & 0xe0) >> 5) 102 103/* st16.w rz, (sp, disp). */ 104#define CSKY_16_IS_STWx0(insn) ((insn & 0xf800) == 0xb800) 105#define CSKY_16_STWx0_VAL_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn) 106 107/* disp. */ 108#define CSKY_16_STWx0_OFFSET(insn) \ 109 ((((insn & 0x700) >> 3) + (insn & 0x1f)) << 2) 110 111/* Check ld16 but not ld16 sp. */ 112#define CSKY_16_IS_LD(insn) \ 113 (((insn & 0xe000) == 0x8000) && (insn & 0x1800) != 0x1800) 114/* size. */ 115#define CSKY_16_LD_SIZE(insn) CSKY_16_ST_SIZE (insn) 116/* rx. */ 117#define CSKY_16_LD_ADDR_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn) 118/* disp. */ 119#define CSKY_16_LD_OFFSET(insn) CSKY_16_ST_OFFSET (insn) 120 121/* ld16.w rz,(sp,disp). */ 122#define CSKY_16_IS_LDWx0(insn) ((insn & 0xf800) == 0x9800) 123/*disp. */ 124#define CSKY_16_LDWx0_OFFSET(insn) CSKY_16_STWx0_OFFSET (insn) 125 126/* st32.b/h/w/d. */ 127#define CSKY_32_IS_ST(insn) ((insn & 0xfc00c000) == 0xdc000000) 128 129/* size: b/h/w/d. */ 130#define CSKY_32_ST_SIZE(insn) (1 << ((insn & 0x3000) >> 12)) 131/* rx. */ 132#define CSKY_32_ST_ADDR_REGNUM(insn) ((insn & 0x001f0000) >> 16) 133/* disp. */ 134#define CSKY_32_ST_OFFSET(insn) ((insn & 0xfff) << ((insn & 0x3000) >> 12)) 135/* ry. */ 136#define CSKY_32_ST_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21) 137 138/* stw ry, (sp, disp). */ 139#define CSKY_32_IS_STWx0(insn) ((insn & 0xfc1ff000) == 0xdc0e2000) 140 141/* stm32 ry-rz, (rx). */ 142#define CSKY_32_IS_STM(insn) ((insn & 0xfc00ffe0) == 0xd4001c20) 143/* rx. */ 144#define CSKY_32_STM_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) 145/* Count of registers. */ 146#define CSKY_32_STM_SIZE(insn) (insn & 0x1f) 147/* ry. */ 148#define CSKY_32_STM_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21) 149/* stm32 ry-rz, (sp). */ 150#define CSKY_32_IS_STMx0(insn) ((insn & 0xfc1fffe0) == 0xd40e1c20) 151 152/* str32.b/h/w rz, (rx, ry << offset). */ 153#define CSKY_32_IS_STR(insn) \ 154 (((insn & 0xfc000000) == 0xd4000000) && !(CSKY_32_IS_STM (insn))) 155/* rx. */ 156#define CSKY_32_STR_X_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) 157/* ry. */ 158#define CSKY_32_STR_Y_REGNUM(insn) ((insn >> 21) & 0x1f) 159/* size: b/h/w. */ 160#define CSKY_32_STR_SIZE(insn) (1 << ((insn & 0x0c00) >> 10)) 161/* imm (for rx + ry * imm). */ 162#define CSKY_32_STR_OFFSET(insn) ((insn & 0x000003e0) >> 5) 163 164/* stex32.w rz, (rx, disp). */ 165#define CSKY_32_IS_STEX(insn) ((insn & 0xfc00f000) == 0xdc007000) 166/* rx. */ 167#define CSKY_32_STEX_ADDR_REGNUM(insn) ((insn & 0x1f0000) >> 16) 168/* disp. */ 169#define CSKY_32_STEX_OFFSET(insn) ((insn & 0x0fff) << 2) 170 171/* ld.b/h/w. */ 172#define CSKY_32_IS_LD(insn) ((insn & 0xfc00c000) == 0xd8000000) 173/* size. */ 174#define CSKY_32_LD_SIZE(insn) CSKY_32_ST_SIZE (insn) 175/* rx. */ 176#define CSKY_32_LD_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) 177/* disp. */ 178#define CSKY_32_LD_OFFSET(insn) CSKY_32_ST_OFFSET (insn) 179#define CSKY_32_IS_LDM(insn) ((insn & 0xfc00ffe0) == 0xd0001c20) 180/* rx. */ 181#define CSKY_32_LDM_ADDR_REGNUM(insn) CSKY_32_STM_ADDR_REGNUM (insn) 182/* Count of registers. */ 183#define CSKY_32_LDM_SIZE(insn) CSKY_32_STM_SIZE (insn) 184 185/* ldr32.b/h/w rz, (rx, ry << offset). */ 186#define CSKY_32_IS_LDR(insn) \ 187 (((insn & 0xfc00fe00) == 0xd0000000) && !(CSKY_32_IS_LDM (insn))) 188/* rx. */ 189#define CSKY_32_LDR_X_REGNUM(insn) CSKY_32_STR_X_REGNUM (insn) 190/* ry. */ 191#define CSKY_32_LDR_Y_REGNUM(insn) CSKY_32_STR_Y_REGNUM (insn) 192/* size: b/h/w. */ 193#define CSKY_32_LDR_SIZE(insn) CSKY_32_STR_SIZE (insn) 194/* imm (for rx + ry*imm). */ 195#define CSKY_32_LDR_OFFSET(insn) CSKY_32_STR_OFFSET (insn) 196 197#define CSKY_32_IS_LDEX(insn) ((insn & 0xfc00f000) == 0xd8007000) 198/* rx. */ 199#define CSKY_32_LDEX_ADDR_REGNUM(insn) CSKY_32_STEX_ADDR_REGNUM (insn) 200/* disp. */ 201#define CSKY_32_LDEX_OFFSET(insn) CSKY_32_STEX_OFFSET (insn) 202 203/* subi.sp sp, disp. */ 204#define CSKY_16_IS_SUBI0(insn) ((insn & 0xfce0) == 0x1420) 205/* disp. */ 206#define CSKY_16_SUBI_IMM(insn) ((((insn & 0x300) >> 3) + (insn & 0x1f)) << 2) 207 208/* subi32 sp,sp,oimm12. */ 209#define CSKY_32_IS_SUBI0(insn) ((insn & 0xfffff000) == 0xe5ce1000) 210/* oimm12. */ 211#define CSKY_32_SUBI_IMM(insn) ((insn & 0xfff) + 1) 212 213/* push16. */ 214#define CSKY_16_IS_PUSH(insn) ((insn & 0xffe0) == 0x14c0) 215#define CSKY_16_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10) 216#define CSKY_16_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */ 217 218/* pop16. */ 219#define CSKY_16_IS_POP(insn) ((insn & 0xffe0) == 0x1480) 220#define CSKY_16_IS_POP_R15(insn) CSKY_16_IS_PUSH_R15 (insn) 221#define CSKY_16_POP_LIST1(insn) CSKY_16_PUSH_LIST1 (insn) /* r4 - r11. */ 222 223/* push32. */ 224#define CSKY_32_IS_PUSH(insn) ((insn & 0xfffffe00) == 0xebe00000) 225#define CSKY_32_IS_PUSH_R29(insn) ((insn & 0x100) == 0x100) 226#define CSKY_32_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10) 227#define CSKY_32_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */ 228#define CSKY_32_PUSH_LIST2(insn) ((insn & 0xe0) >> 5) /* r16 - r17. */ 229 230/* pop32. */ 231#define CSKY_32_IS_POP(insn) ((insn & 0xfffffe00) == 0xebc00000) 232#define CSKY_32_IS_POP_R29(insn) CSKY_32_IS_PUSH_R29 (insn) 233#define CSKY_32_IS_POP_R15(insn) CSKY_32_IS_PUSH_R15 (insn) 234#define CSKY_32_POP_LIST1(insn) CSKY_32_PUSH_LIST1 (insn) /* r4 - r11. */ 235#define CSKY_32_POP_LIST2(insn) CSKY_32_PUSH_LIST2 (insn) /* r16 - r17. */ 236 237/* Adjust sp by r4(l0). */ 238/* lrw r4, literal. */ 239#define CSKY_16_IS_LRW4(x) (((x) &0xfce0) == 0x1080) 240/* movi r4, imm8. */ 241#define CSKY_16_IS_MOVI4(x) (((x) &0xff00) == 0x3400) 242 243/* addi r4, oimm8. */ 244#define CSKY_16_IS_ADDI4(x) (((x) &0xff00) == 0x2400) 245/* subi r4, oimm8. */ 246#define CSKY_16_IS_SUBI4(x) (((x) &0xff00) == 0x2c00) 247 248/* nor16 r4, r4. */ 249#define CSKY_16_IS_NOR4(x) ((x) == 0x6d12) 250 251/* lsli r4, r4, imm5. */ 252#define CSKY_16_IS_LSLI4(x) (((x) &0xffe0) == 0x4480) 253/* bseti r4, imm5. */ 254#define CSKY_16_IS_BSETI4(x) (((x) &0xffe0) == 0x3ca0) 255/* bclri r4, imm5. */ 256#define CSKY_16_IS_BCLRI4(x) (((x) &0xffe0) == 0x3c80) 257 258/* subu sp, r4. */ 259#define CSKY_16_IS_SUBU4(x) ((x) == 0x6392) 260 261#define CSKY_16_IS_R4_ADJUSTER(x) \ 262 (CSKY_16_IS_ADDI4 (x) || CSKY_16_IS_SUBI4 (x) || CSKY_16_IS_BSETI4 (x) \ 263 || CSKY_16_IS_BCLRI4 (x) || CSKY_16_IS_NOR4 (x) || CSKY_16_IS_LSLI4 (x)) 264 265/* lrw r4, literal. */ 266#define CSKY_32_IS_LRW4(x) (((x) &0xffff0000) == 0xea840000) 267/* movi r4, imm16. */ 268#define CSKY_32_IS_MOVI4(x) (((x) &0xffff0000) == 0xea040000) 269/* movih r4, imm16. */ 270#define CSKY_32_IS_MOVIH4(x) (((x) &0xffff0000) == 0xea240000) 271/* bmaski r4, oimm5. */ 272#define CSKY_32_IS_BMASKI4(x) (((x) &0xfc1fffff) == 0xc4005024) 273/* addi r4, r4, oimm12. */ 274#define CSKY_32_IS_ADDI4(x) (((x) &0xfffff000) == 0xe4840000) 275/* subi r4, r4, oimm12. */ 276#define CSKY_32_IS_SUBI4(x) (((x) &0xfffff000) == 0xe4810000) 277 278/* nor32 r4, r4, r4. */ 279#define CSKY_32_IS_NOR4(x) ((x) == 0xc4842484) 280/* rotli r4, r4, imm5. */ 281#define CSKY_32_IS_ROTLI4(x) (((x) &0xfc1fffff) == 0xc4044904) 282/* lsli r4, r4, imm5. */ 283#define CSKY_32_IS_LISI4(x) (((x) &0xfc1fffff) == 0xc4044824) 284/* bseti32 r4, r4, imm5. */ 285#define CSKY_32_IS_BSETI4(x) (((x) &0xfc1fffff) == 0xc4042844) 286/* bclri32 r4, r4, imm5. */ 287#define CSKY_32_IS_BCLRI4(x) (((x) &0xfc1fffff) == 0xc4042824) 288/* ixh r4, r4, r4. */ 289#define CSKY_32_IS_IXH4(x) ((x) == 0xc4840824) 290/* ixw r4, r4, r4. */ 291#define CSKY_32_IS_IXW4(x) ((x) == 0xc4840844) 292/* subu32 sp, sp, r4. */ 293#define CSKY_32_IS_SUBU4(x) ((x) == 0xc48e008e) 294 295#define CSKY_32_IS_R4_ADJUSTER(x) \ 296 (CSKY_32_IS_ADDI4 (x) || CSKY_32_IS_SUBI4 (x) || CSKY_32_IS_ROTLI4 (x) \ 297 || CSKY_32_IS_IXH4 (x) || CSKY_32_IS_IXW4 (x) || CSKY_32_IS_NOR4 (x) \ 298 || CSKY_32_IS_BSETI4 (x) || CSKY_32_IS_BCLRI4 (x) || CSKY_32_IS_LISI4 (x)) 299 300#define CSKY_IS_R4_ADJUSTER(x) \ 301 (CSKY_32_IS_R4_ADJUSTER (x) || CSKY_16_IS_R4_ADJUSTER (x)) 302#define CSKY_IS_SUBU4(x) (CSKY_32_IS_SUBU4 (x) || CSKY_16_IS_SUBU4 (x)) 303 304/* mfcr rz, epsr. */ 305#define CSKY_32_IS_MFCR_EPSR(insn) ((insn & 0xffffffe0) == 0xc0026020) 306/* mfcr rz, fpsr. */ 307#define CSKY_32_IS_MFCR_FPSR(insn) ((insn & 0xffffffe0) == 0xc0036020) 308/* mfcr rz, epc. */ 309#define CSKY_32_IS_MFCR_EPC(insn) ((insn & 0xffffffe0) == 0xc0046020) 310/* mfcr rz, fpc. */ 311#define CSKY_32_IS_MFCR_FPC(insn) ((insn & 0xffffffe0) == 0xc0056020) 312 313#define CSKY_32_IS_RTE(insn) (insn == 0xc0004020) 314#define CSKY_32_IS_RFI(insn) (insn == 0xc0004420) 315#define CSKY_32_IS_JMP(insn) ((insn & 0xffe0ffff) == 0xe8c00000) 316#define CSKY_16_IS_JMP(insn) ((insn & 0xffc3) == 0x7800) 317#define CSKY_32_IS_JMPI(insn) ((insn & 0xffff0000) == 0xeac00000) 318#define CSKY_32_IS_JMPIX(insn) ((insn & 0xffe0fffc) == 0xe9e00000) 319#define CSKY_16_IS_JMPIX(insn) ((insn & 0xf8fc) == 0x38e0) 320 321#define CSKY_16_IS_BR(insn) ((insn & 0xfc00) == 0x0400) 322#define CSKY_32_IS_BR(insn) ((insn & 0xffff0000) == 0xe8000000) 323#define CSKY_16_IS_MOV_FP_SP(insn) (insn == 0x6e3b) /* mov r8, r14. */ 324#define CSKY_32_IS_MOV_FP_SP(insn) (insn == 0xc40e4828) /* mov r8, r14. */ 325#define CSKY_16_IS_MOV_SP_FP(insn) (insn == 0x6fa3) /* mov r14, r8. */ 326#define CSKY_32_INSN_MASK 0xc000 327#define CSKY_BKPT_INSN 0x0 328#define CSKY_NUM_GREGS 32 329/* 32 general regs + 4. */ 330#define CSKY_NUM_GREGS_SAVED_GREGS (CSKY_NUM_GREGS + 4) 331 332/* CSKY software bkpt write-mode. */ 333#define CSKY_WR_BKPT_MODE 4 334 335/* Define insns for parse rt_sigframe. */ 336/* There are three words(sig, pinfo, puc) before siginfo. */ 337#define CSKY_SIGINFO_OFFSET 0xc 338 339/* Size of struct siginfo. */ 340#define CSKY_SIGINFO_SIZE 0x80 341 342/* There are five words(uc_flags, uc_link, and three for uc_stack) 343 in struct ucontext before sigcontext. */ 344#define CSKY_UCONTEXT_SIGCONTEXT 0x14 345 346/* There is a word(sc_mask) before sc_usp. */ 347#define CSKY_SIGCONTEXT_SC_USP 0x4 348 349/* There is a word(sc_usp) before sc_a0. */ 350#define CSKY_SIGCONTEXT_SC_A0 0x4 351 352#define CSKY_MOVI_R7_173 0x00adea07 353#define CSKY_TRAP_0 0x2020c000 354 355#endif 356