1#name: Valid armv8-m.main+fp 2#as: -march=armv8-m.main+fp 3#source: fpv5-sp-d16.s 4#objdump: -dr --prefix-addresses --show-raw-insn 5#skip: *-*-pe *-wince-* 6 7.*: +file format .*arm.* 8 9Disassembly of section .text: 100[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0 110[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1 120[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30 130[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31 140[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0 150[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1 160[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30 170[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31 180[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0 190[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1 200[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30 210[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31 220[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0 230[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1 240[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30 250[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31 260[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0 270[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32 s1, s1 280[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32 s30, s30 290[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32 s0, s0 300[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32 s1, s1 310[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32 s30, s30 320[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31 33