1@c Copyright (C) 1991-2020 Free Software Foundation, Inc.
2@c This is part of the GAS manual.
3@c For copying conditions, see the file as.texinfo.
4@ifset GENERIC
5@page
6@node Sparc-Dependent
7@chapter SPARC Dependent Features
8@end ifset
9@ifclear GENERIC
10@node Machine Dependencies
11@chapter SPARC Dependent Features
12@end ifclear
13
14@cindex SPARC support
15@menu
16* Sparc-Opts::                  Options
17* Sparc-Aligned-Data::		Option to enforce aligned data
18* Sparc-Syntax::		Syntax
19* Sparc-Float::                 Floating Point
20* Sparc-Directives::            Sparc Machine Directives
21@end menu
22
23@node Sparc-Opts
24@section Options
25
26@cindex options for SPARC
27@cindex SPARC options
28@cindex architectures, SPARC
29@cindex SPARC architectures
30The SPARC chip family includes several successive versions, using the same
31core instruction set, but including a few additional instructions at
32each version.  There are exceptions to this however.  For details on what
33instructions each variant supports, please see the chip's architecture
34reference manual.
35
36By default, @code{@value{AS}} assumes the core instruction set (SPARC
37v6), but ``bumps'' the architecture level as needed: it switches to
38successively higher architectures as it encounters instructions that
39only exist in the higher levels.
40
41If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
42past sparclite by default, an option must be passed to enable the
43v9 instructions.
44
45GAS treats sparclite as being compatible with v8, unless an architecture
46is explicitly requested.  SPARC v9 is always incompatible with sparclite.
47
48@c The order here is the same as the order of enum sparc_opcode_arch_val
49@c to give the user a sense of the order of the "bumping".
50
51@table @code
52@kindex -Av6
53@kindex -Av7
54@kindex -Av8
55@kindex -Aleon
56@kindex -Asparclet
57@kindex -Asparclite
58@kindex -Av9
59@kindex -Av9a
60@kindex -Av9b
61@kindex -Av9c
62@kindex -Av9d
63@kindex -Av9e
64@kindex -Av9v
65@kindex -Av9m
66@kindex -Asparc
67@kindex -Asparcvis
68@kindex -Asparcvis2
69@kindex -Asparcfmaf
70@kindex -Asparcima
71@kindex -Asparcvis3
72@kindex -Asparcvis3r
73@item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
74@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |
75@itemx -Av8plusv | -Av8plusm | -Av8plusm8
76@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8
77@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
78@itemx -Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6
79Use one of the @samp{-A} options to select one of the SPARC
80architectures explicitly.  If you select an architecture explicitly,
81@code{@value{AS}} reports a fatal error if it encounters an instruction
82or feature requiring an incompatible or higher level.
83
84@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
85@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
86
87@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d},
88@samp{-Av9e}, @samp{-Av9v} and @samp{-Av9m} select a 64 bit
89environment and are not available unless GAS is explicitly configured
90with 64 bit environment support.
91
92@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
93UltraSPARC VIS 1.0 extensions.
94
95@samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
96as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
97
98@samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
99as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
100
101@samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
102multiply-add, VIS 3.0, and HPC extension instructions, as well as the
103instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
104
105@samp{-Av8pluse} and @samp{-Av9e} enable the cryptographic
106instructions, as well as the instructions enabled by @samp{-Av8plusd}
107and @samp{-Av9d}.
108
109@samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
110multiply-add, and integer multiply-add, as well as the instructions
111enabled by @samp{-Av8pluse} and @samp{-Av9e}.
112
113@samp{-Av8plusm} and @samp{-Av9m} enable the VIS 4.0, subtract extended,
114xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
115enabled by @samp{-Av8plusv} and @samp{-Av9v}.
116
117@samp{-Av8plusm8} and @samp{-Av9m8} enable the instructions introduced
118in the Oracle SPARC Architecture 2017 and the M8 processor, as
119well as the instructions enabled by @samp{-Av8plusm} and @samp{-Av9m}.
120
121@samp{-Asparc} specifies a v9 environment.  It is equivalent to
122@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
123
124@samp{-Asparcvis} specifies a v9a environment.  It is equivalent to
125@samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
126
127@samp{-Asparcvis2} specifies a v9b environment.  It is equivalent to
128@samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
129
130@samp{-Asparcfmaf} specifies a v9b environment with the floating point
131fused multiply-add instructions enabled.
132
133@samp{-Asparcima} specifies a v9b environment with the integer
134multiply-add instructions enabled.
135
136@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
137HPC , and floating point fused multiply-add instructions enabled.
138
139@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
140and floating point unfused multiply-add instructions enabled.
141
142@samp{-Asparc5} is equivalent to @samp{-Av9m}.
143
144@samp{-Asparc6} is equivalent to @samp{-Av9m8}.
145
146@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
147@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |
148@itemx -xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b
149@itemx -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v
150@itemx -xarch=v9m | -xarch=v9m8
151@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
152@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
153@itemx -xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6
154For compatibility with the SunOS v9 assembler.  These options are
155equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
156-Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d,
157-Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2,
158-Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and
159-Asparc6 respectively.
160
161@item -bump
162Warn whenever it is necessary to switch to another level.
163If an architecture level is explicitly requested, GAS will not issue
164warnings until that level is reached, and will then bump the level
165as required (except between incompatible levels).
166
167@item -32 | -64
168Select the word size, either 32 bits or 64 bits.
169These options are only available with the ELF object file format,
170and require that the necessary BFD support has been included.
171
172@item --dcti-couples-detect
173Warn if a DCTI (delayed control transfer instruction) couple is found
174when generating code for a variant of the SPARC architecture in which
175the execution of the couple is unpredictable, or very slow.  This is
176disabled by default.
177@end table
178
179@node Sparc-Aligned-Data
180@section Enforcing aligned data
181
182@cindex data alignment on SPARC
183@cindex SPARC data alignment
184SPARC GAS normally permits data to be misaligned.  For example, it
185permits the @code{.long} pseudo-op to be used on a byte boundary.
186However, the native SunOS assemblers issue an error when they see
187misaligned data.
188
189@kindex --enforce-aligned-data
190You can use the @code{--enforce-aligned-data} option to make SPARC GAS
191also issue an error about misaligned data, just as the SunOS
192assemblers do.
193
194The @code{--enforce-aligned-data} option is not the default because gcc
195issues misaligned data pseudo-ops when it initializes certain packed
196data structures (structures defined using the @code{packed} attribute).
197You may have to assemble with GAS in order to initialize packed data
198structures in your own code.
199
200@cindex SPARC syntax
201@cindex syntax, SPARC
202@node Sparc-Syntax
203@section Sparc Syntax
204The assembler syntax closely follows The Sparc Architecture Manual,
205versions 8 and 9, as well as most extensions defined by Sun
206for their UltraSPARC and Niagara line of processors.
207
208@menu
209* Sparc-Chars::                Special Characters
210* Sparc-Regs::                 Register Names
211* Sparc-Constants::            Constant Names
212* Sparc-Relocs::               Relocations
213* Sparc-Size-Translations::    Size Translations
214@end menu
215
216@node Sparc-Chars
217@subsection Special Characters
218
219@cindex line comment character, Sparc
220@cindex Sparc line comment character
221A @samp{!} character appearing anywhere on a line indicates the start
222of a comment that extends to the end of that line.
223
224If a @samp{#} appears as the first character of a line then the whole
225line is treated as a comment, but in this case the line could also be
226a logical line number directive (@pxref{Comments}) or a preprocessor
227control command (@pxref{Preprocessing}).
228
229@cindex line separator, Sparc
230@cindex statement separator, Sparc
231@cindex Sparc line separator
232@samp{;} can be used instead of a newline to separate statements.
233
234@node Sparc-Regs
235@subsection Register Names
236@cindex Sparc registers
237@cindex register names, Sparc
238
239The Sparc integer register file is broken down into global,
240outgoing, local, and incoming.
241
242@itemize @bullet
243@item
244The 8 global registers are referred to as @samp{%g@var{n}}.
245
246@item
247The 8 outgoing registers are referred to as @samp{%o@var{n}}.
248
249@item
250The 8 local registers are referred to as @samp{%l@var{n}}.
251
252@item
253The 8 incoming registers are referred to as @samp{%i@var{n}}.
254
255@item
256The frame pointer register @samp{%i6} can be referenced using
257the alias @samp{%fp}.
258
259@item
260The stack pointer register @samp{%o6} can be referenced using
261the alias @samp{%sp}.
262@end itemize
263
264Floating point registers are simply referred to as @samp{%f@var{n}}.
265When assembling for pre-V9, only 32 floating point registers
266are available.  For V9 and later there are 64, but there are
267restrictions when referencing the upper 32 registers.  They
268can only be accessed as double or quad, and thus only even
269or quad numbered accesses are allowed.  For example, @samp{%f34}
270is a legal floating point register, but @samp{%f35} is not.
271
272Floating point registers accessed as double can also be referred using
273the @samp{%d@var{n}} notation, where @var{n} is even.  Similarly,
274floating point registers accessed as quad can be referred using the
275@samp{%q@var{n}} notation, where @var{n} is a multiple of 4.  For
276example, @samp{%f4} can be denoted as both @samp{%d4} and @samp{%q4}.
277On the other hand, @samp{%f2} can be denoted as @samp{%d2} but not as
278@samp{%q2}.
279
280Certain V9 instructions allow access to ancillary state registers.
281Most simply they can be referred to as @samp{%asr@var{n}} where
282@var{n} can be from 16 to 31.  However, there are some aliases
283defined to reference ASR registers defined for various UltraSPARC
284processors:
285
286@itemize @bullet
287@item
288The tick compare register is referred to as @samp{%tick_cmpr}.
289
290@item
291The system tick register is referred to as @samp{%stick}.  An alias,
292@samp{%sys_tick}, exists but is deprecated and should not be used
293by new software.
294
295@item
296The system tick compare register is referred to as @samp{%stick_cmpr}.
297An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
298not be used by new software.
299
300@item
301The software interrupt register is referred to as @samp{%softint}.
302
303@item
304The set software interrupt register is referred to as @samp{%set_softint}.
305The mnemonic @samp{%softint_set} is provided as an alias.
306
307@item
308The clear software interrupt register is referred to as
309@samp{%clear_softint}.  The mnemonic @samp{%softint_clear} is provided
310as an alias.
311
312@item
313The performance instrumentation counters register is referred to as
314@samp{%pic}.
315
316@item
317The performance control register is referred to as @samp{%pcr}.
318
319@item
320The graphics status register is referred to as @samp{%gsr}.
321
322@item
323The V9 dispatch control register is referred to as @samp{%dcr}.
324@end itemize
325
326Various V9 branch and conditional move instructions allow
327specification of which set of integer condition codes to
328test.  These are referred to as @samp{%xcc} and @samp{%icc}.
329
330Additionally, GAS supports the so-called ``natural'' condition codes;
331these are referred to as @samp{%ncc} and reference to @samp{%icc} if
332the word size is 32, @samp{%xcc} if the word size is 64.
333
334In V9, there are 4 sets of floating point condition codes
335which are referred to as @samp{%fcc@var{n}}.
336
337Several special privileged and non-privileged registers
338exist:
339
340@itemize @bullet
341@item
342The V9 address space identifier register is referred to as @samp{%asi}.
343
344@item
345The V9 restorable windows register is referred to as @samp{%canrestore}.
346
347@item
348The V9 savable windows register is referred to as @samp{%cansave}.
349
350@item
351The V9 clean windows register is referred to as @samp{%cleanwin}.
352
353@item
354The V9 current window pointer register is referred to as @samp{%cwp}.
355
356@item
357The floating-point queue register is referred to as @samp{%fq}.
358
359@item
360The V8 co-processor queue register is referred to as @samp{%cq}.
361
362@item
363The floating point status register is referred to as @samp{%fsr}.
364
365@item
366The other windows register is referred to as @samp{%otherwin}.
367
368@item
369The V9 program counter register is referred to as @samp{%pc}.
370
371@item
372The V9 next program counter register is referred to as @samp{%npc}.
373
374@item
375The V9 processor interrupt level register is referred to as @samp{%pil}.
376
377@item
378The V9 processor state register is referred to as @samp{%pstate}.
379
380@item
381The trap base address register is referred to as @samp{%tba}.
382
383@item
384The V9 tick register is referred to as @samp{%tick}.
385
386@item
387The V9 trap level is referred to as @samp{%tl}.
388
389@item
390The V9 trap program counter is referred to as @samp{%tpc}.
391
392@item
393The V9 trap next program counter is referred to as @samp{%tnpc}.
394
395@item
396The V9 trap state is referred to as @samp{%tstate}.
397
398@item
399The V9 trap type is referred to as @samp{%tt}.
400
401@item
402The V9 condition codes is referred to as @samp{%ccr}.
403
404@item
405The V9 floating-point registers state is referred to as @samp{%fprs}.
406
407@item
408The V9 version register is referred to as @samp{%ver}.
409
410@item
411The V9 window state register is referred to as @samp{%wstate}.
412
413@item
414The Y register is referred to as @samp{%y}.
415
416@item
417The V8 window invalid mask register is referred to as @samp{%wim}.
418
419@item
420The V8 processor state register is referred to as @samp{%psr}.
421
422@item
423The V9 global register level register is referred to as @samp{%gl}.
424@end itemize
425
426Several special register names exist for hypervisor mode code:
427
428@itemize @bullet
429@item
430The hyperprivileged processor state register is referred to as
431@samp{%hpstate}.
432
433@item
434The hyperprivileged trap state register is referred to as @samp{%htstate}.
435
436@item
437The hyperprivileged interrupt pending register is referred to as
438@samp{%hintp}.
439
440@item
441The hyperprivileged trap base address register is referred to as
442@samp{%htba}.
443
444@item
445The hyperprivileged implementation version register is referred
446to as @samp{%hver}.
447
448@item
449The hyperprivileged system tick offset register is referred to as
450@samp{%hstick_offset}.  Note that there is no @samp{%hstick} register,
451the normal @samp{%stick} is used.
452
453@item
454The hyperprivileged system tick enable register is referred to as
455@samp{%hstick_enable}.
456
457@item
458The hyperprivileged system tick compare register is referred
459to as @samp{%hstick_cmpr}.
460@end itemize
461
462@node Sparc-Constants
463@subsection Constants
464@cindex Sparc constants
465@cindex constants, Sparc
466
467Several Sparc instructions take an immediate operand field for
468which mnemonic names exist.  Two such examples are @samp{membar}
469and @samp{prefetch}.  Another example are the set of V9
470memory access instruction that allow specification of an
471address space identifier.
472
473The @samp{membar} instruction specifies a memory barrier that is
474the defined by the operand which is a bitmask.  The supported
475mask mnemonics are:
476
477@itemize @bullet
478@item
479@samp{#Sync} requests that all operations (including nonmemory
480reference operations) appearing prior to the @code{membar} must have
481been performed and the effects of any exceptions become visible before
482any instructions after the @code{membar} may be initiated.  This
483corresponds to @code{membar} cmask field bit 2.
484
485@item
486@samp{#MemIssue} requests that all memory reference operations
487appearing prior to the @code{membar} must have been performed before
488any memory operation after the @code{membar} may be initiated.  This
489corresponds to @code{membar} cmask field bit 1.
490
491@item
492@samp{#Lookaside} requests that a store appearing prior to the
493@code{membar} must complete before any load following the
494@code{membar} referencing the same address can be initiated.  This
495corresponds to @code{membar} cmask field bit 0.
496
497@item
498@samp{#StoreStore} defines that the effects of all stores appearing
499prior to the @code{membar} instruction must be visible to all
500processors before the effect of any stores following the
501@code{membar}.  Equivalent to the deprecated @code{stbar} instruction.
502This corresponds to @code{membar} mmask field bit 3.
503
504@item
505@samp{#LoadStore} defines all loads appearing prior to the
506@code{membar} instruction must have been performed before the effect
507of any stores following the @code{membar} is visible to any other
508processor.  This corresponds to @code{membar} mmask field bit 2.
509
510@item
511@samp{#StoreLoad} defines that the effects of all stores appearing
512prior to the @code{membar} instruction must be visible to all
513processors before loads following the @code{membar} may be performed.
514This corresponds to @code{membar} mmask field bit 1.
515
516@item
517@samp{#LoadLoad} defines that all loads appearing prior to the
518@code{membar} instruction must have been performed before any loads
519following the @code{membar} may be performed.  This corresponds to
520@code{membar} mmask field bit 0.
521
522@end itemize
523
524These values can be ored together, for example:
525
526@example
527membar #Sync
528membar #StoreLoad | #LoadLoad
529membar #StoreLoad | #StoreStore
530@end example
531
532The @code{prefetch} and @code{prefetcha} instructions take a prefetch
533function code.  The following prefetch function code constant
534mnemonics are available:
535
536@itemize @bullet
537@item
538@samp{#n_reads} requests a prefetch for several reads, and corresponds
539to a prefetch function code of 0.
540
541@samp{#one_read} requests a prefetch for one read, and corresponds
542to a prefetch function code of 1.
543
544@samp{#n_writes} requests a prefetch for several writes (and possibly
545reads), and corresponds to a prefetch function code of 2.
546
547@samp{#one_write} requests a prefetch for one write, and corresponds
548to a prefetch function code of 3.
549
550@samp{#page} requests a prefetch page, and corresponds to a prefetch
551function code of 4.
552
553@samp{#invalidate} requests a prefetch invalidate, and corresponds to
554a prefetch function code of 16.
555
556@samp{#unified} requests a prefetch to the nearest unified cache, and
557corresponds to a prefetch function code of 17.
558
559@samp{#n_reads_strong} requests a strong prefetch for several reads,
560and corresponds to a prefetch function code of 20.
561
562@samp{#one_read_strong} requests a strong prefetch for one read,
563and corresponds to a prefetch function code of 21.
564
565@samp{#n_writes_strong} requests a strong prefetch for several writes,
566and corresponds to a prefetch function code of 22.
567
568@samp{#one_write_strong} requests a strong prefetch for one write,
569and corresponds to a prefetch function code of 23.
570
571Onle one prefetch code may be specified.  Here are some examples:
572
573@example
574prefetch  [%l0 + %l2], #one_read
575prefetch  [%g2 + 8], #n_writes
576prefetcha [%g1] 0x8, #unified
577prefetcha [%o0 + 0x10] %asi, #n_reads
578@end example
579
580The actual behavior of a given prefetch function code is processor
581specific.  If a processor does not implement a given prefetch
582function code, it will treat the prefetch instruction as a nop.
583
584For instructions that accept an immediate address space identifier,
585@code{@value{AS}} provides many mnemonics corresponding to
586V9 defined as well as UltraSPARC and Niagara extended values.
587For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
588See the V9 and processor specific manuals for details.
589
590@end itemize
591
592@node Sparc-Relocs
593@subsection Relocations
594@cindex Sparc relocations
595@cindex relocations, Sparc
596
597ELF relocations are available as defined in the 32-bit and 64-bit
598Sparc ELF specifications.
599
600@code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
601is obtained using @samp{%lo}.  Likewise @code{R_SPARC_HIX22} is
602obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
603using @samp{%lox}.  For example:
604
605@example
606sethi %hi(symbol), %g1
607or    %g1, %lo(symbol), %g1
608
609sethi %hix(symbol), %g1
610xor   %g1, %lox(symbol), %g1
611@end example
612
613These ``high'' mnemonics extract bits 31:10 of their operand,
614and the ``low'' mnemonics extract bits 9:0 of their operand.
615
616V9 code model relocations can be requested as follows:
617
618@itemize @bullet
619@item
620@code{R_SPARC_HH22} is requested using @samp{%hh}.  It can
621also be generated using @samp{%uhi}.
622@item
623@code{R_SPARC_HM10} is requested using @samp{%hm}.  It can
624also be generated using @samp{%ulo}.
625@item
626@code{R_SPARC_LM22} is requested using @samp{%lm}.
627
628@item
629@code{R_SPARC_H44} is requested using @samp{%h44}.
630@item
631@code{R_SPARC_M44} is requested using @samp{%m44}.
632@item
633@code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
634@item
635@code{R_SPARC_H34} is requested using @samp{%h34}.
636@end itemize
637
638The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
639calculates the necessary value, and therefore no explicit
640@code{R_SPARC_L34} relocation needed to be created for this purpose.
641
642The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
643model.  Here is an example abs34 address generation sequence:
644
645@example
646sethi %h34(symbol), %g1
647sllx  %g1, 2, %g1
648or    %g1, %l34(symbol), %g1
649@end example
650
651The PC relative relocation @code{R_SPARC_PC22} can be obtained by
652enclosing an operand inside of @samp{%pc22}.  Likewise, the
653@code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
654These are mostly used when assembling PIC code.  For example, the
655standard PIC sequence on Sparc to get the base of the global offset
656table, PC relative, into a register, can be performed as:
657
658@example
659sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
660add   %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
661@end example
662
663Several relocations exist to allow the link editor to potentially
664optimize GOT data references.  The @code{R_SPARC_GOTDATA_OP_HIX22}
665relocation can obtained by enclosing an operand inside of
666@samp{%gdop_hix22}.  The @code{R_SPARC_GOTDATA_OP_LOX10}
667relocation can obtained by enclosing an operand inside of
668@samp{%gdop_lox10}.  Likewise, @code{R_SPARC_GOTDATA_OP} can be
669obtained by enclosing an operand inside of @samp{%gdop}.
670For example, assuming the GOT base is in register @code{%l7}:
671
672@example
673sethi %gdop_hix22(symbol), %l1
674xor   %l1, %gdop_lox10(symbol), %l1
675ld    [%l7 + %l1], %l2, %gdop(symbol)
676@end example
677
678There are many relocations that can be requested for access to
679thread local storage variables.  All of the Sparc TLS mnemonics
680are supported:
681
682@itemize @bullet
683@item
684@code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
685@item
686@code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
687@item
688@code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
689@item
690@code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
691
692@item
693@code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
694@item
695@code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
696@item
697@code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
698@item
699@code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
700
701@item
702@code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
703@item
704@code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
705@item
706@code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
707
708@item
709@code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
710@item
711@code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
712@item
713@code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
714@item
715@code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
716@item
717@code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
718
719@item
720@code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
721@item
722@code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
723@end itemize
724
725Here are some example TLS model sequences.
726
727First, General Dynamic:
728
729@example
730sethi  %tgd_hi22(symbol), %l1
731add    %l1, %tgd_lo10(symbol), %l1
732add    %l7, %l1, %o0, %tgd_add(symbol)
733call   __tls_get_addr, %tgd_call(symbol)
734nop
735@end example
736
737Local Dynamic:
738
739@example
740sethi  %tldm_hi22(symbol), %l1
741add    %l1, %tldm_lo10(symbol), %l1
742add    %l7, %l1, %o0, %tldm_add(symbol)
743call   __tls_get_addr, %tldm_call(symbol)
744nop
745
746sethi  %tldo_hix22(symbol), %l1
747xor    %l1, %tldo_lox10(symbol), %l1
748add    %o0, %l1, %l1, %tldo_add(symbol)
749@end example
750
751Initial Exec:
752
753@example
754sethi  %tie_hi22(symbol), %l1
755add    %l1, %tie_lo10(symbol), %l1
756ld     [%l7 + %l1], %o0, %tie_ld(symbol)
757add    %g7, %o0, %o0, %tie_add(symbol)
758
759sethi  %tie_hi22(symbol), %l1
760add    %l1, %tie_lo10(symbol), %l1
761ldx    [%l7 + %l1], %o0, %tie_ldx(symbol)
762add    %g7, %o0, %o0, %tie_add(symbol)
763@end example
764
765And finally, Local Exec:
766
767@example
768sethi  %tle_hix22(symbol), %l1
769add    %l1, %tle_lox10(symbol), %l1
770add    %g7, %l1, %l1
771@end example
772
773When assembling for 64-bit, and a secondary constant addend is
774specified in an address expression that would normally generate
775an @code{R_SPARC_LO10} relocation, the assembler will emit an
776@code{R_SPARC_OLO10} instead.
777
778@node Sparc-Size-Translations
779@subsection Size Translations
780@cindex Sparc size translations
781@cindex size, translations, Sparc
782
783Often it is desirable to write code in an operand size agnostic
784manner.  @code{@value{AS}} provides support for this via
785operand size opcode translations.  Translations are supported
786for loads, stores, shifts, compare-and-swap atomics, and the
787@samp{clr} synthetic instruction.
788
789If generating 32-bit code, @code{@value{AS}} will generate the
79032-bit opcode.  Whereas if 64-bit code is being generated,
791the 64-bit opcode will be emitted.  For example @code{ldn}
792will be transformed into @code{ld} for 32-bit code and
793@code{ldx} for 64-bit code.
794
795Here is an example meant to demonstrate all the supported
796opcode translations:
797
798@example
799ldn   [%o0], %o1
800ldna  [%o0] %asi, %o2
801stn   %o1, [%o0]
802stna  %o2, [%o0] %asi
803slln  %o3, 3, %o3
804srln  %o4, 8, %o4
805sran  %o5, 12, %o5
806casn  [%o0], %o1, %o2
807casna [%o0] %asi, %o1, %o2
808clrn  %g1
809@end example
810
811In 32-bit mode @code{@value{AS}} will emit:
812
813@example
814ld   [%o0], %o1
815lda  [%o0] %asi, %o2
816st   %o1, [%o0]
817sta  %o2, [%o0] %asi
818sll  %o3, 3, %o3
819srl  %o4, 8, %o4
820sra  %o5, 12, %o5
821cas  [%o0], %o1, %o2
822casa [%o0] %asi, %o1, %o2
823clr  %g1
824@end example
825
826And in 64-bit mode @code{@value{AS}} will emit:
827
828@example
829ldx   [%o0], %o1
830ldxa  [%o0] %asi, %o2
831stx   %o1, [%o0]
832stxa  %o2, [%o0] %asi
833sllx  %o3, 3, %o3
834srlx  %o4, 8, %o4
835srax  %o5, 12, %o5
836casx  [%o0], %o1, %o2
837casxa [%o0] %asi, %o1, %o2
838clrx  %g1
839@end example
840
841Finally, the @samp{.nword} translating directive is supported
842as well.  It is documented in the section on Sparc machine
843directives.
844
845@node Sparc-Float
846@section Floating Point
847
848@cindex floating point, SPARC (@sc{ieee})
849@cindex SPARC floating point (@sc{ieee})
850The Sparc uses @sc{ieee} floating-point numbers.
851
852@node Sparc-Directives
853@section Sparc Machine Directives
854
855@cindex SPARC machine directives
856@cindex machine directives, SPARC
857The Sparc version of @code{@value{AS}} supports the following additional
858machine directives:
859
860@table @code
861@cindex @code{align} directive, SPARC
862@item .align
863This must be followed by the desired alignment in bytes.
864
865@cindex @code{common} directive, SPARC
866@item .common
867This must be followed by a symbol name, a positive number, and
868@code{"bss"}.  This behaves somewhat like @code{.comm}, but the
869syntax is different.
870
871@cindex @code{half} directive, SPARC
872@item .half
873This is functionally identical to @code{.short}.
874
875@cindex @code{nword} directive, SPARC
876@item .nword
877On the Sparc, the @code{.nword} directive produces native word sized value,
878ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
879with -64 it is equivalent to @code{.xword}.
880
881@cindex @code{proc} directive, SPARC
882@item .proc
883This directive is ignored.  Any text following it on the same
884line is also ignored.
885
886@cindex @code{register} directive, SPARC
887@item .register
888This directive declares use of a global application or system register.
889It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
890the symbol name for that register.  If symbol name is @code{#scratch},
891it is a scratch register, if it is @code{#ignore}, it just suppresses any
892errors about using undeclared global register, but does not emit any
893information about it into the object file.  This can be useful e.g. if you
894save the register before use and restore it after.
895
896@cindex @code{reserve} directive, SPARC
897@item .reserve
898This must be followed by a symbol name, a positive number, and
899@code{"bss"}.  This behaves somewhat like @code{.lcomm}, but the
900syntax is different.
901
902@cindex @code{seg} directive, SPARC
903@item .seg
904This must be followed by @code{"text"}, @code{"data"}, or
905@code{"data1"}.  It behaves like @code{.text}, @code{.data}, or
906@code{.data 1}.
907
908@cindex @code{skip} directive, SPARC
909@item .skip
910This is functionally identical to the @code{.space} directive.
911
912@cindex @code{word} directive, SPARC
913@item .word
914On the Sparc, the @code{.word} directive produces 32 bit values,
915instead of the 16 bit values it produces on many other machines.
916
917@cindex @code{xword} directive, SPARC
918@item .xword
919On the Sparc V9 processor, the @code{.xword} directive produces
92064 bit values.
921@end table
922