1/* tc-m68k.c -- Assemble for the m68k family 2 Copyright (C) 1987-2020 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21#include "as.h" 22#include "safe-ctype.h" 23#include "obstack.h" 24#include "subsegs.h" 25#include "dwarf2dbg.h" 26#include "dw2gencfi.h" 27 28#include "opcode/m68k.h" 29#include "m68k-parse.h" 30#include "elf/m68k.h" 31 32static void m68k_elf_cons (int); 33static void m68k_elf_gnu_attribute (int); 34 35/* This string holds the chars that always start a comment. If the 36 pre-processor is disabled, these aren't very useful. The macro 37 tc_comment_chars points to this. We use this, rather than the 38 usual comment_chars, so that the --bitwise-or option will work. */ 39#if defined (TE_SVR4) || defined (TE_DELTA) 40const char *m68k_comment_chars = "|#"; 41#else 42const char *m68k_comment_chars = "|"; 43#endif 44 45/* This array holds the chars that only start a comment at the beginning of 46 a line. If the line seems to have the form '# 123 filename' 47 .line and .file directives will appear in the pre-processed output */ 48/* Note that input_file.c hand checks for '#' at the beginning of the 49 first line of the input file. This is because the compiler outputs 50 #NO_APP at the beginning of its output. */ 51/* Also note that comments like this one will always work. */ 52const char line_comment_chars[] = "#*"; 53 54const char line_separator_chars[] = ";"; 55 56/* Chars that can be used to separate mant from exp in floating point nums. */ 57const char EXP_CHARS[] = "eE"; 58 59/* Chars that mean this number is a floating point constant, as 60 in "0f12.456" or "0d1.2345e12". */ 61 62const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 63 64/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 65 changed in read.c . Ideally it shouldn't have to know about it at all, 66 but nothing is ideal around here. */ 67 68/* Are we trying to generate PIC code? If so, absolute references 69 ought to be made into linkage table references or pc-relative 70 references. Not implemented. For ELF there are other means 71 to denote pic relocations. */ 72int flag_want_pic; 73 74static int flag_short_refs; /* -l option. */ 75static int flag_long_jumps; /* -S option. */ 76static int flag_keep_pcrel; /* --pcrel option. */ 77 78#ifdef REGISTER_PREFIX_OPTIONAL 79int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 80#else 81int flag_reg_prefix_optional; 82#endif 83 84/* Whether --register-prefix-optional was used on the command line. */ 85static int reg_prefix_optional_seen; 86 87/* The floating point coprocessor to use by default. */ 88static enum m68k_register m68k_float_copnum = COP1; 89 90/* If this is non-zero, then references to number(%pc) will be taken 91 to refer to number, rather than to %pc + number. */ 92static int m68k_abspcadd; 93 94/* If this is non-zero, then the quick forms of the move, add, and sub 95 instructions are used when possible. */ 96static int m68k_quick = 1; 97 98/* If this is non-zero, then if the size is not specified for a base 99 or outer displacement, the assembler assumes that the size should 100 be 32 bits. */ 101static int m68k_rel32 = 1; 102 103/* This is non-zero if m68k_rel32 was set from the command line. */ 104static int m68k_rel32_from_cmdline; 105 106/* The default width to use for an index register when using a base 107 displacement. */ 108static enum m68k_size m68k_index_width_default = SIZE_LONG; 109 110/* We want to warn if any text labels are misaligned. In order to get 111 the right line number, we need to record the line number for each 112 label. */ 113struct label_line 114{ 115 struct label_line *next; 116 symbolS *label; 117 const char *file; 118 unsigned int line; 119 int text; 120}; 121 122/* The list of labels. */ 123 124static struct label_line *labels; 125 126/* The current label. */ 127 128static struct label_line *current_label; 129 130/* Pointer to list holding the opcodes sorted by name. */ 131static struct m68k_opcode const ** m68k_sorted_opcodes; 132 133/* It's an arbitrary name: This means I don't approve of it. 134 See flames below. */ 135static struct obstack robyn; 136 137struct m68k_incant 138 { 139 const char *m_operands; 140 unsigned long m_opcode; 141 short m_opnum; 142 short m_codenum; 143 int m_arch; 144 struct m68k_incant *m_next; 145 }; 146 147#define getone(x) ((((x)->m_opcode)>>16)&0xffff) 148#define gettwo(x) (((x)->m_opcode)&0xffff) 149 150static const enum m68k_register m68000_ctrl[] = { 0 }; 151static const enum m68k_register m68010_ctrl[] = { 152 SFC, DFC, USP, VBR, 153 0 154}; 155static const enum m68k_register m68020_ctrl[] = { 156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, 157 0 158}; 159static const enum m68k_register m68040_ctrl[] = { 160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, 161 USP, VBR, MSP, ISP, MMUSR, URP, SRP, 162 0 163}; 164static const enum m68k_register m68060_ctrl[] = { 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, 166 USP, VBR, URP, SRP, PCR, 167 0 168}; 169static const enum m68k_register mcf_ctrl[] = { 170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, 171 RAMBAR0, RAMBAR1, RAMBAR, MBAR, 172 0 173}; 174static const enum m68k_register mcf51_ctrl[] = { 175 VBR, CPUCR, 176 0 177}; 178static const enum m68k_register mcf5206_ctrl[] = { 179 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, 180 0 181}; 182static const enum m68k_register mcf5208_ctrl[] = { 183 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, 184 0 185}; 186static const enum m68k_register mcf5210a_ctrl[] = { 187 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, 188 0 189}; 190static const enum m68k_register mcf5213_ctrl[] = { 191 VBR, RAMBAR, RAMBAR1, FLASHBAR, 192 0 193}; 194static const enum m68k_register mcf5216_ctrl[] = { 195 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 196 0 197}; 198static const enum m68k_register mcf5221x_ctrl[] = { 199 VBR, FLASHBAR, RAMBAR, RAMBAR1, 200 0 201}; 202static const enum m68k_register mcf52223_ctrl[] = { 203 VBR, FLASHBAR, RAMBAR, RAMBAR1, 204 0 205}; 206static const enum m68k_register mcf52235_ctrl[] = { 207 VBR, FLASHBAR, RAMBAR, RAMBAR1, 208 0 209}; 210static const enum m68k_register mcf5225_ctrl[] = { 211 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, 212 0 213}; 214static const enum m68k_register mcf52259_ctrl[] = { 215 VBR, FLASHBAR, RAMBAR, RAMBAR1, 216 0 217}; 218static const enum m68k_register mcf52277_ctrl[] = { 219 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 220 0 221}; 222static const enum m68k_register mcf5235_ctrl[] = { 223 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 224 0 225}; 226static const enum m68k_register mcf5249_ctrl[] = { 227 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 228 0 229}; 230static const enum m68k_register mcf5250_ctrl[] = { 231 VBR, 232 0 233}; 234static const enum m68k_register mcf5253_ctrl[] = { 235 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 236 0 237}; 238static const enum m68k_register mcf5271_ctrl[] = { 239 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 240 0 241}; 242static const enum m68k_register mcf5272_ctrl[] = { 243 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, 244 0 245}; 246static const enum m68k_register mcf5275_ctrl[] = { 247 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 248 0 249}; 250static const enum m68k_register mcf5282_ctrl[] = { 251 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 252 0 253}; 254static const enum m68k_register mcf53017_ctrl[] = { 255 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 256 0 257}; 258static const enum m68k_register mcf5307_ctrl[] = { 259 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, 260 0 261}; 262static const enum m68k_register mcf5329_ctrl[] = { 263 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 264 0 265}; 266static const enum m68k_register mcf5373_ctrl[] = { 267 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 268 0 269}; 270static const enum m68k_register mcfv4e_ctrl[] = { 271 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 272 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, 273 MBAR, SECMBAR, 274 MPCR /* Multiprocessor Control register */, 275 EDRAMBAR /* Embedded DRAM Base Address Register */, 276 /* Permutation control registers. */ 277 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, 278 PCR3U0, PCR3L0, PCR3U1, PCR3L1, 279 /* Legacy names */ 280 TC /* ASID */, BUSCR /* MMUBAR */, 281 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 282 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, 283 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 284 0 285}; 286static const enum m68k_register mcf5407_ctrl[] = { 287 CACR, ASID, ACR0, ACR1, ACR2, ACR3, 288 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 289 /* Legacy names */ 290 TC /* ASID */, 291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 292 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 293 0 294}; 295static const enum m68k_register mcf54418_ctrl[] = { 296 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, 297 VBR, PC, RAMBAR1, 298 /* Legacy names */ 299 TC /* ASID */, BUSCR /* MMUBAR */, 300 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 301 RAMBAR /* RAMBAR1 */, 302 0 303}; 304static const enum m68k_register mcf54455_ctrl[] = { 305 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 306 VBR, PC, RAMBAR1, 307 /* Legacy names */ 308 TC /* ASID */, BUSCR /* MMUBAR */, 309 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 310 RAMBAR /* RAMBAR1 */, 311 0 312}; 313static const enum m68k_register mcf5475_ctrl[] = { 314 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 315 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 316 /* Legacy names */ 317 TC /* ASID */, BUSCR /* MMUBAR */, 318 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 319 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 320 0 321}; 322static const enum m68k_register mcf5485_ctrl[] = { 323 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 324 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 325 /* Legacy names */ 326 TC /* ASID */, BUSCR /* MMUBAR */, 327 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 328 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 329 0 330}; 331static const enum m68k_register fido_ctrl[] = { 332 SFC, DFC, USP, VBR, CAC, MBO, 333 0 334}; 335#define cpu32_ctrl m68010_ctrl 336 337static const enum m68k_register *control_regs; 338 339/* Internal form of a 68020 instruction. */ 340struct m68k_it 341{ 342 const char *error; 343 const char *args; /* List of opcode info. */ 344 int numargs; 345 346 int numo; /* Number of shorts in opcode. */ 347 short opcode[11]; 348 349 struct m68k_op operands[6]; 350 351 int nexp; /* Number of exprs in use. */ 352 struct m68k_exp exprs[4]; 353 354 int nfrag; /* Number of frags we have to produce. */ 355 struct 356 { 357 int fragoff; /* Where in the current opcode the frag ends. */ 358 symbolS *fadd; 359 offsetT foff; 360 int fragty; 361 } 362 fragb[4]; 363 364 int nrel; /* Num of reloc structs in use. */ 365 struct 366 { 367 int n; 368 expressionS exp; 369 char wid; 370 char pcrel; 371 /* In a pc relative address the difference between the address 372 of the offset and the address that the offset is relative 373 to. This depends on the addressing mode. Basically this 374 is the value to put in the offset field to address the 375 first byte of the offset, without regarding the special 376 significance of some values (in the branch instruction, for 377 example). */ 378 int pcrel_fix; 379 /* Whether this expression needs special pic relocation, and if 380 so, which. */ 381 enum pic_relocation pic_reloc; 382 } 383 reloc[5]; /* Five is enough??? */ 384}; 385 386#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) 387#define float_of_arch(x) ((x) & mfloat) 388#define mmu_of_arch(x) ((x) & mmmu) 389#define arch_coldfire_p(x) ((x) & mcfisa_a) 390#define arch_coldfire_fpu(x) ((x) & cfloat) 391 392/* Macros for determining if cpu supports a specific addressing mode. */ 393#define HAVE_LONG_DISP(x) \ 394 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 395#define HAVE_LONG_CALL(x) \ 396 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 397#define HAVE_LONG_COND(x) \ 398 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 399#define HAVE_LONG_BRANCH(x) \ 400 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) 401#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) 402 403static struct m68k_it the_ins; /* The instruction being assembled. */ 404 405#define op(ex) ((ex)->exp.X_op) 406#define adds(ex) ((ex)->exp.X_add_symbol) 407#define subs(ex) ((ex)->exp.X_op_symbol) 408#define offs(ex) ((ex)->exp.X_add_number) 409 410/* Macros for adding things to the m68k_it struct. */ 411#define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) 412 413/* Like addword, but goes BEFORE general operands. */ 414 415static void 416insop (int w, const struct m68k_incant *opcode) 417{ 418 int z; 419 for (z = the_ins.numo; z > opcode->m_codenum; --z) 420 the_ins.opcode[z] = the_ins.opcode[z - 1]; 421 for (z = 0; z < the_ins.nrel; z++) 422 the_ins.reloc[z].n += 2; 423 for (z = 0; z < the_ins.nfrag; z++) 424 the_ins.fragb[z].fragoff++; 425 the_ins.opcode[opcode->m_codenum] = w; 426 the_ins.numo++; 427} 428 429/* The numo+1 kludge is so we can hit the low order byte of the prev word. 430 Blecch. */ 431static void 432add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) 433{ 434 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' 435 ? the_ins.numo * 2 - 1 436 : (width == 'b' 437 ? the_ins.numo * 2 + 1 438 : the_ins.numo * 2)); 439 the_ins.reloc[the_ins.nrel].exp = exp->exp; 440 the_ins.reloc[the_ins.nrel].wid = width; 441 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; 442 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; 443 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; 444} 445 446/* Cause an extra frag to be generated here, inserting up to 10 bytes 447 (that value is chosen in the frag_var call in md_assemble). TYPE 448 is the subtype of the frag to be generated; its primary type is 449 rs_machine_dependent. 450 451 The TYPE parameter is also used by md_convert_frag_1 and 452 md_estimate_size_before_relax. The appropriate type of fixup will 453 be emitted by md_convert_frag_1. 454 455 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 456static void 457add_frag (symbolS *add, offsetT off, int type) 458{ 459 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; 460 the_ins.fragb[the_ins.nfrag].fadd = add; 461 the_ins.fragb[the_ins.nfrag].foff = off; 462 the_ins.fragb[the_ins.nfrag++].fragty = type; 463} 464 465#define isvar(ex) \ 466 (op (ex) != O_constant && op (ex) != O_big) 467 468static char *crack_operand (char *str, struct m68k_op *opP); 469static int get_num (struct m68k_exp *exp, int ok); 470static int reverse_16_bits (int in); 471static int reverse_8_bits (int in); 472static void install_gen_operand (int mode, int val); 473static void install_operand (int mode, int val); 474static void s_bss (int); 475static void s_data1 (int); 476static void s_data2 (int); 477static void s_even (int); 478static void s_proc (int); 479static void s_chip (int); 480static void s_fopt (int); 481static void s_opt (int); 482static void s_reg (int); 483static void s_restore (int); 484static void s_save (int); 485static void s_mri_if (int); 486static void s_mri_else (int); 487static void s_mri_endi (int); 488static void s_mri_break (int); 489static void s_mri_next (int); 490static void s_mri_for (int); 491static void s_mri_endf (int); 492static void s_mri_repeat (int); 493static void s_mri_until (int); 494static void s_mri_while (int); 495static void s_mri_endw (int); 496static void s_m68k_cpu (int); 497static void s_m68k_arch (int); 498 499struct m68k_cpu 500{ 501 unsigned long arch; /* Architecture features. */ 502 const enum m68k_register *control_regs; /* Control regs on chip */ 503 const char *name; /* Name */ 504 int alias; /* Alias for a canonical name. If 1, then 505 succeeds canonical name, if -1 then 506 succeeds canonical name, if <-1 ||>1 this is a 507 deprecated name, and the next/previous name 508 should be used. */ 509}; 510 511/* We hold flags for features explicitly enabled and explicitly 512 disabled. */ 513static int current_architecture; 514static int not_current_architecture; 515static const struct m68k_cpu *selected_arch; 516static const struct m68k_cpu *selected_cpu; 517static int initialized; 518 519/* Architecture models. */ 520static const struct m68k_cpu m68k_archs[] = 521{ 522 {m68000, m68000_ctrl, "68000", 0}, 523 {m68010, m68010_ctrl, "68010", 0}, 524 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 525 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 526 {m68040, m68040_ctrl, "68040", 0}, 527 {m68060, m68060_ctrl, "68060", 0}, 528 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 529 {fido_a, fido_ctrl, "fidoa", 0}, 530 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, 531 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, 532 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, 533 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, 534 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, 535 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, 536 {0,0,NULL, 0} 537}; 538 539/* For -mno-mac we want to turn off all types of mac. */ 540static const unsigned no_mac = mcfmac | mcfemac; 541 542/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 543 for either. */ 544static const struct m68k_cpu m68k_extensions[] = 545{ 546 {m68851, NULL, "68851", -1}, 547 {m68881, NULL, "68881", -1}, 548 {m68881, NULL, "68882", -1}, 549 550 {cfloat|m68881, NULL, "float", 0}, 551 552 {mcfhwdiv, NULL, "div", 1}, 553 {mcfusp, NULL, "usp", 1}, 554 {mcfmac, (void *)&no_mac, "mac", 1}, 555 {mcfemac, NULL, "emac", 1}, 556 557 {0,NULL,NULL, 0} 558}; 559 560/* Processor list */ 561static const struct m68k_cpu m68k_cpus[] = 562{ 563 {m68000, m68000_ctrl, "68000", 0}, 564 {m68000, m68000_ctrl, "68ec000", 1}, 565 {m68000, m68000_ctrl, "68hc000", 1}, 566 {m68000, m68000_ctrl, "68hc001", 1}, 567 {m68000, m68000_ctrl, "68008", 1}, 568 {m68000, m68000_ctrl, "68302", 1}, 569 {m68000, m68000_ctrl, "68306", 1}, 570 {m68000, m68000_ctrl, "68307", 1}, 571 {m68000, m68000_ctrl, "68322", 1}, 572 {m68000, m68000_ctrl, "68356", 1}, 573 {m68010, m68010_ctrl, "68010", 0}, 574 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 575 {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, 576 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, 577 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 578 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, 579 {m68040, m68040_ctrl, "68040", 0}, 580 {m68040, m68040_ctrl, "68ec040", 1}, 581 {m68060, m68060_ctrl, "68060", 0}, 582 {m68060, m68060_ctrl, "68ec060", 1}, 583 584 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 585 {cpu32|m68881, cpu32_ctrl, "68330", 1}, 586 {cpu32|m68881, cpu32_ctrl, "68331", 1}, 587 {cpu32|m68881, cpu32_ctrl, "68332", 1}, 588 {cpu32|m68881, cpu32_ctrl, "68333", 1}, 589 {cpu32|m68881, cpu32_ctrl, "68334", 1}, 590 {cpu32|m68881, cpu32_ctrl, "68336", 1}, 591 {cpu32|m68881, cpu32_ctrl, "68340", 1}, 592 {cpu32|m68881, cpu32_ctrl, "68341", 1}, 593 {cpu32|m68881, cpu32_ctrl, "68349", 1}, 594 {cpu32|m68881, cpu32_ctrl, "68360", 1}, 595 596 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, 597 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, 598 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, 599 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, 600 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, 601 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, 602 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, 603 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, 604 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, 605 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, 606 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, 607 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, 608 609 {mcfisa_a, mcf_ctrl, "5200", 0}, 610 {mcfisa_a, mcf_ctrl, "5202", 1}, 611 {mcfisa_a, mcf_ctrl, "5204", 1}, 612 {mcfisa_a, mcf5206_ctrl, "5206", 1}, 613 614 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, 615 616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, 617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, 618 619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, 620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, 621 622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, 623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, 624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, 625 626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, 627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, 628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, 629 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, 631 632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, 633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, 634 635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, 636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, 637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, 639 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, 641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, 642 643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, 645 646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, 648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, 649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, 650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, 651 652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, 653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, 654 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, 655 656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, 657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, 659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, 661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, 662 663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, 664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, 665 666 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, 667 668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, 669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, 670 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, 672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, 673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, 674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, 675 676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, 677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, 678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, 679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, 680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, 681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, 682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, 683 684 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, 685 686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, 687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, 688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, 689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, 690 691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, 692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, 693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, 694 695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, 696 697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, 698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, 699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, 700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, 701 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, 702 703 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, 704 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, 705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, 706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, 707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, 708 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, 709 710 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, 711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, 712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, 713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, 714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, 715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, 716 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, 717 718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, 719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, 720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, 721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, 722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, 723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, 724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, 725 726 {fido_a, fido_ctrl, "fidoa", 0}, 727 {fido_a, fido_ctrl, "fido", 1}, 728 729 {0,NULL,NULL, 0} 730 }; 731 732static const struct m68k_cpu *m68k_lookup_cpu 733(const char *, const struct m68k_cpu *, int, int *); 734static int m68k_set_arch (const char *, int, int); 735static int m68k_set_cpu (const char *, int, int); 736static int m68k_set_extension (const char *, int, int); 737static void m68k_init_arch (void); 738 739/* This is the assembler relaxation table for m68k. m68k is a rich CISC 740 architecture and we have a lot of relaxation modes. */ 741 742/* Macros used in the relaxation code. */ 743#define TAB(x,y) (((x) << 2) + (y)) 744#define TABTYPE(x) ((x) >> 2) 745 746/* Relaxation states. */ 747#define BYTE 0 748#define SHORT 1 749#define LONG 2 750#define SZ_UNDEF 3 751 752/* Here are all the relaxation modes we support. First we can relax ordinary 753 branches. On 68020 and higher and on CPU32 all branch instructions take 754 three forms, so on these CPUs all branches always remain as such. When we 755 have to expand to the LONG form on a 68000, though, we substitute an 756 absolute jump instead. This is a direct replacement for unconditional 757 branches and a branch over a jump for conditional branches. However, if the 758 user requires PIC and disables this with --pcrel, we can only relax between 759 BYTE and SHORT forms, punting if that isn't enough. This gives us four 760 different relaxation modes for branches: */ 761 762#define BRANCHBWL 0 /* Branch byte, word, or long. */ 763#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ 764#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ 765#define BRANCHBW 3 /* Branch byte or word. */ 766 767/* We also relax coprocessor branches and DBcc's. All CPUs that support 768 coprocessor branches support them in word and long forms, so we have only 769 one relaxation mode for them. DBcc's are word only on all CPUs. We can 770 relax them to the LONG form with a branch-around sequence. This sequence 771 can use a long branch (if available) or an absolute jump (if acceptable). 772 This gives us two relaxation modes. If long branches are not available and 773 absolute jumps are not acceptable, we don't relax DBcc's. */ 774 775#define FBRANCH 4 /* Coprocessor branch. */ 776#define DBCCLBR 5 /* DBcc relaxable with a long branch. */ 777#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ 778 779/* That's all for instruction relaxation. However, we also relax PC-relative 780 operands. Specifically, we have three operand relaxation modes. On the 781 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and 782 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the 783 two. Also PC+displacement+index operands in their simple form (with a non- 784 suppressed index without memory indirection) are supported on all CPUs, but 785 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher 786 and on CPU32 we relax it to SHORT and LONG forms as well using the extended 787 form of the PC+displacement+index operand. Finally, some absolute operands 788 can be relaxed down to 16-bit PC-relative. */ 789 790#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ 791#define PCINDEX 8 /* PC + displacement + index. */ 792#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ 793 794/* This relaxation is required for branches where there is no long 795 branch and we are in pcrel mode. We generate a bne/beq pair. */ 796#define BRANCHBWPL 10 /* Branch byte, word or pair of longs 797 */ 798 799/* Note that calls to frag_var need to specify the maximum expansion 800 needed; this is currently 12 bytes for bne/beq pair. */ 801#define FRAG_VAR_SIZE 12 802 803/* The fields are: 804 How far Forward this mode will reach: 805 How far Backward this mode will reach: 806 How many bytes this mode will add to the size of the frag 807 Which mode to go to if the offset won't fit in this one 808 809 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ 810relax_typeS md_relax_table[] = 811{ 812 { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, 813 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, 814 { 0, 0, 4, 0 }, 815 { 1, 1, 0, 0 }, 816 817 { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, 818 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, 819 { 0, 0, 4, 0 }, 820 { 1, 1, 0, 0 }, 821 822 { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, 823 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, 824 { 0, 0, 6, 0 }, 825 { 1, 1, 0, 0 }, 826 827 { 127, -128, 0, TAB (BRANCHBW, SHORT) }, 828 { 0, 0, 2, 0 }, 829 { 1, 1, 0, 0 }, 830 { 1, 1, 0, 0 }, 831 832 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ 833 { 32767, -32768, 2, TAB (FBRANCH, LONG) }, 834 { 0, 0, 4, 0 }, 835 { 1, 1, 0, 0 }, 836 837 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 838 { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, 839 { 0, 0, 10, 0 }, 840 { 1, 1, 0, 0 }, 841 842 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 843 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, 844 { 0, 0, 10, 0 }, 845 { 1, 1, 0, 0 }, 846 847 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ 848 { 32767, -32768, 2, TAB (PCREL1632, LONG) }, 849 { 0, 0, 6, 0 }, 850 { 1, 1, 0, 0 }, 851 852 { 125, -130, 0, TAB (PCINDEX, SHORT) }, 853 { 32765, -32770, 2, TAB (PCINDEX, LONG) }, 854 { 0, 0, 4, 0 }, 855 { 1, 1, 0, 0 }, 856 857 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ 858 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, 859 { 0, 0, 4, 0 }, 860 { 1, 1, 0, 0 }, 861 862 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, 863 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, 864 { 0, 0, 10, 0 }, 865 { 1, 1, 0, 0 }, 866}; 867 868/* These are the machine dependent pseudo-ops. These are included so 869 the assembler can work on the output from the SUN C compiler, which 870 generates these. */ 871 872/* This table describes all the machine specific pseudo-ops the assembler 873 has to support. The fields are: 874 pseudo-op name without dot 875 function to call to execute this pseudo-op 876 Integer arg to pass to the function. */ 877const pseudo_typeS md_pseudo_table[] = 878{ 879 {"data1", s_data1, 0}, 880 {"data2", s_data2, 0}, 881 {"bss", s_bss, 0}, 882 {"even", s_even, 0}, 883 {"skip", s_space, 0}, 884 {"proc", s_proc, 0}, 885 {"align", s_align_bytes, 0}, 886 {"swbeg", s_ignore, 0}, 887 {"long", m68k_elf_cons, 4}, 888 {"extend", float_cons, 'x'}, 889 {"ldouble", float_cons, 'x'}, 890 891 {"arch", s_m68k_arch, 0}, 892 {"cpu", s_m68k_cpu, 0}, 893 {"gnu_attribute", m68k_elf_gnu_attribute, 0}, 894 895 /* The following pseudo-ops are supported for MRI compatibility. */ 896 {"chip", s_chip, 0}, 897 {"comline", s_space, 1}, 898 {"fopt", s_fopt, 0}, 899 {"mask2", s_ignore, 0}, 900 {"opt", s_opt, 0}, 901 {"reg", s_reg, 0}, 902 {"restore", s_restore, 0}, 903 {"save", s_save, 0}, 904 905 {"if", s_mri_if, 0}, 906 {"if.b", s_mri_if, 'b'}, 907 {"if.w", s_mri_if, 'w'}, 908 {"if.l", s_mri_if, 'l'}, 909 {"else", s_mri_else, 0}, 910 {"else.s", s_mri_else, 's'}, 911 {"else.l", s_mri_else, 'l'}, 912 {"endi", s_mri_endi, 0}, 913 {"break", s_mri_break, 0}, 914 {"break.s", s_mri_break, 's'}, 915 {"break.l", s_mri_break, 'l'}, 916 {"next", s_mri_next, 0}, 917 {"next.s", s_mri_next, 's'}, 918 {"next.l", s_mri_next, 'l'}, 919 {"for", s_mri_for, 0}, 920 {"for.b", s_mri_for, 'b'}, 921 {"for.w", s_mri_for, 'w'}, 922 {"for.l", s_mri_for, 'l'}, 923 {"endf", s_mri_endf, 0}, 924 {"repeat", s_mri_repeat, 0}, 925 {"until", s_mri_until, 0}, 926 {"until.b", s_mri_until, 'b'}, 927 {"until.w", s_mri_until, 'w'}, 928 {"until.l", s_mri_until, 'l'}, 929 {"while", s_mri_while, 0}, 930 {"while.b", s_mri_while, 'b'}, 931 {"while.w", s_mri_while, 'w'}, 932 {"while.l", s_mri_while, 'l'}, 933 {"endw", s_mri_endw, 0}, 934 935 {0, 0, 0} 936}; 937 938/* The mote pseudo ops are put into the opcode table, since they 939 don't start with a . they look like opcodes to gas. */ 940 941const pseudo_typeS mote_pseudo_table[] = 942{ 943 944 {"dcl", cons, 4}, 945 {"dc", cons, 2}, 946 {"dcw", cons, 2}, 947 {"dcb", cons, 1}, 948 949 {"dsl", s_space, 4}, 950 {"ds", s_space, 2}, 951 {"dsw", s_space, 2}, 952 {"dsb", s_space, 1}, 953 954 {"xdef", s_globl, 0}, 955 {"align", s_align_bytes, 0}, 956 {0, 0, 0} 957}; 958 959/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host 960 gives identical results to a 32-bit host. */ 961#define TRUNC(X) ((valueT) (X) & 0xffffffff) 962#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) 963 964#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) 965#define isubyte(x) ((valueT) TRUNC (x) < 0x100) 966#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) 967#define isuword(x) ((valueT) TRUNC (x) < 0x10000) 968 969#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) 970#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) 971#define islong(x) (1) 972 973static char notend_table[256]; 974static char alt_notend_table[256]; 975#define notend(s) \ 976 (! (notend_table[(unsigned char) *s] \ 977 || (*s == ':' \ 978 && alt_notend_table[(unsigned char) s[1]]))) 979 980 981/* Return zero if the reference to SYMBOL from within the same segment may 982 be relaxed. */ 983 984/* On an ELF system, we can't relax an externally visible symbol, 985 because it may be overridden by a shared library. However, if 986 TARGET_OS is "elf", then we presume that we are assembling for an 987 embedded system, in which case we don't have to worry about shared 988 libraries, and we can relax any external sym. */ 989 990#define relaxable_symbol(symbol) \ 991 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ 992 || S_IS_WEAK (symbol))) 993 994/* Compute the relocation code for a fixup of SIZE bytes, using pc 995 relative relocation if PCREL is non-zero. PIC says whether a special 996 pic relocation was requested. */ 997 998static bfd_reloc_code_real_type 999get_reloc_code (int size, int pcrel, enum pic_relocation pic) 1000{ 1001 switch (pic) 1002 { 1003 case pic_got_pcrel: 1004 switch (size) 1005 { 1006 case 1: 1007 return BFD_RELOC_8_GOT_PCREL; 1008 case 2: 1009 return BFD_RELOC_16_GOT_PCREL; 1010 case 4: 1011 return BFD_RELOC_32_GOT_PCREL; 1012 } 1013 break; 1014 1015 case pic_got_off: 1016 switch (size) 1017 { 1018 case 1: 1019 return BFD_RELOC_8_GOTOFF; 1020 case 2: 1021 return BFD_RELOC_16_GOTOFF; 1022 case 4: 1023 return BFD_RELOC_32_GOTOFF; 1024 } 1025 break; 1026 1027 case pic_plt_pcrel: 1028 switch (size) 1029 { 1030 case 1: 1031 return BFD_RELOC_8_PLT_PCREL; 1032 case 2: 1033 return BFD_RELOC_16_PLT_PCREL; 1034 case 4: 1035 return BFD_RELOC_32_PLT_PCREL; 1036 } 1037 break; 1038 1039 case pic_plt_off: 1040 switch (size) 1041 { 1042 case 1: 1043 return BFD_RELOC_8_PLTOFF; 1044 case 2: 1045 return BFD_RELOC_16_PLTOFF; 1046 case 4: 1047 return BFD_RELOC_32_PLTOFF; 1048 } 1049 break; 1050 1051 case pic_tls_gd: 1052 switch (size) 1053 { 1054 case 1: 1055 return BFD_RELOC_68K_TLS_GD8; 1056 case 2: 1057 return BFD_RELOC_68K_TLS_GD16; 1058 case 4: 1059 return BFD_RELOC_68K_TLS_GD32; 1060 } 1061 break; 1062 1063 case pic_tls_ldm: 1064 switch (size) 1065 { 1066 case 1: 1067 return BFD_RELOC_68K_TLS_LDM8; 1068 case 2: 1069 return BFD_RELOC_68K_TLS_LDM16; 1070 case 4: 1071 return BFD_RELOC_68K_TLS_LDM32; 1072 } 1073 break; 1074 1075 case pic_tls_ldo: 1076 switch (size) 1077 { 1078 case 1: 1079 return BFD_RELOC_68K_TLS_LDO8; 1080 case 2: 1081 return BFD_RELOC_68K_TLS_LDO16; 1082 case 4: 1083 return BFD_RELOC_68K_TLS_LDO32; 1084 } 1085 break; 1086 1087 case pic_tls_ie: 1088 switch (size) 1089 { 1090 case 1: 1091 return BFD_RELOC_68K_TLS_IE8; 1092 case 2: 1093 return BFD_RELOC_68K_TLS_IE16; 1094 case 4: 1095 return BFD_RELOC_68K_TLS_IE32; 1096 } 1097 break; 1098 1099 case pic_tls_le: 1100 switch (size) 1101 { 1102 case 1: 1103 return BFD_RELOC_68K_TLS_LE8; 1104 case 2: 1105 return BFD_RELOC_68K_TLS_LE16; 1106 case 4: 1107 return BFD_RELOC_68K_TLS_LE32; 1108 } 1109 break; 1110 1111 case pic_none: 1112 if (pcrel) 1113 { 1114 switch (size) 1115 { 1116 case 1: 1117 return BFD_RELOC_8_PCREL; 1118 case 2: 1119 return BFD_RELOC_16_PCREL; 1120 case 4: 1121 return BFD_RELOC_32_PCREL; 1122 } 1123 } 1124 else 1125 { 1126 switch (size) 1127 { 1128 case 1: 1129 return BFD_RELOC_8; 1130 case 2: 1131 return BFD_RELOC_16; 1132 case 4: 1133 return BFD_RELOC_32; 1134 } 1135 } 1136 } 1137 1138 if (pcrel) 1139 { 1140 if (pic == pic_none) 1141 as_bad (_("Can not do %d byte pc-relative relocation"), size); 1142 else 1143 as_bad (_("Can not do %d byte pc-relative pic relocation"), size); 1144 } 1145 else 1146 { 1147 if (pic == pic_none) 1148 as_bad (_("Can not do %d byte relocation"), size); 1149 else 1150 as_bad (_("Can not do %d byte pic relocation"), size); 1151 } 1152 1153 return BFD_RELOC_NONE; 1154} 1155 1156/* Here we decide which fixups can be adjusted to make them relative 1157 to the beginning of the section instead of the symbol. Basically 1158 we need to make sure that the dynamic relocations are done 1159 correctly, so in some cases we force the original symbol to be 1160 used. */ 1161int 1162tc_m68k_fix_adjustable (fixS *fixP) 1163{ 1164 /* Adjust_reloc_syms doesn't know about the GOT. */ 1165 switch (fixP->fx_r_type) 1166 { 1167 case BFD_RELOC_8_GOT_PCREL: 1168 case BFD_RELOC_16_GOT_PCREL: 1169 case BFD_RELOC_32_GOT_PCREL: 1170 case BFD_RELOC_8_GOTOFF: 1171 case BFD_RELOC_16_GOTOFF: 1172 case BFD_RELOC_32_GOTOFF: 1173 case BFD_RELOC_8_PLT_PCREL: 1174 case BFD_RELOC_16_PLT_PCREL: 1175 case BFD_RELOC_32_PLT_PCREL: 1176 case BFD_RELOC_8_PLTOFF: 1177 case BFD_RELOC_16_PLTOFF: 1178 case BFD_RELOC_32_PLTOFF: 1179 case BFD_RELOC_68K_TLS_GD32: 1180 case BFD_RELOC_68K_TLS_GD16: 1181 case BFD_RELOC_68K_TLS_GD8: 1182 case BFD_RELOC_68K_TLS_LDM32: 1183 case BFD_RELOC_68K_TLS_LDM16: 1184 case BFD_RELOC_68K_TLS_LDM8: 1185 case BFD_RELOC_68K_TLS_LDO32: 1186 case BFD_RELOC_68K_TLS_LDO16: 1187 case BFD_RELOC_68K_TLS_LDO8: 1188 case BFD_RELOC_68K_TLS_IE32: 1189 case BFD_RELOC_68K_TLS_IE16: 1190 case BFD_RELOC_68K_TLS_IE8: 1191 case BFD_RELOC_68K_TLS_LE32: 1192 case BFD_RELOC_68K_TLS_LE16: 1193 case BFD_RELOC_68K_TLS_LE8: 1194 return 0; 1195 1196 case BFD_RELOC_VTABLE_INHERIT: 1197 case BFD_RELOC_VTABLE_ENTRY: 1198 return 0; 1199 1200 default: 1201 return 1; 1202 } 1203} 1204 1205arelent * 1206tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 1207{ 1208 arelent *reloc; 1209 bfd_reloc_code_real_type code; 1210 1211 /* If the tcbit is set, then this was a fixup of a negative value 1212 that was never resolved. We do not have a reloc to handle this, 1213 so just return. We assume that other code will have detected this 1214 situation and produced a helpful error message, so we just tell the 1215 user that the reloc cannot be produced. */ 1216 if (fixp->fx_tcbit) 1217 { 1218 if (fixp->fx_addsy) 1219 as_bad_where (fixp->fx_file, fixp->fx_line, 1220 _("Unable to produce reloc against symbol '%s'"), 1221 S_GET_NAME (fixp->fx_addsy)); 1222 return NULL; 1223 } 1224 1225 if (fixp->fx_r_type != BFD_RELOC_NONE) 1226 { 1227 code = fixp->fx_r_type; 1228 1229 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible 1230 that fixup_segment converted a non-PC relative reloc into a 1231 PC relative reloc. In such a case, we need to convert the 1232 reloc code. */ 1233 if (fixp->fx_pcrel) 1234 { 1235 switch (code) 1236 { 1237 case BFD_RELOC_8: 1238 code = BFD_RELOC_8_PCREL; 1239 break; 1240 case BFD_RELOC_16: 1241 code = BFD_RELOC_16_PCREL; 1242 break; 1243 case BFD_RELOC_32: 1244 code = BFD_RELOC_32_PCREL; 1245 break; 1246 case BFD_RELOC_8_PCREL: 1247 case BFD_RELOC_16_PCREL: 1248 case BFD_RELOC_32_PCREL: 1249 case BFD_RELOC_8_GOT_PCREL: 1250 case BFD_RELOC_16_GOT_PCREL: 1251 case BFD_RELOC_32_GOT_PCREL: 1252 case BFD_RELOC_8_GOTOFF: 1253 case BFD_RELOC_16_GOTOFF: 1254 case BFD_RELOC_32_GOTOFF: 1255 case BFD_RELOC_8_PLT_PCREL: 1256 case BFD_RELOC_16_PLT_PCREL: 1257 case BFD_RELOC_32_PLT_PCREL: 1258 case BFD_RELOC_8_PLTOFF: 1259 case BFD_RELOC_16_PLTOFF: 1260 case BFD_RELOC_32_PLTOFF: 1261 case BFD_RELOC_68K_TLS_GD32: 1262 case BFD_RELOC_68K_TLS_GD16: 1263 case BFD_RELOC_68K_TLS_GD8: 1264 case BFD_RELOC_68K_TLS_LDM32: 1265 case BFD_RELOC_68K_TLS_LDM16: 1266 case BFD_RELOC_68K_TLS_LDM8: 1267 case BFD_RELOC_68K_TLS_LDO32: 1268 case BFD_RELOC_68K_TLS_LDO16: 1269 case BFD_RELOC_68K_TLS_LDO8: 1270 case BFD_RELOC_68K_TLS_IE32: 1271 case BFD_RELOC_68K_TLS_IE16: 1272 case BFD_RELOC_68K_TLS_IE8: 1273 case BFD_RELOC_68K_TLS_LE32: 1274 case BFD_RELOC_68K_TLS_LE16: 1275 case BFD_RELOC_68K_TLS_LE8: 1276 break; 1277 default: 1278 as_bad_where (fixp->fx_file, fixp->fx_line, 1279 _("Cannot make %s relocation PC relative"), 1280 bfd_get_reloc_code_name (code)); 1281 } 1282 } 1283 } 1284 else 1285 { 1286#define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) 1287 switch (F (fixp->fx_size, fixp->fx_pcrel)) 1288 { 1289#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break 1290 MAP (1, 0, BFD_RELOC_8); 1291 MAP (2, 0, BFD_RELOC_16); 1292 MAP (4, 0, BFD_RELOC_32); 1293 MAP (1, 1, BFD_RELOC_8_PCREL); 1294 MAP (2, 1, BFD_RELOC_16_PCREL); 1295 MAP (4, 1, BFD_RELOC_32_PCREL); 1296 default: 1297 abort (); 1298 } 1299 } 1300#undef F 1301#undef MAP 1302 1303 reloc = XNEW (arelent); 1304 reloc->sym_ptr_ptr = XNEW (asymbol *); 1305 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1306 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1307 if (!fixp->fx_pcrel) 1308 reloc->addend = fixp->fx_addnumber; 1309 else 1310 reloc->addend = (section->vma 1311 + fixp->fx_pcrel_adjust 1312 + fixp->fx_addnumber 1313 + md_pcrel_from (fixp)); 1314 1315 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 1316 gas_assert (reloc->howto != 0); 1317 1318 return reloc; 1319} 1320 1321/* Handle of the OPCODE hash table. NULL means any use before 1322 m68k_ip_begin() will crash. */ 1323static htab_t op_hash; 1324 1325/* Assemble an m68k instruction. */ 1326 1327static void 1328m68k_ip (char *instring) 1329{ 1330 char *p; 1331 struct m68k_op *opP; 1332 const struct m68k_incant *opcode; 1333 const char *s; 1334 int tmpreg = 0, baseo = 0, outro = 0, nextword; 1335 char *pdot, *pdotmove; 1336 enum m68k_size siz1, siz2; 1337 char c; 1338 int losing; 1339 int opsfound; 1340 struct m68k_op operands_backup[6]; 1341 LITTLENUM_TYPE words[6]; 1342 LITTLENUM_TYPE *wordp; 1343 unsigned long ok_arch = 0; 1344 1345 if (*instring == ' ') 1346 instring++; /* Skip leading whitespace. */ 1347 1348 /* Scan up to end of operation-code, which MUST end in end-of-string 1349 or exactly 1 space. */ 1350 pdot = 0; 1351 for (p = instring; *p != '\0'; p++) 1352 { 1353 if (*p == ' ') 1354 break; 1355 if (*p == '.') 1356 pdot = p; 1357 } 1358 1359 if (p == instring) 1360 { 1361 the_ins.error = _("No operator"); 1362 return; 1363 } 1364 1365 /* p now points to the end of the opcode name, probably whitespace. 1366 Make sure the name is null terminated by clobbering the 1367 whitespace, look it up in the hash table, then fix it back. 1368 Remove a dot, first, since the opcode tables have none. */ 1369 if (pdot != NULL) 1370 { 1371 for (pdotmove = pdot; pdotmove < p; pdotmove++) 1372 *pdotmove = pdotmove[1]; 1373 p--; 1374 } 1375 1376 c = *p; 1377 *p = '\0'; 1378 opcode = (const struct m68k_incant *) str_hash_find (op_hash, instring); 1379 *p = c; 1380 1381 if (pdot != NULL) 1382 { 1383 for (pdotmove = p; pdotmove > pdot; pdotmove--) 1384 *pdotmove = pdotmove[-1]; 1385 *pdot = '.'; 1386 ++p; 1387 } 1388 1389 if (opcode == NULL) 1390 { 1391 the_ins.error = _("Unknown operator"); 1392 return; 1393 } 1394 1395 /* Found a legitimate opcode, start matching operands. */ 1396 while (*p == ' ') 1397 ++p; 1398 1399 if (opcode->m_operands == 0) 1400 { 1401 char *old = input_line_pointer; 1402 *old = '\n'; 1403 input_line_pointer = p; 1404 /* Ahh - it's a motorola style pseudo op. */ 1405 mote_pseudo_table[opcode->m_opnum].poc_handler 1406 (mote_pseudo_table[opcode->m_opnum].poc_val); 1407 input_line_pointer = old; 1408 *old = 0; 1409 1410 return; 1411 } 1412 1413 if (flag_mri && opcode->m_opnum == 0) 1414 { 1415 /* In MRI mode, random garbage is allowed after an instruction 1416 which accepts no operands. */ 1417 the_ins.args = opcode->m_operands; 1418 the_ins.numargs = opcode->m_opnum; 1419 the_ins.numo = opcode->m_codenum; 1420 the_ins.opcode[0] = getone (opcode); 1421 the_ins.opcode[1] = gettwo (opcode); 1422 return; 1423 } 1424 1425 for (opP = &the_ins.operands[0]; *p; opP++) 1426 { 1427 p = crack_operand (p, opP); 1428 1429 if (opP->error) 1430 { 1431 the_ins.error = opP->error; 1432 return; 1433 } 1434 } 1435 1436 opsfound = opP - &the_ins.operands[0]; 1437 1438 /* This ugly hack is to support the floating pt opcodes in their 1439 standard form. Essentially, we fake a first entry of type COP#1 */ 1440 if (opcode->m_operands[0] == 'I') 1441 { 1442 int n; 1443 1444 for (n = opsfound; n > 0; --n) 1445 the_ins.operands[n] = the_ins.operands[n - 1]; 1446 1447 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); 1448 the_ins.operands[0].mode = CONTROL; 1449 the_ins.operands[0].reg = m68k_float_copnum; 1450 opsfound++; 1451 } 1452 1453 /* We've got the operands. Find an opcode that'll accept them. */ 1454 for (losing = 0;;) 1455 { 1456 /* If we didn't get the right number of ops, or we have no 1457 common model with this pattern then reject this pattern. */ 1458 1459 ok_arch |= opcode->m_arch; 1460 if (opsfound != opcode->m_opnum 1461 || ((opcode->m_arch & current_architecture) == 0)) 1462 ++losing; 1463 else 1464 { 1465 int i; 1466 1467 /* Make a copy of the operands of this insn so that 1468 we can modify them safely, should we want to. */ 1469 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); 1470 for (i = 0; i < opsfound; i++) 1471 operands_backup[i] = the_ins.operands[i]; 1472 1473 for (s = opcode->m_operands, opP = &operands_backup[0]; 1474 *s && !losing; 1475 s += 2, opP++) 1476 { 1477 /* Warning: this switch is huge! */ 1478 /* I've tried to organize the cases into this order: 1479 non-alpha first, then alpha by letter. Lower-case 1480 goes directly before uppercase counterpart. */ 1481 /* Code with multiple case ...: gets sorted by the lowest 1482 case ... it belongs to. I hope this makes sense. */ 1483 switch (*s) 1484 { 1485 case '!': 1486 switch (opP->mode) 1487 { 1488 case IMMED: 1489 case DREG: 1490 case AREG: 1491 case FPREG: 1492 case CONTROL: 1493 case AINC: 1494 case ADEC: 1495 case REGLST: 1496 losing++; 1497 break; 1498 default: 1499 break; 1500 } 1501 break; 1502 1503 case '<': 1504 switch (opP->mode) 1505 { 1506 case DREG: 1507 case AREG: 1508 case FPREG: 1509 case CONTROL: 1510 case IMMED: 1511 case ADEC: 1512 case REGLST: 1513 losing++; 1514 break; 1515 default: 1516 break; 1517 } 1518 break; 1519 1520 case '>': 1521 switch (opP->mode) 1522 { 1523 case DREG: 1524 case AREG: 1525 case FPREG: 1526 case CONTROL: 1527 case IMMED: 1528 case AINC: 1529 case REGLST: 1530 losing++; 1531 break; 1532 case ABSL: 1533 break; 1534 default: 1535 if (opP->reg == PC 1536 || opP->reg == ZPC) 1537 losing++; 1538 break; 1539 } 1540 break; 1541 1542 case 'm': 1543 switch (opP->mode) 1544 { 1545 case DREG: 1546 case AREG: 1547 case AINDR: 1548 case AINC: 1549 case ADEC: 1550 break; 1551 default: 1552 losing++; 1553 } 1554 break; 1555 1556 case 'n': 1557 switch (opP->mode) 1558 { 1559 case DISP: 1560 break; 1561 default: 1562 losing++; 1563 } 1564 break; 1565 1566 case 'o': 1567 switch (opP->mode) 1568 { 1569 case BASE: 1570 case ABSL: 1571 case IMMED: 1572 break; 1573 default: 1574 losing++; 1575 } 1576 break; 1577 1578 case 'p': 1579 switch (opP->mode) 1580 { 1581 case DREG: 1582 case AREG: 1583 case AINDR: 1584 case AINC: 1585 case ADEC: 1586 break; 1587 case DISP: 1588 if (opP->reg == PC || opP->reg == ZPC) 1589 losing++; 1590 break; 1591 default: 1592 losing++; 1593 } 1594 break; 1595 1596 case 'q': 1597 switch (opP->mode) 1598 { 1599 case DREG: 1600 case AINDR: 1601 case AINC: 1602 case ADEC: 1603 break; 1604 case DISP: 1605 if (opP->reg == PC || opP->reg == ZPC) 1606 losing++; 1607 break; 1608 default: 1609 losing++; 1610 break; 1611 } 1612 break; 1613 1614 case 'v': 1615 switch (opP->mode) 1616 { 1617 case DREG: 1618 case AINDR: 1619 case AINC: 1620 case ADEC: 1621 case ABSL: 1622 break; 1623 case DISP: 1624 if (opP->reg == PC || opP->reg == ZPC) 1625 losing++; 1626 break; 1627 default: 1628 losing++; 1629 break; 1630 } 1631 break; 1632 1633 case '#': 1634 if (opP->mode != IMMED) 1635 losing++; 1636 else if (s[1] == 'b' 1637 && ! isvar (&opP->disp) 1638 && (opP->disp.exp.X_op != O_constant 1639 || ! isbyte (opP->disp.exp.X_add_number))) 1640 losing++; 1641 else if (s[1] == 'B' 1642 && ! isvar (&opP->disp) 1643 && (opP->disp.exp.X_op != O_constant 1644 || ! issbyte (opP->disp.exp.X_add_number))) 1645 losing++; 1646 else if (s[1] == 'w' 1647 && ! isvar (&opP->disp) 1648 && (opP->disp.exp.X_op != O_constant 1649 || ! isword (opP->disp.exp.X_add_number))) 1650 losing++; 1651 else if (s[1] == 'W' 1652 && ! isvar (&opP->disp) 1653 && (opP->disp.exp.X_op != O_constant 1654 || ! issword (opP->disp.exp.X_add_number))) 1655 losing++; 1656 break; 1657 1658 case '^': 1659 case 'T': 1660 if (opP->mode != IMMED) 1661 losing++; 1662 break; 1663 1664 case '$': 1665 if (opP->mode == AREG 1666 || opP->mode == CONTROL 1667 || opP->mode == FPREG 1668 || opP->mode == IMMED 1669 || opP->mode == REGLST 1670 || (opP->mode != ABSL 1671 && (opP->reg == PC 1672 || opP->reg == ZPC))) 1673 losing++; 1674 break; 1675 1676 case '%': 1677 if (opP->mode == CONTROL 1678 || opP->mode == FPREG 1679 || opP->mode == REGLST 1680 || opP->mode == IMMED 1681 || (opP->mode != ABSL 1682 && (opP->reg == PC 1683 || opP->reg == ZPC))) 1684 losing++; 1685 break; 1686 1687 case '&': 1688 switch (opP->mode) 1689 { 1690 case DREG: 1691 case AREG: 1692 case FPREG: 1693 case CONTROL: 1694 case IMMED: 1695 case AINC: 1696 case ADEC: 1697 case REGLST: 1698 losing++; 1699 break; 1700 case ABSL: 1701 break; 1702 default: 1703 if (opP->reg == PC 1704 || opP->reg == ZPC) 1705 losing++; 1706 break; 1707 } 1708 break; 1709 1710 case '*': 1711 if (opP->mode == CONTROL 1712 || opP->mode == FPREG 1713 || opP->mode == REGLST) 1714 losing++; 1715 break; 1716 1717 case '+': 1718 if (opP->mode != AINC) 1719 losing++; 1720 break; 1721 1722 case '-': 1723 if (opP->mode != ADEC) 1724 losing++; 1725 break; 1726 1727 case '/': 1728 switch (opP->mode) 1729 { 1730 case AREG: 1731 case CONTROL: 1732 case FPREG: 1733 case AINC: 1734 case ADEC: 1735 case IMMED: 1736 case REGLST: 1737 losing++; 1738 break; 1739 default: 1740 break; 1741 } 1742 break; 1743 1744 case ';': 1745 switch (opP->mode) 1746 { 1747 case AREG: 1748 case CONTROL: 1749 case FPREG: 1750 case REGLST: 1751 losing++; 1752 break; 1753 default: 1754 break; 1755 } 1756 break; 1757 1758 case '?': 1759 switch (opP->mode) 1760 { 1761 case AREG: 1762 case CONTROL: 1763 case FPREG: 1764 case AINC: 1765 case ADEC: 1766 case IMMED: 1767 case REGLST: 1768 losing++; 1769 break; 1770 case ABSL: 1771 break; 1772 default: 1773 if (opP->reg == PC || opP->reg == ZPC) 1774 losing++; 1775 break; 1776 } 1777 break; 1778 1779 case '@': 1780 switch (opP->mode) 1781 { 1782 case AREG: 1783 case CONTROL: 1784 case FPREG: 1785 case IMMED: 1786 case REGLST: 1787 losing++; 1788 break; 1789 default: 1790 break; 1791 } 1792 break; 1793 1794 case '~': /* For now! (JF FOO is this right?) */ 1795 switch (opP->mode) 1796 { 1797 case DREG: 1798 case AREG: 1799 case CONTROL: 1800 case FPREG: 1801 case IMMED: 1802 case REGLST: 1803 losing++; 1804 break; 1805 case ABSL: 1806 break; 1807 default: 1808 if (opP->reg == PC 1809 || opP->reg == ZPC) 1810 losing++; 1811 break; 1812 } 1813 break; 1814 1815 case '3': 1816 if (opP->mode != CONTROL 1817 || (opP->reg != TT0 && opP->reg != TT1)) 1818 losing++; 1819 break; 1820 1821 case 'A': 1822 if (opP->mode != AREG) 1823 losing++; 1824 break; 1825 1826 case 'a': 1827 if (opP->mode != AINDR) 1828 ++losing; 1829 break; 1830 1831 case '4': 1832 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC 1833 && (opP->mode != DISP 1834 || opP->reg < ADDR0 1835 || opP->reg > ADDR7)) 1836 ++losing; 1837 break; 1838 1839 case 'B': /* FOO */ 1840 if (opP->mode != ABSL 1841 || (flag_long_jumps 1842 && strncmp (instring, "jbsr", 4) == 0)) 1843 losing++; 1844 break; 1845 1846 case 'b': 1847 switch (opP->mode) 1848 { 1849 case IMMED: 1850 case ABSL: 1851 case AREG: 1852 case FPREG: 1853 case CONTROL: 1854 case POST: 1855 case PRE: 1856 case REGLST: 1857 losing++; 1858 break; 1859 default: 1860 break; 1861 } 1862 break; 1863 1864 case 'C': 1865 if (opP->mode != CONTROL || opP->reg != CCR) 1866 losing++; 1867 break; 1868 1869 case 'd': 1870 if (opP->mode != DISP 1871 || opP->reg < ADDR0 1872 || opP->reg > ADDR7) 1873 losing++; 1874 break; 1875 1876 case 'D': 1877 if (opP->mode != DREG) 1878 losing++; 1879 break; 1880 1881 case 'E': 1882 if (opP->reg != ACC) 1883 losing++; 1884 break; 1885 1886 case 'e': 1887 if (opP->reg != ACC && opP->reg != ACC1 1888 && opP->reg != ACC2 && opP->reg != ACC3) 1889 losing++; 1890 break; 1891 1892 case 'F': 1893 if (opP->mode != FPREG) 1894 losing++; 1895 break; 1896 1897 case 'G': 1898 if (opP->reg != MACSR) 1899 losing++; 1900 break; 1901 1902 case 'g': 1903 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) 1904 losing++; 1905 break; 1906 1907 case 'H': 1908 if (opP->reg != MASK) 1909 losing++; 1910 break; 1911 1912 case 'I': 1913 if (opP->mode != CONTROL 1914 || opP->reg < COP0 1915 || opP->reg > COP7) 1916 losing++; 1917 break; 1918 1919 case 'i': 1920 if (opP->mode != LSH && opP->mode != RSH) 1921 losing++; 1922 break; 1923 1924 case 'J': 1925 if (opP->mode != CONTROL 1926 || opP->reg < USP 1927 || opP->reg > last_movec_reg 1928 || !control_regs) 1929 losing++; 1930 else 1931 { 1932 const enum m68k_register *rp; 1933 1934 for (rp = control_regs; *rp; rp++) 1935 { 1936 if (*rp == opP->reg) 1937 break; 1938 /* In most CPUs RAMBAR refers to control reg 1939 c05 (RAMBAR1), but a few CPUs have it 1940 refer to c04 (RAMBAR0). */ 1941 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) 1942 { 1943 opP->reg = RAMBAR_ALT; 1944 break; 1945 } 1946 } 1947 if (*rp == 0) 1948 losing++; 1949 } 1950 break; 1951 1952 case 'k': 1953 if (opP->mode != IMMED) 1954 losing++; 1955 break; 1956 1957 case 'l': 1958 case 'L': 1959 if (opP->mode == DREG 1960 || opP->mode == AREG 1961 || opP->mode == FPREG) 1962 { 1963 if (s[1] == '8') 1964 losing++; 1965 else 1966 { 1967 switch (opP->mode) 1968 { 1969 case DREG: 1970 opP->mask = 1 << (opP->reg - DATA0); 1971 break; 1972 case AREG: 1973 opP->mask = 1 << (opP->reg - ADDR0 + 8); 1974 break; 1975 case FPREG: 1976 opP->mask = 1 << (opP->reg - FP0 + 16); 1977 break; 1978 default: 1979 abort (); 1980 } 1981 opP->mode = REGLST; 1982 } 1983 } 1984 else if (opP->mode == CONTROL) 1985 { 1986 if (s[1] != '8') 1987 losing++; 1988 else 1989 { 1990 switch (opP->reg) 1991 { 1992 case FPI: 1993 opP->mask = 1 << 24; 1994 break; 1995 case FPS: 1996 opP->mask = 1 << 25; 1997 break; 1998 case FPC: 1999 opP->mask = 1 << 26; 2000 break; 2001 default: 2002 losing++; 2003 break; 2004 } 2005 opP->mode = REGLST; 2006 } 2007 } 2008 else if (opP->mode != REGLST) 2009 losing++; 2010 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) 2011 losing++; 2012 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) 2013 losing++; 2014 break; 2015 2016 case 'M': 2017 if (opP->mode != IMMED) 2018 losing++; 2019 else if (opP->disp.exp.X_op != O_constant 2020 || ! issbyte (opP->disp.exp.X_add_number)) 2021 losing++; 2022 else if (! m68k_quick 2023 && instring[3] != 'q' 2024 && instring[4] != 'q') 2025 losing++; 2026 break; 2027 2028 case 'O': 2029 if (opP->mode != DREG 2030 && opP->mode != IMMED 2031 && opP->mode != ABSL) 2032 losing++; 2033 break; 2034 2035 case 'Q': 2036 if (opP->mode != IMMED) 2037 losing++; 2038 else if (opP->disp.exp.X_op != O_constant 2039 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2040 losing++; 2041 else if (! m68k_quick 2042 && (strncmp (instring, "add", 3) == 0 2043 || strncmp (instring, "sub", 3) == 0) 2044 && instring[3] != 'q') 2045 losing++; 2046 break; 2047 2048 case 'R': 2049 if (opP->mode != DREG && opP->mode != AREG) 2050 losing++; 2051 break; 2052 2053 case 'r': 2054 if (opP->mode != AINDR 2055 && (opP->mode != BASE 2056 || (opP->reg != 0 2057 && opP->reg != ZADDR0) 2058 || opP->disp.exp.X_op != O_absent 2059 || ((opP->index.reg < DATA0 2060 || opP->index.reg > DATA7) 2061 && (opP->index.reg < ADDR0 2062 || opP->index.reg > ADDR7)) 2063 || opP->index.size != SIZE_UNSPEC 2064 || opP->index.scale != 1)) 2065 losing++; 2066 break; 2067 2068 case 's': 2069 if (opP->mode != CONTROL 2070 || ! (opP->reg == FPI 2071 || opP->reg == FPS 2072 || opP->reg == FPC)) 2073 losing++; 2074 break; 2075 2076 case 'S': 2077 if (opP->mode != CONTROL || opP->reg != SR) 2078 losing++; 2079 break; 2080 2081 case 't': 2082 if (opP->mode != IMMED) 2083 losing++; 2084 else if (opP->disp.exp.X_op != O_constant 2085 || TRUNC (opP->disp.exp.X_add_number) > 7) 2086 losing++; 2087 break; 2088 2089 case 'U': 2090 if (opP->mode != CONTROL || opP->reg != USP) 2091 losing++; 2092 break; 2093 2094 case 'x': 2095 if (opP->mode != IMMED) 2096 losing++; 2097 else if (opP->disp.exp.X_op != O_constant 2098 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff 2099 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) 2100 losing++; 2101 break; 2102 2103 case 'j': 2104 if (opP->mode != IMMED) 2105 losing++; 2106 else if (opP->disp.exp.X_op != O_constant 2107 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2108 losing++; 2109 break; 2110 2111 case 'K': 2112 if (opP->mode != IMMED) 2113 losing++; 2114 else if (opP->disp.exp.X_op != O_constant 2115 || TRUNC (opP->disp.exp.X_add_number) > 511) 2116 losing++; 2117 break; 2118 2119 /* JF these are out of order. We could put them 2120 in order if we were willing to put up with 2121 bunches of #ifdef m68851s in the code. 2122 2123 Don't forget that you need these operands 2124 to use 68030 MMU instructions. */ 2125#ifndef NO_68851 2126 /* Memory addressing mode used by pflushr. */ 2127 case '|': 2128 if (opP->mode == CONTROL 2129 || opP->mode == FPREG 2130 || opP->mode == DREG 2131 || opP->mode == AREG 2132 || opP->mode == REGLST) 2133 losing++; 2134 /* We should accept immediate operands, but they 2135 supposedly have to be quad word, and we don't 2136 handle that. I would like to see what a Motorola 2137 assembler does before doing something here. */ 2138 if (opP->mode == IMMED) 2139 losing++; 2140 break; 2141 2142 case 'f': 2143 if (opP->mode != CONTROL 2144 || (opP->reg != SFC && opP->reg != DFC)) 2145 losing++; 2146 break; 2147 2148 case '0': 2149 if (opP->mode != CONTROL || opP->reg != TC) 2150 losing++; 2151 break; 2152 2153 case '1': 2154 if (opP->mode != CONTROL || opP->reg != AC) 2155 losing++; 2156 break; 2157 2158 case '2': 2159 if (opP->mode != CONTROL 2160 || (opP->reg != CAL 2161 && opP->reg != VAL 2162 && opP->reg != SCC)) 2163 losing++; 2164 break; 2165 2166 case 'V': 2167 if (opP->mode != CONTROL 2168 || opP->reg != VAL) 2169 losing++; 2170 break; 2171 2172 case 'W': 2173 if (opP->mode != CONTROL 2174 || (opP->reg != DRP 2175 && opP->reg != SRP 2176 && opP->reg != CRP)) 2177 losing++; 2178 break; 2179 2180 case 'w': 2181 switch (opP->mode) 2182 { 2183 case IMMED: 2184 case ABSL: 2185 case AREG: 2186 case DREG: 2187 case FPREG: 2188 case CONTROL: 2189 case POST: 2190 case PRE: 2191 case REGLST: 2192 losing++; 2193 break; 2194 default: 2195 break; 2196 } 2197 break; 2198 2199 case 'X': 2200 if (opP->mode != CONTROL 2201 || (!(opP->reg >= BAD && opP->reg <= BAD + 7) 2202 && !(opP->reg >= BAC && opP->reg <= BAC + 7))) 2203 losing++; 2204 break; 2205 2206 case 'Y': 2207 if (opP->mode != CONTROL || opP->reg != PSR) 2208 losing++; 2209 break; 2210 2211 case 'Z': 2212 if (opP->mode != CONTROL || opP->reg != PCSR) 2213 losing++; 2214 break; 2215#endif 2216 case 'c': 2217 if (opP->mode != CONTROL 2218 || (opP->reg != NC 2219 && opP->reg != IC 2220 && opP->reg != DC 2221 && opP->reg != BC)) 2222 losing++; 2223 break; 2224 2225 case '_': 2226 if (opP->mode != ABSL) 2227 ++losing; 2228 break; 2229 2230 case 'u': 2231 if (opP->reg < DATA0L || opP->reg > ADDR7U) 2232 losing++; 2233 /* FIXME: kludge instead of fixing parser: 2234 upper/lower registers are *not* CONTROL 2235 registers, but ordinary ones. */ 2236 if ((opP->reg >= DATA0L && opP->reg <= DATA7L) 2237 || (opP->reg >= DATA0U && opP->reg <= DATA7U)) 2238 opP->mode = DREG; 2239 else 2240 opP->mode = AREG; 2241 break; 2242 2243 case 'y': 2244 if (!(opP->mode == AINDR 2245 || (opP->mode == DISP 2246 && !(opP->reg == PC || opP->reg == ZPC)))) 2247 losing++; 2248 break; 2249 2250 case 'z': 2251 if (!(opP->mode == AINDR || opP->mode == DISP)) 2252 losing++; 2253 break; 2254 2255 default: 2256 abort (); 2257 } 2258 2259 if (losing) 2260 break; 2261 } 2262 2263 /* Since we have found the correct instruction, copy 2264 in the modifications that we may have made. */ 2265 if (!losing) 2266 for (i = 0; i < opsfound; i++) 2267 the_ins.operands[i] = operands_backup[i]; 2268 } 2269 2270 if (!losing) 2271 break; 2272 2273 opcode = opcode->m_next; 2274 2275 if (!opcode) 2276 { 2277 if (ok_arch 2278 && !(ok_arch & current_architecture)) 2279 { 2280 const struct m68k_cpu *cpu; 2281 int any = 0; 2282 size_t space = 400; 2283 char *buf = XNEWVEC (char, space + 1); 2284 size_t len; 2285 int paren = 1; 2286 2287 the_ins.error = buf; 2288 /* Make sure there's a NUL at the end of the buffer -- strncpy 2289 won't write one when it runs out of buffer. */ 2290 buf[space] = 0; 2291#define APPEND(STRING) \ 2292 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) 2293 2294 APPEND (_("invalid instruction for this architecture; needs ")); 2295 switch (ok_arch) 2296 { 2297 case mcfisa_a: 2298 APPEND ("ColdFire ISA_A"); 2299 break; 2300 case mcfhwdiv: 2301 APPEND ("ColdFire "); 2302 APPEND (_("hardware divide")); 2303 break; 2304 case mcfisa_aa: 2305 APPEND ("ColdFire ISA_A+"); 2306 break; 2307 case mcfisa_b: 2308 APPEND ("ColdFire ISA_B"); 2309 break; 2310 case mcfisa_c: 2311 APPEND ("ColdFire ISA_C"); 2312 break; 2313 case cfloat: 2314 APPEND ("ColdFire fpu"); 2315 break; 2316 case mfloat: 2317 APPEND ("M68K fpu"); 2318 break; 2319 case mmmu: 2320 APPEND ("M68K mmu"); 2321 break; 2322 case m68020up: 2323 APPEND ("68020 "); 2324 APPEND (_("or higher")); 2325 break; 2326 case m68000up: 2327 APPEND ("68000 "); 2328 APPEND (_("or higher")); 2329 break; 2330 case m68010up: 2331 APPEND ("68010 "); 2332 APPEND (_("or higher")); 2333 break; 2334 default: 2335 paren = 0; 2336 } 2337 if (paren) 2338 APPEND (" ("); 2339 2340 for (cpu = m68k_cpus; cpu->name; cpu++) 2341 if (!cpu->alias && (cpu->arch & ok_arch)) 2342 { 2343 const struct m68k_cpu *alias; 2344 int seen_master = 0; 2345 2346 if (any) 2347 APPEND (", "); 2348 any = 0; 2349 APPEND (cpu->name); 2350 for (alias = cpu; alias != m68k_cpus; alias--) 2351 if (alias[-1].alias >= 0) 2352 break; 2353 for (; !seen_master || alias->alias > 0; alias++) 2354 { 2355 if (!alias->alias) 2356 seen_master = 1; 2357 else 2358 { 2359 if (any) 2360 APPEND (", "); 2361 else 2362 APPEND (" ["); 2363 APPEND (alias->name); 2364 any = 1; 2365 } 2366 } 2367 if (any) 2368 APPEND ("]"); 2369 any = 1; 2370 } 2371 if (paren) 2372 APPEND (")"); 2373#undef APPEND 2374 if (!space) 2375 { 2376 /* We ran out of space, so replace the end of the list 2377 with ellipsis. */ 2378 buf -= 4; 2379 while (*buf != ' ') 2380 buf--; 2381 strcpy (buf, " ..."); 2382 } 2383 } 2384 else 2385 the_ins.error = _("operands mismatch"); 2386 return; 2387 } 2388 2389 losing = 0; 2390 } 2391 2392 /* Now assemble it. */ 2393 the_ins.args = opcode->m_operands; 2394 the_ins.numargs = opcode->m_opnum; 2395 the_ins.numo = opcode->m_codenum; 2396 the_ins.opcode[0] = getone (opcode); 2397 the_ins.opcode[1] = gettwo (opcode); 2398 2399 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) 2400 { 2401 int have_disp = 0; 2402 int use_pl = 0; 2403 2404 /* This switch is a doozy. 2405 Watch the first step; it's a big one! */ 2406 switch (s[0]) 2407 { 2408 2409 case '*': 2410 case '~': 2411 case '%': 2412 case ';': 2413 case '@': 2414 case '!': 2415 case '&': 2416 case '$': 2417 case '?': 2418 case '/': 2419 case '<': 2420 case '>': 2421 case 'b': 2422 case 'm': 2423 case 'n': 2424 case 'o': 2425 case 'p': 2426 case 'q': 2427 case 'v': 2428 case 'w': 2429 case 'y': 2430 case 'z': 2431 case '4': 2432#ifndef NO_68851 2433 case '|': 2434#endif 2435 switch (opP->mode) 2436 { 2437 case IMMED: 2438 tmpreg = 0x3c; /* 7.4 */ 2439 if (strchr ("bwl", s[1])) 2440 nextword = get_num (&opP->disp, 90); 2441 else 2442 nextword = get_num (&opP->disp, 0); 2443 if (isvar (&opP->disp)) 2444 add_fix (s[1], &opP->disp, 0, 0); 2445 switch (s[1]) 2446 { 2447 case 'b': 2448 if (!isbyte (nextword)) 2449 opP->error = _("operand out of range"); 2450 addword (nextword); 2451 baseo = 0; 2452 break; 2453 case 'w': 2454 if (!isword (nextword)) 2455 opP->error = _("operand out of range"); 2456 addword (nextword); 2457 baseo = 0; 2458 break; 2459 case 'W': 2460 if (!issword (nextword)) 2461 opP->error = _("operand out of range"); 2462 addword (nextword); 2463 baseo = 0; 2464 break; 2465 case 'l': 2466 addword (nextword >> 16); 2467 addword (nextword); 2468 baseo = 0; 2469 break; 2470 2471 case 'f': 2472 baseo = 2; 2473 outro = 8; 2474 break; 2475 case 'F': 2476 baseo = 4; 2477 outro = 11; 2478 break; 2479 case 'x': 2480 baseo = 6; 2481 outro = 15; 2482 break; 2483 case 'p': 2484 baseo = 6; 2485 outro = -1; 2486 break; 2487 default: 2488 abort (); 2489 } 2490 if (!baseo) 2491 break; 2492 2493 /* We gotta put out some float. */ 2494 if (op (&opP->disp) != O_big) 2495 { 2496 valueT val; 2497 int gencnt; 2498 2499 /* Can other cases happen here? */ 2500 if (op (&opP->disp) != O_constant) 2501 abort (); 2502 2503 val = (valueT) offs (&opP->disp); 2504 gencnt = 0; 2505 do 2506 { 2507 generic_bignum[gencnt] = (LITTLENUM_TYPE) val; 2508 val >>= LITTLENUM_NUMBER_OF_BITS; 2509 ++gencnt; 2510 } 2511 while (val != 0); 2512 offs (&opP->disp) = gencnt; 2513 } 2514 if (offs (&opP->disp) > 0) 2515 { 2516 if (offs (&opP->disp) > baseo) 2517 { 2518 as_warn (_("Bignum too big for %c format; truncated"), 2519 s[1]); 2520 offs (&opP->disp) = baseo; 2521 } 2522 baseo -= offs (&opP->disp); 2523 while (baseo--) 2524 addword (0); 2525 for (wordp = generic_bignum + offs (&opP->disp) - 1; 2526 offs (&opP->disp)--; 2527 --wordp) 2528 addword (*wordp); 2529 break; 2530 } 2531 gen_to_words (words, baseo, (long) outro); 2532 for (wordp = words; baseo--; wordp++) 2533 addword (*wordp); 2534 break; 2535 case DREG: 2536 tmpreg = opP->reg - DATA; /* 0.dreg */ 2537 break; 2538 case AREG: 2539 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ 2540 break; 2541 case AINDR: 2542 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2543 break; 2544 case ADEC: 2545 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ 2546 break; 2547 case AINC: 2548 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ 2549 break; 2550 case DISP: 2551 2552 nextword = get_num (&opP->disp, 90); 2553 2554 /* Convert mode 5 addressing with a zero offset into 2555 mode 2 addressing to reduce the instruction size by a 2556 word. */ 2557 if (! isvar (&opP->disp) 2558 && (nextword == 0) 2559 && (opP->disp.size == SIZE_UNSPEC) 2560 && (opP->reg >= ADDR0) 2561 && (opP->reg <= ADDR7)) 2562 { 2563 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2564 break; 2565 } 2566 2567 if (opP->reg == PC 2568 && ! isvar (&opP->disp) 2569 && m68k_abspcadd) 2570 { 2571 opP->disp.exp.X_op = O_symbol; 2572 opP->disp.exp.X_add_symbol = 2573 section_symbol (absolute_section); 2574 } 2575 2576 /* Force into index mode. Hope this works. */ 2577 2578 /* We do the first bit for 32-bit displacements, and the 2579 second bit for 16 bit ones. It is possible that we 2580 should make the default be WORD instead of LONG, but 2581 I think that'd break GCC, so we put up with a little 2582 inefficiency for the sake of working output. */ 2583 2584 if (!issword (nextword) 2585 || (isvar (&opP->disp) 2586 && ((opP->disp.size == SIZE_UNSPEC 2587 && flag_short_refs == 0 2588 && cpu_of_arch (current_architecture) >= m68020 2589 && ! arch_coldfire_p (current_architecture)) 2590 || opP->disp.size == SIZE_LONG))) 2591 { 2592 if (cpu_of_arch (current_architecture) < m68020 2593 || arch_coldfire_p (current_architecture)) 2594 opP->error = 2595 _("displacement too large for this architecture; needs 68020 or higher"); 2596 if (opP->reg == PC) 2597 tmpreg = 0x3B; /* 7.3 */ 2598 else 2599 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2600 if (isvar (&opP->disp)) 2601 { 2602 if (opP->reg == PC) 2603 { 2604 if (opP->disp.size == SIZE_LONG 2605 /* If the displacement needs pic 2606 relocation it cannot be relaxed. */ 2607 || opP->disp.pic_reloc != pic_none) 2608 { 2609 addword (0x0170); 2610 add_fix ('l', &opP->disp, 1, 2); 2611 } 2612 else 2613 { 2614 add_frag (adds (&opP->disp), 2615 SEXT (offs (&opP->disp)), 2616 TAB (PCREL1632, SZ_UNDEF)); 2617 break; 2618 } 2619 } 2620 else 2621 { 2622 addword (0x0170); 2623 add_fix ('l', &opP->disp, 0, 0); 2624 } 2625 } 2626 else 2627 addword (0x0170); 2628 addword (nextword >> 16); 2629 } 2630 else 2631 { 2632 if (opP->reg == PC) 2633 tmpreg = 0x3A; /* 7.2 */ 2634 else 2635 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ 2636 2637 if (isvar (&opP->disp)) 2638 { 2639 if (opP->reg == PC) 2640 { 2641 add_fix ('w', &opP->disp, 1, 0); 2642 } 2643 else 2644 add_fix ('w', &opP->disp, 0, 0); 2645 } 2646 } 2647 addword (nextword); 2648 break; 2649 2650 case POST: 2651 case PRE: 2652 case BASE: 2653 nextword = 0; 2654 baseo = get_num (&opP->disp, 90); 2655 if (opP->mode == POST || opP->mode == PRE) 2656 outro = get_num (&opP->odisp, 90); 2657 /* Figure out the `addressing mode'. 2658 Also turn on the BASE_DISABLE bit, if needed. */ 2659 if (opP->reg == PC || opP->reg == ZPC) 2660 { 2661 tmpreg = 0x3b; /* 7.3 */ 2662 if (opP->reg == ZPC) 2663 nextword |= 0x80; 2664 } 2665 else if (opP->reg == 0) 2666 { 2667 nextword |= 0x80; 2668 tmpreg = 0x30; /* 6.garbage */ 2669 } 2670 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) 2671 { 2672 nextword |= 0x80; 2673 tmpreg = 0x30 + opP->reg - ZADDR0; 2674 } 2675 else 2676 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2677 2678 siz1 = opP->disp.size; 2679 if (opP->mode == POST || opP->mode == PRE) 2680 siz2 = opP->odisp.size; 2681 else 2682 siz2 = SIZE_UNSPEC; 2683 2684 /* Index register stuff. */ 2685 if (opP->index.reg != 0 2686 && opP->index.reg >= DATA 2687 && opP->index.reg <= ADDR7) 2688 { 2689 nextword |= (opP->index.reg - DATA) << 12; 2690 2691 if (opP->index.size == SIZE_LONG 2692 || (opP->index.size == SIZE_UNSPEC 2693 && m68k_index_width_default == SIZE_LONG)) 2694 nextword |= 0x800; 2695 2696 if ((opP->index.scale != 1 2697 && cpu_of_arch (current_architecture) < m68020) 2698 || (opP->index.scale == 8 2699 && (arch_coldfire_p (current_architecture) 2700 && !arch_coldfire_fpu (current_architecture)))) 2701 { 2702 opP->error = 2703 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); 2704 } 2705 2706 if (arch_coldfire_p (current_architecture) 2707 && opP->index.size == SIZE_WORD) 2708 opP->error = _("invalid index size for coldfire"); 2709 2710 switch (opP->index.scale) 2711 { 2712 case 1: 2713 break; 2714 case 2: 2715 nextword |= 0x200; 2716 break; 2717 case 4: 2718 nextword |= 0x400; 2719 break; 2720 case 8: 2721 nextword |= 0x600; 2722 break; 2723 default: 2724 abort (); 2725 } 2726 /* IF it's simple, 2727 GET US OUT OF HERE! */ 2728 2729 /* Must be INDEX, with an index register. Address 2730 register cannot be ZERO-PC, and either :b was 2731 forced, or we know it will fit. For a 68000 or 2732 68010, force this mode anyways, because the 2733 larger modes aren't supported. */ 2734 if (opP->mode == BASE 2735 && ((opP->reg >= ADDR0 2736 && opP->reg <= ADDR7) 2737 || opP->reg == PC)) 2738 { 2739 if (siz1 == SIZE_BYTE 2740 || cpu_of_arch (current_architecture) < m68020 2741 || arch_coldfire_p (current_architecture) 2742 || (siz1 == SIZE_UNSPEC 2743 && ! isvar (&opP->disp) 2744 && issbyte (baseo))) 2745 { 2746 nextword += baseo & 0xff; 2747 addword (nextword); 2748 if (isvar (&opP->disp)) 2749 { 2750 /* Do a byte relocation. If it doesn't 2751 fit (possible on m68000) let the 2752 fixup processing complain later. */ 2753 if (opP->reg == PC) 2754 add_fix ('B', &opP->disp, 1, 1); 2755 else 2756 add_fix ('B', &opP->disp, 0, 0); 2757 } 2758 else if (siz1 != SIZE_BYTE) 2759 { 2760 if (siz1 != SIZE_UNSPEC) 2761 as_warn (_("Forcing byte displacement")); 2762 if (! issbyte (baseo)) 2763 opP->error = _("byte displacement out of range"); 2764 } 2765 2766 break; 2767 } 2768 else if (siz1 == SIZE_UNSPEC 2769 && opP->reg == PC 2770 && isvar (&opP->disp) 2771 && subs (&opP->disp) == NULL 2772 /* If the displacement needs pic 2773 relocation it cannot be relaxed. */ 2774 && opP->disp.pic_reloc == pic_none) 2775 { 2776 /* The code in md_convert_frag_1 needs to be 2777 able to adjust nextword. Call frag_grow 2778 to ensure that we have enough space in 2779 the frag obstack to make all the bytes 2780 contiguous. */ 2781 frag_grow (14); 2782 nextword += baseo & 0xff; 2783 addword (nextword); 2784 add_frag (adds (&opP->disp), 2785 SEXT (offs (&opP->disp)), 2786 TAB (PCINDEX, SZ_UNDEF)); 2787 2788 break; 2789 } 2790 } 2791 } 2792 else 2793 { 2794 nextword |= 0x40; /* No index reg. */ 2795 if (opP->index.reg >= ZDATA0 2796 && opP->index.reg <= ZDATA7) 2797 nextword |= (opP->index.reg - ZDATA0) << 12; 2798 else if (opP->index.reg >= ZADDR0 2799 && opP->index.reg <= ZADDR7) 2800 nextword |= (opP->index.reg - ZADDR0 + 8) << 12; 2801 } 2802 2803 /* It isn't simple. */ 2804 2805 if (cpu_of_arch (current_architecture) < m68020 2806 || arch_coldfire_p (current_architecture)) 2807 opP->error = 2808 _("invalid operand mode for this architecture; needs 68020 or higher"); 2809 2810 nextword |= 0x100; 2811 /* If the guy specified a width, we assume that it is 2812 wide enough. Maybe it isn't. If so, we lose. */ 2813 switch (siz1) 2814 { 2815 case SIZE_UNSPEC: 2816 if (isvar (&opP->disp) 2817 ? m68k_rel32 2818 : ! issword (baseo)) 2819 { 2820 siz1 = SIZE_LONG; 2821 nextword |= 0x30; 2822 } 2823 else if (! isvar (&opP->disp) && baseo == 0) 2824 nextword |= 0x10; 2825 else 2826 { 2827 nextword |= 0x20; 2828 siz1 = SIZE_WORD; 2829 } 2830 break; 2831 case SIZE_BYTE: 2832 as_warn (_(":b not permitted; defaulting to :w")); 2833 /* Fall through. */ 2834 case SIZE_WORD: 2835 nextword |= 0x20; 2836 break; 2837 case SIZE_LONG: 2838 nextword |= 0x30; 2839 break; 2840 } 2841 2842 /* Figure out inner displacement stuff. */ 2843 if (opP->mode == POST || opP->mode == PRE) 2844 { 2845 if (cpu_of_arch (current_architecture) & cpu32) 2846 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); 2847 switch (siz2) 2848 { 2849 case SIZE_UNSPEC: 2850 if (isvar (&opP->odisp) 2851 ? m68k_rel32 2852 : ! issword (outro)) 2853 { 2854 siz2 = SIZE_LONG; 2855 nextword |= 0x3; 2856 } 2857 else if (! isvar (&opP->odisp) && outro == 0) 2858 nextword |= 0x1; 2859 else 2860 { 2861 nextword |= 0x2; 2862 siz2 = SIZE_WORD; 2863 } 2864 break; 2865 case 1: 2866 as_warn (_(":b not permitted; defaulting to :w")); 2867 /* Fall through. */ 2868 case 2: 2869 nextword |= 0x2; 2870 break; 2871 case 3: 2872 nextword |= 0x3; 2873 break; 2874 } 2875 if (opP->mode == POST 2876 && (nextword & 0x40) == 0) 2877 nextword |= 0x04; 2878 } 2879 addword (nextword); 2880 2881 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) 2882 { 2883 if (opP->reg == PC || opP->reg == ZPC) 2884 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); 2885 else 2886 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); 2887 } 2888 if (siz1 == SIZE_LONG) 2889 addword (baseo >> 16); 2890 if (siz1 != SIZE_UNSPEC) 2891 addword (baseo); 2892 2893 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) 2894 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); 2895 if (siz2 == SIZE_LONG) 2896 addword (outro >> 16); 2897 if (siz2 != SIZE_UNSPEC) 2898 addword (outro); 2899 2900 break; 2901 2902 case ABSL: 2903 nextword = get_num (&opP->disp, 90); 2904 switch (opP->disp.size) 2905 { 2906 default: 2907 abort (); 2908 case SIZE_UNSPEC: 2909 if (!isvar (&opP->disp) && issword (offs (&opP->disp))) 2910 { 2911 tmpreg = 0x38; /* 7.0 */ 2912 addword (nextword); 2913 break; 2914 } 2915 if (isvar (&opP->disp) 2916 && !subs (&opP->disp) 2917 && adds (&opP->disp) 2918 /* If the displacement needs pic relocation it 2919 cannot be relaxed. */ 2920 && opP->disp.pic_reloc == pic_none 2921 && !flag_long_jumps 2922 && !strchr ("~%&$?", s[0])) 2923 { 2924 tmpreg = 0x3A; /* 7.2 */ 2925 add_frag (adds (&opP->disp), 2926 SEXT (offs (&opP->disp)), 2927 TAB (ABSTOPCREL, SZ_UNDEF)); 2928 break; 2929 } 2930 /* Fall through. */ 2931 case SIZE_LONG: 2932 if (isvar (&opP->disp)) 2933 add_fix ('l', &opP->disp, 0, 0); 2934 2935 tmpreg = 0x39;/* 7.1 mode */ 2936 addword (nextword >> 16); 2937 addword (nextword); 2938 break; 2939 2940 case SIZE_BYTE: 2941 as_bad (_("unsupported byte value; use a different suffix")); 2942 /* Fall through. */ 2943 2944 case SIZE_WORD: 2945 if (isvar (&opP->disp)) 2946 add_fix ('w', &opP->disp, 0, 0); 2947 2948 tmpreg = 0x38;/* 7.0 mode */ 2949 addword (nextword); 2950 break; 2951 } 2952 break; 2953 case CONTROL: 2954 case FPREG: 2955 default: 2956 as_bad (_("unknown/incorrect operand")); 2957 /* abort (); */ 2958 } 2959 2960 /* If s[0] is '4', then this is for the mac instructions 2961 that can have a trailing_ampersand set. If so, set 0x100 2962 bit on tmpreg so install_gen_operand can check for it and 2963 set the appropriate bit (word2, bit 5). */ 2964 if (s[0] == '4') 2965 { 2966 if (opP->trailing_ampersand) 2967 tmpreg |= 0x100; 2968 } 2969 install_gen_operand (s[1], tmpreg); 2970 break; 2971 2972 case '#': 2973 case '^': 2974 switch (s[1]) 2975 { /* JF: I hate floating point! */ 2976 case 'j': 2977 tmpreg = 70; 2978 break; 2979 case '8': 2980 tmpreg = 20; 2981 break; 2982 case 'C': 2983 tmpreg = 50; 2984 break; 2985 case '3': 2986 default: 2987 tmpreg = 90; 2988 break; 2989 } 2990 tmpreg = get_num (&opP->disp, tmpreg); 2991 if (isvar (&opP->disp)) 2992 add_fix (s[1], &opP->disp, 0, 0); 2993 switch (s[1]) 2994 { 2995 case 'b': /* Danger: These do no check for 2996 certain types of overflow. 2997 user beware! */ 2998 if (!isbyte (tmpreg)) 2999 opP->error = _("out of range"); 3000 insop (tmpreg, opcode); 3001 if (isvar (&opP->disp)) 3002 the_ins.reloc[the_ins.nrel - 1].n = 3003 (opcode->m_codenum) * 2 + 1; 3004 break; 3005 case 'B': 3006 if (!issbyte (tmpreg)) 3007 opP->error = _("out of range"); 3008 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; 3009 if (isvar (&opP->disp)) 3010 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; 3011 break; 3012 case 'w': 3013 if (!isword (tmpreg)) 3014 opP->error = _("out of range"); 3015 insop (tmpreg, opcode); 3016 if (isvar (&opP->disp)) 3017 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3018 break; 3019 case 'W': 3020 if (!issword (tmpreg)) 3021 opP->error = _("out of range"); 3022 insop (tmpreg, opcode); 3023 if (isvar (&opP->disp)) 3024 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3025 break; 3026 case 'l': 3027 /* Because of the way insop works, we put these two out 3028 backwards. */ 3029 insop (tmpreg, opcode); 3030 insop (tmpreg >> 16, opcode); 3031 if (isvar (&opP->disp)) 3032 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3033 break; 3034 case '3': 3035 tmpreg &= 0xFF; 3036 /* Fall through. */ 3037 case '8': 3038 case 'C': 3039 case 'j': 3040 install_operand (s[1], tmpreg); 3041 break; 3042 default: 3043 abort (); 3044 } 3045 break; 3046 3047 case '+': 3048 case '-': 3049 case 'A': 3050 case 'a': 3051 install_operand (s[1], opP->reg - ADDR); 3052 break; 3053 3054 case 'B': 3055 tmpreg = get_num (&opP->disp, 90); 3056 3057 switch (s[1]) 3058 { 3059 case 'B': 3060 add_fix ('B', &opP->disp, 1, -1); 3061 break; 3062 case 'W': 3063 add_fix ('w', &opP->disp, 1, 0); 3064 addword (0); 3065 break; 3066 case 'L': 3067 long_branch: 3068 the_ins.opcode[0] |= 0xff; 3069 add_fix ('l', &opP->disp, 1, 0); 3070 addword (0); 3071 addword (0); 3072 break; 3073 case 'g': /* Conditional branch */ 3074 have_disp = HAVE_LONG_CALL (current_architecture); 3075 goto var_branch; 3076 3077 case 'b': /* Unconditional branch */ 3078 have_disp = HAVE_LONG_BRANCH (current_architecture); 3079 use_pl = LONG_BRANCH_VIA_COND (current_architecture); 3080 goto var_branch; 3081 3082 case 's': /* Unconditional subroutine */ 3083 have_disp = HAVE_LONG_CALL (current_architecture); 3084 3085 var_branch: 3086 if (subs (&opP->disp) /* We can't relax it. */ 3087 /* If the displacement needs pic relocation it cannot be 3088 relaxed. */ 3089 || opP->disp.pic_reloc != pic_none) 3090 { 3091 if (!have_disp) 3092 as_warn (_("Can't use long branches on this architecture")); 3093 goto long_branch; 3094 } 3095 3096 /* This could either be a symbol, or an absolute 3097 address. If it's an absolute address, turn it into 3098 an absolute jump right here and keep it out of the 3099 relaxer. */ 3100 if (adds (&opP->disp) == 0) 3101 { 3102 if (the_ins.opcode[0] == 0x6000) /* jbra */ 3103 the_ins.opcode[0] = 0x4EF9; 3104 else if (the_ins.opcode[0] == 0x6100) /* jbsr */ 3105 the_ins.opcode[0] = 0x4EB9; 3106 else /* jCC */ 3107 { 3108 the_ins.opcode[0] ^= 0x0100; 3109 the_ins.opcode[0] |= 0x0006; 3110 addword (0x4EF9); 3111 } 3112 add_fix ('l', &opP->disp, 0, 0); 3113 addword (0); 3114 addword (0); 3115 break; 3116 } 3117 3118 /* Now we know it's going into the relaxer. Now figure 3119 out which mode. We try in this order of preference: 3120 long branch, absolute jump, byte/word branches only. */ 3121 if (have_disp) 3122 add_frag (adds (&opP->disp), 3123 SEXT (offs (&opP->disp)), 3124 TAB (BRANCHBWL, SZ_UNDEF)); 3125 else if (! flag_keep_pcrel) 3126 { 3127 if ((the_ins.opcode[0] == 0x6000) 3128 || (the_ins.opcode[0] == 0x6100)) 3129 add_frag (adds (&opP->disp), 3130 SEXT (offs (&opP->disp)), 3131 TAB (BRABSJUNC, SZ_UNDEF)); 3132 else 3133 add_frag (adds (&opP->disp), 3134 SEXT (offs (&opP->disp)), 3135 TAB (BRABSJCOND, SZ_UNDEF)); 3136 } 3137 else 3138 add_frag (adds (&opP->disp), 3139 SEXT (offs (&opP->disp)), 3140 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) 3141 : TAB (BRANCHBW, SZ_UNDEF))); 3142 break; 3143 case 'w': 3144 if (isvar (&opP->disp)) 3145 { 3146 /* Check for DBcc instructions. We can relax them, 3147 but only if we have long branches and/or absolute 3148 jumps. */ 3149 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) 3150 && (HAVE_LONG_BRANCH (current_architecture) 3151 || ! flag_keep_pcrel)) 3152 { 3153 if (HAVE_LONG_BRANCH (current_architecture)) 3154 add_frag (adds (&opP->disp), 3155 SEXT (offs (&opP->disp)), 3156 TAB (DBCCLBR, SZ_UNDEF)); 3157 else 3158 add_frag (adds (&opP->disp), 3159 SEXT (offs (&opP->disp)), 3160 TAB (DBCCABSJ, SZ_UNDEF)); 3161 break; 3162 } 3163 add_fix ('w', &opP->disp, 1, 0); 3164 } 3165 addword (0); 3166 break; 3167 case 'C': /* Fixed size LONG coproc branches. */ 3168 add_fix ('l', &opP->disp, 1, 0); 3169 addword (0); 3170 addword (0); 3171 break; 3172 case 'c': /* Var size Coprocesssor branches. */ 3173 if (subs (&opP->disp) || (adds (&opP->disp) == 0)) 3174 { 3175 the_ins.opcode[the_ins.numo - 1] |= 0x40; 3176 add_fix ('l', &opP->disp, 1, 0); 3177 addword (0); 3178 addword (0); 3179 } 3180 else 3181 add_frag (adds (&opP->disp), 3182 SEXT (offs (&opP->disp)), 3183 TAB (FBRANCH, SZ_UNDEF)); 3184 break; 3185 default: 3186 abort (); 3187 } 3188 break; 3189 3190 case 'C': /* Ignore it. */ 3191 break; 3192 3193 case 'd': /* JF this is a kludge. */ 3194 install_operand ('s', opP->reg - ADDR); 3195 tmpreg = get_num (&opP->disp, 90); 3196 if (!issword (tmpreg)) 3197 { 3198 as_warn (_("Expression out of range, using 0")); 3199 tmpreg = 0; 3200 } 3201 addword (tmpreg); 3202 break; 3203 3204 case 'D': 3205 install_operand (s[1], opP->reg - DATA); 3206 break; 3207 3208 case 'e': /* EMAC ACCx, reg/reg. */ 3209 install_operand (s[1], opP->reg - ACC); 3210 break; 3211 3212 case 'E': /* Ignore it. */ 3213 break; 3214 3215 case 'F': 3216 install_operand (s[1], opP->reg - FP0); 3217 break; 3218 3219 case 'g': /* EMAC ACCEXTx. */ 3220 install_operand (s[1], opP->reg - ACCEXT01); 3221 break; 3222 3223 case 'G': /* Ignore it. */ 3224 case 'H': 3225 break; 3226 3227 case 'I': 3228 tmpreg = opP->reg - COP0; 3229 install_operand (s[1], tmpreg); 3230 break; 3231 3232 case 'i': /* MAC/EMAC scale factor. */ 3233 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); 3234 break; 3235 3236 case 'J': /* JF foo. */ 3237 switch (opP->reg) 3238 { 3239 case SFC: 3240 tmpreg = 0x000; 3241 break; 3242 case DFC: 3243 tmpreg = 0x001; 3244 break; 3245 case CACR: 3246 tmpreg = 0x002; 3247 break; 3248 case TC: 3249 case ASID: 3250 tmpreg = 0x003; 3251 break; 3252 case ACR0: 3253 case ITT0: 3254 tmpreg = 0x004; 3255 break; 3256 case ACR1: 3257 case ITT1: 3258 tmpreg = 0x005; 3259 break; 3260 case ACR2: 3261 case DTT0: 3262 tmpreg = 0x006; 3263 break; 3264 case ACR3: 3265 case DTT1: 3266 tmpreg = 0x007; 3267 break; 3268 case BUSCR: 3269 case MMUBAR: 3270 tmpreg = 0x008; 3271 break; 3272 case RGPIOBAR: 3273 tmpreg = 0x009; 3274 break; 3275 case ACR4: 3276 case ACR5: 3277 case ACR6: 3278 case ACR7: 3279 tmpreg = 0x00c + (opP->reg - ACR4); 3280 break; 3281 3282 case USP: 3283 tmpreg = 0x800; 3284 break; 3285 case VBR: 3286 tmpreg = 0x801; 3287 break; 3288 case CAAR: 3289 case CPUCR: 3290 tmpreg = 0x802; 3291 break; 3292 case MSP: 3293 tmpreg = 0x803; 3294 break; 3295 case ISP: 3296 tmpreg = 0x804; 3297 break; 3298 case MMUSR: 3299 tmpreg = 0x805; 3300 break; 3301 case URP: 3302 tmpreg = 0x806; 3303 break; 3304 case SRP: 3305 tmpreg = 0x807; 3306 break; 3307 case PCR: 3308 tmpreg = 0x808; 3309 break; 3310 case ROMBAR: 3311 case ROMBAR0: 3312 tmpreg = 0xC00; 3313 break; 3314 case ROMBAR1: 3315 tmpreg = 0xC01; 3316 break; 3317 case FLASHBAR: 3318 case RAMBAR0: 3319 case RAMBAR_ALT: 3320 tmpreg = 0xC04; 3321 break; 3322 case RAMBAR: 3323 case RAMBAR1: 3324 tmpreg = 0xC05; 3325 break; 3326 case MPCR: 3327 tmpreg = 0xC0C; 3328 break; 3329 case EDRAMBAR: 3330 tmpreg = 0xC0D; 3331 break; 3332 case MBAR0: 3333 case MBAR2: 3334 case SECMBAR: 3335 tmpreg = 0xC0E; 3336 break; 3337 case MBAR1: 3338 case MBAR: 3339 tmpreg = 0xC0F; 3340 break; 3341 case PCR1U0: 3342 tmpreg = 0xD02; 3343 break; 3344 case PCR1L0: 3345 tmpreg = 0xD03; 3346 break; 3347 case PCR2U0: 3348 tmpreg = 0xD04; 3349 break; 3350 case PCR2L0: 3351 tmpreg = 0xD05; 3352 break; 3353 case PCR3U0: 3354 tmpreg = 0xD06; 3355 break; 3356 case PCR3L0: 3357 tmpreg = 0xD07; 3358 break; 3359 case PCR1L1: 3360 tmpreg = 0xD0A; 3361 break; 3362 case PCR1U1: 3363 tmpreg = 0xD0B; 3364 break; 3365 case PCR2L1: 3366 tmpreg = 0xD0C; 3367 break; 3368 case PCR2U1: 3369 tmpreg = 0xD0D; 3370 break; 3371 case PCR3L1: 3372 tmpreg = 0xD0E; 3373 break; 3374 case PCR3U1: 3375 tmpreg = 0xD0F; 3376 break; 3377 case CAC: 3378 tmpreg = 0xFFE; 3379 break; 3380 case MBO: 3381 tmpreg = 0xFFF; 3382 break; 3383 default: 3384 abort (); 3385 } 3386 install_operand (s[1], tmpreg); 3387 break; 3388 3389 case 'k': 3390 tmpreg = get_num (&opP->disp, 55); 3391 install_operand (s[1], tmpreg & 0x7f); 3392 break; 3393 3394 case 'l': 3395 tmpreg = opP->mask; 3396 if (s[1] == 'w') 3397 { 3398 if (tmpreg & 0x7FF0000) 3399 as_bad (_("Floating point register in register list")); 3400 insop (reverse_16_bits (tmpreg), opcode); 3401 } 3402 else 3403 { 3404 if (tmpreg & 0x700FFFF) 3405 as_bad (_("Wrong register in floating-point reglist")); 3406 install_operand (s[1], reverse_8_bits (tmpreg >> 16)); 3407 } 3408 break; 3409 3410 case 'L': 3411 tmpreg = opP->mask; 3412 if (s[1] == 'w') 3413 { 3414 if (tmpreg & 0x7FF0000) 3415 as_bad (_("Floating point register in register list")); 3416 insop (tmpreg, opcode); 3417 } 3418 else if (s[1] == '8') 3419 { 3420 if (tmpreg & 0x0FFFFFF) 3421 as_bad (_("incorrect register in reglist")); 3422 install_operand (s[1], tmpreg >> 24); 3423 } 3424 else 3425 { 3426 if (tmpreg & 0x700FFFF) 3427 as_bad (_("wrong register in floating-point reglist")); 3428 else 3429 install_operand (s[1], tmpreg >> 16); 3430 } 3431 break; 3432 3433 case 'M': 3434 install_operand (s[1], get_num (&opP->disp, 60)); 3435 break; 3436 3437 case 'O': 3438 tmpreg = ((opP->mode == DREG) 3439 ? 0x20 + (int) (opP->reg - DATA) 3440 : (get_num (&opP->disp, 40) & 0x1F)); 3441 install_operand (s[1], tmpreg); 3442 break; 3443 3444 case 'Q': 3445 tmpreg = get_num (&opP->disp, 10); 3446 if (tmpreg == 8) 3447 tmpreg = 0; 3448 install_operand (s[1], tmpreg); 3449 break; 3450 3451 case 'R': 3452 /* This depends on the fact that ADDR registers are eight 3453 more than their corresponding DATA regs, so the result 3454 will have the ADDR_REG bit set. */ 3455 install_operand (s[1], opP->reg - DATA); 3456 break; 3457 3458 case 'r': 3459 if (opP->mode == AINDR) 3460 install_operand (s[1], opP->reg - DATA); 3461 else 3462 install_operand (s[1], opP->index.reg - DATA); 3463 break; 3464 3465 case 's': 3466 if (opP->reg == FPI) 3467 tmpreg = 0x1; 3468 else if (opP->reg == FPS) 3469 tmpreg = 0x2; 3470 else if (opP->reg == FPC) 3471 tmpreg = 0x4; 3472 else 3473 abort (); 3474 install_operand (s[1], tmpreg); 3475 break; 3476 3477 case 'S': /* Ignore it. */ 3478 break; 3479 3480 case 'T': 3481 install_operand (s[1], get_num (&opP->disp, 30)); 3482 break; 3483 3484 case 'U': /* Ignore it. */ 3485 break; 3486 3487 case 'c': 3488 switch (opP->reg) 3489 { 3490 case NC: 3491 tmpreg = 0; 3492 break; 3493 case DC: 3494 tmpreg = 1; 3495 break; 3496 case IC: 3497 tmpreg = 2; 3498 break; 3499 case BC: 3500 tmpreg = 3; 3501 break; 3502 default: 3503 as_fatal (_("failed sanity check")); 3504 } /* switch on cache token. */ 3505 install_operand (s[1], tmpreg); 3506 break; 3507#ifndef NO_68851 3508 /* JF: These are out of order, I fear. */ 3509 case 'f': 3510 switch (opP->reg) 3511 { 3512 case SFC: 3513 tmpreg = 0; 3514 break; 3515 case DFC: 3516 tmpreg = 1; 3517 break; 3518 default: 3519 abort (); 3520 } 3521 install_operand (s[1], tmpreg); 3522 break; 3523 3524 case '0': 3525 case '1': 3526 case '2': 3527 switch (opP->reg) 3528 { 3529 case TC: 3530 tmpreg = 0; 3531 break; 3532 case CAL: 3533 tmpreg = 4; 3534 break; 3535 case VAL: 3536 tmpreg = 5; 3537 break; 3538 case SCC: 3539 tmpreg = 6; 3540 break; 3541 case AC: 3542 tmpreg = 7; 3543 break; 3544 default: 3545 abort (); 3546 } 3547 install_operand (s[1], tmpreg); 3548 break; 3549 3550 case 'V': 3551 if (opP->reg == VAL) 3552 break; 3553 abort (); 3554 3555 case 'W': 3556 switch (opP->reg) 3557 { 3558 case DRP: 3559 tmpreg = 1; 3560 break; 3561 case SRP: 3562 tmpreg = 2; 3563 break; 3564 case CRP: 3565 tmpreg = 3; 3566 break; 3567 default: 3568 abort (); 3569 } 3570 install_operand (s[1], tmpreg); 3571 break; 3572 3573 case 'X': 3574 switch (opP->reg) 3575 { 3576 case BAD: 3577 case BAD + 1: 3578 case BAD + 2: 3579 case BAD + 3: 3580 case BAD + 4: 3581 case BAD + 5: 3582 case BAD + 6: 3583 case BAD + 7: 3584 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 3585 break; 3586 3587 case BAC: 3588 case BAC + 1: 3589 case BAC + 2: 3590 case BAC + 3: 3591 case BAC + 4: 3592 case BAC + 5: 3593 case BAC + 6: 3594 case BAC + 7: 3595 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 3596 break; 3597 3598 default: 3599 abort (); 3600 } 3601 install_operand (s[1], tmpreg); 3602 break; 3603 case 'Y': 3604 know (opP->reg == PSR); 3605 break; 3606 case 'Z': 3607 know (opP->reg == PCSR); 3608 break; 3609#endif /* m68851 */ 3610 case '3': 3611 switch (opP->reg) 3612 { 3613 case TT0: 3614 tmpreg = 2; 3615 break; 3616 case TT1: 3617 tmpreg = 3; 3618 break; 3619 default: 3620 abort (); 3621 } 3622 install_operand (s[1], tmpreg); 3623 break; 3624 case 't': 3625 tmpreg = get_num (&opP->disp, 20); 3626 install_operand (s[1], tmpreg); 3627 break; 3628 case '_': /* used only for move16 absolute 32-bit address. */ 3629 if (isvar (&opP->disp)) 3630 add_fix ('l', &opP->disp, 0, 0); 3631 tmpreg = get_num (&opP->disp, 90); 3632 addword (tmpreg >> 16); 3633 addword (tmpreg & 0xFFFF); 3634 break; 3635 case 'u': 3636 install_operand (s[1], opP->reg - DATA0L); 3637 opP->reg -= (DATA0L); 3638 opP->reg &= 0x0F; /* remove upper/lower bit. */ 3639 break; 3640 case 'x': 3641 tmpreg = get_num (&opP->disp, 80); 3642 if (tmpreg == -1) 3643 tmpreg = 0; 3644 install_operand (s[1], tmpreg); 3645 break; 3646 case 'j': 3647 tmpreg = get_num (&opP->disp, 10); 3648 install_operand (s[1], tmpreg - 1); 3649 break; 3650 case 'K': 3651 tmpreg = get_num (&opP->disp, 65); 3652 install_operand (s[1], tmpreg); 3653 break; 3654 default: 3655 abort (); 3656 } 3657 } 3658 3659 /* By the time when get here (FINALLY) the_ins contains the complete 3660 instruction, ready to be emitted. . . */ 3661} 3662 3663static int 3664reverse_16_bits (int in) 3665{ 3666 int out = 0; 3667 int n; 3668 3669 static int mask[16] = 3670 { 3671 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3672 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 3673 }; 3674 for (n = 0; n < 16; n++) 3675 { 3676 if (in & mask[n]) 3677 out |= mask[15 - n]; 3678 } 3679 return out; 3680} /* reverse_16_bits() */ 3681 3682static int 3683reverse_8_bits (int in) 3684{ 3685 int out = 0; 3686 int n; 3687 3688 static int mask[8] = 3689 { 3690 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3691 }; 3692 3693 for (n = 0; n < 8; n++) 3694 { 3695 if (in & mask[n]) 3696 out |= mask[7 - n]; 3697 } 3698 return out; 3699} /* reverse_8_bits() */ 3700 3701/* Cause an extra frag to be generated here, inserting up to 3702 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be 3703 generated; its primary type is rs_machine_dependent. 3704 3705 The TYPE parameter is also used by md_convert_frag_1 and 3706 md_estimate_size_before_relax. The appropriate type of fixup will 3707 be emitted by md_convert_frag_1. 3708 3709 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 3710static void 3711install_operand (int mode, int val) 3712{ 3713 switch (mode) 3714 { 3715 case 's': 3716 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ 3717 break; 3718 case 'd': 3719 the_ins.opcode[0] |= val << 9; 3720 break; 3721 case 'E': 3722 the_ins.opcode[1] |= val << 9; 3723 break; 3724 case '1': 3725 the_ins.opcode[1] |= val << 12; 3726 break; 3727 case '2': 3728 the_ins.opcode[1] |= val << 6; 3729 break; 3730 case '3': 3731 the_ins.opcode[1] |= val; 3732 break; 3733 case '4': 3734 the_ins.opcode[2] |= val << 12; 3735 break; 3736 case '5': 3737 the_ins.opcode[2] |= val << 6; 3738 break; 3739 case '6': 3740 /* DANGER! This is a hack to force cas2l and cas2w cmds to be 3741 three words long! */ 3742 the_ins.numo++; 3743 the_ins.opcode[2] |= val; 3744 break; 3745 case '7': 3746 the_ins.opcode[1] |= val << 7; 3747 break; 3748 case '8': 3749 the_ins.opcode[1] |= val << 10; 3750 break; 3751#ifndef NO_68851 3752 case '9': 3753 the_ins.opcode[1] |= val << 5; 3754 break; 3755#endif 3756 3757 case 't': 3758 the_ins.opcode[1] |= (val << 10) | (val << 7); 3759 break; 3760 case 'D': 3761 the_ins.opcode[1] |= (val << 12) | val; 3762 break; 3763 case 'g': 3764 the_ins.opcode[0] |= val = 0xff; 3765 break; 3766 case 'i': 3767 the_ins.opcode[0] |= val << 9; 3768 break; 3769 case 'C': 3770 the_ins.opcode[1] |= val; 3771 break; 3772 case 'j': 3773 the_ins.opcode[1] |= val; 3774 the_ins.numo++; /* What a hack. */ 3775 break; 3776 case 'k': 3777 the_ins.opcode[1] |= val << 4; 3778 break; 3779 case 'b': 3780 case 'w': 3781 case 'W': 3782 case 'l': 3783 break; 3784 case 'e': 3785 the_ins.opcode[0] |= (val << 6); 3786 break; 3787 case 'L': 3788 the_ins.opcode[1] = (val >> 16); 3789 the_ins.opcode[2] = val & 0xffff; 3790 break; 3791 case 'm': 3792 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3793 the_ins.opcode[0] |= ((val & 0x7) << 9); 3794 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3795 break; 3796 case 'n': /* MAC/EMAC Rx on !load. */ 3797 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3798 the_ins.opcode[0] |= ((val & 0x7) << 9); 3799 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3800 break; 3801 case 'o': /* MAC/EMAC Rx on load. */ 3802 the_ins.opcode[1] |= val << 12; 3803 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3804 break; 3805 case 'M': /* MAC/EMAC Ry on !load. */ 3806 the_ins.opcode[0] |= (val & 0xF); 3807 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3808 break; 3809 case 'N': /* MAC/EMAC Ry on load. */ 3810 the_ins.opcode[1] |= (val & 0xF); 3811 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3812 break; 3813 case 'h': 3814 the_ins.opcode[1] |= ((val != 1) << 10); 3815 break; 3816 case 'F': 3817 the_ins.opcode[0] |= ((val & 0x3) << 9); 3818 break; 3819 case 'f': 3820 the_ins.opcode[0] |= ((val & 0x3) << 0); 3821 break; 3822 case 'G': /* EMAC accumulator in a EMAC load instruction. */ 3823 the_ins.opcode[0] |= ((~val & 0x1) << 7); 3824 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3825 break; 3826 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ 3827 the_ins.opcode[0] |= ((val & 0x1) << 7); 3828 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3829 break; 3830 case 'I': 3831 the_ins.opcode[1] |= ((val & 0x3) << 9); 3832 break; 3833 case ']': 3834 the_ins.opcode[0] |= (val & 0x1) <<10; 3835 break; 3836 case 'c': 3837 default: 3838 as_fatal (_("failed sanity check.")); 3839 } 3840} 3841 3842static void 3843install_gen_operand (int mode, int val) 3844{ 3845 switch (mode) 3846 { 3847 case '/': /* Special for mask loads for mac/msac insns with 3848 possible mask; trailing_ampersand set in bit 8. */ 3849 the_ins.opcode[0] |= (val & 0x3f); 3850 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); 3851 break; 3852 case 's': 3853 the_ins.opcode[0] |= val; 3854 break; 3855 case 'd': 3856 /* This is a kludge!!! */ 3857 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; 3858 break; 3859 case 'b': 3860 case 'w': 3861 case 'l': 3862 case 'f': 3863 case 'F': 3864 case 'x': 3865 case 'p': 3866 the_ins.opcode[0] |= val; 3867 break; 3868 /* more stuff goes here. */ 3869 default: 3870 as_fatal (_("failed sanity check.")); 3871 } 3872} 3873 3874/* Verify that we have some number of paren pairs, do m68k_ip_op(), and 3875 then deal with the bitfield hack. */ 3876 3877static char * 3878crack_operand (char *str, struct m68k_op *opP) 3879{ 3880 int parens; 3881 int c; 3882 char *beg_str; 3883 int inquote = 0; 3884 3885 if (!str) 3886 { 3887 return str; 3888 } 3889 beg_str = str; 3890 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) 3891 { 3892 if (! inquote) 3893 { 3894 if (*str == '(') 3895 parens++; 3896 else if (*str == ')') 3897 { 3898 if (!parens) 3899 { /* ERROR. */ 3900 opP->error = _("Extra )"); 3901 return str; 3902 } 3903 --parens; 3904 } 3905 } 3906 if (flag_mri && *str == '\'') 3907 inquote = ! inquote; 3908 } 3909 if (!*str && parens) 3910 { /* ERROR. */ 3911 opP->error = _("Missing )"); 3912 return str; 3913 } 3914 c = *str; 3915 *str = '\0'; 3916 if (m68k_ip_op (beg_str, opP) != 0) 3917 { 3918 *str = c; 3919 return str; 3920 } 3921 *str = c; 3922 if (c == '}') 3923 c = *++str; /* JF bitfield hack. */ 3924 if (c) 3925 { 3926 c = *++str; 3927 if (!c) 3928 as_bad (_("Missing operand")); 3929 } 3930 3931 /* Detect MRI REG symbols and convert them to REGLSTs. */ 3932 if (opP->mode == CONTROL && (int)opP->reg < 0) 3933 { 3934 opP->mode = REGLST; 3935 opP->mask = ~(int)opP->reg; 3936 opP->reg = 0; 3937 } 3938 3939 return str; 3940} 3941 3942/* This is the guts of the machine-dependent assembler. STR points to a 3943 machine dependent instruction. This function is supposed to emit 3944 the frags/bytes it assembles to. 3945 */ 3946 3947static void 3948insert_reg (const char *regname, int regnum) 3949{ 3950 char buf[100]; 3951 int i; 3952 3953#ifdef REGISTER_PREFIX 3954 if (!flag_reg_prefix_optional) 3955 { 3956 buf[0] = REGISTER_PREFIX; 3957 strcpy (buf + 1, regname); 3958 regname = buf; 3959 } 3960#endif 3961 3962 symbol_table_insert (symbol_new (regname, reg_section, 3963 &zero_address_frag, regnum)); 3964 3965 for (i = 0; regname[i]; i++) 3966 buf[i] = TOUPPER (regname[i]); 3967 buf[i] = '\0'; 3968 3969 symbol_table_insert (symbol_new (buf, reg_section, 3970 &zero_address_frag, regnum)); 3971} 3972 3973struct init_entry 3974 { 3975 const char *name; 3976 int number; 3977 }; 3978 3979static const struct init_entry init_table[] = 3980{ 3981 { "d0", DATA0 }, 3982 { "d1", DATA1 }, 3983 { "d2", DATA2 }, 3984 { "d3", DATA3 }, 3985 { "d4", DATA4 }, 3986 { "d5", DATA5 }, 3987 { "d6", DATA6 }, 3988 { "d7", DATA7 }, 3989 { "a0", ADDR0 }, 3990 { "a1", ADDR1 }, 3991 { "a2", ADDR2 }, 3992 { "a3", ADDR3 }, 3993 { "a4", ADDR4 }, 3994 { "a5", ADDR5 }, 3995 { "a6", ADDR6 }, 3996 { "fp", ADDR6 }, 3997 { "a7", ADDR7 }, 3998 { "sp", ADDR7 }, 3999 { "ssp", ADDR7 }, 4000 { "fp0", FP0 }, 4001 { "fp1", FP1 }, 4002 { "fp2", FP2 }, 4003 { "fp3", FP3 }, 4004 { "fp4", FP4 }, 4005 { "fp5", FP5 }, 4006 { "fp6", FP6 }, 4007 { "fp7", FP7 }, 4008 { "fpi", FPI }, 4009 { "fpiar", FPI }, 4010 { "fpc", FPI }, 4011 { "fps", FPS }, 4012 { "fpsr", FPS }, 4013 { "fpc", FPC }, 4014 { "fpcr", FPC }, 4015 { "control", FPC }, 4016 { "status", FPS }, 4017 { "iaddr", FPI }, 4018 4019 { "cop0", COP0 }, 4020 { "cop1", COP1 }, 4021 { "cop2", COP2 }, 4022 { "cop3", COP3 }, 4023 { "cop4", COP4 }, 4024 { "cop5", COP5 }, 4025 { "cop6", COP6 }, 4026 { "cop7", COP7 }, 4027 { "pc", PC }, 4028 { "zpc", ZPC }, 4029 { "sr", SR }, 4030 4031 { "ccr", CCR }, 4032 { "cc", CCR }, 4033 4034 { "acc", ACC }, 4035 { "acc0", ACC }, 4036 { "acc1", ACC1 }, 4037 { "acc2", ACC2 }, 4038 { "acc3", ACC3 }, 4039 { "accext01", ACCEXT01 }, 4040 { "accext23", ACCEXT23 }, 4041 { "macsr", MACSR }, 4042 { "mask", MASK }, 4043 4044 /* Control registers. */ 4045 { "sfc", SFC }, /* Source Function Code. */ 4046 { "sfcr", SFC }, 4047 { "dfc", DFC }, /* Destination Function Code. */ 4048 { "dfcr", DFC }, 4049 { "cacr", CACR }, /* Cache Control Register. */ 4050 { "caar", CAAR }, /* Cache Address Register. */ 4051 { "cpucr", CPUCR }, /* CPU Control Register. */ 4052 4053 { "usp", USP }, /* User Stack Pointer. */ 4054 { "vbr", VBR }, /* Vector Base Register. */ 4055 { "msp", MSP }, /* Master Stack Pointer. */ 4056 { "isp", ISP }, /* Interrupt Stack Pointer. */ 4057 4058 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ 4059 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ 4060 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ 4061 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ 4062 4063 /* 68ec040 versions of same */ 4064 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ 4065 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ 4066 { "dacr0", DTT0 }, /* Data Access Control Register 0. */ 4067 { "dacr1", DTT1 }, /* Data Access Control Register 0. */ 4068 4069 /* Coldfire versions of same. The ColdFire programmer's reference 4070 manual indicated that the order is 2,3,0,1, but Ken Rose 4071 <rose@netcom.com> says that 0,1,2,3 is the correct order. */ 4072 { "acr0", ACR0 }, /* Access Control Unit 0. */ 4073 { "acr1", ACR1 }, /* Access Control Unit 1. */ 4074 { "acr2", ACR2 }, /* Access Control Unit 2. */ 4075 { "acr3", ACR3 }, /* Access Control Unit 3. */ 4076 { "acr4", ACR4 }, /* Access Control Unit 4. */ 4077 { "acr5", ACR5 }, /* Access Control Unit 5. */ 4078 { "acr6", ACR6 }, /* Access Control Unit 6. */ 4079 { "acr7", ACR7 }, /* Access Control Unit 7. */ 4080 4081 { "tc", TC }, /* MMU Translation Control Register. */ 4082 { "tcr", TC }, 4083 { "asid", ASID }, 4084 4085 { "mmusr", MMUSR }, /* MMU Status Register. */ 4086 { "srp", SRP }, /* User Root Pointer. */ 4087 { "urp", URP }, /* Supervisor Root Pointer. */ 4088 4089 { "buscr", BUSCR }, 4090 { "mmubar", MMUBAR }, 4091 { "pcr", PCR }, 4092 4093 { "rombar", ROMBAR }, /* ROM Base Address Register. */ 4094 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ 4095 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ 4096 { "mbar", MBAR }, /* Module Base Address Register. */ 4097 4098 { "mbar0", MBAR0 }, /* mcfv4e registers. */ 4099 { "mbar1", MBAR1 }, /* mcfv4e registers. */ 4100 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ 4101 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ 4102 { "mpcr", MPCR }, /* mcfv4e registers. */ 4103 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ 4104 { "secmbar", SECMBAR }, /* mcfv4e registers. */ 4105 { "asid", TC }, /* mcfv4e registers. */ 4106 { "mmubar", BUSCR }, /* mcfv4e registers. */ 4107 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ 4108 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ 4109 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ 4110 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ 4111 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ 4112 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ 4113 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ 4114 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ 4115 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ 4116 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ 4117 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ 4118 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ 4119 4120 { "flashbar", FLASHBAR }, /* mcf528x registers. */ 4121 { "rambar", RAMBAR }, /* mcf528x registers. */ 4122 4123 { "mbar2", MBAR2 }, /* mcf5249 registers. */ 4124 4125 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ 4126 4127 { "cac", CAC }, /* fido registers. */ 4128 { "mbb", MBO }, /* fido registers (obsolete). */ 4129 { "mbo", MBO }, /* fido registers. */ 4130 /* End of control registers. */ 4131 4132 { "ac", AC }, 4133 { "bc", BC }, 4134 { "cal", CAL }, 4135 { "crp", CRP }, 4136 { "drp", DRP }, 4137 { "pcsr", PCSR }, 4138 { "psr", PSR }, 4139 { "scc", SCC }, 4140 { "val", VAL }, 4141 { "bad0", BAD0 }, 4142 { "bad1", BAD1 }, 4143 { "bad2", BAD2 }, 4144 { "bad3", BAD3 }, 4145 { "bad4", BAD4 }, 4146 { "bad5", BAD5 }, 4147 { "bad6", BAD6 }, 4148 { "bad7", BAD7 }, 4149 { "bac0", BAC0 }, 4150 { "bac1", BAC1 }, 4151 { "bac2", BAC2 }, 4152 { "bac3", BAC3 }, 4153 { "bac4", BAC4 }, 4154 { "bac5", BAC5 }, 4155 { "bac6", BAC6 }, 4156 { "bac7", BAC7 }, 4157 4158 { "ic", IC }, 4159 { "dc", DC }, 4160 { "nc", NC }, 4161 4162 { "tt0", TT0 }, 4163 { "tt1", TT1 }, 4164 /* 68ec030 versions of same. */ 4165 { "ac0", TT0 }, 4166 { "ac1", TT1 }, 4167 /* 68ec030 access control unit, identical to 030 MMU status reg. */ 4168 { "acusr", PSR }, 4169 4170 /* Suppressed data and address registers. */ 4171 { "zd0", ZDATA0 }, 4172 { "zd1", ZDATA1 }, 4173 { "zd2", ZDATA2 }, 4174 { "zd3", ZDATA3 }, 4175 { "zd4", ZDATA4 }, 4176 { "zd5", ZDATA5 }, 4177 { "zd6", ZDATA6 }, 4178 { "zd7", ZDATA7 }, 4179 { "za0", ZADDR0 }, 4180 { "za1", ZADDR1 }, 4181 { "za2", ZADDR2 }, 4182 { "za3", ZADDR3 }, 4183 { "za4", ZADDR4 }, 4184 { "za5", ZADDR5 }, 4185 { "za6", ZADDR6 }, 4186 { "za7", ZADDR7 }, 4187 4188 /* Upper and lower data and address registers, used by macw and msacw. */ 4189 { "d0l", DATA0L }, 4190 { "d1l", DATA1L }, 4191 { "d2l", DATA2L }, 4192 { "d3l", DATA3L }, 4193 { "d4l", DATA4L }, 4194 { "d5l", DATA5L }, 4195 { "d6l", DATA6L }, 4196 { "d7l", DATA7L }, 4197 4198 { "a0l", ADDR0L }, 4199 { "a1l", ADDR1L }, 4200 { "a2l", ADDR2L }, 4201 { "a3l", ADDR3L }, 4202 { "a4l", ADDR4L }, 4203 { "a5l", ADDR5L }, 4204 { "a6l", ADDR6L }, 4205 { "a7l", ADDR7L }, 4206 4207 { "d0u", DATA0U }, 4208 { "d1u", DATA1U }, 4209 { "d2u", DATA2U }, 4210 { "d3u", DATA3U }, 4211 { "d4u", DATA4U }, 4212 { "d5u", DATA5U }, 4213 { "d6u", DATA6U }, 4214 { "d7u", DATA7U }, 4215 4216 { "a0u", ADDR0U }, 4217 { "a1u", ADDR1U }, 4218 { "a2u", ADDR2U }, 4219 { "a3u", ADDR3U }, 4220 { "a4u", ADDR4U }, 4221 { "a5u", ADDR5U }, 4222 { "a6u", ADDR6U }, 4223 { "a7u", ADDR7U }, 4224 4225 { 0, 0 } 4226}; 4227 4228static void 4229init_regtable (void) 4230{ 4231 int i; 4232 for (i = 0; init_table[i].name; i++) 4233 insert_reg (init_table[i].name, init_table[i].number); 4234} 4235 4236void 4237md_assemble (char *str) 4238{ 4239 const char *er; 4240 short *fromP; 4241 char *toP = NULL; 4242 int m, n = 0; 4243 char *to_beg_P; 4244 int shorts_this_frag; 4245 fixS *fixP; 4246 4247 if (!selected_cpu && !selected_arch) 4248 { 4249 /* We've not selected an architecture yet. Set the default 4250 now. We do this lazily so that an initial .cpu or .arch directive 4251 can specify. */ 4252 if (!m68k_set_cpu (TARGET_CPU, 1, 1)) 4253 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); 4254 } 4255 if (!initialized) 4256 m68k_init_arch (); 4257 4258 /* In MRI mode, the instruction and operands are separated by a 4259 space. Anything following the operands is a comment. The label 4260 has already been removed. */ 4261 if (flag_mri) 4262 { 4263 char *s; 4264 int fields = 0; 4265 int infield = 0; 4266 int inquote = 0; 4267 4268 for (s = str; *s != '\0'; s++) 4269 { 4270 if ((*s == ' ' || *s == '\t') && ! inquote) 4271 { 4272 if (infield) 4273 { 4274 ++fields; 4275 if (fields >= 2) 4276 { 4277 *s = '\0'; 4278 break; 4279 } 4280 infield = 0; 4281 } 4282 } 4283 else 4284 { 4285 if (! infield) 4286 infield = 1; 4287 if (*s == '\'') 4288 inquote = ! inquote; 4289 } 4290 } 4291 } 4292 4293 memset (&the_ins, '\0', sizeof (the_ins)); 4294 m68k_ip (str); 4295 er = the_ins.error; 4296 if (!er) 4297 { 4298 for (n = 0; n < the_ins.numargs; n++) 4299 if (the_ins.operands[n].error) 4300 { 4301 er = the_ins.operands[n].error; 4302 break; 4303 } 4304 } 4305 if (er) 4306 { 4307 as_bad (_("%s -- statement `%s' ignored"), er, str); 4308 return; 4309 } 4310 4311 /* If there is a current label, record that it marks an instruction. */ 4312 if (current_label != NULL) 4313 { 4314 current_label->text = 1; 4315 current_label = NULL; 4316 } 4317 4318 /* Tie dwarf2 debug info to the address at the start of the insn. */ 4319 dwarf2_emit_insn (0); 4320 4321 if (the_ins.nfrag == 0) 4322 { 4323 /* No frag hacking involved; just put it out. */ 4324 toP = frag_more (2 * the_ins.numo); 4325 fromP = &the_ins.opcode[0]; 4326 for (m = the_ins.numo; m; --m) 4327 { 4328 md_number_to_chars (toP, (long) (*fromP), 2); 4329 toP += 2; 4330 fromP++; 4331 } 4332 /* Put out symbol-dependent info. */ 4333 for (m = 0; m < the_ins.nrel; m++) 4334 { 4335 switch (the_ins.reloc[m].wid) 4336 { 4337 case 'B': 4338 n = 1; 4339 break; 4340 case 'b': 4341 n = 1; 4342 break; 4343 case '3': 4344 n = 1; 4345 break; 4346 case 'w': 4347 case 'W': 4348 n = 2; 4349 break; 4350 case 'l': 4351 n = 4; 4352 break; 4353 default: 4354 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"), 4355 the_ins.reloc[m].wid); 4356 } 4357 4358 fixP = fix_new_exp (frag_now, 4359 ((toP - frag_now->fr_literal) 4360 - the_ins.numo * 2 + the_ins.reloc[m].n), 4361 n, 4362 &the_ins.reloc[m].exp, 4363 the_ins.reloc[m].pcrel, 4364 get_reloc_code (n, the_ins.reloc[m].pcrel, 4365 the_ins.reloc[m].pic_reloc)); 4366 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4367 if (the_ins.reloc[m].wid == 'B') 4368 fixP->fx_signed = 1; 4369 } 4370 return; 4371 } 4372 4373 /* There's some frag hacking. */ 4374 { 4375 /* Calculate the max frag size. */ 4376 int wid; 4377 4378 wid = 2 * the_ins.fragb[0].fragoff; 4379 for (n = 1; n < the_ins.nfrag; n++) 4380 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4381 /* frag_var part. */ 4382 wid += FRAG_VAR_SIZE; 4383 /* Make sure the whole insn fits in one chunk, in particular that 4384 the var part is attached, as we access one byte before the 4385 variable frag for byte branches. */ 4386 frag_grow (wid); 4387 } 4388 4389 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) 4390 { 4391 int wid; 4392 4393 if (n == 0) 4394 wid = 2 * the_ins.fragb[n].fragoff; 4395 else 4396 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4397 toP = frag_more (wid); 4398 to_beg_P = toP; 4399 shorts_this_frag = 0; 4400 for (m = wid / 2; m; --m) 4401 { 4402 md_number_to_chars (toP, (long) (*fromP), 2); 4403 toP += 2; 4404 fromP++; 4405 shorts_this_frag++; 4406 } 4407 for (m = 0; m < the_ins.nrel; m++) 4408 { 4409 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) 4410 { 4411 the_ins.reloc[m].n -= 2 * shorts_this_frag; 4412 break; 4413 } 4414 wid = the_ins.reloc[m].wid; 4415 if (wid == 0) 4416 continue; 4417 the_ins.reloc[m].wid = 0; 4418 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4419 4420 fixP = fix_new_exp (frag_now, 4421 ((toP - frag_now->fr_literal) 4422 - the_ins.numo * 2 + the_ins.reloc[m].n), 4423 wid, 4424 &the_ins.reloc[m].exp, 4425 the_ins.reloc[m].pcrel, 4426 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4427 the_ins.reloc[m].pic_reloc)); 4428 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4429 } 4430 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, 4431 (relax_substateT) (the_ins.fragb[n].fragty), 4432 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); 4433 } 4434 gas_assert (the_ins.nfrag >= 1); 4435 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff; 4436 shorts_this_frag = 0; 4437 if (n) 4438 { 4439 toP = frag_more (n * 2); 4440 while (n--) 4441 { 4442 md_number_to_chars (toP, (long) (*fromP), 2); 4443 toP += 2; 4444 fromP++; 4445 shorts_this_frag++; 4446 } 4447 } 4448 for (m = 0; m < the_ins.nrel; m++) 4449 { 4450 int wid; 4451 4452 wid = the_ins.reloc[m].wid; 4453 if (wid == 0) 4454 continue; 4455 the_ins.reloc[m].wid = 0; 4456 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4457 4458 fixP = fix_new_exp (frag_now, 4459 ((the_ins.reloc[m].n + toP - frag_now->fr_literal) 4460 - shorts_this_frag * 2), 4461 wid, 4462 &the_ins.reloc[m].exp, 4463 the_ins.reloc[m].pcrel, 4464 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4465 the_ins.reloc[m].pic_reloc)); 4466 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4467 } 4468} 4469 4470/* Comparison function used by qsort to rank the opcode entries by name. */ 4471 4472static int 4473m68k_compare_opcode (const void * v1, const void * v2) 4474{ 4475 struct m68k_opcode * op1, * op2; 4476 int ret; 4477 4478 if (v1 == v2) 4479 return 0; 4480 4481 op1 = *(struct m68k_opcode **) v1; 4482 op2 = *(struct m68k_opcode **) v2; 4483 4484 /* Compare the two names. If different, return the comparison. 4485 If the same, return the order they are in the opcode table. */ 4486 ret = strcmp (op1->name, op2->name); 4487 if (ret) 4488 return ret; 4489 if (op1 < op2) 4490 return -1; 4491 return 1; 4492} 4493 4494void 4495md_begin (void) 4496{ 4497 const struct m68k_opcode *ins; 4498 struct m68k_incant *hack, *slak; 4499 int i; 4500 4501 /* Set up hash tables with 68000 instructions. 4502 similar to what the vax assembler does. */ 4503 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 4504 a copy of it at runtime, adding in the information we want but isn't 4505 there. I think it'd be better to have an awk script hack the table 4506 at compile time. Or even just xstr the table and use it as-is. But 4507 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 4508 names. */ 4509 4510 if (flag_mri) 4511 { 4512 flag_reg_prefix_optional = 1; 4513 m68k_abspcadd = 1; 4514 if (! m68k_rel32_from_cmdline) 4515 m68k_rel32 = 0; 4516 } 4517 4518 /* First sort the opcode table into alphabetical order to separate 4519 the order that the assembler wants to see the opcodes from the 4520 order that the disassembler wants to see them. */ 4521 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes); 4522 4523 for (i = m68k_numopcodes; i--;) 4524 m68k_sorted_opcodes[i] = m68k_opcodes + i; 4525 4526 qsort (m68k_sorted_opcodes, m68k_numopcodes, 4527 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); 4528 4529 op_hash = str_htab_create (); 4530 4531 obstack_begin (&robyn, 4000); 4532 for (i = 0; i < m68k_numopcodes; i++) 4533 { 4534 hack = slak = XOBNEW (&robyn, struct m68k_incant); 4535 do 4536 { 4537 ins = m68k_sorted_opcodes[i]; 4538 4539 /* We must enter all insns into the table, because .arch and 4540 .cpu directives can change things. */ 4541 slak->m_operands = ins->args; 4542 slak->m_arch = ins->arch; 4543 slak->m_opcode = ins->opcode; 4544 4545 /* In most cases we can determine the number of opcode words 4546 by checking the second word of the mask. Unfortunately 4547 some instructions have 2 opcode words, but no fixed bits 4548 in the second word. A leading dot in the operands 4549 string also indicates 2 opcodes. */ 4550 if (*slak->m_operands == '.') 4551 { 4552 slak->m_operands++; 4553 slak->m_codenum = 2; 4554 } 4555 else if (ins->match & 0xffffL) 4556 slak->m_codenum = 2; 4557 else 4558 slak->m_codenum = 1; 4559 slak->m_opnum = strlen (slak->m_operands) / 2; 4560 4561 if (i + 1 != m68k_numopcodes 4562 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) 4563 { 4564 slak->m_next = XOBNEW (&robyn, struct m68k_incant); 4565 i++; 4566 } 4567 else 4568 slak->m_next = 0; 4569 slak = slak->m_next; 4570 } 4571 while (slak); 4572 4573 if (str_hash_insert (op_hash, ins->name, hack, 0) != NULL) 4574 as_fatal (_("duplicate %s"), ins->name); 4575 } 4576 4577 for (i = 0; i < m68k_numaliases; i++) 4578 { 4579 const char *name = m68k_opcode_aliases[i].primary; 4580 const char *alias = m68k_opcode_aliases[i].alias; 4581 void *val = (void *) str_hash_find (op_hash, name); 4582 4583 if (!val) 4584 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4585 if (str_hash_insert (op_hash, alias, val, 0) != NULL) 4586 as_fatal (_("duplicate %s"), alias); 4587 } 4588 4589 /* In MRI mode, all unsized branches are variable sized. Normally, 4590 they are word sized. */ 4591 if (flag_mri) 4592 { 4593 static struct m68k_opcode_alias mri_aliases[] = 4594 { 4595 { "bhi", "jhi", }, 4596 { "bls", "jls", }, 4597 { "bcc", "jcc", }, 4598 { "bcs", "jcs", }, 4599 { "bne", "jne", }, 4600 { "beq", "jeq", }, 4601 { "bvc", "jvc", }, 4602 { "bvs", "jvs", }, 4603 { "bpl", "jpl", }, 4604 { "bmi", "jmi", }, 4605 { "bge", "jge", }, 4606 { "blt", "jlt", }, 4607 { "bgt", "jgt", }, 4608 { "ble", "jle", }, 4609 { "bra", "jra", }, 4610 { "bsr", "jbsr", }, 4611 }; 4612 4613 for (i = 0; 4614 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); 4615 i++) 4616 { 4617 const char *name = mri_aliases[i].primary; 4618 const char *alias = mri_aliases[i].alias; 4619 void *val = (void *) str_hash_find (op_hash, name); 4620 4621 if (!val) 4622 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4623 str_hash_insert (op_hash, alias, val, 1); 4624 } 4625 } 4626 4627 for (i = 0; i < (int) sizeof (notend_table); i++) 4628 { 4629 notend_table[i] = 0; 4630 alt_notend_table[i] = 0; 4631 } 4632 4633 notend_table[','] = 1; 4634 notend_table['{'] = 1; 4635 notend_table['}'] = 1; 4636 alt_notend_table['a'] = 1; 4637 alt_notend_table['A'] = 1; 4638 alt_notend_table['d'] = 1; 4639 alt_notend_table['D'] = 1; 4640 alt_notend_table['#'] = 1; 4641 alt_notend_table['&'] = 1; 4642 alt_notend_table['f'] = 1; 4643 alt_notend_table['F'] = 1; 4644#ifdef REGISTER_PREFIX 4645 alt_notend_table[REGISTER_PREFIX] = 1; 4646#endif 4647 4648 /* We need to put '(' in alt_notend_table to handle 4649 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ 4650 alt_notend_table['('] = 1; 4651 4652 /* We need to put '@' in alt_notend_table to handle 4653 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ 4654 alt_notend_table['@'] = 1; 4655 4656 /* We need to put digits in alt_notend_table to handle 4657 bfextu %d0{24:1},%d0 */ 4658 alt_notend_table['0'] = 1; 4659 alt_notend_table['1'] = 1; 4660 alt_notend_table['2'] = 1; 4661 alt_notend_table['3'] = 1; 4662 alt_notend_table['4'] = 1; 4663 alt_notend_table['5'] = 1; 4664 alt_notend_table['6'] = 1; 4665 alt_notend_table['7'] = 1; 4666 alt_notend_table['8'] = 1; 4667 alt_notend_table['9'] = 1; 4668 4669#ifndef MIT_SYNTAX_ONLY 4670 /* Insert pseudo ops, these have to go into the opcode table since 4671 gas expects pseudo ops to start with a dot. */ 4672 { 4673 int n = 0; 4674 4675 while (mote_pseudo_table[n].poc_name) 4676 { 4677 hack = XOBNEW (&robyn, struct m68k_incant); 4678 str_hash_insert (op_hash, 4679 mote_pseudo_table[n].poc_name, hack, 0); 4680 hack->m_operands = 0; 4681 hack->m_opnum = n; 4682 n++; 4683 } 4684 } 4685#endif 4686 4687 init_regtable (); 4688 4689 record_alignment (text_section, 2); 4690 record_alignment (data_section, 2); 4691 record_alignment (bss_section, 2); 4692} 4693 4694 4695/* This is called when a label is defined. */ 4696 4697void 4698m68k_frob_label (symbolS *sym) 4699{ 4700 struct label_line *n; 4701 4702 n = XNEW (struct label_line); 4703 n->next = labels; 4704 n->label = sym; 4705 n->file = as_where (&n->line); 4706 n->text = 0; 4707 labels = n; 4708 current_label = n; 4709 4710 dwarf2_emit_label (sym); 4711} 4712 4713/* This is called when a value that is not an instruction is emitted. */ 4714 4715void 4716m68k_flush_pending_output (void) 4717{ 4718 current_label = NULL; 4719} 4720 4721/* This is called at the end of the assembly, when the final value of 4722 the label is known. We warn if this is a text symbol aligned at an 4723 odd location. */ 4724 4725void 4726m68k_frob_symbol (symbolS *sym) 4727{ 4728 if (S_GET_SEGMENT (sym) == reg_section 4729 && (int) S_GET_VALUE (sym) < 0) 4730 { 4731 S_SET_SEGMENT (sym, absolute_section); 4732 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); 4733 } 4734 else if ((S_GET_VALUE (sym) & 1) != 0) 4735 { 4736 struct label_line *l; 4737 4738 for (l = labels; l != NULL; l = l->next) 4739 { 4740 if (l->label == sym) 4741 { 4742 if (l->text) 4743 as_warn_where (l->file, l->line, 4744 _("text label `%s' aligned to odd boundary"), 4745 S_GET_NAME (sym)); 4746 break; 4747 } 4748 } 4749 } 4750} 4751 4752/* This is called if we go in or out of MRI mode because of the .mri 4753 pseudo-op. */ 4754 4755void 4756m68k_mri_mode_change (int on) 4757{ 4758 if (on) 4759 { 4760 if (! flag_reg_prefix_optional) 4761 { 4762 flag_reg_prefix_optional = 1; 4763#ifdef REGISTER_PREFIX 4764 init_regtable (); 4765#endif 4766 } 4767 m68k_abspcadd = 1; 4768 if (! m68k_rel32_from_cmdline) 4769 m68k_rel32 = 0; 4770 } 4771 else 4772 { 4773 if (! reg_prefix_optional_seen) 4774 { 4775#ifdef REGISTER_PREFIX_OPTIONAL 4776 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 4777#else 4778 flag_reg_prefix_optional = 0; 4779#endif 4780#ifdef REGISTER_PREFIX 4781 init_regtable (); 4782#endif 4783 } 4784 m68k_abspcadd = 0; 4785 if (! m68k_rel32_from_cmdline) 4786 m68k_rel32 = 1; 4787 } 4788} 4789 4790const char * 4791md_atof (int type, char *litP, int *sizeP) 4792{ 4793 return ieee_md_atof (type, litP, sizeP, TRUE); 4794} 4795 4796void 4797md_number_to_chars (char *buf, valueT val, int n) 4798{ 4799 number_to_chars_bigendian (buf, val, n); 4800} 4801 4802void 4803md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4804{ 4805 offsetT val = *valP; 4806 addressT upper_limit; 4807 offsetT lower_limit; 4808 4809 /* This is unnecessary but it convinces the native rs6000 compiler 4810 to generate the code we want. */ 4811 char *buf = fixP->fx_frag->fr_literal; 4812 buf += fixP->fx_where; 4813 /* End ibm compiler workaround. */ 4814 4815 val = SEXT (val); 4816 4817 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 4818 fixP->fx_done = 1; 4819 4820 if (fixP->fx_addsy) 4821 { 4822 memset (buf, 0, fixP->fx_size); 4823 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4824 4825 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4826 && !S_IS_DEFINED (fixP->fx_addsy) 4827 && !S_IS_WEAK (fixP->fx_addsy)) 4828 S_SET_WEAK (fixP->fx_addsy); 4829 4830 switch (fixP->fx_r_type) 4831 { 4832 case BFD_RELOC_68K_TLS_GD32: 4833 case BFD_RELOC_68K_TLS_GD16: 4834 case BFD_RELOC_68K_TLS_GD8: 4835 case BFD_RELOC_68K_TLS_LDM32: 4836 case BFD_RELOC_68K_TLS_LDM16: 4837 case BFD_RELOC_68K_TLS_LDM8: 4838 case BFD_RELOC_68K_TLS_LDO32: 4839 case BFD_RELOC_68K_TLS_LDO16: 4840 case BFD_RELOC_68K_TLS_LDO8: 4841 case BFD_RELOC_68K_TLS_IE32: 4842 case BFD_RELOC_68K_TLS_IE16: 4843 case BFD_RELOC_68K_TLS_IE8: 4844 case BFD_RELOC_68K_TLS_LE32: 4845 case BFD_RELOC_68K_TLS_LE16: 4846 case BFD_RELOC_68K_TLS_LE8: 4847 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4848 break; 4849 4850 default: 4851 break; 4852 } 4853 4854 return; 4855 } 4856 4857 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4858 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4859 return; 4860 4861 switch (fixP->fx_size) 4862 { 4863 /* The cast to offsetT below are necessary to make code 4864 correct for machines where ints are smaller than offsetT. */ 4865 case 1: 4866 *buf++ = val; 4867 upper_limit = 0x7f; 4868 lower_limit = - (offsetT) 0x80; 4869 break; 4870 case 2: 4871 *buf++ = (val >> 8); 4872 *buf++ = val; 4873 upper_limit = 0x7fff; 4874 lower_limit = - (offsetT) 0x8000; 4875 break; 4876 case 4: 4877 *buf++ = (val >> 24); 4878 *buf++ = (val >> 16); 4879 *buf++ = (val >> 8); 4880 *buf++ = val; 4881 upper_limit = 0x7fffffff; 4882 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ 4883 break; 4884 default: 4885 BAD_CASE (fixP->fx_size); 4886 } 4887 4888 /* Fix up a negative reloc. */ 4889 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) 4890 { 4891 fixP->fx_addsy = fixP->fx_subsy; 4892 fixP->fx_subsy = NULL; 4893 fixP->fx_tcbit = 1; 4894 } 4895 4896 /* For non-pc-relative values, it's conceivable we might get something 4897 like "0xff" for a byte field. So extend the upper part of the range 4898 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", 4899 so that we can do any range checking at all. */ 4900 if (! fixP->fx_pcrel && ! fixP->fx_signed) 4901 upper_limit = upper_limit * 2 + 1; 4902 4903 if ((addressT) val > upper_limit 4904 && (val > 0 || val < lower_limit)) 4905 as_bad_where (fixP->fx_file, fixP->fx_line, 4906 _("value %ld out of range"), (long)val); 4907 4908 /* A one byte PC-relative reloc means a short branch. We can't use 4909 a short branch with a value of 0 or -1, because those indicate 4910 different opcodes (branches with longer offsets). fixup_segment 4911 in write.c may have clobbered fx_pcrel, so we need to examine the 4912 reloc type. */ 4913 if ((fixP->fx_pcrel 4914 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 4915 && fixP->fx_size == 1 4916 && (fixP->fx_addsy == NULL 4917 || S_IS_DEFINED (fixP->fx_addsy)) 4918 && (val == 0 || val == -1)) 4919 as_bad_where (fixP->fx_file, fixP->fx_line, 4920 _("invalid byte branch offset")); 4921} 4922 4923/* *fragP has been relaxed to its final size, and now needs to have 4924 the bytes inside it modified to conform to the new size There is UGLY 4925 MAGIC here. .. 4926 */ 4927static void 4928md_convert_frag_1 (fragS *fragP) 4929{ 4930 long disp; 4931 fixS *fixP = NULL; 4932 4933 /* Address in object code of the displacement. */ 4934 int object_address = fragP->fr_fix + fragP->fr_address; 4935 4936 /* Address in gas core of the place to store the displacement. */ 4937 /* This convinces the native rs6000 compiler to generate the code we 4938 want. */ 4939 char *buffer_address = fragP->fr_literal; 4940 buffer_address += fragP->fr_fix; 4941 /* End ibm compiler workaround. */ 4942 4943 /* The displacement of the address, from current location. */ 4944 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; 4945 disp = (disp + fragP->fr_offset) - object_address; 4946 4947 switch (fragP->fr_subtype) 4948 { 4949 case TAB (BRANCHBWL, BYTE): 4950 case TAB (BRABSJUNC, BYTE): 4951 case TAB (BRABSJCOND, BYTE): 4952 case TAB (BRANCHBW, BYTE): 4953 case TAB (BRANCHBWPL, BYTE): 4954 know (issbyte (disp)); 4955 if (disp == 0) 4956 as_bad_where (fragP->fr_file, fragP->fr_line, 4957 _("short branch with zero offset: use :w")); 4958 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 4959 fragP->fr_offset, 1, RELAX_RELOC_PC8); 4960 fixP->fx_pcrel_adjust = -1; 4961 break; 4962 case TAB (BRANCHBWL, SHORT): 4963 case TAB (BRABSJUNC, SHORT): 4964 case TAB (BRABSJCOND, SHORT): 4965 case TAB (BRANCHBW, SHORT): 4966 case TAB (BRANCHBWPL, SHORT): 4967 fragP->fr_opcode[1] = 0x00; 4968 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4969 fragP->fr_offset, 1, RELAX_RELOC_PC16); 4970 fragP->fr_fix += 2; 4971 break; 4972 case TAB (BRANCHBWL, LONG): 4973 fragP->fr_opcode[1] = (char) 0xFF; 4974 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4975 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4976 fragP->fr_fix += 4; 4977 break; 4978 case TAB (BRANCHBWPL, LONG): 4979 /* Here we are converting an unconditional branch into a pair of 4980 conditional branches, in order to get the range. */ 4981 fragP->fr_opcode[0] = 0x66; /* bne */ 4982 fragP->fr_opcode[1] = 0xFF; 4983 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4984 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4985 fixP->fx_file = fragP->fr_file; 4986 fixP->fx_line = fragP->fr_line; 4987 fragP->fr_fix += 4; /* Skip first offset */ 4988 buffer_address += 4; 4989 *buffer_address++ = 0x67; /* beq */ 4990 *buffer_address++ = 0xff; 4991 fragP->fr_fix += 2; /* Skip second branch opcode */ 4992 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 4993 fragP->fr_offset, 1, RELAX_RELOC_PC32); 4994 fragP->fr_fix += 4; 4995 break; 4996 case TAB (BRABSJUNC, LONG): 4997 if (fragP->fr_opcode[0] == 0x61) /* jbsr */ 4998 { 4999 if (flag_keep_pcrel) 5000 as_bad_where (fragP->fr_file, fragP->fr_line, 5001 _("Conversion of PC relative BSR to absolute JSR")); 5002 fragP->fr_opcode[0] = 0x4E; 5003 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ 5004 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5005 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5006 fragP->fr_fix += 4; 5007 } 5008 else if (fragP->fr_opcode[0] == 0x60) /* jbra */ 5009 { 5010 if (flag_keep_pcrel) 5011 as_bad_where (fragP->fr_file, fragP->fr_line, 5012 _("Conversion of PC relative branch to absolute jump")); 5013 fragP->fr_opcode[0] = 0x4E; 5014 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ 5015 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5016 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5017 fragP->fr_fix += 4; 5018 } 5019 else 5020 { 5021 /* This cannot happen, because jbsr and jbra are the only two 5022 unconditional branches. */ 5023 abort (); 5024 } 5025 break; 5026 case TAB (BRABSJCOND, LONG): 5027 if (flag_keep_pcrel) 5028 as_bad_where (fragP->fr_file, fragP->fr_line, 5029 _("Conversion of PC relative conditional branch to absolute jump")); 5030 5031 /* Only Bcc 68000 instructions can come here 5032 Change bcc into b!cc/jmp absl long. */ 5033 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ 5034 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ 5035 5036 /* JF: these used to be fr_opcode[2,3], but they may be in a 5037 different frag, in which case referring to them is a no-no. 5038 Only fr_opcode[0,1] are guaranteed to work. */ 5039 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ 5040 *buffer_address++ = (char) 0xf9; 5041 fragP->fr_fix += 2; /* Account for jmp instruction. */ 5042 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5043 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5044 fragP->fr_fix += 4; 5045 break; 5046 case TAB (FBRANCH, SHORT): 5047 know ((fragP->fr_opcode[1] & 0x40) == 0); 5048 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5049 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5050 fragP->fr_fix += 2; 5051 break; 5052 case TAB (FBRANCH, LONG): 5053 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ 5054 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5055 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5056 fragP->fr_fix += 4; 5057 break; 5058 case TAB (DBCCLBR, SHORT): 5059 case TAB (DBCCABSJ, SHORT): 5060 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5061 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5062 fragP->fr_fix += 2; 5063 break; 5064 case TAB (DBCCLBR, LONG): 5065 /* Only DBcc instructions can come here. 5066 Change dbcc into dbcc/bral. 5067 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5068 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5069 *buffer_address++ = 0x04; 5070 *buffer_address++ = 0x60; /* Put in bra pc+6. */ 5071 *buffer_address++ = 0x06; 5072 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ 5073 *buffer_address++ = (char) 0xff; 5074 5075 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5076 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5077 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5078 fragP->fr_fix += 4; 5079 break; 5080 case TAB (DBCCABSJ, LONG): 5081 /* Only DBcc instructions can come here. 5082 Change dbcc into dbcc/jmp. 5083 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5084 if (flag_keep_pcrel) 5085 as_bad_where (fragP->fr_file, fragP->fr_line, 5086 _("Conversion of PC relative conditional branch to absolute jump")); 5087 5088 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5089 *buffer_address++ = 0x04; 5090 *buffer_address++ = 0x60; /* Put in bra pc + 6. */ 5091 *buffer_address++ = 0x06; 5092 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ 5093 *buffer_address++ = (char) 0xf9; 5094 5095 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5096 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5097 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5098 fragP->fr_fix += 4; 5099 break; 5100 case TAB (PCREL1632, SHORT): 5101 fragP->fr_opcode[1] &= ~0x3F; 5102 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ 5103 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5104 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5105 fragP->fr_fix += 2; 5106 break; 5107 case TAB (PCREL1632, LONG): 5108 /* Already set to mode 7.3; this indicates: PC indirect with 5109 suppressed index, 32-bit displacement. */ 5110 *buffer_address++ = 0x01; 5111 *buffer_address++ = 0x70; 5112 fragP->fr_fix += 2; 5113 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5114 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5115 fixP->fx_pcrel_adjust = 2; 5116 fragP->fr_fix += 4; 5117 break; 5118 case TAB (PCINDEX, BYTE): 5119 gas_assert (fragP->fr_fix >= 2); 5120 buffer_address[-2] &= ~1; 5121 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5122 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5123 fixP->fx_pcrel_adjust = 1; 5124 break; 5125 case TAB (PCINDEX, SHORT): 5126 gas_assert (fragP->fr_fix >= 2); 5127 buffer_address[-2] |= 0x1; 5128 buffer_address[-1] = 0x20; 5129 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5130 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5131 fixP->fx_pcrel_adjust = 2; 5132 fragP->fr_fix += 2; 5133 break; 5134 case TAB (PCINDEX, LONG): 5135 gas_assert (fragP->fr_fix >= 2); 5136 buffer_address[-2] |= 0x1; 5137 buffer_address[-1] = 0x30; 5138 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5139 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5140 fixP->fx_pcrel_adjust = 2; 5141 fragP->fr_fix += 4; 5142 break; 5143 case TAB (ABSTOPCREL, SHORT): 5144 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5145 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5146 fragP->fr_fix += 2; 5147 break; 5148 case TAB (ABSTOPCREL, LONG): 5149 if (flag_keep_pcrel) 5150 as_bad_where (fragP->fr_file, fragP->fr_line, 5151 _("Conversion of PC relative displacement to absolute")); 5152 /* The thing to do here is force it to ABSOLUTE LONG, since 5153 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ 5154 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) 5155 abort (); 5156 fragP->fr_opcode[1] &= ~0x3F; 5157 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 5158 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5159 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5160 fragP->fr_fix += 4; 5161 break; 5162 } 5163 if (fixP) 5164 { 5165 fixP->fx_file = fragP->fr_file; 5166 fixP->fx_line = fragP->fr_line; 5167 } 5168} 5169 5170void 5171md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 5172 segT sec ATTRIBUTE_UNUSED, 5173 fragS *fragP) 5174{ 5175 md_convert_frag_1 (fragP); 5176} 5177 5178/* Force truly undefined symbols to their maximum size, and generally set up 5179 the frag list to be relaxed 5180 */ 5181int 5182md_estimate_size_before_relax (fragS *fragP, segT segment) 5183{ 5184 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ 5185 switch (fragP->fr_subtype) 5186 { 5187 case TAB (BRANCHBWL, SZ_UNDEF): 5188 case TAB (BRANCHBWPL, SZ_UNDEF): 5189 case TAB (BRABSJUNC, SZ_UNDEF): 5190 case TAB (BRABSJCOND, SZ_UNDEF): 5191 { 5192 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5193 && relaxable_symbol (fragP->fr_symbol)) 5194 { 5195 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5196 } 5197 else if (flag_short_refs) 5198 { 5199 /* Symbol is undefined and we want short ref. */ 5200 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5201 } 5202 else 5203 { 5204 /* Symbol is still undefined. Make it LONG. */ 5205 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5206 } 5207 break; 5208 } 5209 5210 case TAB (BRANCHBW, SZ_UNDEF): 5211 { 5212 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5213 && relaxable_symbol (fragP->fr_symbol)) 5214 { 5215 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5216 } 5217 else 5218 { 5219 /* Symbol is undefined and we don't have long branches. */ 5220 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5221 } 5222 break; 5223 } 5224 5225 case TAB (FBRANCH, SZ_UNDEF): 5226 case TAB (DBCCLBR, SZ_UNDEF): 5227 case TAB (DBCCABSJ, SZ_UNDEF): 5228 case TAB (PCREL1632, SZ_UNDEF): 5229 { 5230 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5231 && relaxable_symbol (fragP->fr_symbol)) 5232 || flag_short_refs) 5233 { 5234 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5235 } 5236 else 5237 { 5238 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5239 } 5240 break; 5241 } 5242 5243 case TAB (PCINDEX, SZ_UNDEF): 5244 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5245 && relaxable_symbol (fragP->fr_symbol))) 5246 { 5247 fragP->fr_subtype = TAB (PCINDEX, BYTE); 5248 } 5249 else 5250 { 5251 fragP->fr_subtype = TAB (PCINDEX, LONG); 5252 } 5253 break; 5254 5255 case TAB (ABSTOPCREL, SZ_UNDEF): 5256 { 5257 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5258 && relaxable_symbol (fragP->fr_symbol))) 5259 { 5260 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); 5261 } 5262 else 5263 { 5264 fragP->fr_subtype = TAB (ABSTOPCREL, LONG); 5265 } 5266 break; 5267 } 5268 5269 default: 5270 break; 5271 } 5272 5273 /* Now that SZ_UNDEF are taken care of, check others. */ 5274 switch (fragP->fr_subtype) 5275 { 5276 case TAB (BRANCHBWL, BYTE): 5277 case TAB (BRABSJUNC, BYTE): 5278 case TAB (BRABSJCOND, BYTE): 5279 case TAB (BRANCHBW, BYTE): 5280 /* We can't do a short jump to the next instruction, so in that 5281 case we force word mode. If the symbol is at the start of a 5282 frag, and it is the next frag with any data in it (usually 5283 this is just the next frag, but assembler listings may 5284 introduce empty frags), we must use word mode. */ 5285 if (fragP->fr_symbol) 5286 { 5287 fragS *sym_frag; 5288 5289 sym_frag = symbol_get_frag (fragP->fr_symbol); 5290 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) 5291 { 5292 fragS *l; 5293 5294 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) 5295 if (l->fr_fix != 0) 5296 break; 5297 if (l == sym_frag) 5298 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5299 } 5300 } 5301 break; 5302 default: 5303 break; 5304 } 5305 return md_relax_table[fragP->fr_subtype].rlx_length; 5306} 5307 5308#ifndef WORKING_DOT_WORD 5309int md_short_jump_size = 4; 5310int md_long_jump_size = 6; 5311 5312void 5313md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, 5314 fragS *frag ATTRIBUTE_UNUSED, 5315 symbolS *to_symbol ATTRIBUTE_UNUSED) 5316{ 5317 valueT offset; 5318 5319 offset = to_addr - (from_addr + 2); 5320 5321 md_number_to_chars (ptr, (valueT) 0x6000, 2); 5322 md_number_to_chars (ptr + 2, (valueT) offset, 2); 5323} 5324 5325void 5326md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, 5327 fragS *frag, symbolS *to_symbol) 5328{ 5329 valueT offset; 5330 5331 if (!HAVE_LONG_BRANCH (current_architecture)) 5332 { 5333 if (flag_keep_pcrel) 5334 as_fatal (_("Tried to convert PC relative branch to absolute jump")); 5335 offset = to_addr - S_GET_VALUE (to_symbol); 5336 md_number_to_chars (ptr, (valueT) 0x4EF9, 2); 5337 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5338 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, 5339 0, NO_RELOC); 5340 } 5341 else 5342 { 5343 offset = to_addr - (from_addr + 2); 5344 md_number_to_chars (ptr, (valueT) 0x60ff, 2); 5345 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5346 } 5347} 5348 5349#endif 5350 5351/* Different values of OK tell what it's OK to return. Things that 5352 aren't OK are an error (what a shock, no?) 5353 5354 0: Everything is OK 5355 10: Absolute 1:8 only 5356 20: Absolute 0:7 only 5357 30: absolute 0:15 only 5358 40: Absolute 0:31 only 5359 50: absolute 0:127 only 5360 55: absolute -64:63 only 5361 60: absolute -128:127 only 5362 65: absolute 0:511 only 5363 70: absolute 0:4095 only 5364 80: absolute -1, 1:7 only 5365 90: No bignums. */ 5366 5367static int 5368get_num (struct m68k_exp *exp, int ok) 5369{ 5370 if (exp->exp.X_op == O_absent) 5371 { 5372 /* Do the same thing the VAX asm does. */ 5373 op (exp) = O_constant; 5374 adds (exp) = 0; 5375 subs (exp) = 0; 5376 offs (exp) = 0; 5377 if (ok == 10) 5378 { 5379 as_warn (_("expression out of range: defaulting to 1")); 5380 offs (exp) = 1; 5381 } 5382 } 5383 else if (exp->exp.X_op == O_constant) 5384 { 5385 switch (ok) 5386 { 5387 case 10: 5388 if ((valueT) TRUNC (offs (exp)) - 1 > 7) 5389 { 5390 as_warn (_("expression out of range: defaulting to 1")); 5391 offs (exp) = 1; 5392 } 5393 break; 5394 case 20: 5395 if ((valueT) TRUNC (offs (exp)) > 7) 5396 goto outrange; 5397 break; 5398 case 30: 5399 if ((valueT) TRUNC (offs (exp)) > 15) 5400 goto outrange; 5401 break; 5402 case 40: 5403 if ((valueT) TRUNC (offs (exp)) > 32) 5404 goto outrange; 5405 break; 5406 case 50: 5407 if ((valueT) TRUNC (offs (exp)) > 127) 5408 goto outrange; 5409 break; 5410 case 55: 5411 if ((valueT) SEXT (offs (exp)) + 64 > 127) 5412 goto outrange; 5413 break; 5414 case 60: 5415 if ((valueT) SEXT (offs (exp)) + 128 > 255) 5416 goto outrange; 5417 break; 5418 case 65: 5419 if ((valueT) TRUNC (offs (exp)) > 511) 5420 goto outrange; 5421 break; 5422 case 70: 5423 if ((valueT) TRUNC (offs (exp)) > 4095) 5424 { 5425 outrange: 5426 as_warn (_("expression out of range: defaulting to 0")); 5427 offs (exp) = 0; 5428 } 5429 break; 5430 case 80: 5431 if ((valueT) TRUNC (offs (exp)) != 0xffffffff 5432 && (valueT) TRUNC (offs (exp)) - 1 > 6) 5433 { 5434 as_warn (_("expression out of range: defaulting to 1")); 5435 offs (exp) = 1; 5436 } 5437 break; 5438 default: 5439 break; 5440 } 5441 } 5442 else if (exp->exp.X_op == O_big) 5443 { 5444 if (offs (exp) <= 0 /* flonum. */ 5445 && (ok == 90 /* no bignums */ 5446 || (ok > 10 /* Small-int ranges including 0 ok. */ 5447 /* If we have a flonum zero, a zero integer should 5448 do as well (e.g., in moveq). */ 5449 && generic_floating_point_number.exponent == 0 5450 && generic_floating_point_number.low[0] == 0))) 5451 { 5452 /* HACK! Turn it into a long. */ 5453 LITTLENUM_TYPE words[6]; 5454 5455 gen_to_words (words, 2, 8L); /* These numbers are magic! */ 5456 op (exp) = O_constant; 5457 adds (exp) = 0; 5458 subs (exp) = 0; 5459 offs (exp) = words[1] | (words[0] << 16); 5460 } 5461 else if (ok != 0) 5462 { 5463 op (exp) = O_constant; 5464 adds (exp) = 0; 5465 subs (exp) = 0; 5466 offs (exp) = (ok == 10) ? 1 : 0; 5467 as_warn (_("Can't deal with expression; defaulting to %ld"), 5468 (long) offs (exp)); 5469 } 5470 } 5471 else 5472 { 5473 if (ok >= 10 && ok <= 80) 5474 { 5475 op (exp) = O_constant; 5476 adds (exp) = 0; 5477 subs (exp) = 0; 5478 offs (exp) = (ok == 10) ? 1 : 0; 5479 as_warn (_("Can't deal with expression; defaulting to %ld"), 5480 (long) offs (exp)); 5481 } 5482 } 5483 5484 if (exp->size != SIZE_UNSPEC) 5485 { 5486 switch (exp->size) 5487 { 5488 case SIZE_UNSPEC: 5489 case SIZE_LONG: 5490 break; 5491 case SIZE_BYTE: 5492 if (!isbyte (offs (exp))) 5493 as_warn (_("expression doesn't fit in BYTE")); 5494 break; 5495 case SIZE_WORD: 5496 if (!isword (offs (exp))) 5497 as_warn (_("expression doesn't fit in WORD")); 5498 break; 5499 } 5500 } 5501 5502 return offs (exp); 5503} 5504 5505/* These are the back-ends for the various machine dependent pseudo-ops. */ 5506 5507static void 5508s_data1 (int ignore ATTRIBUTE_UNUSED) 5509{ 5510 subseg_set (data_section, 1); 5511 demand_empty_rest_of_line (); 5512} 5513 5514static void 5515s_data2 (int ignore ATTRIBUTE_UNUSED) 5516{ 5517 subseg_set (data_section, 2); 5518 demand_empty_rest_of_line (); 5519} 5520 5521static void 5522s_bss (int ignore ATTRIBUTE_UNUSED) 5523{ 5524 /* We don't support putting frags in the BSS segment, we fake it 5525 by marking in_bss, then looking at s_skip for clues. */ 5526 5527 subseg_set (bss_section, 0); 5528 demand_empty_rest_of_line (); 5529} 5530 5531static void 5532s_even (int ignore ATTRIBUTE_UNUSED) 5533{ 5534 int temp; 5535 long temp_fill; 5536 5537 temp = 1; /* JF should be 2? */ 5538 temp_fill = get_absolute_expression (); 5539 if (!need_pass_2) /* Never make frag if expect extra pass. */ 5540 frag_align (temp, (int) temp_fill, 0); 5541 demand_empty_rest_of_line (); 5542 record_alignment (now_seg, temp); 5543} 5544 5545static void 5546s_proc (int ignore ATTRIBUTE_UNUSED) 5547{ 5548 demand_empty_rest_of_line (); 5549} 5550 5551/* Pseudo-ops handled for MRI compatibility. */ 5552 5553/* This function returns non-zero if the argument is a conditional 5554 pseudo-op. This is called when checking whether a pending 5555 alignment is needed. */ 5556 5557int 5558m68k_conditional_pseudoop (const pseudo_typeS *pop) 5559{ 5560 return (pop->poc_handler == s_mri_if 5561 || pop->poc_handler == s_mri_else); 5562} 5563 5564/* Handle an MRI style chip specification. */ 5565 5566static void 5567mri_chip (void) 5568{ 5569 char *s; 5570 char c; 5571 int i; 5572 5573 s = input_line_pointer; 5574 /* We can't use get_symbol_name since the processor names are not proper 5575 symbols. */ 5576 while (is_part_of_name (c = *input_line_pointer++)) 5577 ; 5578 *--input_line_pointer = 0; 5579 for (i = 0; m68k_cpus[i].name; i++) 5580 if (strcasecmp (s, m68k_cpus[i].name) == 0) 5581 break; 5582 if (!m68k_cpus[i].name) 5583 { 5584 as_bad (_("%s: unrecognized processor name"), s); 5585 *input_line_pointer = c; 5586 ignore_rest_of_line (); 5587 return; 5588 } 5589 *input_line_pointer = c; 5590 5591 if (*input_line_pointer == '/') 5592 current_architecture = 0; 5593 else 5594 current_architecture &= m68881 | m68851; 5595 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); 5596 control_regs = m68k_cpus[i].control_regs; 5597 5598 while (*input_line_pointer == '/') 5599 { 5600 ++input_line_pointer; 5601 s = input_line_pointer; 5602 /* We can't use get_symbol_name since the processor names are not 5603 proper symbols. */ 5604 while (is_part_of_name (c = *input_line_pointer++)) 5605 ; 5606 *--input_line_pointer = 0; 5607 if (strcmp (s, "68881") == 0) 5608 current_architecture |= m68881; 5609 else if (strcmp (s, "68851") == 0) 5610 current_architecture |= m68851; 5611 *input_line_pointer = c; 5612 } 5613} 5614 5615/* The MRI CHIP pseudo-op. */ 5616 5617static void 5618s_chip (int ignore ATTRIBUTE_UNUSED) 5619{ 5620 char *stop = NULL; 5621 char stopc; 5622 5623 if (flag_mri) 5624 stop = mri_comment_field (&stopc); 5625 mri_chip (); 5626 if (flag_mri) 5627 mri_comment_end (stop, stopc); 5628 demand_empty_rest_of_line (); 5629} 5630 5631/* The MRI FOPT pseudo-op. */ 5632 5633static void 5634s_fopt (int ignore ATTRIBUTE_UNUSED) 5635{ 5636 SKIP_WHITESPACE (); 5637 5638 if (strncasecmp (input_line_pointer, "ID=", 3) == 0) 5639 { 5640 int temp; 5641 5642 input_line_pointer += 3; 5643 temp = get_absolute_expression (); 5644 if (temp < 0 || temp > 7) 5645 as_bad (_("bad coprocessor id")); 5646 else 5647 m68k_float_copnum = COP0 + temp; 5648 } 5649 else 5650 { 5651 as_bad (_("unrecognized fopt option")); 5652 ignore_rest_of_line (); 5653 return; 5654 } 5655 5656 demand_empty_rest_of_line (); 5657} 5658 5659/* The structure used to handle the MRI OPT pseudo-op. */ 5660 5661struct opt_action 5662{ 5663 /* The name of the option. */ 5664 const char *name; 5665 5666 /* If this is not NULL, just call this function. The first argument 5667 is the ARG field of this structure, the second argument is 5668 whether the option was negated. */ 5669 void (*pfn) (int arg, int on); 5670 5671 /* If this is not NULL, and the PFN field is NULL, set the variable 5672 this points to. Set it to the ARG field if the option was not 5673 negated, and the NOTARG field otherwise. */ 5674 int *pvar; 5675 5676 /* The value to pass to PFN or to assign to *PVAR. */ 5677 int arg; 5678 5679 /* The value to assign to *PVAR if the option is negated. If PFN is 5680 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then 5681 the option may not be negated. */ 5682 int notarg; 5683}; 5684 5685/* The table used to handle the MRI OPT pseudo-op. */ 5686 5687static void skip_to_comma (int, int); 5688static void opt_nest (int, int); 5689static void opt_chip (int, int); 5690static void opt_list (int, int); 5691static void opt_list_symbols (int, int); 5692 5693static const struct opt_action opt_table[] = 5694{ 5695 { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, 5696 5697 /* We do relaxing, so there is little use for these options. */ 5698 { "b", 0, 0, 0, 0 }, 5699 { "brs", 0, 0, 0, 0 }, 5700 { "brb", 0, 0, 0, 0 }, 5701 { "brl", 0, 0, 0, 0 }, 5702 { "brw", 0, 0, 0, 0 }, 5703 5704 { "c", 0, 0, 0, 0 }, 5705 { "cex", 0, 0, 0, 0 }, 5706 { "case", 0, &symbols_case_sensitive, 1, 0 }, 5707 { "cl", 0, 0, 0, 0 }, 5708 { "cre", 0, 0, 0, 0 }, 5709 { "d", 0, &flag_keep_locals, 1, 0 }, 5710 { "e", 0, 0, 0, 0 }, 5711 { "f", 0, &flag_short_refs, 1, 0 }, 5712 { "frs", 0, &flag_short_refs, 1, 0 }, 5713 { "frl", 0, &flag_short_refs, 0, 1 }, 5714 { "g", 0, 0, 0, 0 }, 5715 { "i", 0, 0, 0, 0 }, 5716 { "m", 0, 0, 0, 0 }, 5717 { "mex", 0, 0, 0, 0 }, 5718 { "mc", 0, 0, 0, 0 }, 5719 { "md", 0, 0, 0, 0 }, 5720 { "nest", opt_nest, 0, 0, 0 }, 5721 { "next", skip_to_comma, 0, 0, 0 }, 5722 { "o", 0, 0, 0, 0 }, 5723 { "old", 0, 0, 0, 0 }, 5724 { "op", skip_to_comma, 0, 0, 0 }, 5725 { "pco", 0, 0, 0, 0 }, 5726 { "p", opt_chip, 0, 0, 0 }, 5727 { "pcr", 0, 0, 0, 0 }, 5728 { "pcs", 0, 0, 0, 0 }, 5729 { "r", 0, 0, 0, 0 }, 5730 { "quick", 0, &m68k_quick, 1, 0 }, 5731 { "rel32", 0, &m68k_rel32, 1, 0 }, 5732 { "s", opt_list, 0, 0, 0 }, 5733 { "t", opt_list_symbols, 0, 0, 0 }, 5734 { "w", 0, &flag_no_warnings, 0, 1 }, 5735 { "x", 0, 0, 0, 0 } 5736}; 5737 5738#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) 5739 5740/* The MRI OPT pseudo-op. */ 5741 5742static void 5743s_opt (int ignore ATTRIBUTE_UNUSED) 5744{ 5745 do 5746 { 5747 int t; 5748 char *s; 5749 char c; 5750 int i; 5751 const struct opt_action *o; 5752 5753 SKIP_WHITESPACE (); 5754 5755 t = 1; 5756 if (*input_line_pointer == '-') 5757 { 5758 ++input_line_pointer; 5759 t = 0; 5760 } 5761 else if (strncasecmp (input_line_pointer, "NO", 2) == 0) 5762 { 5763 input_line_pointer += 2; 5764 t = 0; 5765 } 5766 5767 c = get_symbol_name (&s); 5768 5769 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) 5770 { 5771 if (strcasecmp (s, o->name) == 0) 5772 { 5773 if (o->pfn) 5774 { 5775 /* Restore input_line_pointer now in case the option 5776 takes arguments. */ 5777 (void) restore_line_pointer (c); 5778 (*o->pfn) (o->arg, t); 5779 } 5780 else if (o->pvar != NULL) 5781 { 5782 if (! t && o->arg == o->notarg) 5783 as_bad (_("option `%s' may not be negated"), s); 5784 restore_line_pointer (c); 5785 *o->pvar = t ? o->arg : o->notarg; 5786 } 5787 else 5788 *input_line_pointer = c; 5789 break; 5790 } 5791 } 5792 if (i >= OPTCOUNT) 5793 { 5794 as_bad (_("option `%s' not recognized"), s); 5795 restore_line_pointer (c); 5796 } 5797 } 5798 while (*input_line_pointer++ == ','); 5799 5800 /* Move back to terminating character. */ 5801 --input_line_pointer; 5802 demand_empty_rest_of_line (); 5803} 5804 5805/* Skip ahead to a comma. This is used for OPT options which we do 5806 not support and which take arguments. */ 5807 5808static void 5809skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5810{ 5811 while (*input_line_pointer != ',' 5812 && ! is_end_of_line[(unsigned char) *input_line_pointer]) 5813 ++input_line_pointer; 5814} 5815 5816/* Handle the OPT NEST=depth option. */ 5817 5818static void 5819opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5820{ 5821 if (*input_line_pointer != '=') 5822 { 5823 as_bad (_("bad format of OPT NEST=depth")); 5824 return; 5825 } 5826 5827 ++input_line_pointer; 5828 max_macro_nest = get_absolute_expression (); 5829} 5830 5831/* Handle the OPT P=chip option. */ 5832 5833static void 5834opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5835{ 5836 if (*input_line_pointer != '=') 5837 { 5838 /* This is just OPT P, which we do not support. */ 5839 return; 5840 } 5841 5842 ++input_line_pointer; 5843 mri_chip (); 5844} 5845 5846/* Handle the OPT S option. */ 5847 5848static void 5849opt_list (int arg ATTRIBUTE_UNUSED, int on) 5850{ 5851 listing_list (on); 5852} 5853 5854/* Handle the OPT T option. */ 5855 5856static void 5857opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) 5858{ 5859 if (on) 5860 listing |= LISTING_SYMBOLS; 5861 else 5862 listing &= ~LISTING_SYMBOLS; 5863} 5864 5865/* Handle the MRI REG pseudo-op. */ 5866 5867static void 5868s_reg (int ignore ATTRIBUTE_UNUSED) 5869{ 5870 char *s; 5871 int c; 5872 struct m68k_op rop; 5873 int mask; 5874 char *stop = NULL; 5875 char stopc; 5876 5877 if (line_label == NULL) 5878 { 5879 as_bad (_("missing label")); 5880 ignore_rest_of_line (); 5881 return; 5882 } 5883 5884 if (flag_mri) 5885 stop = mri_comment_field (&stopc); 5886 5887 SKIP_WHITESPACE (); 5888 5889 s = input_line_pointer; 5890 while (ISALNUM (*input_line_pointer) 5891#ifdef REGISTER_PREFIX 5892 || *input_line_pointer == REGISTER_PREFIX 5893#endif 5894 || *input_line_pointer == '/' 5895 || *input_line_pointer == '-') 5896 ++input_line_pointer; 5897 c = *input_line_pointer; 5898 *input_line_pointer = '\0'; 5899 5900 if (m68k_ip_op (s, &rop) != 0) 5901 { 5902 if (rop.error == NULL) 5903 as_bad (_("bad register list")); 5904 else 5905 as_bad (_("bad register list: %s"), rop.error); 5906 *input_line_pointer = c; 5907 ignore_rest_of_line (); 5908 return; 5909 } 5910 5911 *input_line_pointer = c; 5912 5913 if (rop.mode == REGLST) 5914 mask = rop.mask; 5915 else if (rop.mode == DREG) 5916 mask = 1 << (rop.reg - DATA0); 5917 else if (rop.mode == AREG) 5918 mask = 1 << (rop.reg - ADDR0 + 8); 5919 else if (rop.mode == FPREG) 5920 mask = 1 << (rop.reg - FP0 + 16); 5921 else if (rop.mode == CONTROL 5922 && rop.reg == FPI) 5923 mask = 1 << 24; 5924 else if (rop.mode == CONTROL 5925 && rop.reg == FPS) 5926 mask = 1 << 25; 5927 else if (rop.mode == CONTROL 5928 && rop.reg == FPC) 5929 mask = 1 << 26; 5930 else 5931 { 5932 as_bad (_("bad register list")); 5933 ignore_rest_of_line (); 5934 return; 5935 } 5936 5937 S_SET_SEGMENT (line_label, reg_section); 5938 S_SET_VALUE (line_label, ~mask); 5939 symbol_set_frag (line_label, &zero_address_frag); 5940 5941 if (flag_mri) 5942 mri_comment_end (stop, stopc); 5943 5944 demand_empty_rest_of_line (); 5945} 5946 5947/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ 5948 5949struct save_opts 5950{ 5951 struct save_opts *next; 5952 int abspcadd; 5953 int symbols_case_sensitive; 5954 int keep_locals; 5955 int short_refs; 5956 int architecture; 5957 const enum m68k_register *control_regs; 5958 int quick; 5959 int rel32; 5960 int listing; 5961 int no_warnings; 5962 /* FIXME: We don't save OPT S. */ 5963}; 5964 5965/* This variable holds the stack of saved options. */ 5966 5967static struct save_opts *save_stack; 5968 5969/* The MRI SAVE pseudo-op. */ 5970 5971static void 5972s_save (int ignore ATTRIBUTE_UNUSED) 5973{ 5974 struct save_opts *s; 5975 5976 s = XNEW (struct save_opts); 5977 s->abspcadd = m68k_abspcadd; 5978 s->symbols_case_sensitive = symbols_case_sensitive; 5979 s->keep_locals = flag_keep_locals; 5980 s->short_refs = flag_short_refs; 5981 s->architecture = current_architecture; 5982 s->control_regs = control_regs; 5983 s->quick = m68k_quick; 5984 s->rel32 = m68k_rel32; 5985 s->listing = listing; 5986 s->no_warnings = flag_no_warnings; 5987 5988 s->next = save_stack; 5989 save_stack = s; 5990 5991 demand_empty_rest_of_line (); 5992} 5993 5994/* The MRI RESTORE pseudo-op. */ 5995 5996static void 5997s_restore (int ignore ATTRIBUTE_UNUSED) 5998{ 5999 struct save_opts *s; 6000 6001 if (save_stack == NULL) 6002 { 6003 as_bad (_("restore without save")); 6004 ignore_rest_of_line (); 6005 return; 6006 } 6007 6008 s = save_stack; 6009 save_stack = s->next; 6010 6011 m68k_abspcadd = s->abspcadd; 6012 symbols_case_sensitive = s->symbols_case_sensitive; 6013 flag_keep_locals = s->keep_locals; 6014 flag_short_refs = s->short_refs; 6015 current_architecture = s->architecture; 6016 control_regs = s->control_regs; 6017 m68k_quick = s->quick; 6018 m68k_rel32 = s->rel32; 6019 listing = s->listing; 6020 flag_no_warnings = s->no_warnings; 6021 6022 free (s); 6023 6024 demand_empty_rest_of_line (); 6025} 6026 6027/* Types of MRI structured control directives. */ 6028 6029enum mri_control_type 6030{ 6031 mri_for, 6032 mri_if, 6033 mri_repeat, 6034 mri_while 6035}; 6036 6037/* This structure is used to stack the MRI structured control 6038 directives. */ 6039 6040struct mri_control_info 6041{ 6042 /* The directive within which this one is enclosed. */ 6043 struct mri_control_info *outer; 6044 6045 /* The type of directive. */ 6046 enum mri_control_type type; 6047 6048 /* Whether an ELSE has been in an IF. */ 6049 int else_seen; 6050 6051 /* The add or sub statement at the end of a FOR. */ 6052 char *incr; 6053 6054 /* The label of the top of a FOR or REPEAT loop. */ 6055 char *top; 6056 6057 /* The label to jump to for the next iteration, or the else 6058 expression of a conditional. */ 6059 char *next; 6060 6061 /* The label to jump to to break out of the loop, or the label past 6062 the end of a conditional. */ 6063 char *bottom; 6064}; 6065 6066/* The stack of MRI structured control directives. */ 6067 6068static struct mri_control_info *mri_control_stack; 6069 6070/* The current MRI structured control directive index number, used to 6071 generate label names. */ 6072 6073static int mri_control_index; 6074 6075/* Assemble an instruction for an MRI structured control directive. */ 6076 6077static void 6078mri_assemble (char *str) 6079{ 6080 char *s; 6081 6082 /* md_assemble expects the opcode to be in lower case. */ 6083 for (s = str; *s != ' ' && *s != '\0'; s++) 6084 *s = TOLOWER (*s); 6085 6086 md_assemble (str); 6087} 6088 6089/* Generate a new MRI label structured control directive label name. */ 6090 6091static char * 6092mri_control_label (void) 6093{ 6094 char *n; 6095 6096 n = XNEWVEC (char, 20); 6097 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); 6098 ++mri_control_index; 6099 return n; 6100} 6101 6102/* Create a new MRI structured control directive. */ 6103 6104static struct mri_control_info * 6105push_mri_control (enum mri_control_type type) 6106{ 6107 struct mri_control_info *n; 6108 6109 n = XNEW (struct mri_control_info); 6110 6111 n->type = type; 6112 n->else_seen = 0; 6113 if (type == mri_if || type == mri_while) 6114 n->top = NULL; 6115 else 6116 n->top = mri_control_label (); 6117 n->next = mri_control_label (); 6118 n->bottom = mri_control_label (); 6119 6120 n->outer = mri_control_stack; 6121 mri_control_stack = n; 6122 6123 return n; 6124} 6125 6126/* Pop off the stack of MRI structured control directives. */ 6127 6128static void 6129pop_mri_control (void) 6130{ 6131 struct mri_control_info *n; 6132 6133 n = mri_control_stack; 6134 mri_control_stack = n->outer; 6135 free (n->top); 6136 free (n->next); 6137 free (n->bottom); 6138 free (n); 6139} 6140 6141/* Recognize a condition code in an MRI structured control expression. */ 6142 6143static int 6144parse_mri_condition (int *pcc) 6145{ 6146 char c1, c2; 6147 6148 know (*input_line_pointer == '<'); 6149 6150 ++input_line_pointer; 6151 c1 = *input_line_pointer++; 6152 c2 = *input_line_pointer++; 6153 6154 if (*input_line_pointer != '>') 6155 { 6156 as_bad (_("syntax error in structured control directive")); 6157 return 0; 6158 } 6159 6160 ++input_line_pointer; 6161 SKIP_WHITESPACE (); 6162 6163 c1 = TOLOWER (c1); 6164 c2 = TOLOWER (c2); 6165 6166 *pcc = (c1 << 8) | c2; 6167 6168 return 1; 6169} 6170 6171/* Parse a single operand in an MRI structured control expression. */ 6172 6173static int 6174parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, 6175 char **rightstart, char **rightstop) 6176{ 6177 char *s; 6178 6179 SKIP_WHITESPACE (); 6180 6181 *pcc = -1; 6182 *leftstart = NULL; 6183 *leftstop = NULL; 6184 *rightstart = NULL; 6185 *rightstop = NULL; 6186 6187 if (*input_line_pointer == '<') 6188 { 6189 /* It's just a condition code. */ 6190 return parse_mri_condition (pcc); 6191 } 6192 6193 /* Look ahead for the condition code. */ 6194 for (s = input_line_pointer; *s != '\0'; ++s) 6195 { 6196 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') 6197 break; 6198 } 6199 if (*s == '\0') 6200 { 6201 as_bad (_("missing condition code in structured control directive")); 6202 return 0; 6203 } 6204 6205 *leftstart = input_line_pointer; 6206 *leftstop = s; 6207 if (*leftstop > *leftstart 6208 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) 6209 --*leftstop; 6210 6211 input_line_pointer = s; 6212 if (! parse_mri_condition (pcc)) 6213 return 0; 6214 6215 /* Look ahead for AND or OR or end of line. */ 6216 for (s = input_line_pointer; *s != '\0'; ++s) 6217 { 6218 /* We must make sure we don't misinterpret AND/OR at the end of labels! 6219 if d0 <eq> #FOOAND and d1 <ne> #BAROR then 6220 ^^^ ^^ */ 6221 if ((s == input_line_pointer 6222 || *(s-1) == ' ' 6223 || *(s-1) == '\t') 6224 && ((strncasecmp (s, "AND", 3) == 0 6225 && (s[3] == '.' || ! is_part_of_name (s[3]))) 6226 || (strncasecmp (s, "OR", 2) == 0 6227 && (s[2] == '.' || ! is_part_of_name (s[2]))))) 6228 break; 6229 } 6230 6231 *rightstart = input_line_pointer; 6232 *rightstop = s; 6233 if (*rightstop > *rightstart 6234 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) 6235 --*rightstop; 6236 6237 input_line_pointer = s; 6238 6239 return 1; 6240} 6241 6242#define MCC(b1, b2) (((b1) << 8) | (b2)) 6243 6244/* Swap the sense of a condition. This changes the condition so that 6245 it generates the same result when the operands are swapped. */ 6246 6247static int 6248swap_mri_condition (int cc) 6249{ 6250 switch (cc) 6251 { 6252 case MCC ('h', 'i'): return MCC ('c', 's'); 6253 case MCC ('l', 's'): return MCC ('c', 'c'); 6254 /* <HS> is an alias for <CC>. */ 6255 case MCC ('h', 's'): 6256 case MCC ('c', 'c'): return MCC ('l', 's'); 6257 /* <LO> is an alias for <CS>. */ 6258 case MCC ('l', 'o'): 6259 case MCC ('c', 's'): return MCC ('h', 'i'); 6260 case MCC ('p', 'l'): return MCC ('m', 'i'); 6261 case MCC ('m', 'i'): return MCC ('p', 'l'); 6262 case MCC ('g', 'e'): return MCC ('l', 'e'); 6263 case MCC ('l', 't'): return MCC ('g', 't'); 6264 case MCC ('g', 't'): return MCC ('l', 't'); 6265 case MCC ('l', 'e'): return MCC ('g', 'e'); 6266 /* Issue a warning for conditions we can not swap. */ 6267 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ 6268 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ 6269 case MCC ('v', 'c'): 6270 case MCC ('v', 's'): 6271 default : 6272 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), 6273 (char) (cc >> 8), (char) (cc)); 6274 break; 6275 } 6276 return cc; 6277} 6278 6279/* Reverse the sense of a condition. */ 6280 6281static int 6282reverse_mri_condition (int cc) 6283{ 6284 switch (cc) 6285 { 6286 case MCC ('h', 'i'): return MCC ('l', 's'); 6287 case MCC ('l', 's'): return MCC ('h', 'i'); 6288 /* <HS> is an alias for <CC> */ 6289 case MCC ('h', 's'): return MCC ('l', 'o'); 6290 case MCC ('c', 'c'): return MCC ('c', 's'); 6291 /* <LO> is an alias for <CS> */ 6292 case MCC ('l', 'o'): return MCC ('h', 's'); 6293 case MCC ('c', 's'): return MCC ('c', 'c'); 6294 case MCC ('n', 'e'): return MCC ('e', 'q'); 6295 case MCC ('e', 'q'): return MCC ('n', 'e'); 6296 case MCC ('v', 'c'): return MCC ('v', 's'); 6297 case MCC ('v', 's'): return MCC ('v', 'c'); 6298 case MCC ('p', 'l'): return MCC ('m', 'i'); 6299 case MCC ('m', 'i'): return MCC ('p', 'l'); 6300 case MCC ('g', 'e'): return MCC ('l', 't'); 6301 case MCC ('l', 't'): return MCC ('g', 'e'); 6302 case MCC ('g', 't'): return MCC ('l', 'e'); 6303 case MCC ('l', 'e'): return MCC ('g', 't'); 6304 } 6305 return cc; 6306} 6307 6308/* Build an MRI structured control expression. This generates test 6309 and branch instructions. It goes to TRUELAB if the condition is 6310 true, and to FALSELAB if the condition is false. Exactly one of 6311 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL 6312 is the size qualifier for the expression. EXTENT is the size to 6313 use for the branch. */ 6314 6315static void 6316build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, 6317 char *rightstart, char *rightstop, 6318 const char *truelab, const char *falselab, 6319 int extent) 6320{ 6321 char *buf; 6322 char *s; 6323 6324 if (leftstart != NULL) 6325 { 6326 struct m68k_op leftop, rightop; 6327 char c; 6328 6329 /* Swap the compare operands, if necessary, to produce a legal 6330 m68k compare instruction. Comparing a register operand with 6331 a non-register operand requires the register to be on the 6332 right (cmp, cmpa). Comparing an immediate value with 6333 anything requires the immediate value to be on the left 6334 (cmpi). */ 6335 6336 c = *leftstop; 6337 *leftstop = '\0'; 6338 (void) m68k_ip_op (leftstart, &leftop); 6339 *leftstop = c; 6340 6341 c = *rightstop; 6342 *rightstop = '\0'; 6343 (void) m68k_ip_op (rightstart, &rightop); 6344 *rightstop = c; 6345 6346 if (rightop.mode == IMMED 6347 || ((leftop.mode == DREG || leftop.mode == AREG) 6348 && (rightop.mode != DREG && rightop.mode != AREG))) 6349 { 6350 char *temp; 6351 6352 /* Correct conditional handling: 6353 if #1 <lt> d0 then ;means if (1 < d0) 6354 ... 6355 endi 6356 6357 should assemble to: 6358 6359 cmp #1,d0 if we do *not* swap the operands 6360 bgt true we need the swapped condition! 6361 ble false 6362 true: 6363 ... 6364 false: 6365 */ 6366 temp = leftstart; 6367 leftstart = rightstart; 6368 rightstart = temp; 6369 temp = leftstop; 6370 leftstop = rightstop; 6371 rightstop = temp; 6372 } 6373 else 6374 { 6375 cc = swap_mri_condition (cc); 6376 } 6377 } 6378 6379 if (truelab == NULL) 6380 { 6381 cc = reverse_mri_condition (cc); 6382 truelab = falselab; 6383 } 6384 6385 if (leftstart != NULL) 6386 { 6387 buf = XNEWVEC (char, (20 6388 + (leftstop - leftstart) 6389 + (rightstop - rightstart))); 6390 s = buf; 6391 *s++ = 'c'; 6392 *s++ = 'm'; 6393 *s++ = 'p'; 6394 if (qual != '\0') 6395 *s++ = TOLOWER (qual); 6396 *s++ = ' '; 6397 memcpy (s, leftstart, leftstop - leftstart); 6398 s += leftstop - leftstart; 6399 *s++ = ','; 6400 memcpy (s, rightstart, rightstop - rightstart); 6401 s += rightstop - rightstart; 6402 *s = '\0'; 6403 mri_assemble (buf); 6404 free (buf); 6405 } 6406 6407 buf = XNEWVEC (char, 20 + strlen (truelab)); 6408 s = buf; 6409 *s++ = 'b'; 6410 *s++ = cc >> 8; 6411 *s++ = cc & 0xff; 6412 if (extent != '\0') 6413 *s++ = TOLOWER (extent); 6414 *s++ = ' '; 6415 strcpy (s, truelab); 6416 mri_assemble (buf); 6417 free (buf); 6418} 6419 6420/* Parse an MRI structured control expression. This generates test 6421 and branch instructions. STOP is where the expression ends. It 6422 goes to TRUELAB if the condition is true, and to FALSELAB if the 6423 condition is false. Exactly one of TRUELAB and FALSELAB will be 6424 NULL, meaning to fall through. QUAL is the size qualifier for the 6425 expression. EXTENT is the size to use for the branch. */ 6426 6427static void 6428parse_mri_control_expression (char *stop, int qual, const char *truelab, 6429 const char *falselab, int extent) 6430{ 6431 int c; 6432 int cc; 6433 char *leftstart; 6434 char *leftstop; 6435 char *rightstart; 6436 char *rightstop; 6437 6438 c = *stop; 6439 *stop = '\0'; 6440 6441 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6442 &rightstart, &rightstop)) 6443 { 6444 *stop = c; 6445 return; 6446 } 6447 6448 if (strncasecmp (input_line_pointer, "AND", 3) == 0) 6449 { 6450 const char *flab; 6451 6452 if (falselab != NULL) 6453 flab = falselab; 6454 else 6455 flab = mri_control_label (); 6456 6457 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6458 rightstop, (const char *) NULL, flab, extent); 6459 6460 input_line_pointer += 3; 6461 if (*input_line_pointer != '.' 6462 || input_line_pointer[1] == '\0') 6463 qual = '\0'; 6464 else 6465 { 6466 qual = input_line_pointer[1]; 6467 input_line_pointer += 2; 6468 } 6469 6470 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6471 &rightstart, &rightstop)) 6472 { 6473 *stop = c; 6474 return; 6475 } 6476 6477 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6478 rightstop, truelab, falselab, extent); 6479 6480 if (falselab == NULL) 6481 colon (flab); 6482 } 6483 else if (strncasecmp (input_line_pointer, "OR", 2) == 0) 6484 { 6485 const char *tlab; 6486 6487 if (truelab != NULL) 6488 tlab = truelab; 6489 else 6490 tlab = mri_control_label (); 6491 6492 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6493 rightstop, tlab, (const char *) NULL, extent); 6494 6495 input_line_pointer += 2; 6496 if (*input_line_pointer != '.' 6497 || input_line_pointer[1] == '\0') 6498 qual = '\0'; 6499 else 6500 { 6501 qual = input_line_pointer[1]; 6502 input_line_pointer += 2; 6503 } 6504 6505 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6506 &rightstart, &rightstop)) 6507 { 6508 *stop = c; 6509 return; 6510 } 6511 6512 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6513 rightstop, truelab, falselab, extent); 6514 6515 if (truelab == NULL) 6516 colon (tlab); 6517 } 6518 else 6519 { 6520 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6521 rightstop, truelab, falselab, extent); 6522 } 6523 6524 *stop = c; 6525 if (input_line_pointer != stop) 6526 as_bad (_("syntax error in structured control directive")); 6527} 6528 6529/* Handle the MRI IF pseudo-op. This may be a structured control 6530 directive, or it may be a regular assembler conditional, depending 6531 on its operands. */ 6532 6533static void 6534s_mri_if (int qual) 6535{ 6536 char *s; 6537 int c; 6538 struct mri_control_info *n; 6539 6540 /* A structured control directive must end with THEN with an 6541 optional qualifier. */ 6542 s = input_line_pointer; 6543 /* We only accept '*' as introduction of comments if preceded by white space 6544 or at first column of a line (I think this can't actually happen here?) 6545 This is important when assembling: 6546 if d0 <ne> 12(a0,d0*2) then 6547 if d0 <ne> #CONST*20 then. */ 6548 while (! (is_end_of_line[(unsigned char) *s] 6549 || (flag_mri 6550 && *s == '*' 6551 && (s == input_line_pointer 6552 || *(s-1) == ' ' 6553 || *(s-1) == '\t')))) 6554 ++s; 6555 --s; 6556 while (s > input_line_pointer && (*s == ' ' || *s == '\t')) 6557 --s; 6558 6559 if (s - input_line_pointer > 1 6560 && s[-1] == '.') 6561 s -= 2; 6562 6563 if (s - input_line_pointer < 3 6564 || strncasecmp (s - 3, "THEN", 4) != 0) 6565 { 6566 if (qual != '\0') 6567 { 6568 as_bad (_("missing then")); 6569 ignore_rest_of_line (); 6570 return; 6571 } 6572 6573 /* It's a conditional. */ 6574 s_if (O_ne); 6575 return; 6576 } 6577 6578 /* Since this might be a conditional if, this pseudo-op will be 6579 called even if we are supported to be ignoring input. Double 6580 check now. Clobber *input_line_pointer so that ignore_input 6581 thinks that this is not a special pseudo-op. */ 6582 c = *input_line_pointer; 6583 *input_line_pointer = 0; 6584 if (ignore_input ()) 6585 { 6586 *input_line_pointer = c; 6587 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6588 ++input_line_pointer; 6589 demand_empty_rest_of_line (); 6590 return; 6591 } 6592 *input_line_pointer = c; 6593 6594 n = push_mri_control (mri_if); 6595 6596 parse_mri_control_expression (s - 3, qual, (const char *) NULL, 6597 n->next, s[1] == '.' ? s[2] : '\0'); 6598 6599 if (s[1] == '.') 6600 input_line_pointer = s + 3; 6601 else 6602 input_line_pointer = s + 1; 6603 6604 if (flag_mri) 6605 { 6606 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6607 ++input_line_pointer; 6608 } 6609 6610 demand_empty_rest_of_line (); 6611} 6612 6613/* Handle the MRI else pseudo-op. If we are currently doing an MRI 6614 structured IF, associate the ELSE with the IF. Otherwise, assume 6615 it is a conditional else. */ 6616 6617static void 6618s_mri_else (int qual) 6619{ 6620 int c; 6621 char *buf; 6622 char q[2]; 6623 6624 if (qual == '\0' 6625 && (mri_control_stack == NULL 6626 || mri_control_stack->type != mri_if 6627 || mri_control_stack->else_seen)) 6628 { 6629 s_else (0); 6630 return; 6631 } 6632 6633 c = *input_line_pointer; 6634 *input_line_pointer = 0; 6635 if (ignore_input ()) 6636 { 6637 *input_line_pointer = c; 6638 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6639 ++input_line_pointer; 6640 demand_empty_rest_of_line (); 6641 return; 6642 } 6643 *input_line_pointer = c; 6644 6645 if (mri_control_stack == NULL 6646 || mri_control_stack->type != mri_if 6647 || mri_control_stack->else_seen) 6648 { 6649 as_bad (_("else without matching if")); 6650 ignore_rest_of_line (); 6651 return; 6652 } 6653 6654 mri_control_stack->else_seen = 1; 6655 6656 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom)); 6657 q[0] = TOLOWER (qual); 6658 q[1] = '\0'; 6659 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); 6660 mri_assemble (buf); 6661 free (buf); 6662 6663 colon (mri_control_stack->next); 6664 6665 if (flag_mri) 6666 { 6667 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6668 ++input_line_pointer; 6669 } 6670 6671 demand_empty_rest_of_line (); 6672} 6673 6674/* Handle the MRI ENDI pseudo-op. */ 6675 6676static void 6677s_mri_endi (int ignore ATTRIBUTE_UNUSED) 6678{ 6679 if (mri_control_stack == NULL 6680 || mri_control_stack->type != mri_if) 6681 { 6682 as_bad (_("endi without matching if")); 6683 ignore_rest_of_line (); 6684 return; 6685 } 6686 6687 /* ignore_input will not return true for ENDI, so we don't need to 6688 worry about checking it again here. */ 6689 6690 if (! mri_control_stack->else_seen) 6691 colon (mri_control_stack->next); 6692 colon (mri_control_stack->bottom); 6693 6694 pop_mri_control (); 6695 6696 if (flag_mri) 6697 { 6698 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6699 ++input_line_pointer; 6700 } 6701 6702 demand_empty_rest_of_line (); 6703} 6704 6705/* Handle the MRI BREAK pseudo-op. */ 6706 6707static void 6708s_mri_break (int extent) 6709{ 6710 struct mri_control_info *n; 6711 char *buf; 6712 char ex[2]; 6713 6714 n = mri_control_stack; 6715 while (n != NULL 6716 && n->type != mri_for 6717 && n->type != mri_repeat 6718 && n->type != mri_while) 6719 n = n->outer; 6720 if (n == NULL) 6721 { 6722 as_bad (_("break outside of structured loop")); 6723 ignore_rest_of_line (); 6724 return; 6725 } 6726 6727 buf = XNEWVEC (char, 20 + strlen (n->bottom)); 6728 ex[0] = TOLOWER (extent); 6729 ex[1] = '\0'; 6730 sprintf (buf, "bra%s %s", ex, n->bottom); 6731 mri_assemble (buf); 6732 free (buf); 6733 6734 if (flag_mri) 6735 { 6736 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6737 ++input_line_pointer; 6738 } 6739 6740 demand_empty_rest_of_line (); 6741} 6742 6743/* Handle the MRI NEXT pseudo-op. */ 6744 6745static void 6746s_mri_next (int extent) 6747{ 6748 struct mri_control_info *n; 6749 char *buf; 6750 char ex[2]; 6751 6752 n = mri_control_stack; 6753 while (n != NULL 6754 && n->type != mri_for 6755 && n->type != mri_repeat 6756 && n->type != mri_while) 6757 n = n->outer; 6758 if (n == NULL) 6759 { 6760 as_bad (_("next outside of structured loop")); 6761 ignore_rest_of_line (); 6762 return; 6763 } 6764 6765 buf = XNEWVEC (char, 20 + strlen (n->next)); 6766 ex[0] = TOLOWER (extent); 6767 ex[1] = '\0'; 6768 sprintf (buf, "bra%s %s", ex, n->next); 6769 mri_assemble (buf); 6770 free (buf); 6771 6772 if (flag_mri) 6773 { 6774 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6775 ++input_line_pointer; 6776 } 6777 6778 demand_empty_rest_of_line (); 6779} 6780 6781/* Handle the MRI FOR pseudo-op. */ 6782 6783static void 6784s_mri_for (int qual) 6785{ 6786 const char *varstart, *varstop; 6787 const char *initstart, *initstop; 6788 const char *endstart, *endstop; 6789 const char *bystart, *bystop; 6790 int up; 6791 int by; 6792 int extent; 6793 struct mri_control_info *n; 6794 char *buf; 6795 char *s; 6796 char ex[2]; 6797 6798 /* The syntax is 6799 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e 6800 */ 6801 6802 SKIP_WHITESPACE (); 6803 varstart = input_line_pointer; 6804 6805 /* Look for the '='. */ 6806 while (! is_end_of_line[(unsigned char) *input_line_pointer] 6807 && *input_line_pointer != '=') 6808 ++input_line_pointer; 6809 if (*input_line_pointer != '=') 6810 { 6811 as_bad (_("missing =")); 6812 ignore_rest_of_line (); 6813 return; 6814 } 6815 6816 varstop = input_line_pointer; 6817 if (varstop > varstart 6818 && (varstop[-1] == ' ' || varstop[-1] == '\t')) 6819 --varstop; 6820 6821 ++input_line_pointer; 6822 6823 initstart = input_line_pointer; 6824 6825 /* Look for TO or DOWNTO. */ 6826 up = 1; 6827 initstop = NULL; 6828 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6829 { 6830 if (strncasecmp (input_line_pointer, "TO", 2) == 0 6831 && ! is_part_of_name (input_line_pointer[2])) 6832 { 6833 initstop = input_line_pointer; 6834 input_line_pointer += 2; 6835 break; 6836 } 6837 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 6838 && ! is_part_of_name (input_line_pointer[6])) 6839 { 6840 initstop = input_line_pointer; 6841 up = 0; 6842 input_line_pointer += 6; 6843 break; 6844 } 6845 ++input_line_pointer; 6846 } 6847 if (initstop == NULL) 6848 { 6849 as_bad (_("missing to or downto")); 6850 ignore_rest_of_line (); 6851 return; 6852 } 6853 if (initstop > initstart 6854 && (initstop[-1] == ' ' || initstop[-1] == '\t')) 6855 --initstop; 6856 6857 SKIP_WHITESPACE (); 6858 endstart = input_line_pointer; 6859 6860 /* Look for BY or DO. */ 6861 by = 0; 6862 endstop = NULL; 6863 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6864 { 6865 if (strncasecmp (input_line_pointer, "BY", 2) == 0 6866 && ! is_part_of_name (input_line_pointer[2])) 6867 { 6868 endstop = input_line_pointer; 6869 by = 1; 6870 input_line_pointer += 2; 6871 break; 6872 } 6873 if (strncasecmp (input_line_pointer, "DO", 2) == 0 6874 && (input_line_pointer[2] == '.' 6875 || ! is_part_of_name (input_line_pointer[2]))) 6876 { 6877 endstop = input_line_pointer; 6878 input_line_pointer += 2; 6879 break; 6880 } 6881 ++input_line_pointer; 6882 } 6883 if (endstop == NULL) 6884 { 6885 as_bad (_("missing do")); 6886 ignore_rest_of_line (); 6887 return; 6888 } 6889 if (endstop > endstart 6890 && (endstop[-1] == ' ' || endstop[-1] == '\t')) 6891 --endstop; 6892 6893 if (! by) 6894 { 6895 bystart = "#1"; 6896 bystop = bystart + 2; 6897 } 6898 else 6899 { 6900 SKIP_WHITESPACE (); 6901 bystart = input_line_pointer; 6902 6903 /* Look for DO. */ 6904 bystop = NULL; 6905 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6906 { 6907 if (strncasecmp (input_line_pointer, "DO", 2) == 0 6908 && (input_line_pointer[2] == '.' 6909 || ! is_part_of_name (input_line_pointer[2]))) 6910 { 6911 bystop = input_line_pointer; 6912 input_line_pointer += 2; 6913 break; 6914 } 6915 ++input_line_pointer; 6916 } 6917 if (bystop == NULL) 6918 { 6919 as_bad (_("missing do")); 6920 ignore_rest_of_line (); 6921 return; 6922 } 6923 if (bystop > bystart 6924 && (bystop[-1] == ' ' || bystop[-1] == '\t')) 6925 --bystop; 6926 } 6927 6928 if (*input_line_pointer != '.') 6929 extent = '\0'; 6930 else 6931 { 6932 extent = input_line_pointer[1]; 6933 input_line_pointer += 2; 6934 } 6935 6936 /* We have fully parsed the FOR operands. Now build the loop. */ 6937 n = push_mri_control (mri_for); 6938 6939 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart)); 6940 6941 /* Move init,var. */ 6942 s = buf; 6943 *s++ = 'm'; 6944 *s++ = 'o'; 6945 *s++ = 'v'; 6946 *s++ = 'e'; 6947 if (qual != '\0') 6948 *s++ = TOLOWER (qual); 6949 *s++ = ' '; 6950 memcpy (s, initstart, initstop - initstart); 6951 s += initstop - initstart; 6952 *s++ = ','; 6953 memcpy (s, varstart, varstop - varstart); 6954 s += varstop - varstart; 6955 *s = '\0'; 6956 mri_assemble (buf); 6957 6958 colon (n->top); 6959 6960 /* cmp end,var. */ 6961 s = buf; 6962 *s++ = 'c'; 6963 *s++ = 'm'; 6964 *s++ = 'p'; 6965 if (qual != '\0') 6966 *s++ = TOLOWER (qual); 6967 *s++ = ' '; 6968 memcpy (s, endstart, endstop - endstart); 6969 s += endstop - endstart; 6970 *s++ = ','; 6971 memcpy (s, varstart, varstop - varstart); 6972 s += varstop - varstart; 6973 *s = '\0'; 6974 mri_assemble (buf); 6975 6976 /* bcc bottom. */ 6977 ex[0] = TOLOWER (extent); 6978 ex[1] = '\0'; 6979 if (up) 6980 sprintf (buf, "blt%s %s", ex, n->bottom); 6981 else 6982 sprintf (buf, "bgt%s %s", ex, n->bottom); 6983 mri_assemble (buf); 6984 6985 /* Put together the add or sub instruction used by ENDF. */ 6986 s = buf; 6987 if (up) 6988 strcpy (s, "add"); 6989 else 6990 strcpy (s, "sub"); 6991 s += 3; 6992 if (qual != '\0') 6993 *s++ = TOLOWER (qual); 6994 *s++ = ' '; 6995 memcpy (s, bystart, bystop - bystart); 6996 s += bystop - bystart; 6997 *s++ = ','; 6998 memcpy (s, varstart, varstop - varstart); 6999 s += varstop - varstart; 7000 *s = '\0'; 7001 n->incr = buf; 7002 7003 if (flag_mri) 7004 { 7005 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7006 ++input_line_pointer; 7007 } 7008 7009 demand_empty_rest_of_line (); 7010} 7011 7012/* Handle the MRI ENDF pseudo-op. */ 7013 7014static void 7015s_mri_endf (int ignore ATTRIBUTE_UNUSED) 7016{ 7017 if (mri_control_stack == NULL 7018 || mri_control_stack->type != mri_for) 7019 { 7020 as_bad (_("endf without for")); 7021 ignore_rest_of_line (); 7022 return; 7023 } 7024 7025 colon (mri_control_stack->next); 7026 7027 mri_assemble (mri_control_stack->incr); 7028 7029 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); 7030 mri_assemble (mri_control_stack->incr); 7031 7032 free (mri_control_stack->incr); 7033 7034 colon (mri_control_stack->bottom); 7035 7036 pop_mri_control (); 7037 7038 if (flag_mri) 7039 { 7040 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7041 ++input_line_pointer; 7042 } 7043 7044 demand_empty_rest_of_line (); 7045} 7046 7047/* Handle the MRI REPEAT pseudo-op. */ 7048 7049static void 7050s_mri_repeat (int ignore ATTRIBUTE_UNUSED) 7051{ 7052 struct mri_control_info *n; 7053 7054 n = push_mri_control (mri_repeat); 7055 colon (n->top); 7056 if (flag_mri) 7057 { 7058 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7059 ++input_line_pointer; 7060 } 7061 demand_empty_rest_of_line (); 7062} 7063 7064/* Handle the MRI UNTIL pseudo-op. */ 7065 7066static void 7067s_mri_until (int qual) 7068{ 7069 char *s; 7070 7071 if (mri_control_stack == NULL 7072 || mri_control_stack->type != mri_repeat) 7073 { 7074 as_bad (_("until without repeat")); 7075 ignore_rest_of_line (); 7076 return; 7077 } 7078 7079 colon (mri_control_stack->next); 7080 7081 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) 7082 ; 7083 7084 parse_mri_control_expression (s, qual, (const char *) NULL, 7085 mri_control_stack->top, '\0'); 7086 7087 colon (mri_control_stack->bottom); 7088 7089 input_line_pointer = s; 7090 7091 pop_mri_control (); 7092 7093 if (flag_mri) 7094 { 7095 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7096 ++input_line_pointer; 7097 } 7098 7099 demand_empty_rest_of_line (); 7100} 7101 7102/* Handle the MRI WHILE pseudo-op. */ 7103 7104static void 7105s_mri_while (int qual) 7106{ 7107 char *s; 7108 7109 struct mri_control_info *n; 7110 7111 s = input_line_pointer; 7112 /* We only accept '*' as introduction of comments if preceded by white space 7113 or at first column of a line (I think this can't actually happen here?) 7114 This is important when assembling: 7115 while d0 <ne> 12(a0,d0*2) do 7116 while d0 <ne> #CONST*20 do. */ 7117 while (! (is_end_of_line[(unsigned char) *s] 7118 || (flag_mri 7119 && *s == '*' 7120 && (s == input_line_pointer 7121 || *(s-1) == ' ' 7122 || *(s-1) == '\t')))) 7123 s++; 7124 --s; 7125 while (*s == ' ' || *s == '\t') 7126 --s; 7127 if (s - input_line_pointer > 1 7128 && s[-1] == '.') 7129 s -= 2; 7130 if (s - input_line_pointer < 2 7131 || strncasecmp (s - 1, "DO", 2) != 0) 7132 { 7133 as_bad (_("missing do")); 7134 ignore_rest_of_line (); 7135 return; 7136 } 7137 7138 n = push_mri_control (mri_while); 7139 7140 colon (n->next); 7141 7142 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, 7143 s[1] == '.' ? s[2] : '\0'); 7144 7145 input_line_pointer = s + 1; 7146 if (*input_line_pointer == '.') 7147 input_line_pointer += 2; 7148 7149 if (flag_mri) 7150 { 7151 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7152 ++input_line_pointer; 7153 } 7154 7155 demand_empty_rest_of_line (); 7156} 7157 7158/* Handle the MRI ENDW pseudo-op. */ 7159 7160static void 7161s_mri_endw (int ignore ATTRIBUTE_UNUSED) 7162{ 7163 char *buf; 7164 7165 if (mri_control_stack == NULL 7166 || mri_control_stack->type != mri_while) 7167 { 7168 as_bad (_("endw without while")); 7169 ignore_rest_of_line (); 7170 return; 7171 } 7172 7173 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next)); 7174 sprintf (buf, "bra %s", mri_control_stack->next); 7175 mri_assemble (buf); 7176 free (buf); 7177 7178 colon (mri_control_stack->bottom); 7179 7180 pop_mri_control (); 7181 7182 if (flag_mri) 7183 { 7184 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7185 ++input_line_pointer; 7186 } 7187 7188 demand_empty_rest_of_line (); 7189} 7190 7191/* Parse a .cpu directive. */ 7192 7193static void 7194s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) 7195{ 7196 char saved_char; 7197 char *name; 7198 7199 if (initialized) 7200 { 7201 as_bad (_("already assembled instructions")); 7202 ignore_rest_of_line (); 7203 return; 7204 } 7205 7206 name = input_line_pointer; 7207 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 7208 input_line_pointer++; 7209 saved_char = *input_line_pointer; 7210 *input_line_pointer = 0; 7211 7212 m68k_set_cpu (name, 1, 0); 7213 7214 *input_line_pointer = saved_char; 7215 demand_empty_rest_of_line (); 7216 return; 7217} 7218 7219/* Parse a .arch directive. */ 7220 7221static void 7222s_m68k_arch (int ignored ATTRIBUTE_UNUSED) 7223{ 7224 char saved_char; 7225 char *name; 7226 7227 if (initialized) 7228 { 7229 as_bad (_("already assembled instructions")); 7230 ignore_rest_of_line (); 7231 return; 7232 } 7233 7234 name = input_line_pointer; 7235 while (*input_line_pointer && *input_line_pointer != ',' 7236 && !ISSPACE (*input_line_pointer)) 7237 input_line_pointer++; 7238 saved_char = *input_line_pointer; 7239 *input_line_pointer = 0; 7240 7241 if (m68k_set_arch (name, 1, 0)) 7242 { 7243 /* Scan extensions. */ 7244 do 7245 { 7246 *input_line_pointer++ = saved_char; 7247 if (!*input_line_pointer || ISSPACE (*input_line_pointer)) 7248 break; 7249 name = input_line_pointer; 7250 while (*input_line_pointer && *input_line_pointer != ',' 7251 && !ISSPACE (*input_line_pointer)) 7252 input_line_pointer++; 7253 saved_char = *input_line_pointer; 7254 *input_line_pointer = 0; 7255 } 7256 while (m68k_set_extension (name, 1, 0)); 7257 } 7258 7259 *input_line_pointer = saved_char; 7260 demand_empty_rest_of_line (); 7261 return; 7262} 7263 7264/* Lookup a cpu name in TABLE and return the slot found. Return NULL 7265 if none is found, the caller is responsible for emitting an error 7266 message. If ALLOW_M is non-zero, we allow an initial 'm' on the 7267 cpu name, if it begins with a '6' (possibly skipping an intervening 7268 'c'. We also allow a 'c' in the same place. if NEGATED is 7269 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if 7270 the option is indeed negated. */ 7271 7272static const struct m68k_cpu * 7273m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, 7274 int allow_m, int *negated) 7275{ 7276 /* allow negated value? */ 7277 if (negated) 7278 { 7279 *negated = 0; 7280 7281 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') 7282 { 7283 arg += 3; 7284 *negated = 1; 7285 } 7286 } 7287 7288 /* Remove 'm' or 'mc' prefix from 68k variants. */ 7289 if (allow_m) 7290 { 7291 if (arg[0] == 'm') 7292 { 7293 if (arg[1] == '6') 7294 arg += 1; 7295 else if (arg[1] == 'c' && arg[2] == '6') 7296 arg += 2; 7297 } 7298 } 7299 else if (arg[0] == 'c' && arg[1] == '6') 7300 arg += 1; 7301 7302 for (; table->name; table++) 7303 if (!strcmp (arg, table->name)) 7304 { 7305 if (table->alias < -1 || table->alias > 1) 7306 as_bad (_("`%s' is deprecated, use `%s'"), 7307 table->name, table[table->alias < 0 ? 1 : -1].name); 7308 return table; 7309 } 7310 return 0; 7311} 7312 7313/* Set the cpu, issuing errors if it is unrecognized. */ 7314 7315static int 7316m68k_set_cpu (char const *name, int allow_m, int silent) 7317{ 7318 const struct m68k_cpu *cpu; 7319 7320 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); 7321 7322 if (!cpu) 7323 { 7324 if (!silent) 7325 as_bad (_("cpu `%s' unrecognized"), name); 7326 return 0; 7327 } 7328 selected_cpu = cpu; 7329 return 1; 7330} 7331 7332/* Set the architecture, issuing errors if it is unrecognized. */ 7333 7334static int 7335m68k_set_arch (char const *name, int allow_m, int silent) 7336{ 7337 const struct m68k_cpu *arch; 7338 7339 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); 7340 7341 if (!arch) 7342 { 7343 if (!silent) 7344 as_bad (_("architecture `%s' unrecognized"), name); 7345 return 0; 7346 } 7347 selected_arch = arch; 7348 return 1; 7349} 7350 7351/* Set the architecture extension, issuing errors if it is 7352 unrecognized, or invalid */ 7353 7354static int 7355m68k_set_extension (char const *name, int allow_m, int silent) 7356{ 7357 int negated; 7358 const struct m68k_cpu *ext; 7359 7360 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); 7361 7362 if (!ext) 7363 { 7364 if (!silent) 7365 as_bad (_("extension `%s' unrecognized"), name); 7366 return 0; 7367 } 7368 7369 if (negated) 7370 not_current_architecture |= (ext->control_regs 7371 ? *(unsigned *)ext->control_regs: ext->arch); 7372 else 7373 current_architecture |= ext->arch; 7374 return 1; 7375} 7376 7377/* md_parse_option 7378 Invocation line includes a switch not recognized by the base assembler. 7379 */ 7380 7381const char *md_shortopts = "lSA:m:kQ:V"; 7382 7383struct option md_longopts[] = { 7384#define OPTION_PIC (OPTION_MD_BASE) 7385 {"pic", no_argument, NULL, OPTION_PIC}, 7386#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) 7387 {"register-prefix-optional", no_argument, NULL, 7388 OPTION_REGISTER_PREFIX_OPTIONAL}, 7389#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) 7390 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, 7391#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) 7392 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, 7393#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) 7394 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, 7395#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) 7396 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, 7397#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) 7398 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 7399#define OPTION_PCREL (OPTION_MD_BASE + 7) 7400 {"pcrel", no_argument, NULL, OPTION_PCREL}, 7401 {NULL, no_argument, NULL, 0} 7402}; 7403size_t md_longopts_size = sizeof (md_longopts); 7404 7405int 7406md_parse_option (int c, const char *arg) 7407{ 7408 switch (c) 7409 { 7410 case 'l': /* -l means keep external to 2 bit offset 7411 rather than 16 bit one. */ 7412 flag_short_refs = 1; 7413 break; 7414 7415 case 'S': /* -S means that jbsr's always turn into 7416 jsr's. */ 7417 flag_long_jumps = 1; 7418 break; 7419 7420 case OPTION_PCREL: /* --pcrel means never turn PC-relative 7421 branches into absolute jumps. */ 7422 flag_keep_pcrel = 1; 7423 break; 7424 7425 case OPTION_PIC: 7426 case 'k': 7427 flag_want_pic = 1; 7428 break; /* -pic, Position Independent Code. */ 7429 7430 case OPTION_REGISTER_PREFIX_OPTIONAL: 7431 flag_reg_prefix_optional = 1; 7432 reg_prefix_optional_seen = 1; 7433 break; 7434 7435 /* -V: SVR4 argument to print version ID. */ 7436 case 'V': 7437 print_version_id (); 7438 break; 7439 7440 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 7441 should be emitted or not. FIXME: Not implemented. */ 7442 case 'Q': 7443 break; 7444 7445 case OPTION_BITWISE_OR: 7446 { 7447 char *n, *t; 7448 const char *s; 7449 7450 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1); 7451 t = n; 7452 for (s = m68k_comment_chars; *s != '\0'; s++) 7453 if (*s != '|') 7454 *t++ = *s; 7455 *t = '\0'; 7456 m68k_comment_chars = n; 7457 } 7458 break; 7459 7460 case OPTION_BASE_SIZE_DEFAULT_16: 7461 m68k_index_width_default = SIZE_WORD; 7462 break; 7463 7464 case OPTION_BASE_SIZE_DEFAULT_32: 7465 m68k_index_width_default = SIZE_LONG; 7466 break; 7467 7468 case OPTION_DISP_SIZE_DEFAULT_16: 7469 m68k_rel32 = 0; 7470 m68k_rel32_from_cmdline = 1; 7471 break; 7472 7473 case OPTION_DISP_SIZE_DEFAULT_32: 7474 m68k_rel32 = 1; 7475 m68k_rel32_from_cmdline = 1; 7476 break; 7477 7478 case 'A': 7479#if WARN_DEPRECATED 7480 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", 7481 arg, arg)); 7482#endif 7483 /* Intentional fall-through. */ 7484 case 'm': 7485 if (!strncmp (arg, "arch=", 5)) 7486 m68k_set_arch (arg + 5, 1, 0); 7487 else if (!strncmp (arg, "cpu=", 4)) 7488 m68k_set_cpu (arg + 4, 1, 0); 7489 else if (m68k_set_extension (arg, 0, 1)) 7490 ; 7491 else if (m68k_set_arch (arg, 0, 1)) 7492 ; 7493 else if (m68k_set_cpu (arg, 0, 1)) 7494 ; 7495 else 7496 return 0; 7497 break; 7498 7499 default: 7500 return 0; 7501 } 7502 7503 return 1; 7504} 7505 7506/* Setup tables from the selected arch and/or cpu */ 7507 7508static void 7509m68k_init_arch (void) 7510{ 7511 if (not_current_architecture & current_architecture) 7512 { 7513 as_bad (_("architecture features both enabled and disabled")); 7514 not_current_architecture &= ~current_architecture; 7515 } 7516 if (selected_arch) 7517 { 7518 current_architecture |= selected_arch->arch; 7519 control_regs = selected_arch->control_regs; 7520 } 7521 else 7522 current_architecture |= selected_cpu->arch; 7523 7524 current_architecture &= ~not_current_architecture; 7525 7526 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) 7527 { 7528 /* Determine which float is really meant. */ 7529 if (current_architecture & (m68k_mask & ~m68881)) 7530 current_architecture ^= cfloat; 7531 else 7532 current_architecture ^= m68881; 7533 } 7534 7535 if (selected_cpu) 7536 { 7537 control_regs = selected_cpu->control_regs; 7538 if (current_architecture & ~selected_cpu->arch) 7539 { 7540 as_bad (_("selected processor does not have all features of selected architecture")); 7541 current_architecture 7542 = selected_cpu->arch & ~not_current_architecture; 7543 } 7544 } 7545 7546 if ((current_architecture & m68k_mask) 7547 && (current_architecture & ~m68k_mask)) 7548 { 7549 as_bad (_ ("m68k and cf features both selected")); 7550 if (current_architecture & m68k_mask) 7551 current_architecture &= m68k_mask; 7552 else 7553 current_architecture &= ~m68k_mask; 7554 } 7555 7556 /* Permit m68881 specification with all cpus; those that can't work 7557 with a coprocessor could be doing emulation. */ 7558 if (current_architecture & m68851) 7559 { 7560 if (current_architecture & m68040) 7561 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); 7562 } 7563 /* What other incompatibilities could we check for? */ 7564 7565 if (cpu_of_arch (current_architecture) < m68020 7566 || arch_coldfire_p (current_architecture)) 7567 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; 7568 7569 initialized = 1; 7570} 7571 7572void 7573md_show_usage (FILE *stream) 7574{ 7575 const char *default_cpu = TARGET_CPU; 7576 int i; 7577 7578 /* Get the canonical name for the default target CPU. */ 7579 if (*default_cpu == 'm') 7580 default_cpu++; 7581 for (i = 0; m68k_cpus[i].name; i++) 7582 { 7583 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) 7584 { 7585 while (m68k_cpus[i].alias > 0) 7586 i--; 7587 while (m68k_cpus[i].alias < 0) 7588 i++; 7589 default_cpu = m68k_cpus[i].name; 7590 } 7591 } 7592 7593 fprintf (stream, _("\ 7594-march=<arch> set architecture\n\ 7595-mcpu=<cpu> set cpu [default %s]\n\ 7596"), default_cpu); 7597 for (i = 0; m68k_extensions[i].name; i++) 7598 fprintf (stream, _("\ 7599-m[no-]%-16s enable/disable %s architecture extension\n\ 7600"), m68k_extensions[i].name, 7601 m68k_extensions[i].alias > 0 ? " ColdFire" 7602 : m68k_extensions[i].alias < 0 ? " m68k" : ""); 7603 7604 fprintf (stream, _("\ 7605-l use 1 word for refs to undefined symbols [default 2]\n\ 7606-pic, -k generate position independent code\n\ 7607-S turn jbsr into jsr\n\ 7608--pcrel never turn PC-relative branches into absolute jumps\n\ 7609--register-prefix-optional\n\ 7610 recognize register names without prefix character\n\ 7611--bitwise-or do not treat `|' as a comment character\n\ 7612--base-size-default-16 base reg without size is 16 bits\n\ 7613--base-size-default-32 base reg without size is 32 bits (default)\n\ 7614--disp-size-default-16 displacement with unknown size is 16 bits\n\ 7615--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ 7616")); 7617 7618 fprintf (stream, _("Architecture variants are: ")); 7619 for (i = 0; m68k_archs[i].name; i++) 7620 { 7621 if (i) 7622 fprintf (stream, " | "); 7623 fprintf (stream, "%s", m68k_archs[i].name); 7624 } 7625 fprintf (stream, "\n"); 7626 7627 fprintf (stream, _("Processor variants are: ")); 7628 for (i = 0; m68k_cpus[i].name; i++) 7629 { 7630 if (i) 7631 fprintf (stream, " | "); 7632 fprintf (stream, "%s", m68k_cpus[i].name); 7633 } 7634 fprintf (stream, _("\n")); 7635} 7636 7637#ifdef TEST2 7638 7639/* TEST2: Test md_assemble() */ 7640/* Warning, this routine probably doesn't work anymore. */ 7641int 7642main (void) 7643{ 7644 struct m68k_it the_ins; 7645 char buf[120]; 7646 char *cp; 7647 int n; 7648 7649 m68k_ip_begin (); 7650 for (;;) 7651 { 7652 if (!gets (buf) || !*buf) 7653 break; 7654 if (buf[0] == '|' || buf[1] == '.') 7655 continue; 7656 for (cp = buf; *cp; cp++) 7657 if (*cp == '\t') 7658 *cp = ' '; 7659 if (is_label (buf)) 7660 continue; 7661 memset (&the_ins, '\0', sizeof (the_ins)); 7662 m68k_ip (&the_ins, buf); 7663 if (the_ins.error) 7664 { 7665 printf (_("Error %s in %s\n"), the_ins.error, buf); 7666 } 7667 else 7668 { 7669 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); 7670 for (n = 0; n < the_ins.numo; n++) 7671 printf (" 0x%x", the_ins.opcode[n] & 0xffff); 7672 printf (" "); 7673 print_the_insn (&the_ins.opcode[0], stdout); 7674 (void) putchar ('\n'); 7675 } 7676 for (n = 0; n < strlen (the_ins.args) / 2; n++) 7677 { 7678 if (the_ins.operands[n].error) 7679 { 7680 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); 7681 continue; 7682 } 7683 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, 7684 the_ins.operands[n].reg); 7685 if (the_ins.operands[n].b_const) 7686 printf ("Constant: '%.*s', ", 7687 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, 7688 the_ins.operands[n].b_const); 7689 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, 7690 the_ins.operands[n].isiz, the_ins.operands[n].imul); 7691 if (the_ins.operands[n].b_iadd) 7692 printf ("Iadd: '%.*s',", 7693 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, 7694 the_ins.operands[n].b_iadd); 7695 putchar ('\n'); 7696 } 7697 } 7698 m68k_ip_end (); 7699 return 0; 7700} 7701 7702int 7703is_label (char *str) 7704{ 7705 while (*str == ' ') 7706 str++; 7707 while (*str && *str != ' ') 7708 str++; 7709 if (str[-1] == ':' || str[1] == '=') 7710 return 1; 7711 return 0; 7712} 7713 7714#endif 7715 7716/* Possible states for relaxation: 7717 7718 0 0 branch offset byte (bra, etc) 7719 0 1 word 7720 0 2 long 7721 7722 1 0 indexed offsets byte a0@(32,d4:w:1) etc 7723 1 1 word 7724 1 2 long 7725 7726 2 0 two-offset index word-word a0@(32,d4)@(45) etc 7727 2 1 word-long 7728 2 2 long-word 7729 2 3 long-long 7730 7731 */ 7732 7733/* We have no need to default values of symbols. */ 7734 7735symbolS * 7736md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 7737{ 7738 return 0; 7739} 7740 7741/* Round up a section size to the appropriate boundary. */ 7742valueT 7743md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 7744{ 7745 return size; 7746} 7747 7748/* Exactly what point is a PC-relative offset relative TO? 7749 On the 68k, it is relative to the address of the first extension 7750 word. The difference between the addresses of the offset and the 7751 first extension word is stored in fx_pcrel_adjust. */ 7752long 7753md_pcrel_from (fixS *fixP) 7754{ 7755 int adjust; 7756 7757 adjust = fixP->fx_pcrel_adjust; 7758 if (adjust == 64) 7759 adjust = -1; 7760 return fixP->fx_where + fixP->fx_frag->fr_address - adjust; 7761} 7762 7763void 7764m68k_elf_final_processing (void) 7765{ 7766 unsigned flags = 0; 7767 7768 if (arch_coldfire_fpu (current_architecture)) 7769 flags |= EF_M68K_CFV4E; 7770 /* Set file-specific flags if this is a cpu32 processor. */ 7771 if (cpu_of_arch (current_architecture) & cpu32) 7772 flags |= EF_M68K_CPU32; 7773 else if (cpu_of_arch (current_architecture) & fido_a) 7774 flags |= EF_M68K_FIDO; 7775 else if ((cpu_of_arch (current_architecture) & m68000up) 7776 && !(cpu_of_arch (current_architecture) & m68020up)) 7777 flags |= EF_M68K_M68000; 7778 7779 if (current_architecture & mcfisa_a) 7780 { 7781 static const unsigned isa_features[][2] = 7782 { 7783 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, 7784 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, 7785 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, 7786 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, 7787 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, 7788 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, 7789 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, 7790 {0,0}, 7791 }; 7792 static const unsigned mac_features[][2] = 7793 { 7794 {EF_M68K_CF_MAC, mcfmac}, 7795 {EF_M68K_CF_EMAC, mcfemac}, 7796 {0,0}, 7797 }; 7798 unsigned ix; 7799 unsigned pattern; 7800 7801 pattern = (current_architecture 7802 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); 7803 for (ix = 0; isa_features[ix][1]; ix++) 7804 { 7805 if (pattern == isa_features[ix][1]) 7806 { 7807 flags |= isa_features[ix][0]; 7808 break; 7809 } 7810 } 7811 if (!isa_features[ix][1]) 7812 { 7813 cf_bad: 7814 as_warn (_("Not a defined coldfire architecture")); 7815 } 7816 else 7817 { 7818 if (current_architecture & cfloat) 7819 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; 7820 7821 pattern = current_architecture & (mcfmac|mcfemac); 7822 if (pattern) 7823 { 7824 for (ix = 0; mac_features[ix][1]; ix++) 7825 { 7826 if (pattern == mac_features[ix][1]) 7827 { 7828 flags |= mac_features[ix][0]; 7829 break; 7830 } 7831 } 7832 if (!mac_features[ix][1]) 7833 goto cf_bad; 7834 } 7835 } 7836 } 7837 elf_elfheader (stdoutput)->e_flags |= flags; 7838} 7839 7840/* Parse @TLSLDO and return the desired relocation. */ 7841static bfd_reloc_code_real_type 7842m68k_elf_suffix (char **str_p, expressionS *exp_p) 7843{ 7844 char ident[20]; 7845 char *str = *str_p; 7846 char *str2; 7847 int ch; 7848 int len; 7849 7850 if (*str++ != '@') 7851 return BFD_RELOC_UNUSED; 7852 7853 for (ch = *str, str2 = ident; 7854 (str2 < ident + sizeof (ident) - 1 7855 && (ISALNUM (ch) || ch == '@')); 7856 ch = *++str) 7857 { 7858 *str2++ = ch; 7859 } 7860 7861 *str2 = '\0'; 7862 len = str2 - ident; 7863 7864 if (strncmp (ident, "TLSLDO", 6) == 0 7865 && len == 6) 7866 { 7867 /* Now check for identifier@suffix+constant. */ 7868 if (*str == '-' || *str == '+') 7869 { 7870 char *orig_line = input_line_pointer; 7871 expressionS new_exp; 7872 7873 input_line_pointer = str; 7874 expression (&new_exp); 7875 if (new_exp.X_op == O_constant) 7876 { 7877 exp_p->X_add_number += new_exp.X_add_number; 7878 str = input_line_pointer; 7879 } 7880 7881 if (&input_line_pointer != str_p) 7882 input_line_pointer = orig_line; 7883 } 7884 *str_p = str; 7885 7886 return BFD_RELOC_68K_TLS_LDO32; 7887 } 7888 7889 return BFD_RELOC_UNUSED; 7890} 7891 7892/* Handles .long <tls_symbol>+0x8000 debug info. 7893 Clobbers input_line_pointer, checks end-of-line. 7894 Adapted from tc-ppc.c:ppc_elf_cons. */ 7895static void 7896m68k_elf_cons (int nbytes /* 4=.long */) 7897{ 7898 if (is_it_end_of_statement ()) 7899 { 7900 demand_empty_rest_of_line (); 7901 return; 7902 } 7903 7904 do 7905 { 7906 expressionS exp; 7907 bfd_reloc_code_real_type reloc; 7908 7909 expression (&exp); 7910 if (exp.X_op == O_symbol 7911 && *input_line_pointer == '@' 7912 && (reloc = m68k_elf_suffix (&input_line_pointer, 7913 &exp)) != BFD_RELOC_UNUSED) 7914 { 7915 reloc_howto_type *reloc_howto; 7916 int size; 7917 7918 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); 7919 size = bfd_get_reloc_size (reloc_howto); 7920 7921 if (size > nbytes) 7922 { 7923 as_bad (ngettext ("%s relocations do not fit in %u byte", 7924 "%s relocations do not fit in %u bytes", 7925 nbytes), 7926 reloc_howto->name, nbytes); 7927 } 7928 else 7929 { 7930 char *p; 7931 int offset; 7932 7933 p = frag_more (nbytes); 7934 offset = 0; 7935 if (target_big_endian) 7936 offset = nbytes - size; 7937 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, 7938 &exp, 0, reloc); 7939 } 7940 } 7941 else 7942 emit_expr (&exp, (unsigned int) nbytes); 7943 } 7944 while (*input_line_pointer++ == ','); 7945 7946 /* Put terminator back into stream. */ 7947 input_line_pointer--; 7948 demand_empty_rest_of_line (); 7949} 7950 7951/* Parse a .gnu_attribute directive. */ 7952static void 7953m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) 7954{ 7955 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); 7956 7957 /* Check validity of defined m68k tags. */ 7958 if (tag == Tag_GNU_M68K_ABI_FP) 7959 { 7960 unsigned int val; 7961 7962 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); 7963 7964 if (tag == Tag_GNU_M68K_ABI_FP && val > 2) 7965 as_warn (_("unknown .gnu_attribute value")); 7966 } 7967} 7968 7969int 7970tc_m68k_regname_to_dw2regnum (const char *regname) 7971{ 7972 unsigned int regnum; 7973 static const char *const regnames[] = 7974 { 7975 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 7976 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", 7977 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", 7978 "pc" 7979 }; 7980 7981 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) 7982 if (strcmp (regname, regnames[regnum]) == 0) 7983 return regnum; 7984 7985 return -1; 7986} 7987 7988void 7989tc_m68k_frame_initial_instructions (void) 7990{ 7991 static int sp_regno = -1; 7992 7993 if (sp_regno < 0) 7994 sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); 7995 7996 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); 7997 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); 7998} 7999 8000/* Check and emit error if broken-word handling has failed to fix up a 8001 case-table. This is called from write.c, after doing everything it 8002 knows about how to handle broken words. */ 8003 8004void 8005tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 8006{ 8007 if (new_offset > 32767 || new_offset < -32768) 8008 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 8009 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."), 8010 (long) new_offset); 8011} 8012 8013