1/* tc-h8300.c -- Assemble code for the Renesas H8/300 2 Copyright (C) 1991-2020 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21/* Written By Steve Chamberlain <sac@cygnus.com>. */ 22 23#include "as.h" 24#include "subsegs.h" 25#include "dwarf2dbg.h" 26 27#define DEFINE_TABLE 28#define h8_opcodes ops 29#include "opcode/h8300.h" 30#include "safe-ctype.h" 31#include "elf/h8.h" 32 33const char comment_chars[] = ";"; 34const char line_comment_chars[] = "#"; 35#ifdef TE_LINUX 36const char line_separator_chars[] = "!"; 37#else 38const char line_separator_chars[] = ""; 39#endif 40 41static void sbranch (int); 42static void h8300hmode (int); 43static void h8300smode (int); 44static void h8300hnmode (int); 45static void h8300snmode (int); 46static void h8300sxmode (int); 47static void h8300sxnmode (int); 48static void pint (int); 49 50int Hmode; 51int Smode; 52int Nmode; 53int SXmode; 54 55static int default_mach = bfd_mach_h8300; 56 57#define PSIZE (Hmode && !Nmode ? L_32 : L_16) 58 59static int bsize = L_8; /* Default branch displacement. */ 60 61struct h8_instruction 62{ 63 int length; 64 int noperands; 65 int idx; 66 int size; 67 const struct h8_opcode *opcode; 68}; 69 70static struct h8_instruction *h8_instructions; 71 72static void 73h8300hmode (int arg ATTRIBUTE_UNUSED) 74{ 75 Hmode = 1; 76 Smode = 0; 77 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) 78 as_warn (_("could not set architecture and machine")); 79} 80 81static void 82h8300smode (int arg ATTRIBUTE_UNUSED) 83{ 84 Smode = 1; 85 Hmode = 1; 86 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) 87 as_warn (_("could not set architecture and machine")); 88} 89 90static void 91h8300hnmode (int arg ATTRIBUTE_UNUSED) 92{ 93 Hmode = 1; 94 Smode = 0; 95 Nmode = 1; 96 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) 97 as_warn (_("could not set architecture and machine")); 98} 99 100static void 101h8300snmode (int arg ATTRIBUTE_UNUSED) 102{ 103 Smode = 1; 104 Hmode = 1; 105 Nmode = 1; 106 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) 107 as_warn (_("could not set architecture and machine")); 108} 109 110static void 111h8300sxmode (int arg ATTRIBUTE_UNUSED) 112{ 113 Smode = 1; 114 Hmode = 1; 115 SXmode = 1; 116 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) 117 as_warn (_("could not set architecture and machine")); 118} 119 120static void 121h8300sxnmode (int arg ATTRIBUTE_UNUSED) 122{ 123 Smode = 1; 124 Hmode = 1; 125 SXmode = 1; 126 Nmode = 1; 127 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) 128 as_warn (_("could not set architecture and machine")); 129} 130 131static void 132sbranch (int size) 133{ 134 bsize = size; 135} 136 137static void 138pint (int arg ATTRIBUTE_UNUSED) 139{ 140 cons (Hmode ? 4 : 2); 141} 142 143/* Like obj_elf_section, but issues a warning for new 144 sections which do not have an attribute specification. */ 145 146static void 147h8300_elf_section (int push) 148{ 149 static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; 150 static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; 151 char * saved_ilp = input_line_pointer; 152 const char * name; 153 154 name = obj_elf_section_name (); 155 if (name == NULL) 156 return; 157 158 if (* input_line_pointer != ',' 159 && bfd_get_section_by_name (stdoutput, name) == NULL) 160 { 161 signed int i; 162 163 /* Ignore this warning for well known data sections. */ 164 for (i = ARRAY_SIZE (known_data_sections); i--;) 165 if (strcmp (name, known_data_sections[i]) == 0) 166 break; 167 168 if (i < 0) 169 for (i = ARRAY_SIZE (known_data_prefixes); i--;) 170 if (strncmp (name, known_data_prefixes[i], 171 strlen (known_data_prefixes[i])) == 0) 172 break; 173 174 if (i < 0) 175 as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); 176 } 177 178 /* FIXME: We ought to free the memory allocated by obj_elf_section_name() 179 for 'name', but we do not know if it was taken from the obstack, via 180 demand_copy_C_string(), or xmalloc()ed. */ 181 input_line_pointer = saved_ilp; 182 obj_elf_section (push); 183} 184 185/* This table describes all the machine specific pseudo-ops the assembler 186 has to support. The fields are: 187 pseudo-op name without dot 188 function to call to execute this pseudo-op 189 Integer arg to pass to the function. */ 190 191const pseudo_typeS md_pseudo_table[] = 192{ 193 {"h8300h", h8300hmode, 0}, 194 {"h8300hn", h8300hnmode, 0}, 195 {"h8300s", h8300smode, 0}, 196 {"h8300sn", h8300snmode, 0}, 197 {"h8300sx", h8300sxmode, 0}, 198 {"h8300sxn", h8300sxnmode, 0}, 199 {"sbranch", sbranch, L_8}, 200 {"lbranch", sbranch, L_16}, 201 202 {"int", pint, 0}, 203 {"data.b", cons, 1}, 204 {"data.w", cons, 2}, 205 {"data.l", cons, 4}, 206 {"form", listing_psize, 0}, 207 {"heading", listing_title, 0}, 208 {"import", s_ignore, 0}, 209 {"page", listing_eject, 0}, 210 {"program", s_ignore, 0}, 211 212 {"section", h8300_elf_section, 0}, 213 {"section.s", h8300_elf_section, 0}, 214 {"sect", h8300_elf_section, 0}, 215 {"sect.s", h8300_elf_section, 0}, 216 217 {0, 0, 0} 218}; 219 220const char EXP_CHARS[] = "eE"; 221 222/* Chars that mean this number is a floating point constant 223 As in 0f12.456 224 or 0d1.2345e12. */ 225const char FLT_CHARS[] = "rRsSfFdDxXpP"; 226 227static htab_t opcode_hash_control; /* Opcode mnemonics. */ 228 229/* This function is called once, at assembler startup time. This 230 should set up all the tables, etc. that the MD part of the assembler 231 needs. */ 232 233void 234md_begin (void) 235{ 236 unsigned int nopcodes; 237 struct h8_opcode *p, *p1; 238 struct h8_instruction *pi; 239 char prev_buffer[100]; 240 int idx = 0; 241 242 if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) 243 as_warn (_("could not set architecture and machine")); 244 245 opcode_hash_control = str_htab_create (); 246 prev_buffer[0] = 0; 247 248 nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); 249 250 h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); 251 252 pi = h8_instructions; 253 p1 = h8_opcodes; 254 /* We do a minimum amount of sorting on the opcode table; this is to 255 make it easy to describe the mova instructions without unnecessary 256 code duplication. 257 Sorting only takes place inside blocks of instructions of the form 258 X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ 259 while (p1) 260 { 261 struct h8_opcode *first_skipped = 0; 262 int len, cmplen = 0; 263 const char *src = p1->name; 264 char *dst, *buffer; 265 266 if (p1->name == 0) 267 break; 268 /* Strip off any . part when inserting the opcode and only enter 269 unique codes into the hash table. */ 270 dst = buffer = XNEWVEC (char, strlen (src) + 1); 271 while (*src) 272 { 273 if (*src == '.') 274 { 275 src++; 276 break; 277 } 278 if (*src == '/') 279 cmplen = src - p1->name + 1; 280 *dst++ = *src++; 281 } 282 *dst = 0; 283 len = dst - buffer; 284 if (cmplen == 0) 285 cmplen = len; 286 str_hash_insert (opcode_hash_control, buffer, pi, 0); 287 strcpy (prev_buffer, buffer); 288 idx++; 289 290 for (p = p1; p->name; p++) 291 { 292 /* A negative TIME is used to indicate that we've added this opcode 293 already. */ 294 if (p->time == -1) 295 continue; 296 if (strncmp (p->name, buffer, cmplen) != 0 297 || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' 298 && p->name[cmplen - 1] != '/')) 299 { 300 if (first_skipped == 0) 301 first_skipped = p; 302 break; 303 } 304 if (strncmp (p->name, buffer, len) != 0) 305 { 306 if (first_skipped == 0) 307 first_skipped = p; 308 continue; 309 } 310 311 p->time = -1; 312 pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; 313 pi->idx = idx; 314 315 /* Find the number of operands. */ 316 pi->noperands = 0; 317 while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) 318 pi->noperands++; 319 320 /* Find the length of the opcode in bytes. */ 321 pi->length = 0; 322 while (p->data.nib[pi->length * 2] != (op_type) E) 323 pi->length++; 324 325 pi->opcode = p; 326 pi++; 327 } 328 p1 = first_skipped; 329 } 330 331 /* Add entry for the NULL vector terminator. */ 332 pi->length = 0; 333 pi->noperands = 0; 334 pi->idx = 0; 335 pi->size = 0; 336 pi->opcode = 0; 337 338 linkrelax = 1; 339} 340 341struct h8_op 342{ 343 op_type mode; 344 unsigned reg; 345 expressionS exp; 346}; 347 348static void clever_message (const struct h8_instruction *, struct h8_op *); 349static void fix_operand_size (struct h8_op *, int); 350static void build_bytes (const struct h8_instruction *, struct h8_op *); 351static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); 352static void check_operand (struct h8_op *, unsigned int, const char *); 353static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; 354static char *get_operands (unsigned, char *, struct h8_op *); 355static void get_operand (char **, struct h8_op *, int); 356static int parse_reg (char *, op_type *, unsigned *, int); 357static char *skip_colonthing (char *, int *); 358static char *parse_exp (char *, struct h8_op *); 359 360static int constant_fits_size_p (struct h8_op *, int, int); 361 362/* 363 parse operands 364 WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp 365 r0l,r0h,..r7l,r7h 366 @WREG 367 @WREG+ 368 @-WREG 369 #const 370 ccr 371*/ 372 373/* Try to parse a reg name. Return the number of chars consumed. */ 374 375static int 376parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) 377{ 378 char *end; 379 int len; 380 381 /* Cribbed from get_symbol_name. */ 382 if (!is_name_beginner (*src) || *src == '\001') 383 return 0; 384 end = src + 1; 385 while ((is_part_of_name (*end) && *end != '.') || *end == '\001') 386 end++; 387 len = end - src; 388 389 if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') 390 { 391 *mode = PSIZE | REG | direction; 392 *reg = 7; 393 return len; 394 } 395 if (len == 3 && 396 TOLOWER (src[0]) == 'c' && 397 TOLOWER (src[1]) == 'c' && 398 TOLOWER (src[2]) == 'r') 399 { 400 *mode = CCR; 401 *reg = 0; 402 return len; 403 } 404 if (len == 3 && 405 TOLOWER (src[0]) == 'e' && 406 TOLOWER (src[1]) == 'x' && 407 TOLOWER (src[2]) == 'r') 408 { 409 *mode = EXR; 410 *reg = 1; 411 return len; 412 } 413 if (len == 3 && 414 TOLOWER (src[0]) == 'v' && 415 TOLOWER (src[1]) == 'b' && 416 TOLOWER (src[2]) == 'r') 417 { 418 *mode = VBR; 419 *reg = 6; 420 return len; 421 } 422 if (len == 3 && 423 TOLOWER (src[0]) == 's' && 424 TOLOWER (src[1]) == 'b' && 425 TOLOWER (src[2]) == 'r') 426 { 427 *mode = SBR; 428 *reg = 7; 429 return len; 430 } 431 if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') 432 { 433 *mode = PSIZE | REG | direction; 434 *reg = 6; 435 return len; 436 } 437 if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 438 src[2] >= '0' && src[2] <= '7') 439 { 440 *mode = L_32 | REG | direction; 441 *reg = src[2] - '0'; 442 if (!Hmode) 443 as_warn (_("Reg not valid for H8/300")); 444 return len; 445 } 446 if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') 447 { 448 *mode = L_16 | REG | direction; 449 *reg = src[1] - '0' + 8; 450 if (!Hmode) 451 as_warn (_("Reg not valid for H8/300")); 452 return len; 453 } 454 455 if (TOLOWER (src[0]) == 'r') 456 { 457 if (src[1] >= '0' && src[1] <= '7') 458 { 459 if (len == 3 && TOLOWER (src[2]) == 'l') 460 { 461 *mode = L_8 | REG | direction; 462 *reg = (src[1] - '0') + 8; 463 return len; 464 } 465 if (len == 3 && TOLOWER (src[2]) == 'h') 466 { 467 *mode = L_8 | REG | direction; 468 *reg = (src[1] - '0'); 469 return len; 470 } 471 if (len == 2) 472 { 473 *mode = L_16 | REG | direction; 474 *reg = (src[1] - '0'); 475 return len; 476 } 477 } 478 } 479 480 return 0; 481} 482 483 484/* Parse an immediate or address-related constant and store it in OP. 485 If the user also specifies the operand's size, store that size 486 in OP->MODE, otherwise leave it for later code to decide. */ 487 488static char * 489parse_exp (char *src, struct h8_op *op) 490{ 491 char *save; 492 493 save = input_line_pointer; 494 input_line_pointer = src; 495 expression (&op->exp); 496 if (op->exp.X_op == O_absent) 497 as_bad (_("missing operand")); 498 src = input_line_pointer; 499 input_line_pointer = save; 500 501 return skip_colonthing (src, &op->mode); 502} 503 504 505/* If SRC starts with an explicit operand size, skip it and store the size 506 in *MODE. Leave *MODE unchanged otherwise. */ 507 508static char * 509skip_colonthing (char *src, int *mode) 510{ 511 if (*src == ':') 512 { 513 src++; 514 *mode &= ~SIZE; 515 if (src[0] == '8' && !ISDIGIT (src[1])) 516 *mode |= L_8; 517 else if (src[0] == '2' && !ISDIGIT (src[1])) 518 *mode |= L_2; 519 else if (src[0] == '3' && !ISDIGIT (src[1])) 520 *mode |= L_3; 521 else if (src[0] == '4' && !ISDIGIT (src[1])) 522 *mode |= L_4; 523 else if (src[0] == '5' && !ISDIGIT (src[1])) 524 *mode |= L_5; 525 else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) 526 *mode |= L_24; 527 else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) 528 *mode |= L_32; 529 else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) 530 *mode |= L_16; 531 else 532 as_bad (_("invalid operand size requested")); 533 534 while (ISDIGIT (*src)) 535 src++; 536 } 537 return src; 538} 539 540/* The many forms of operand: 541 542 Rn Register direct 543 @Rn Register indirect 544 @(exp[:16], Rn) Register indirect with displacement 545 @Rn+ 546 @-Rn 547 @aa:8 absolute 8 bit 548 @aa:16 absolute 16 bit 549 @aa absolute 16 bit 550 551 #xx[:size] immediate data 552 @(exp:[8], pc) pc rel 553 @@aa[:8] memory indirect. */ 554 555static int 556constant_fits_width_p (struct h8_op *operand, offsetT width) 557{ 558 offsetT num; 559 560 num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; 561 return (num & ~width) == 0 || (num | width) == ~0; 562} 563 564static int 565constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) 566{ 567 offsetT num; 568 569 if (no_symbols 570 && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) 571 return 0; 572 num = operand->exp.X_add_number & 0xffffffff; 573 switch (size) 574 { 575 case L_2: 576 return (num & ~3) == 0; 577 case L_3: 578 return (num & ~7) == 0; 579 case L_3NZ: 580 return num >= 1 && num < 8; 581 case L_4: 582 return (num & ~15) == 0; 583 case L_5: 584 return num >= 1 && num < 32; 585 case L_8: 586 num = (num ^ 0x80000000) - 0x80000000; 587 return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; 588 case L_8U: 589 return (num & ~0xFF) == 0; 590 case L_16: 591 num = (num ^ 0x80000000) - 0x80000000; 592 return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; 593 case L_16U: 594 return (num & ~0xFFFF) == 0; 595 case L_32: 596 return 1; 597 default: 598 abort (); 599 } 600} 601 602static void 603get_operand (char **ptr, struct h8_op *op, int direction) 604{ 605 char *src = *ptr; 606 op_type mode; 607 unsigned int num; 608 unsigned int len; 609 610 op->mode = 0; 611 612 /* Check for '(' and ')' for instructions ldm and stm. */ 613 if (src[0] == '(' && src[8] == ')') 614 ++ src; 615 616 /* Gross. Gross. ldm and stm have a format not easily handled 617 by get_operand. We deal with it explicitly here. */ 618 if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && 619 ISDIGIT (src[2]) && src[3] == '-' && 620 TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) 621 { 622 int low, high; 623 624 low = src[2] - '0'; 625 high = src[6] - '0'; 626 627 /* Check register pair's validity as per tech note TN-H8*-193A/E 628 from Renesas for H8S and H8SX hardware manual. */ 629 if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) 630 && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) 631 && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) 632 && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) 633 && !(low == 4 && (high == 5 || high == 6)) 634 && !(low == 4 && high == 7 && SXmode) 635 && !(low == 5 && (high == 6 || high == 7) && SXmode) 636 && !(low == 6 && high == 7 && SXmode)) 637 as_bad (_("Invalid register list for ldm/stm\n")); 638 639 /* Even sicker. We encode two registers into op->reg. One 640 for the low register to save, the other for the high 641 register to save; we also set the high bit in op->reg 642 so we know this is "very special". */ 643 op->reg = 0x80000000 | (high << 8) | low; 644 op->mode = REG; 645 if (src[7] == ')') 646 *ptr = src + 8; 647 else 648 *ptr = src + 7; 649 return; 650 } 651 652 len = parse_reg (src, &op->mode, &op->reg, direction); 653 if (len) 654 { 655 src += len; 656 if (*src == '.') 657 { 658 int size = op->mode & SIZE; 659 switch (src[1]) 660 { 661 case 'l': case 'L': 662 if (size != L_32) 663 as_warn (_("mismatch between register and suffix")); 664 op->mode = (op->mode & ~MODE) | LOWREG; 665 break; 666 case 'w': case 'W': 667 if (size != L_32 && size != L_16) 668 as_warn (_("mismatch between register and suffix")); 669 op->mode = (op->mode & ~MODE) | LOWREG; 670 op->mode = (op->mode & ~SIZE) | L_16; 671 break; 672 case 'b': case 'B': 673 op->mode = (op->mode & ~MODE) | LOWREG; 674 if (size != L_32 && size != L_8) 675 as_warn (_("mismatch between register and suffix")); 676 op->mode = (op->mode & ~MODE) | LOWREG; 677 op->mode = (op->mode & ~SIZE) | L_8; 678 break; 679 default: 680 as_warn (_("invalid suffix after register.")); 681 break; 682 } 683 src += 2; 684 } 685 *ptr = src; 686 return; 687 } 688 689 if (*src == '@') 690 { 691 src++; 692 if (*src == '@') 693 { 694 *ptr = parse_exp (src + 1, op); 695 if (op->exp.X_add_number >= 0x100) 696 { 697 int divisor = 1; 698 699 op->mode = VECIND; 700 /* FIXME : 2? or 4? */ 701 if (op->exp.X_add_number >= 0x400) 702 as_bad (_("address too high for vector table jmp/jsr")); 703 else if (op->exp.X_add_number >= 0x200) 704 divisor = 4; 705 else 706 divisor = 2; 707 708 op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; 709 } 710 else 711 op->mode = MEMIND; 712 return; 713 } 714 715 if (*src == '-' || *src == '+') 716 { 717 len = parse_reg (src + 1, &mode, &num, direction); 718 if (len == 0) 719 { 720 /* Oops, not a reg after all, must be ordinary exp. */ 721 op->mode = ABS | direction; 722 *ptr = parse_exp (src, op); 723 return; 724 } 725 726 if (((mode & SIZE) != PSIZE) 727 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 728 && (!Nmode || ((mode & SIZE) != L_32))) 729 as_bad (_("Wrong size pointer register for architecture.")); 730 731 op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; 732 op->reg = num; 733 *ptr = src + 1 + len; 734 return; 735 } 736 if (*src == '(') 737 { 738 src++; 739 740 /* See if this is @(ERn.x, PC). */ 741 len = parse_reg (src, &mode, &op->reg, direction); 742 if (len != 0 && (mode & MODE) == REG && src[len] == '.') 743 { 744 switch (TOLOWER (src[len + 1])) 745 { 746 case 'b': 747 mode = PCIDXB | direction; 748 break; 749 case 'w': 750 mode = PCIDXW | direction; 751 break; 752 case 'l': 753 mode = PCIDXL | direction; 754 break; 755 default: 756 mode = 0; 757 break; 758 } 759 if (mode 760 && src[len + 2] == ',' 761 && TOLOWER (src[len + 3]) != 'p' 762 && TOLOWER (src[len + 4]) != 'c' 763 && src[len + 5] != ')') 764 { 765 *ptr = src + len + 6; 766 op->mode |= mode; 767 return; 768 } 769 /* Fall through into disp case - the grammar is somewhat 770 ambiguous, so we should try whether it's a DISP operand 771 after all ("ER3.L" might be a poorly named label...). */ 772 } 773 774 /* Disp. */ 775 776 /* Start off assuming a 16 bit offset. */ 777 778 src = parse_exp (src, op); 779 if (*src == ')') 780 { 781 op->mode |= ABS | direction; 782 *ptr = src + 1; 783 return; 784 } 785 786 if (*src != ',') 787 { 788 as_bad (_("expected @(exp, reg16)")); 789 return; 790 } 791 src++; 792 793 len = parse_reg (src, &mode, &op->reg, direction); 794 if (len == 0 || (mode & MODE) != REG) 795 { 796 as_bad (_("expected @(exp, reg16)")); 797 return; 798 } 799 src += len; 800 if (src[0] == '.') 801 { 802 switch (TOLOWER (src[1])) 803 { 804 case 'b': 805 op->mode |= INDEXB | direction; 806 break; 807 case 'w': 808 op->mode |= INDEXW | direction; 809 break; 810 case 'l': 811 op->mode |= INDEXL | direction; 812 break; 813 default: 814 as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); 815 } 816 src += 2; 817 op->reg &= 7; 818 } 819 else 820 op->mode |= DISP | direction; 821 src = skip_colonthing (src, &op->mode); 822 823 if (*src != ')') 824 { 825 as_bad (_("expected @(exp, reg16)")); 826 return; 827 } 828 *ptr = src + 1; 829 return; 830 } 831 len = parse_reg (src, &mode, &num, direction); 832 833 if (len) 834 { 835 src += len; 836 if (*src == '+' || *src == '-') 837 { 838 if (((mode & SIZE) != PSIZE) 839 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 840 && (!Nmode || ((mode & SIZE) != L_32))) 841 as_bad (_("Wrong size pointer register for architecture.")); 842 op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; 843 op->reg = num; 844 src++; 845 *ptr = src; 846 return; 847 } 848 if (((mode & SIZE) != PSIZE) 849 /* For Normal mode accept 16 bit and 32 bit pointer registers. */ 850 && (!Nmode || ((mode & SIZE) != L_32))) 851 as_bad (_("Wrong size pointer register for architecture.")); 852 853 op->mode = direction | IND | PSIZE; 854 op->reg = num; 855 *ptr = src; 856 857 return; 858 } 859 else 860 { 861 /* must be a symbol */ 862 863 op->mode = ABS | direction; 864 *ptr = parse_exp (src, op); 865 return; 866 } 867 } 868 869 if (*src == '#') 870 { 871 op->mode = IMM; 872 *ptr = parse_exp (src + 1, op); 873 return; 874 } 875 else if (strncmp (src, "mach", 4) == 0 || 876 strncmp (src, "macl", 4) == 0 || 877 strncmp (src, "MACH", 4) == 0 || 878 strncmp (src, "MACL", 4) == 0) 879 { 880 op->reg = TOLOWER (src[3]) == 'l'; 881 op->mode = MACREG; 882 *ptr = src + 4; 883 return; 884 } 885 else 886 { 887 op->mode = PCREL; 888 *ptr = parse_exp (src, op); 889 } 890} 891 892static char * 893get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) 894{ 895 char *ptr = op_end; 896 897 switch (noperands) 898 { 899 case 0: 900 break; 901 902 case 1: 903 ptr++; 904 get_operand (&ptr, operand + 0, SRC); 905 if (*ptr == ',') 906 { 907 ptr++; 908 get_operand (&ptr, operand + 1, DST); 909 } 910 break; 911 912 case 2: 913 ptr++; 914 get_operand (&ptr, operand + 0, SRC); 915 if (*ptr == ',') 916 ptr++; 917 get_operand (&ptr, operand + 1, DST); 918 break; 919 920 case 3: 921 ptr++; 922 get_operand (&ptr, operand + 0, SRC); 923 if (*ptr == ',') 924 ptr++; 925 get_operand (&ptr, operand + 1, DST); 926 if (*ptr == ',') 927 ptr++; 928 get_operand (&ptr, operand + 2, OP3); 929 break; 930 931 default: 932 abort (); 933 } 934 935 return ptr; 936} 937 938/* MOVA has special requirements. Rather than adding twice the amount of 939 addressing modes, we simply special case it a bit. */ 940static void 941get_mova_operands (char *op_end, struct h8_op *operand) 942{ 943 char *ptr = op_end; 944 945 if (ptr[1] != '@' || ptr[2] != '(') 946 goto error; 947 ptr += 3; 948 operand[0].mode = 0; 949 ptr = parse_exp (ptr, &operand[0]); 950 951 if (*ptr !=',') 952 goto error; 953 ptr++; 954 get_operand (&ptr, operand + 1, DST); 955 956 if (*ptr =='.') 957 { 958 ptr++; 959 switch (*ptr++) 960 { 961 case 'b': case 'B': 962 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 963 break; 964 case 'w': case 'W': 965 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 966 break; 967 case 'l': case 'L': 968 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 969 break; 970 default: 971 goto error; 972 } 973 } 974 else if ((operand[1].mode & MODE) == LOWREG) 975 { 976 switch (operand[1].mode & SIZE) 977 { 978 case L_8: 979 operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; 980 break; 981 case L_16: 982 operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; 983 break; 984 case L_32: 985 operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; 986 break; 987 default: 988 goto error; 989 } 990 } 991 else 992 goto error; 993 994 if (*ptr++ != ')' || *ptr++ != ',') 995 goto error; 996 get_operand (&ptr, operand + 2, OP3); 997 /* See if we can use the short form of MOVA. */ 998 if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) 999 && (operand[2].mode & MODE) == REG 1000 && (operand[1].reg & 7) == (operand[2].reg & 7)) 1001 { 1002 operand[1].mode = operand[2].mode = 0; 1003 operand[0].reg = operand[2].reg & 7; 1004 } 1005 return; 1006 1007 error: 1008 as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); 1009} 1010 1011static void 1012get_rtsl_operands (char *ptr, struct h8_op *operand) 1013{ 1014 int mode, len, type = 0; 1015 unsigned int num, num2; 1016 1017 ptr++; 1018 if (*ptr == '(') 1019 { 1020 ptr++; 1021 type = 1; 1022 } 1023 len = parse_reg (ptr, &mode, &num, SRC); 1024 if (len == 0 || (mode & MODE) != REG) 1025 { 1026 as_bad (_("expected register")); 1027 return; 1028 } 1029 ptr += len; 1030 if (*ptr == '-') 1031 { 1032 len = parse_reg (++ptr, &mode, &num2, SRC); 1033 if (len == 0 || (mode & MODE) != REG) 1034 { 1035 as_bad (_("expected register")); 1036 return; 1037 } 1038 ptr += len; 1039 /* CONST_xxx are used as placeholders in the opcode table. */ 1040 num = num2 - num; 1041 if (num > 3) 1042 { 1043 as_bad (_("invalid register list")); 1044 return; 1045 } 1046 } 1047 else 1048 num2 = num, num = 0; 1049 if (type == 1 && *ptr++ != ')') 1050 { 1051 as_bad (_("expected closing paren")); 1052 return; 1053 } 1054 operand[0].mode = RS32; 1055 operand[1].mode = RD32; 1056 operand[0].reg = num; 1057 operand[1].reg = num2; 1058} 1059 1060/* Passed a pointer to a list of opcodes which use different 1061 addressing modes, return the opcode which matches the opcodes 1062 provided. */ 1063 1064static const struct h8_instruction * 1065get_specific (const struct h8_instruction *instruction, 1066 struct h8_op *operands, int size) 1067{ 1068 const struct h8_instruction *this_try = instruction; 1069 const struct h8_instruction *found_other = 0, *found_mismatched = 0; 1070 int found = 0; 1071 int this_index = instruction->idx; 1072 int noperands = 0; 1073 1074 /* There's only one ldm/stm and it's easier to just 1075 get out quick for them. */ 1076 if (OP_KIND (instruction->opcode->how) == O_LDM 1077 || OP_KIND (instruction->opcode->how) == O_STM) 1078 return this_try; 1079 1080 while (noperands < 3 && operands[noperands].mode != 0) 1081 noperands++; 1082 1083 while (this_index == instruction->idx && !found) 1084 { 1085 int this_size; 1086 1087 found = 1; 1088 this_try = instruction++; 1089 this_size = this_try->opcode->how & SN; 1090 1091 if (this_try->noperands != noperands) 1092 found = 0; 1093 else if (this_try->noperands > 0) 1094 { 1095 int i; 1096 1097 for (i = 0; i < this_try->noperands && found; i++) 1098 { 1099 op_type op = this_try->opcode->args.nib[i]; 1100 int op_mode = op & MODE; 1101 int op_size = op & SIZE; 1102 int x = operands[i].mode; 1103 int x_mode = x & MODE; 1104 int x_size = x & SIZE; 1105 1106 if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) 1107 { 1108 if ((x_size == L_8 && (operands[i].reg & 8) == 0) 1109 || (x_size == L_16 && (operands[i].reg & 8) == 8)) 1110 as_warn (_("can't use high part of register in operand %d"), i); 1111 1112 if (x_size != op_size) 1113 found = 0; 1114 } 1115 else if (op_mode == REG) 1116 { 1117 if (x_mode == LOWREG) 1118 x_mode = REG; 1119 if (x_mode != REG) 1120 found = 0; 1121 1122 if (x_size == L_P) 1123 x_size = (Hmode ? L_32 : L_16); 1124 if (op_size == L_P) 1125 op_size = (Hmode ? L_32 : L_16); 1126 1127 /* The size of the reg is v important. */ 1128 if (op_size != x_size) 1129 found = 0; 1130 } 1131 else if (op_mode & CTRL) /* control register */ 1132 { 1133 if (!(x_mode & CTRL)) 1134 found = 0; 1135 1136 switch (x_mode) 1137 { 1138 case CCR: 1139 if (op_mode != CCR && 1140 op_mode != CCR_EXR && 1141 op_mode != CC_EX_VB_SB) 1142 found = 0; 1143 break; 1144 case EXR: 1145 if (op_mode != EXR && 1146 op_mode != CCR_EXR && 1147 op_mode != CC_EX_VB_SB) 1148 found = 0; 1149 break; 1150 case MACH: 1151 if (op_mode != MACH && 1152 op_mode != MACREG) 1153 found = 0; 1154 break; 1155 case MACL: 1156 if (op_mode != MACL && 1157 op_mode != MACREG) 1158 found = 0; 1159 break; 1160 case VBR: 1161 if (op_mode != VBR && 1162 op_mode != VBR_SBR && 1163 op_mode != CC_EX_VB_SB) 1164 found = 0; 1165 break; 1166 case SBR: 1167 if (op_mode != SBR && 1168 op_mode != VBR_SBR && 1169 op_mode != CC_EX_VB_SB) 1170 found = 0; 1171 break; 1172 } 1173 } 1174 else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) 1175 { 1176 operands[i].mode &= ~MODE; 1177 operands[i].mode |= ABSJMP; 1178 /* But it may not be 24 bits long. */ 1179 if (x_mode == ABS && !Hmode) 1180 { 1181 operands[i].mode &= ~SIZE; 1182 operands[i].mode |= L_16; 1183 } 1184 if ((operands[i].mode & SIZE) == L_32 1185 && (op_mode & SIZE) != L_32) 1186 found = 0; 1187 } 1188 else if (x_mode == IMM && op_mode != IMM) 1189 { 1190 offsetT num = operands[i].exp.X_add_number & 0xffffffff; 1191 if (op_mode == KBIT || op_mode == DBIT) 1192 /* This is ok if the immediate value is sensible. */; 1193 else if (op_mode == CONST_2) 1194 found = num == 2; 1195 else if (op_mode == CONST_4) 1196 found = num == 4; 1197 else if (op_mode == CONST_8) 1198 found = num == 8; 1199 else if (op_mode == CONST_16) 1200 found = num == 16; 1201 else 1202 found = 0; 1203 } 1204 else if (op_mode == PCREL && op_mode == x_mode) 1205 { 1206 /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: 1207 If x_size is L_8, promote it. */ 1208 if (OP_KIND (this_try->opcode->how) == O_MOVSD 1209 || OP_KIND (this_try->opcode->how) == O_BSRBC 1210 || OP_KIND (this_try->opcode->how) == O_BSRBS) 1211 if (x_size == L_8) 1212 x_size = L_16; 1213 1214 /* The size of the displacement is important. */ 1215 if (op_size != x_size) 1216 found = 0; 1217 } 1218 else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS 1219 || op_mode == INDEXB || op_mode == INDEXW 1220 || op_mode == INDEXL) 1221 && op_mode == x_mode) 1222 { 1223 /* Promote a L_24 to L_32 if it makes us match. */ 1224 if (x_size == L_24 && op_size == L_32) 1225 { 1226 x &= ~SIZE; 1227 x |= x_size = L_32; 1228 } 1229 1230 if (((x_size == L_16 && op_size == L_16U) 1231 || (x_size == L_8 && op_size == L_8U) 1232 || (x_size == L_3 && op_size == L_3NZ)) 1233 /* We're deliberately more permissive for ABS modes. */ 1234 && (op_mode == ABS 1235 || constant_fits_size_p (operands + i, op_size, 1236 op & NO_SYMBOLS))) 1237 x_size = op_size; 1238 1239 if (x_size != 0 && op_size != x_size) 1240 found = 0; 1241 else if (x_size == 0 1242 && ! constant_fits_size_p (operands + i, op_size, 1243 op & NO_SYMBOLS)) 1244 found = 0; 1245 } 1246 else if (op_mode != x_mode) 1247 { 1248 found = 0; 1249 } 1250 } 1251 } 1252 if (found) 1253 { 1254 if ((this_try->opcode->available == AV_H8SX && ! SXmode) 1255 || (this_try->opcode->available == AV_H8S && ! Smode) 1256 || (this_try->opcode->available == AV_H8H && ! Hmode)) 1257 found = 0, found_other = this_try; 1258 else if (this_size != size && (this_size != SN && size != SN)) 1259 found_mismatched = this_try, found = 0; 1260 1261 } 1262 } 1263 if (found) 1264 return this_try; 1265 if (found_other) 1266 { 1267 as_warn (_("Opcode `%s' with these operand types not available in %s mode"), 1268 found_other->opcode->name, 1269 (! Hmode && ! Smode ? "H8/300" 1270 : SXmode ? "H8sx" 1271 : Smode ? "H8/300S" 1272 : "H8/300H")); 1273 } 1274 else if (found_mismatched) 1275 { 1276 as_warn (_("mismatch between opcode size and operand size")); 1277 return found_mismatched; 1278 } 1279 return 0; 1280} 1281 1282static void 1283check_operand (struct h8_op *operand, unsigned int width, const char *string) 1284{ 1285 if (operand->exp.X_add_symbol == 0 1286 && operand->exp.X_op_symbol == 0) 1287 { 1288 /* No symbol involved, let's look at offset, it's dangerous if 1289 any of the high bits are not 0 or ff's, find out by oring or 1290 anding with the width and seeing if the answer is 0 or all 1291 fs. */ 1292 1293 if (! constant_fits_width_p (operand, width)) 1294 { 1295 if (width == 255 1296 && (operand->exp.X_add_number & 0xff00) == 0xff00) 1297 { 1298 /* Just ignore this one - which happens when trying to 1299 fit a 16 bit address truncated into an 8 bit address 1300 of something like bset. */ 1301 } 1302 else if (strcmp (string, "@") == 0 1303 && width == 0xffff 1304 && (operand->exp.X_add_number & 0xff8000) == 0xff8000) 1305 { 1306 /* Just ignore this one - which happens when trying to 1307 fit a 24 bit address truncated into a 16 bit address 1308 of something like mov.w. */ 1309 } 1310 else 1311 { 1312 as_warn (_("operand %s0x%lx out of range."), string, 1313 (unsigned long) operand->exp.X_add_number); 1314 } 1315 } 1316 } 1317} 1318 1319/* RELAXMODE has one of 3 values: 1320 1321 0 Output a "normal" reloc, no relaxing possible for this insn/reloc 1322 1323 1 Output a relaxable 24bit absolute mov.w address relocation 1324 (may relax into a 16bit absolute address). 1325 1326 2 Output a relaxable 16/24 absolute mov.b address relocation 1327 (may relax into an 8bit absolute address). */ 1328 1329static void 1330do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) 1331{ 1332 int idx; 1333 int size; 1334 int where; 1335 char *bytes = frag_now->fr_literal + offset; 1336 1337 const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; 1338 1339 if (operand->exp.X_add_symbol == 0) 1340 { 1341 switch (operand->mode & SIZE) 1342 { 1343 case L_2: 1344 check_operand (operand, 0x3, t); 1345 bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); 1346 break; 1347 case L_3: 1348 case L_3NZ: 1349 check_operand (operand, 0x7, t); 1350 bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); 1351 break; 1352 case L_4: 1353 check_operand (operand, 0xF, t); 1354 bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); 1355 break; 1356 case L_5: 1357 check_operand (operand, 0x1F, t); 1358 bytes[0] |= operand->exp.X_add_number & 31; 1359 break; 1360 case L_8: 1361 case L_8U: 1362 check_operand (operand, 0xff, t); 1363 bytes[0] |= operand->exp.X_add_number; 1364 break; 1365 case L_16: 1366 case L_16U: 1367 check_operand (operand, 0xffff, t); 1368 bytes[0] |= operand->exp.X_add_number >> 8; 1369 bytes[1] |= operand->exp.X_add_number >> 0; 1370 /* MOVA needs both relocs to relax the second operand properly. */ 1371 if (relaxmode != 0 1372 && (OP_KIND(this_try->opcode->how) == O_MOVAB 1373 || OP_KIND(this_try->opcode->how) == O_MOVAW 1374 || OP_KIND(this_try->opcode->how) == O_MOVAL)) 1375 { 1376 idx = BFD_RELOC_16; 1377 fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); 1378 } 1379 break; 1380 case L_24: 1381 check_operand (operand, 0xffffff, t); 1382 bytes[0] |= operand->exp.X_add_number >> 16; 1383 bytes[1] |= operand->exp.X_add_number >> 8; 1384 bytes[2] |= operand->exp.X_add_number >> 0; 1385 break; 1386 1387 case L_32: 1388 /* This should be done with bfd. */ 1389 bytes[0] |= operand->exp.X_add_number >> 24; 1390 bytes[1] |= operand->exp.X_add_number >> 16; 1391 bytes[2] |= operand->exp.X_add_number >> 8; 1392 bytes[3] |= operand->exp.X_add_number >> 0; 1393 if (relaxmode != 0) 1394 { 1395 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1396 idx = BFD_RELOC_H8_DISP32A16; 1397 else 1398 idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; 1399 fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); 1400 } 1401 break; 1402 } 1403 } 1404 else 1405 { 1406 switch (operand->mode & SIZE) 1407 { 1408 case L_24: 1409 case L_32: 1410 size = 4; 1411 where = (operand->mode & SIZE) == L_24 ? -1 : 0; 1412 if ((operand->mode & MODE) == DISP && relaxmode == 1) 1413 idx = BFD_RELOC_H8_DISP32A16; 1414 else if (relaxmode == 2) 1415 idx = R_MOV24B1; 1416 else if (relaxmode == 1) 1417 idx = R_MOVL1; 1418 else 1419 idx = R_RELLONG; 1420 break; 1421 default: 1422 as_bad (_("Can't work out size of operand.\n")); 1423 /* Fall through. */ 1424 case L_16: 1425 case L_16U: 1426 size = 2; 1427 where = 0; 1428 if (relaxmode == 2) 1429 idx = R_MOV16B1; 1430 else 1431 idx = R_RELWORD; 1432 operand->exp.X_add_number = 1433 ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1434 operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; 1435 break; 1436 case L_8: 1437 size = 1; 1438 where = 0; 1439 idx = R_RELBYTE; 1440 operand->exp.X_add_number = 1441 ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1442 operand->exp.X_add_number |= bytes[0]; 1443 } 1444 1445 fix_new_exp (frag_now, 1446 offset + where, 1447 size, 1448 &operand->exp, 1449 0, 1450 idx); 1451 } 1452} 1453 1454/* Now we know what sort of opcodes it is, let's build the bytes. */ 1455 1456static void 1457build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) 1458{ 1459 int i; 1460 char *output = frag_more (this_try->length); 1461 const op_type *nibble_ptr = this_try->opcode->data.nib; 1462 op_type c; 1463 unsigned int nibble_count = 0; 1464 int op_at[3]; 1465 int nib = 0; 1466 int movb = 0; 1467 char asnibbles[100]; 1468 char *p = asnibbles; 1469 int high, low; 1470 1471 if (!Hmode && this_try->opcode->available != AV_H8) 1472 as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), 1473 this_try->opcode->name); 1474 else if (!Smode 1475 && this_try->opcode->available != AV_H8 1476 && this_try->opcode->available != AV_H8H) 1477 as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), 1478 this_try->opcode->name); 1479 else if (!SXmode 1480 && this_try->opcode->available != AV_H8 1481 && this_try->opcode->available != AV_H8H 1482 && this_try->opcode->available != AV_H8S) 1483 as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), 1484 this_try->opcode->name); 1485 1486 while (*nibble_ptr != (op_type) E) 1487 { 1488 int d; 1489 1490 nib = 0; 1491 c = *nibble_ptr++; 1492 1493 d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; 1494 1495 if (c < 16) 1496 nib = c; 1497 else 1498 { 1499 int c2 = c & MODE; 1500 1501 if (c2 == REG || c2 == LOWREG 1502 || c2 == IND || c2 == PREINC || c2 == PREDEC 1503 || c2 == POSTINC || c2 == POSTDEC) 1504 { 1505 nib = operand[d].reg; 1506 if (c2 == LOWREG) 1507 nib &= 7; 1508 } 1509 1510 else if (c & CTRL) /* Control reg operand. */ 1511 nib = operand[d].reg; 1512 1513 else if ((c & DISPREG) == (DISPREG)) 1514 { 1515 nib = operand[d].reg; 1516 } 1517 else if (c2 == ABS) 1518 { 1519 operand[d].mode = c; 1520 op_at[d] = nibble_count; 1521 nib = 0; 1522 } 1523 else if (c2 == IMM || c2 == PCREL || c2 == ABS 1524 || (c & ABSJMP) || c2 == DISP) 1525 { 1526 operand[d].mode = c; 1527 op_at[d] = nibble_count; 1528 nib = 0; 1529 } 1530 else if ((c & IGNORE) || (c & DATA)) 1531 nib = 0; 1532 1533 else if (c2 == DBIT) 1534 { 1535 switch (operand[0].exp.X_add_number) 1536 { 1537 case 1: 1538 nib = c; 1539 break; 1540 case 2: 1541 nib = 0x8 | c; 1542 break; 1543 default: 1544 as_bad (_("Need #1 or #2 here")); 1545 } 1546 } 1547 else if (c2 == KBIT) 1548 { 1549 switch (operand[0].exp.X_add_number) 1550 { 1551 case 1: 1552 nib = 0; 1553 break; 1554 case 2: 1555 nib = 8; 1556 break; 1557 case 4: 1558 if (!Hmode) 1559 as_warn (_("#4 not valid on H8/300.")); 1560 nib = 9; 1561 break; 1562 1563 default: 1564 as_bad (_("Need #1 or #2 here")); 1565 break; 1566 } 1567 /* Stop it making a fix. */ 1568 operand[0].mode = 0; 1569 } 1570 1571 if (c & MEMRELAX) 1572 operand[d].mode |= MEMRELAX; 1573 1574 if (c & B31) 1575 nib |= 0x8; 1576 1577 if (c & B21) 1578 nib |= 0x4; 1579 1580 if (c & B11) 1581 nib |= 0x2; 1582 1583 if (c & B01) 1584 nib |= 0x1; 1585 1586 if (c2 == MACREG) 1587 { 1588 if (operand[0].mode == MACREG) 1589 /* stmac has mac[hl] as the first operand. */ 1590 nib = 2 + operand[0].reg; 1591 else 1592 /* ldmac has mac[hl] as the second operand. */ 1593 nib = 2 + operand[1].reg; 1594 } 1595 } 1596 nibble_count++; 1597 1598 *p++ = nib; 1599 } 1600 1601 /* Disgusting. Why, oh why didn't someone ask us for advice 1602 on the assembler format. */ 1603 if (OP_KIND (this_try->opcode->how) == O_LDM) 1604 { 1605 high = (operand[1].reg >> 8) & 0xf; 1606 low = (operand[1].reg) & 0xf; 1607 asnibbles[2] = high - low; 1608 asnibbles[7] = high; 1609 } 1610 else if (OP_KIND (this_try->opcode->how) == O_STM) 1611 { 1612 high = (operand[0].reg >> 8) & 0xf; 1613 low = (operand[0].reg) & 0xf; 1614 asnibbles[2] = high - low; 1615 asnibbles[7] = low; 1616 } 1617 1618 for (i = 0; i < this_try->length; i++) 1619 output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; 1620 1621 /* Note if this is a mov.b or a bit manipulation instruction 1622 there is a special relaxation which only applies. */ 1623 if ( this_try->opcode->how == O (O_MOV, SB) 1624 || this_try->opcode->how == O (O_BCLR, SB) 1625 || this_try->opcode->how == O (O_BAND, SB) 1626 || this_try->opcode->how == O (O_BIAND, SB) 1627 || this_try->opcode->how == O (O_BILD, SB) 1628 || this_try->opcode->how == O (O_BIOR, SB) 1629 || this_try->opcode->how == O (O_BIST, SB) 1630 || this_try->opcode->how == O (O_BIXOR, SB) 1631 || this_try->opcode->how == O (O_BLD, SB) 1632 || this_try->opcode->how == O (O_BNOT, SB) 1633 || this_try->opcode->how == O (O_BOR, SB) 1634 || this_try->opcode->how == O (O_BSET, SB) 1635 || this_try->opcode->how == O (O_BST, SB) 1636 || this_try->opcode->how == O (O_BTST, SB) 1637 || this_try->opcode->how == O (O_BXOR, SB)) 1638 movb = 1; 1639 1640 /* Output any fixes. */ 1641 for (i = 0; i < this_try->noperands; i++) 1642 { 1643 int x = operand[i].mode; 1644 int x_mode = x & MODE; 1645 1646 if (x_mode == IMM || x_mode == DISP) 1647 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1648 op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, 1649 this_try); 1650 else if (x_mode == ABS) 1651 do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, 1652 op_at[i] & 1, operand + i, 1653 (x & MEMRELAX) ? movb + 1 : 0, 1654 this_try); 1655 1656 else if (x_mode == PCREL) 1657 { 1658 int size16 = (x & SIZE) == L_16; 1659 int size = size16 ? 2 : 1; 1660 int type = size16 ? R_PCRWORD : R_PCRBYTE; 1661 fixS *fixP; 1662 1663 check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); 1664 1665 if (operand[i].exp.X_add_number & 1) 1666 as_warn (_("branch operand has odd offset (%lx)\n"), 1667 (unsigned long) operand->exp.X_add_number); 1668 if (size16) 1669 { 1670 operand[i].exp.X_add_number = 1671 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1672 } 1673 else 1674 { 1675 operand[i].exp.X_add_number = 1676 ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; 1677 } 1678 1679 /* For BRA/S. */ 1680 if (! size16) 1681 operand[i].exp.X_add_number |= output[op_at[i] / 2]; 1682 1683 fixP = fix_new_exp (frag_now, 1684 output - frag_now->fr_literal + op_at[i] / 2, 1685 size, 1686 &operand[i].exp, 1687 1, 1688 type); 1689 fixP->fx_signed = 1; 1690 } 1691 else if (x_mode == MEMIND) 1692 { 1693 check_operand (operand + i, 0xff, "@@"); 1694 fix_new_exp (frag_now, 1695 output - frag_now->fr_literal + 1, 1696 1, 1697 &operand[i].exp, 1698 0, 1699 R_MEM_INDIRECT); 1700 } 1701 else if (x_mode == VECIND) 1702 { 1703 check_operand (operand + i, 0x7f, "@@"); 1704 /* FIXME: approximating the effect of "B31" here... 1705 This is very hackish, and ought to be done a better way. */ 1706 operand[i].exp.X_add_number |= 0x80; 1707 fix_new_exp (frag_now, 1708 output - frag_now->fr_literal + 1, 1709 1, 1710 &operand[i].exp, 1711 0, 1712 R_MEM_INDIRECT); 1713 } 1714 else if (x & ABSJMP) 1715 { 1716 int where = 0; 1717 bfd_reloc_code_real_type reloc_type = R_JMPL1; 1718 1719 /* To be compatible with the proposed H8 ELF format, we 1720 want the relocation's offset to point to the first byte 1721 that will be modified, not to the start of the instruction. */ 1722 1723 if ((operand->mode & SIZE) == L_32) 1724 { 1725 where = 2; 1726 reloc_type = R_RELLONG; 1727 } 1728 else 1729 where = 1; 1730 1731 /* This jmp may be a jump or a branch. */ 1732 1733 check_operand (operand + i, 1734 SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, 1735 "@"); 1736 1737 if (operand[i].exp.X_add_number & 1) 1738 as_warn (_("branch operand has odd offset (%lx)\n"), 1739 (unsigned long) operand->exp.X_add_number); 1740 1741 if (!Hmode) 1742 operand[i].exp.X_add_number = 1743 ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; 1744 fix_new_exp (frag_now, 1745 output - frag_now->fr_literal + where, 1746 4, 1747 &operand[i].exp, 1748 0, 1749 reloc_type); 1750 } 1751 } 1752} 1753 1754/* Try to give an intelligent error message for common and simple to 1755 detect errors. */ 1756 1757static void 1758clever_message (const struct h8_instruction *instruction, 1759 struct h8_op *operand) 1760{ 1761 /* Find out if there was more than one possible opcode. */ 1762 1763 if ((instruction + 1)->idx != instruction->idx) 1764 { 1765 int argn; 1766 1767 /* Only one opcode of this flavour, try to guess which operand 1768 didn't match. */ 1769 for (argn = 0; argn < instruction->noperands; argn++) 1770 { 1771 switch (instruction->opcode->args.nib[argn]) 1772 { 1773 case RD16: 1774 if (operand[argn].mode != RD16) 1775 { 1776 as_bad (_("destination operand must be 16 bit register")); 1777 return; 1778 1779 } 1780 break; 1781 1782 case RS8: 1783 if (operand[argn].mode != RS8) 1784 { 1785 as_bad (_("source operand must be 8 bit register")); 1786 return; 1787 } 1788 break; 1789 1790 case ABS16DST: 1791 if (operand[argn].mode != ABS16DST) 1792 { 1793 as_bad (_("destination operand must be 16bit absolute address")); 1794 return; 1795 } 1796 break; 1797 case RD8: 1798 if (operand[argn].mode != RD8) 1799 { 1800 as_bad (_("destination operand must be 8 bit register")); 1801 return; 1802 } 1803 break; 1804 1805 case ABS16SRC: 1806 if (operand[argn].mode != ABS16SRC) 1807 { 1808 as_bad (_("source operand must be 16bit absolute address")); 1809 return; 1810 } 1811 break; 1812 1813 } 1814 } 1815 } 1816 as_bad (_("invalid operands")); 1817} 1818 1819 1820/* If OPERAND is part of an address, adjust its size and value given 1821 that it addresses SIZE bytes. 1822 1823 This function decides how big non-immediate constants are when no 1824 size was explicitly given. It also scales down the assembly-level 1825 displacement in an @(d:2,ERn) operand. */ 1826 1827static void 1828fix_operand_size (struct h8_op *operand, int size) 1829{ 1830 if (SXmode && (operand->mode & MODE) == DISP) 1831 { 1832 /* If the user didn't specify an operand width, see if we 1833 can use @(d:2,ERn). */ 1834 if ((operand->mode & SIZE) == 0 1835 && operand->exp.X_add_symbol == 0 1836 && operand->exp.X_op_symbol == 0 1837 && (operand->exp.X_add_number == size 1838 || operand->exp.X_add_number == size * 2 1839 || operand->exp.X_add_number == size * 3)) 1840 operand->mode |= L_2; 1841 1842 /* Scale down the displacement in an @(d:2,ERn) operand. 1843 X_add_number then contains the desired field value. */ 1844 if ((operand->mode & SIZE) == L_2) 1845 { 1846 if (operand->exp.X_add_number % size != 0) 1847 as_warn (_("operand/size mis-match")); 1848 operand->exp.X_add_number /= size; 1849 } 1850 } 1851 1852 if ((operand->mode & SIZE) == 0) 1853 switch (operand->mode & MODE) 1854 { 1855 case DISP: 1856 case INDEXB: 1857 case INDEXW: 1858 case INDEXL: 1859 case ABS: 1860 /* Pick a 24-bit address unless we know that a 16-bit address 1861 is safe. get_specific() will relax L_24 into L_32 where 1862 necessary. */ 1863 if (Hmode 1864 && !Nmode 1865 && ((((addressT) operand->exp.X_add_number + 0x8000) 1866 & 0xffffffff) > 0xffff 1867 || operand->exp.X_add_symbol != 0 1868 || operand->exp.X_op_symbol != 0)) 1869 operand->mode |= L_24; 1870 else 1871 operand->mode |= L_16; 1872 break; 1873 1874 case PCREL: 1875 if ((((addressT) operand->exp.X_add_number + 0x80) 1876 & 0xffffffff) <= 0xff) 1877 { 1878 if (operand->exp.X_add_symbol != NULL) 1879 operand->mode |= bsize; 1880 else 1881 operand->mode |= L_8; 1882 } 1883 else 1884 operand->mode |= L_16; 1885 break; 1886 } 1887} 1888 1889 1890/* This is the guts of the machine-dependent assembler. STR points to 1891 a machine dependent instruction. This function is supposed to emit 1892 the frags/bytes it assembles. */ 1893 1894void 1895md_assemble (char *str) 1896{ 1897 char *op_start; 1898 char *op_end; 1899 struct h8_op operand[3]; 1900 const struct h8_instruction *instruction; 1901 const struct h8_instruction *prev_instruction; 1902 1903 char *dot = 0; 1904 char *slash = 0; 1905 char c; 1906 int size, i; 1907 1908 /* Drop leading whitespace. */ 1909 while (*str == ' ') 1910 str++; 1911 1912 /* Find the op code end. */ 1913 for (op_start = op_end = str; 1914 *op_end != 0 && *op_end != ' '; 1915 op_end++) 1916 { 1917 if (*op_end == '.') 1918 { 1919 dot = op_end + 1; 1920 *op_end = 0; 1921 op_end += 2; 1922 break; 1923 } 1924 else if (*op_end == '/' && ! slash) 1925 slash = op_end; 1926 } 1927 1928 if (op_end == op_start) 1929 { 1930 as_bad (_("can't find opcode ")); 1931 } 1932 c = *op_end; 1933 1934 *op_end = 0; 1935 1936 /* The assembler stops scanning the opcode at slashes, so it fails 1937 to make characters following them lower case. Fix them. */ 1938 if (slash) 1939 while (*++slash) 1940 *slash = TOLOWER (*slash); 1941 1942 instruction = (const struct h8_instruction *) 1943 str_hash_find (opcode_hash_control, op_start); 1944 1945 if (instruction == NULL) 1946 { 1947 as_bad (_("unknown opcode")); 1948 return; 1949 } 1950 1951 /* We used to set input_line_pointer to the result of get_operands, 1952 but that is wrong. Our caller assumes we don't change it. */ 1953 1954 operand[0].mode = 0; 1955 operand[1].mode = 0; 1956 operand[2].mode = 0; 1957 1958 if (OP_KIND (instruction->opcode->how) == O_MOVAB 1959 || OP_KIND (instruction->opcode->how) == O_MOVAW 1960 || OP_KIND (instruction->opcode->how) == O_MOVAL) 1961 get_mova_operands (op_end, operand); 1962 else if (OP_KIND (instruction->opcode->how) == O_RTEL 1963 || OP_KIND (instruction->opcode->how) == O_RTSL) 1964 get_rtsl_operands (op_end, operand); 1965 else 1966 get_operands (instruction->noperands, op_end, operand); 1967 1968 *op_end = c; 1969 prev_instruction = instruction; 1970 1971 /* Now we have operands from instruction. 1972 Let's check them out for ldm and stm. */ 1973 if (OP_KIND (instruction->opcode->how) == O_LDM) 1974 { 1975 /* The first operand must be @er7+, and the 1976 second operand must be a register pair. */ 1977 if ((operand[0].mode != RSINC) 1978 || (operand[0].reg != 7) 1979 || ((operand[1].reg & 0x80000000) == 0)) 1980 as_bad (_("invalid operand in ldm")); 1981 } 1982 else if (OP_KIND (instruction->opcode->how) == O_STM) 1983 { 1984 /* The first operand must be a register pair, 1985 and the second operand must be @-er7. */ 1986 if (((operand[0].reg & 0x80000000) == 0) 1987 || (operand[1].mode != RDDEC) 1988 || (operand[1].reg != 7)) 1989 as_bad (_("invalid operand in stm")); 1990 } 1991 1992 size = SN; 1993 if (dot) 1994 { 1995 switch (TOLOWER (*dot)) 1996 { 1997 case 'b': 1998 size = SB; 1999 break; 2000 2001 case 'w': 2002 size = SW; 2003 break; 2004 2005 case 'l': 2006 size = SL; 2007 break; 2008 } 2009 } 2010 if (OP_KIND (instruction->opcode->how) == O_MOVAB || 2011 OP_KIND (instruction->opcode->how) == O_MOVAW || 2012 OP_KIND (instruction->opcode->how) == O_MOVAL) 2013 { 2014 switch (operand[0].mode & MODE) 2015 { 2016 case INDEXB: 2017 default: 2018 fix_operand_size (&operand[1], 1); 2019 break; 2020 case INDEXW: 2021 fix_operand_size (&operand[1], 2); 2022 break; 2023 case INDEXL: 2024 fix_operand_size (&operand[1], 4); 2025 break; 2026 } 2027 } 2028 else 2029 { 2030 for (i = 0; i < 3 && operand[i].mode != 0; i++) 2031 switch (size) 2032 { 2033 case SN: 2034 case SB: 2035 default: 2036 fix_operand_size (&operand[i], 1); 2037 break; 2038 case SW: 2039 fix_operand_size (&operand[i], 2); 2040 break; 2041 case SL: 2042 fix_operand_size (&operand[i], 4); 2043 break; 2044 } 2045 } 2046 2047 instruction = get_specific (instruction, operand, size); 2048 2049 if (instruction == 0) 2050 { 2051 /* Couldn't find an opcode which matched the operands. */ 2052 char *where = frag_more (2); 2053 2054 where[0] = 0x0; 2055 where[1] = 0x0; 2056 clever_message (prev_instruction, operand); 2057 2058 return; 2059 } 2060 2061 build_bytes (instruction, operand); 2062 2063 dwarf2_emit_insn (instruction->length); 2064} 2065 2066symbolS * 2067md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 2068{ 2069 return 0; 2070} 2071 2072/* Various routines to kill one day. */ 2073 2074const char * 2075md_atof (int type, char *litP, int *sizeP) 2076{ 2077 return ieee_md_atof (type, litP, sizeP, TRUE); 2078} 2079 2080#define OPTION_H_TICK_HEX (OPTION_MD_BASE) 2081#define OPTION_MACH (OPTION_MD_BASE+1) 2082 2083const char *md_shortopts = ""; 2084struct option md_longopts[] = 2085{ 2086 { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, 2087 { "mach", required_argument, NULL, OPTION_MACH }, 2088 {NULL, no_argument, NULL, 0} 2089}; 2090 2091size_t md_longopts_size = sizeof (md_longopts); 2092 2093struct mach_func 2094{ 2095 const char *name; 2096 void (*func) (void); 2097}; 2098 2099static void 2100mach_h8300h (void) 2101{ 2102 Hmode = 1; 2103 Smode = 0; 2104 Nmode = 0; 2105 SXmode = 0; 2106 default_mach = bfd_mach_h8300h; 2107} 2108 2109static void 2110mach_h8300hn (void) 2111{ 2112 Hmode = 1; 2113 Smode = 0; 2114 Nmode = 1; 2115 SXmode = 0; 2116 default_mach = bfd_mach_h8300hn; 2117} 2118 2119static void 2120mach_h8300s (void) 2121{ 2122 Hmode = 1; 2123 Smode = 1; 2124 Nmode = 0; 2125 SXmode = 0; 2126 default_mach = bfd_mach_h8300s; 2127} 2128 2129static void 2130mach_h8300sn (void) 2131{ 2132 Hmode = 1; 2133 Smode = 1; 2134 Nmode = 1; 2135 SXmode = 0; 2136 default_mach = bfd_mach_h8300sn; 2137} 2138 2139static void 2140mach_h8300sx (void) 2141{ 2142 Hmode = 1; 2143 Smode = 1; 2144 Nmode = 0; 2145 SXmode = 1; 2146 default_mach = bfd_mach_h8300sx; 2147} 2148 2149static void 2150mach_h8300sxn (void) 2151{ 2152 Hmode = 1; 2153 Smode = 1; 2154 Nmode = 1; 2155 SXmode = 1; 2156 default_mach = bfd_mach_h8300sxn; 2157} 2158 2159const struct mach_func mach_table[] = 2160{ 2161 {"h8300h", mach_h8300h}, 2162 {"h8300hn", mach_h8300hn}, 2163 {"h8300s", mach_h8300s}, 2164 {"h8300sn", mach_h8300sn}, 2165 {"h8300sx", mach_h8300sx}, 2166 {"h8300sxn", mach_h8300sxn} 2167}; 2168 2169int 2170md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 2171{ 2172 unsigned int i; 2173 switch (c) 2174 { 2175 case OPTION_H_TICK_HEX: 2176 enable_h_tick_hex = 1; 2177 break; 2178 case OPTION_MACH: 2179 for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) 2180 { 2181 if (strcasecmp (arg, mach_table[i].name) == 0) 2182 { 2183 mach_table[i].func(); 2184 break; 2185 } 2186 } 2187 if (i >= sizeof(mach_table) / sizeof(struct mach_func)) 2188 as_bad (_("Invalid argument to --mach option: %s"), arg); 2189 break; 2190 default: 2191 return 0; 2192 } 2193 return 1; 2194} 2195 2196void 2197md_show_usage (FILE *stream) 2198{ 2199 fprintf (stream, _(" H8300-specific assembler options:\n")); 2200 fprintf (stream, _("\ 2201 -mach=<name> Set the H8300 machine type to one of:\n\ 2202 h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); 2203 fprintf (stream, _("\ 2204 -h-tick-hex Support H'00 style hex constants\n")); 2205} 2206 2207void tc_aout_fix_to_chars (void); 2208 2209void 2210tc_aout_fix_to_chars (void) 2211{ 2212 printf (_("call to tc_aout_fix_to_chars \n")); 2213 abort (); 2214} 2215 2216void 2217md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, 2218 segT seg ATTRIBUTE_UNUSED, 2219 fragS *fragP ATTRIBUTE_UNUSED) 2220{ 2221 printf (_("call to md_convert_frag \n")); 2222 abort (); 2223} 2224 2225valueT 2226md_section_align (segT segment, valueT size) 2227{ 2228 int align = bfd_section_alignment (segment); 2229 return ((size + (1 << align) - 1) & (-1U << align)); 2230} 2231 2232void 2233md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2234{ 2235 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 2236 long val = *valP; 2237 2238 switch (fixP->fx_size) 2239 { 2240 case 1: 2241 *buf++ = val; 2242 break; 2243 case 2: 2244 *buf++ = (val >> 8); 2245 *buf++ = val; 2246 break; 2247 case 4: 2248 *buf++ = (val >> 24); 2249 *buf++ = (val >> 16); 2250 *buf++ = (val >> 8); 2251 *buf++ = val; 2252 break; 2253 case 8: 2254 /* This can arise when the .quad or .8byte pseudo-ops are used. 2255 Returning here (without setting fx_done) will cause the code 2256 to attempt to generate a reloc which will then fail with the 2257 slightly more helpful error message: "Cannot represent 2258 relocation type BFD_RELOC_64". */ 2259 return; 2260 default: 2261 abort (); 2262 } 2263 2264 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 2265 fixP->fx_done = 1; 2266} 2267 2268int 2269md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, 2270 segT segment_type ATTRIBUTE_UNUSED) 2271{ 2272 printf (_("call to md_estimate_size_before_relax \n")); 2273 abort (); 2274} 2275 2276/* Put number into target byte order. */ 2277void 2278md_number_to_chars (char *ptr, valueT use, int nbytes) 2279{ 2280 number_to_chars_bigendian (ptr, use, nbytes); 2281} 2282 2283long 2284md_pcrel_from (fixS *fixp) 2285{ 2286 as_bad_where (fixp->fx_file, fixp->fx_line, 2287 _("Unexpected reference to a symbol in a non-code section")); 2288 return 0; 2289} 2290 2291arelent * 2292tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2293{ 2294 arelent *rel; 2295 bfd_reloc_code_real_type r_type; 2296 2297 if (fixp->fx_addsy && fixp->fx_subsy) 2298 { 2299 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) 2300 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) 2301 { 2302 as_bad_where (fixp->fx_file, fixp->fx_line, 2303 _("Difference of symbols in different sections is not supported")); 2304 return NULL; 2305 } 2306 } 2307 2308 rel = XNEW (arelent); 2309 rel->sym_ptr_ptr = XNEW (asymbol *); 2310 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2311 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 2312 rel->addend = fixp->fx_offset; 2313 2314 r_type = fixp->fx_r_type; 2315 2316#define DEBUG 0 2317#if DEBUG 2318 fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); 2319 fflush (stderr); 2320#endif 2321 rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); 2322 if (rel->howto == NULL) 2323 { 2324 as_bad_where (fixp->fx_file, fixp->fx_line, 2325 _("Cannot represent relocation type %s"), 2326 bfd_get_reloc_code_name (r_type)); 2327 return NULL; 2328 } 2329 2330 return rel; 2331} 2332