1/* Definitions of target machine for GNU compiler for Renesas / SuperH SH. 2 Copyright (C) 1993-2022 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com). 4 Improved by Jim Wilson (wilson@cygnus.com). 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 3, or (at your option) 11any later version. 12 13GCC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22#ifndef GCC_SH_H 23#define GCC_SH_H 24 25#include "config/vxworks-dummy.h" 26 27/* Unfortunately, insn-attrtab.cc doesn't include insn-codes.h. We can't 28 include it here, because bconfig.h is also included by gencodes.cc . */ 29/* ??? No longer true. */ 30extern int code_for_indirect_jump_scratch; 31 32#define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile) 33 34/* Value should be nonzero if functions must have frame pointers. 35 Zero means the frame pointer need not be set up (and parms may be accessed 36 via the stack pointer) in functions that seem suitable. */ 37 38#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 39#define SUBTARGET_FRAME_POINTER_REQUIRED 0 40#endif 41 42 43/* Nonzero if this is an ELF target - compile time only */ 44#define TARGET_ELF 0 45 46/* Nonzero if we should generate code using type 2E insns. */ 47#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) 48 49/* Nonzero if we should generate code using type 2A insns. */ 50#define TARGET_SH2A TARGET_HARD_SH2A 51/* Nonzero if we should generate code using type 2A SF insns. */ 52#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) 53/* Nonzero if we should generate code using type 2A DF insns. */ 54#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) 55 56/* Nonzero if we should generate code using type 3E insns. */ 57#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) 58 59/* Nonzero if we schedule for a superscalar implementation. */ 60#define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A) 61 62/* Nonzero if a double-precision FPU is available. */ 63#define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE) 64 65/* Nonzero if an FPU is available. */ 66#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) 67 68/* Nonzero if we're generating code for SH4a, unless the use of the 69 FPU is disabled (which makes it compatible with SH4al-dsp). */ 70#define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) 71 72/* True if the FPU is a SH4-300 variant. */ 73#define TARGET_FPU_SH4_300 (TARGET_FPU_ANY && TARGET_SH4_300) 74 75/* This is not used by the SH2E calling convention */ 76#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ 77 (! TARGET_SH2E \ 78 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) 79 80#ifndef TARGET_CPU_DEFAULT 81#define TARGET_CPU_DEFAULT SELECT_SH1 82#define SUPPORT_SH1 1 83#define SUPPORT_SH2E 1 84#define SUPPORT_SH4 1 85#define SUPPORT_SH4_SINGLE 1 86#define SUPPORT_SH2A 1 87#define SUPPORT_SH2A_SINGLE 1 88#endif 89 90#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) 91#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) 92#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) 93 94#define SELECT_SH1 (MASK_SH1) 95#define SELECT_SH2 (MASK_SH2 | SELECT_SH1) 96#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ 97 | MASK_FPU_SINGLE) 98#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ 99 | MASK_HARD_SH2A_DOUBLE \ 100 | MASK_SH2 | MASK_SH1) 101#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) 102#define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ 103 | MASK_SH1 | MASK_FPU_SINGLE \ 104 | MASK_FPU_SINGLE_ONLY) 105#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ 106 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ 107 | MASK_SH2 | MASK_SH1) 108#define SELECT_SH3 (MASK_SH3 | SELECT_SH2) 109#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) 110#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) 111#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \ 112 | MASK_FPU_SINGLE_ONLY) 113#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ 114 | SELECT_SH3) 115#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) 116#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) 117#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) 118#define SELECT_SH4A (MASK_SH4A | SELECT_SH4) 119#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) 120 121#if SUPPORT_SH1 122#define SUPPORT_SH2 1 123#endif 124#if SUPPORT_SH2 125#define SUPPORT_SH3 1 126#define SUPPORT_SH2A_NOFPU 1 127#endif 128#if SUPPORT_SH3 129#define SUPPORT_SH4_NOFPU 1 130#endif 131#if SUPPORT_SH4_NOFPU 132#define SUPPORT_SH4A_NOFPU 1 133#define SUPPORT_SH4AL 1 134#endif 135 136#if SUPPORT_SH2E 137#define SUPPORT_SH3E 1 138#define SUPPORT_SH2A_SINGLE_ONLY 1 139#endif 140#if SUPPORT_SH3E 141#define SUPPORT_SH4_SINGLE_ONLY 1 142#endif 143#if SUPPORT_SH4_SINGLE_ONLY 144#define SUPPORT_SH4A_SINGLE_ONLY 1 145#endif 146 147#if SUPPORT_SH4 148#define SUPPORT_SH4A 1 149#endif 150 151#if SUPPORT_SH4_SINGLE 152#define SUPPORT_SH4A_SINGLE 1 153#endif 154 155/* Reset all target-selection flags. */ 156#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ 157 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ 158 | MASK_HARD_SH4 | MASK_FPU_SINGLE \ 159 | MASK_FPU_SINGLE_ONLY) 160 161/* This defaults us to big-endian. */ 162#ifndef TARGET_ENDIAN_DEFAULT 163#define TARGET_ENDIAN_DEFAULT 0 164#endif 165 166#ifndef TARGET_OPT_DEFAULT 167#define TARGET_OPT_DEFAULT 0 168#endif 169 170#define TARGET_DEFAULT \ 171 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) 172 173#ifndef SH_MULTILIB_CPU_DEFAULT 174#define SH_MULTILIB_CPU_DEFAULT "m1" 175#endif 176 177#if TARGET_ENDIAN_DEFAULT 178#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } 179#else 180#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } 181#endif 182 183#define CPP_SPEC " %(subtarget_cpp_spec) " 184 185#ifndef SUBTARGET_CPP_SPEC 186#define SUBTARGET_CPP_SPEC "" 187#endif 188 189#ifndef SUBTARGET_EXTRA_SPECS 190#define SUBTARGET_EXTRA_SPECS 191#endif 192 193#define EXTRA_SPECS \ 194 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 195 { "link_emul_prefix", LINK_EMUL_PREFIX }, \ 196 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ 197 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ 198 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ 199 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ 200 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ 201 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ 202 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 203 SUBTARGET_EXTRA_SPECS 204 205#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 206#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}" 207#else 208#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" 209#endif 210 211/* Define which ISA type to pass to the assembler. 212 For SH4 we pass SH4A to allow using some instructions that are available 213 on some SH4 variants, but officially are part of the SH4A ISA. */ 214#define SH_ASM_SPEC \ 215 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ 216%(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ 217%{m1:--isa=sh} \ 218%{m2:--isa=sh2} \ 219%{m2e:--isa=sh2e} \ 220%{m3:--isa=sh3} \ 221%{m3e:--isa=sh3e} \ 222%{m4:--isa=sh4a} \ 223%{m4-single:--isa=sh4a} \ 224%{m4-single-only:--isa=sh4a} \ 225%{m4-nofpu:--isa=sh4a-nofpu} \ 226%{m4a:--isa=sh4a} \ 227%{m4a-single:--isa=sh4a} \ 228%{m4a-single-only:--isa=sh4a} \ 229%{m4a-nofpu:--isa=sh4a-nofpu} \ 230%{m2a:--isa=sh2a} \ 231%{m2a-single:--isa=sh2a} \ 232%{m2a-single-only:--isa=sh2a} \ 233%{m2a-nofpu:--isa=sh2a-nofpu} \ 234%{m4al:-dsp}" 235 236#define ASM_SPEC SH_ASM_SPEC 237 238#ifndef SUBTARGET_ASM_ENDIAN_SPEC 239#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 240#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" 241#else 242#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" 243#endif 244#endif 245 246#if STRICT_NOFPU == 1 247/* Strict nofpu means that the compiler should tell the assembler 248 to reject FPU instructions. E.g. from ASM inserts. */ 249#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) 250#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" 251#else 252 253#define SUBTARGET_ASM_ISA_SPEC \ 254 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC 255#endif 256#else /* ! STRICT_NOFPU */ 257#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC 258#endif 259 260#ifndef SUBTARGET_ASM_SPEC 261#define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" 262#endif 263 264#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 265#define LINK_EMUL_PREFIX "sh%{!mb:l}" 266#else 267#define LINK_EMUL_PREFIX "sh%{ml:l}" 268#endif 269 270#define LINK_DEFAULT_CPU_EMUL "" 271#define ASM_ISA_DEFAULT_SPEC "" 272 273#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" 274#define SUBTARGET_LINK_SPEC "" 275 276/* Go via SH_LINK_SPEC to avoid code replication. */ 277#define LINK_SPEC SH_LINK_SPEC 278 279#define SH_LINK_SPEC "\ 280-m %(link_emul_prefix)\ 281%{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\ 282%(subtarget_link_emul_suffix) \ 283%{mrelax:-relax} %(subtarget_link_spec)" 284 285#ifndef SH_DIV_STR_FOR_SIZE 286#define SH_DIV_STR_FOR_SIZE "call" 287#endif 288 289/* SH2A does not support little-endian. Catch such combinations 290 taking into account the default configuration. */ 291#if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN 292#define IS_LITTLE_ENDIAN_OPTION "%{ml:" 293#else 294#define IS_LITTLE_ENDIAN_OPTION "%{!mb:" 295#endif 296 297#if TARGET_CPU_DEFAULT & MASK_HARD_SH2A 298#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ 299"%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}" 300#else 301#define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ 302"%{m2a*:%eSH2a does not support little-endian}}" 303#endif 304 305#ifdef FDPIC_DEFAULT 306#define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" 307#else 308#define FDPIC_SELF_SPECS 309#endif 310 311#undef DRIVER_SELF_SPECS 312#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ 313 FDPIC_SELF_SPECS 314 315#undef SUBTARGET_DRIVER_SELF_SPECS 316#define SUBTARGET_DRIVER_SELF_SPECS 317 318#define ASSEMBLER_DIALECT assembler_dialect 319 320extern int assembler_dialect; 321 322enum sh_divide_strategy_e { 323 /* SH1 .. SH4 strategies. Because of the small number of registers 324 available, the compiler uses knowledge of the actual set of registers 325 being clobbered by the different functions called. */ 326 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ 327 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ 328 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ 329 SH_DIV_INTRINSIC 330}; 331 332extern enum sh_divide_strategy_e sh_div_strategy; 333 334#ifndef SH_DIV_STRATEGY_DEFAULT 335#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 336#endif 337 338#ifdef __cplusplus 339 340/* Atomic model. */ 341struct sh_atomic_model 342{ 343 enum enum_type 344 { 345 none = 0, 346 soft_gusa, 347 hard_llcs, 348 soft_tcb, 349 soft_imask, 350 351 num_models 352 }; 353 354 /* If strict is set, disallow mixing of different models, as it would 355 happen on SH4A. */ 356 bool strict; 357 enum_type type; 358 359 /* Name string as it was specified on the command line. */ 360 const char* name; 361 362 /* Name string as it is used in C/C++ defines. */ 363 const char* cdef_name; 364 365 /* GBR offset variable for TCB model. */ 366 int tcb_gbr_offset; 367}; 368 369extern const sh_atomic_model& selected_atomic_model (void); 370 371/* Shortcuts to check the currently selected atomic model. */ 372#define TARGET_ATOMIC_ANY \ 373 (selected_atomic_model ().type != sh_atomic_model::none) 374 375#define TARGET_ATOMIC_STRICT \ 376 (selected_atomic_model ().strict) 377 378#define TARGET_ATOMIC_SOFT_GUSA \ 379 (selected_atomic_model ().type == sh_atomic_model::soft_gusa) 380 381#define TARGET_ATOMIC_HARD_LLCS \ 382 (selected_atomic_model ().type == sh_atomic_model::hard_llcs) 383 384#define TARGET_ATOMIC_SOFT_TCB \ 385 (selected_atomic_model ().type == sh_atomic_model::soft_tcb) 386 387#define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ 388 GEN_INT (selected_atomic_model ().tcb_gbr_offset) 389 390#define TARGET_ATOMIC_SOFT_IMASK \ 391 (selected_atomic_model ().type == sh_atomic_model::soft_imask) 392 393#endif // __cplusplus 394 395#define SUBTARGET_OVERRIDE_OPTIONS (void) 0 396 397 398/* Target machine storage layout. */ 399 400#define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN) 401 402#define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0) 403#define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) 404 405/* Define this if most significant bit is lowest numbered 406 in instructions that operate on numbered bit-fields. */ 407#define BITS_BIG_ENDIAN 0 408 409/* Define this if most significant byte of a word is the lowest numbered. */ 410#define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN 411 412/* Define this if most significant word of a multiword number is the lowest 413 numbered. */ 414#define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN 415 416#define MAX_BITS_PER_WORD 64 417 418/* Width in bits of an `int'. We want just 32-bits, even if words are 419 longer. */ 420#define INT_TYPE_SIZE 32 421 422/* Width in bits of a `long'. */ 423#define LONG_TYPE_SIZE (32) 424 425/* Width in bits of a `long long'. */ 426#define LONG_LONG_TYPE_SIZE 64 427 428/* Width in bits of a `long double'. */ 429#define LONG_DOUBLE_TYPE_SIZE 64 430 431/* Width of a word, in units (bytes). */ 432#define UNITS_PER_WORD (4) 433#define MIN_UNITS_PER_WORD 4 434 435/* Scaling factor for Dwarf data offsets for CFI information. 436 The dwarf2out.cc default would use -UNITS_PER_WORD. */ 437#define DWARF_CIE_DATA_ALIGNMENT -4 438 439/* Width in bits of a pointer. 440 See also the macro `Pmode' defined below. */ 441#define POINTER_SIZE (32) 442 443/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 444#define PARM_BOUNDARY (32) 445 446/* Boundary (in *bits*) on which stack pointer should be aligned. */ 447#define STACK_BOUNDARY BIGGEST_ALIGNMENT 448 449/* The log (base 2) of the cache line size, in bytes. Processors prior to 450 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. 451 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ 452#define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2) 453 454/* ABI given & required minimum allocation boundary (in *bits*) for the 455 code of a function. */ 456#define FUNCTION_BOUNDARY (16) 457 458/* Alignment of field after `int : 0' in a structure. */ 459#define EMPTY_FIELD_BOUNDARY 32 460 461/* No data type wants to be aligned rounder than this. */ 462#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 463 464/* The best alignment to use in cases where we have a choice. */ 465#define FASTEST_ALIGNMENT (32) 466 467/* get_mode_alignment assumes complex values are always held in multiple 468 registers, but that is not the case on the SH; CQImode and CHImode are 469 held in a single integer register. */ 470#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 471 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ 472 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ 473 ? (unsigned) MIN (BIGGEST_ALIGNMENT, \ 474 GET_MODE_BITSIZE (as_a <fixed_size_mode> \ 475 (TYPE_MODE (TYPE)))) \ 476 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) 477 478/* Make arrays of chars word-aligned for the same reasons. */ 479#define DATA_ALIGNMENT(TYPE, ALIGN) \ 480 (TREE_CODE (TYPE) == ARRAY_TYPE \ 481 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 482 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 483 484/* Number of bits which any structure or union's size must be a 485 multiple of. Each structure or union's size is rounded up to a 486 multiple of this. */ 487#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) 488 489/* Set this nonzero if move instructions will actually fail to work 490 when given unaligned data. */ 491#define STRICT_ALIGNMENT 1 492 493/* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 494#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 495 barrier_align (LABEL_AFTER_BARRIER) 496 497#define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL) 498 499#define LABEL_ALIGN(A_LABEL) \ 500( \ 501 (PREV_INSN (A_LABEL) \ 502 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ 503 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 504 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ 505 /* explicit alignment insn in constant tables. */ \ 506 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 507 : 0) 508 509/* Jump tables must be 32 bit aligned, no matter the size of the element. */ 510#define ADDR_VEC_ALIGN(ADDR_VEC) 2 511 512/* The base two logarithm of the known minimum alignment of an insn length. */ 513#define INSN_LENGTH_ALIGNMENT(A_INSN) \ 514 (NONJUMP_INSN_P (A_INSN) \ 515 ? 1 \ 516 : JUMP_P (A_INSN) || CALL_P (A_INSN) \ 517 ? 1 \ 518 : CACHE_LOG) 519 520/* Standard register usage. */ 521 522/* Register allocation for the Renesas calling convention: 523 524 r0 arg return 525 r1..r3 scratch 526 r4..r7 args in 527 r8..r13 call saved 528 r14 frame pointer/call saved 529 r15 stack pointer 530 ap arg pointer (doesn't really exist, always eliminated) 531 pr subroutine return address 532 t t bit 533 mach multiply/accumulate result, high part 534 macl multiply/accumulate result, low part. 535 fpul fp/int communication register 536 rap return address pointer register 537 fr0 fp arg return 538 fr1..fr3 scratch floating point registers 539 fr4..fr11 fp args in 540 fr12..fr15 call saved floating point registers */ 541 542#define MAX_REGISTER_NAME_LENGTH 6 543extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; 544 545#define SH_REGISTER_NAMES_INITIALIZER \ 546{ \ 547 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 548 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 549 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 550 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 551 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 552 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 553 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 554 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 555 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ 556 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ 557 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ 558 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ 559 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ 560 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ 561 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ 562 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ 563 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ 564 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ 565 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ 566 "rap", "sfp", "fpscr0", "fpscr1" \ 567} 568 569#define REGNAMES_ARR_INDEX_1(index) \ 570 (sh_register_names[index]) 571#define REGNAMES_ARR_INDEX_2(index) \ 572 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) 573#define REGNAMES_ARR_INDEX_4(index) \ 574 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) 575#define REGNAMES_ARR_INDEX_8(index) \ 576 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) 577#define REGNAMES_ARR_INDEX_16(index) \ 578 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) 579#define REGNAMES_ARR_INDEX_32(index) \ 580 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) 581#define REGNAMES_ARR_INDEX_64(index) \ 582 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) 583 584#define REGISTER_NAMES \ 585{ \ 586 REGNAMES_ARR_INDEX_64 (0), \ 587 REGNAMES_ARR_INDEX_64 (64), \ 588 REGNAMES_ARR_INDEX_8 (128), \ 589 REGNAMES_ARR_INDEX_8 (136), \ 590 REGNAMES_ARR_INDEX_8 (144), \ 591 REGNAMES_ARR_INDEX_4 (152) \ 592} 593 594#define ADDREGNAMES_SIZE 32 595#define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 596extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ 597 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; 598 599#define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ 600{ \ 601 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ 602 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ 603 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ 604 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ 605} 606 607#define ADDREGNAMES_REGNO(index) \ 608 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ 609 : (-1)) 610 611#define ADDREGNAMES_ARR_INDEX_1(index) \ 612 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } 613#define ADDREGNAMES_ARR_INDEX_2(index) \ 614 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) 615#define ADDREGNAMES_ARR_INDEX_4(index) \ 616 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) 617#define ADDREGNAMES_ARR_INDEX_8(index) \ 618 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) 619#define ADDREGNAMES_ARR_INDEX_16(index) \ 620 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) 621#define ADDREGNAMES_ARR_INDEX_32(index) \ 622 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) 623 624#define ADDITIONAL_REGISTER_NAMES \ 625{ \ 626 ADDREGNAMES_ARR_INDEX_32 (0) \ 627} 628 629/* Number of actual hardware registers. 630 The hardware registers are assigned numbers for the compiler 631 from 0 to just below FIRST_PSEUDO_REGISTER. 632 All registers that the compiler knows about must be given numbers, 633 even those that are not normally considered general registers. */ 634 635/* There are many other relevant definitions in sh.md's md_constants. */ 636 637#define FIRST_GENERAL_REG R0_REG 638#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15)) 639#define FIRST_FP_REG DR0_REG 640#define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) 641#define FIRST_XD_REG XD0_REG 642#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) 643 644/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ 645#define FIRST_BANKED_REG R0_REG 646#define LAST_BANKED_REG R7_REG 647 648#define BANKED_REGISTER_P(REGNO) \ 649 IN_RANGE ((REGNO), \ 650 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ 651 (unsigned HOST_WIDE_INT) LAST_BANKED_REG) 652 653#define GENERAL_REGISTER_P(REGNO) \ 654 IN_RANGE ((REGNO), \ 655 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 656 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) 657 658#define GENERAL_OR_AP_REGISTER_P(REGNO) \ 659 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ 660 || ((REGNO) == FRAME_POINTER_REGNUM)) 661 662#define FP_REGISTER_P(REGNO) \ 663 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) 664 665#define XD_REGISTER_P(REGNO) \ 666 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) 667 668#define FP_OR_XD_REGISTER_P(REGNO) \ 669 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) 670 671#define FP_ANY_REGISTER_P(REGNO) \ 672 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) 673 674#define SPECIAL_REGISTER_P(REGNO) \ 675 ((REGNO) == GBR_REG || (REGNO) == T_REG \ 676 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ 677 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) 678 679#define VALID_REGISTER_P(REGNO) \ 680 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ 681 || XD_REGISTER_P (REGNO) \ 682 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ 683 || (REGNO) == FRAME_POINTER_REGNUM \ 684 || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ 685 || (TARGET_SH2E && (REGNO) == FPUL_REG)) 686 687/* The mode that should be generally used to store a register by 688 itself in the stack, or to load it back. */ 689#define REGISTER_NATURAL_MODE(REGNO) \ 690 (FP_REGISTER_P (REGNO) ? E_SFmode \ 691 : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode) 692 693 694#define FIRST_PSEUDO_REGISTER 156 695 696/* Don't count soft frame pointer. */ 697#define DWARF_FRAME_REGISTERS (153) 698 699/* 1 for registers that have pervasive standard uses 700 and are not available for the register allocator. 701 702 Mach register is fixed 'cause it's only 10 bits wide for SH1. 703 It is 32 bits wide for SH2. */ 704#define FIXED_REGISTERS \ 705{ \ 706/* Regular registers. */ \ 707 0, 0, 0, 0, 0, 0, 0, 0, \ 708 0, 0, 0, 0, 0, 0, 0, 1, \ 709 /* r16 is reserved, r18 is the former pr. */ \ 710 1, 0, 0, 0, 0, 0, 0, 0, \ 711 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ 712 /* r26 is a global variable data pointer; r27 is for constants. */ \ 713 1, 1, 1, 1, 0, 0, 0, 0, \ 714 0, 0, 0, 0, 0, 0, 0, 0, \ 715 0, 0, 0, 0, 0, 0, 0, 0, \ 716 0, 0, 0, 0, 0, 0, 0, 0, \ 717 0, 0, 0, 0, 0, 0, 0, 1, \ 718/* FP registers. */ \ 719 0, 0, 0, 0, 0, 0, 0, 0, \ 720 0, 0, 0, 0, 0, 0, 0, 0, \ 721 0, 0, 0, 0, 0, 0, 0, 0, \ 722 0, 0, 0, 0, 0, 0, 0, 0, \ 723 0, 0, 0, 0, 0, 0, 0, 0, \ 724 0, 0, 0, 0, 0, 0, 0, 0, \ 725 0, 0, 0, 0, 0, 0, 0, 0, \ 726 0, 0, 0, 0, 0, 0, 0, 0, \ 727/* Branch target registers. */ \ 728 0, 0, 0, 0, 0, 0, 0, 0, \ 729/* XD registers. */ \ 730 0, 0, 0, 0, 0, 0, 0, 0, \ 731/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 732 1, 1, 1, 1, 1, 1, 0, 1, \ 733/*"rap", "sfp","fpscr0","fpscr1" */ \ 734 1, 1, 1, 1, \ 735} 736 737/* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then 738 overridden by -fcall-saved-* and -fcall-used-* options and then by 739 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a 740 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */ 741#define CALL_REALLY_USED_REGISTERS \ 742{ \ 743/* Regular registers. */ \ 744 1, 1, 1, 1, 1, 1, 1, 1, \ 745 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ 746 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ 747 across SH5 function calls. */ \ 748 0, 0, 0, 0, 0, 0, 0, 1, \ 749 1, 1, 1, 1, 1, 1, 1, 1, \ 750 1, 1, 1, 1, 0, 0, 0, 0, \ 751 0, 0, 0, 0, 1, 1, 1, 1, \ 752 1, 1, 1, 1, 0, 0, 0, 0, \ 753 0, 0, 0, 0, 0, 0, 0, 0, \ 754 0, 0, 0, 0, 1, 1, 1, 1, \ 755/* FP registers. */ \ 756 1, 1, 1, 1, 1, 1, 1, 1, \ 757 1, 1, 1, 1, 0, 0, 0, 0, \ 758 1, 1, 1, 1, 1, 1, 1, 1, \ 759 1, 1, 1, 1, 1, 1, 1, 1, \ 760 1, 1, 1, 1, 0, 0, 0, 0, \ 761 0, 0, 0, 0, 0, 0, 0, 0, \ 762 0, 0, 0, 0, 0, 0, 0, 0, \ 763 0, 0, 0, 0, 0, 0, 0, 0, \ 764/* Branch target registers. */ \ 765 1, 1, 1, 1, 1, 0, 0, 0, \ 766/* XD registers. */ \ 767 1, 1, 1, 1, 1, 1, 0, 0, \ 768/*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 769 0, 1, 1, 1, 1, 1, 1, 1, \ 770/*"rap", "sfp","fpscr0","fpscr1" */ \ 771 1, 1, 0, 0, \ 772} 773 774/* Specify the modes required to caller save a given hard regno. */ 775#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 776 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 777 778/* A C expression that is nonzero if hard register NEW_REG can be 779 considered for use as a rename register for OLD_REG register */ 780#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 781 sh_hard_regno_rename_ok (OLD_REG, NEW_REG) 782 783/* Specify the registers used for certain standard purposes. 784 The values of these macros are register numbers. */ 785 786/* Define this if the program counter is overloaded on a register. */ 787/* #define PC_REGNUM 15*/ 788 789/* Register to use for pushing function arguments. */ 790#define STACK_POINTER_REGNUM SP_REG 791 792/* Base register for access to local variables of the function. */ 793#define HARD_FRAME_POINTER_REGNUM FP_REG 794 795/* Base register for access to local variables of the function. */ 796#define FRAME_POINTER_REGNUM 153 797 798/* Fake register that holds the address on the stack of the 799 current function's return address. */ 800#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG 801 802/* Register to hold the addressing base for position independent 803 code access to data items. */ 804#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) 805 806/* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 807 entries would need to handle saving and restoring it). */ 808#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 809 810#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 811 812/* Definitions for register eliminations. 813 814 We have three registers that can be eliminated on the SH. First, the 815 frame pointer register can often be eliminated in favor of the stack 816 pointer register. Secondly, the argument pointer register can always be 817 eliminated; it is replaced with either the stack or frame pointer. 818 Third, there is the return address pointer, which can also be replaced 819 with either the stack or the frame pointer. 820 821 This is an array of structures. Each structure initializes one pair 822 of eliminable registers. The "from" register number is given first, 823 followed by "to". Eliminations of the same "from" register are listed 824 in order of preference. 825 826 If you add any registers here that are not actually hard registers, 827 and that have any alternative of elimination that doesn't always 828 apply, you need to amend calc_live_regs to exclude it, because 829 reload spills all eliminable registers where it sees an 830 can_eliminate == 0 entry, thus making them 'live' . 831 If you add any hard registers that can be eliminated in different 832 ways, you have to patch reload to spill them only when all alternatives 833 of elimination fail. */ 834#define ELIMINABLE_REGS \ 835{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 836 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 837 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 838 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 839 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 840 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 841 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} 842 843/* Define the offset between two registers, one to be eliminated, and the other 844 its replacement, at the start of a routine. */ 845#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 846 OFFSET = initial_elimination_offset ((FROM), (TO)) 847 848/* Base register for access to arguments of the function. */ 849#define ARG_POINTER_REGNUM AP_REG 850 851/* Register in which the static-chain is passed to a function. */ 852#define STATIC_CHAIN_REGNUM (3) 853 854/* Don't default to pcc-struct-return, because we have already specified 855 exactly how to return structures in the TARGET_RETURN_IN_MEMORY 856 target hook. */ 857#define DEFAULT_PCC_STRUCT_RETURN 0 858 859 860/* Define the classes of registers for register constraints in the 861 machine description. Also define ranges of constants. 862 863 One of the classes must always be named ALL_REGS and include all hard regs. 864 If there is more than one class, another class must be named NO_REGS 865 and contain no registers. 866 867 The name GENERAL_REGS must be the name of a class (or an alias for 868 another name such as ALL_REGS). This is the class of registers 869 that is allowed by "g" or "r" in a register constraint. 870 Also, registers outside this class are allocated only when 871 instructions express preferences for them. 872 873 The classes must be numbered in nondecreasing order; that is, 874 a larger-numbered class must never be contained completely 875 in a smaller-numbered class. 876 877 For any two classes, it is very desirable that there be another 878 class that represents their union. 879 880 The SH has two sorts of general registers, R0 and the rest. R0 can 881 be used as the destination of some of the arithmetic ops. There are 882 also some special purpose registers; the T bit register, the 883 Procedure Return Register and the Multiply Accumulate Registers. 884 885 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by 886 reg_class_subunion. We don't want to have an actual union class 887 of these, because it would only be used when both classes are calculated 888 to give the same cost, but there is only one FPUL register. 889 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS 890 applying to the actual instruction alternative considered. E.g., the 891 y/r alternative of movsi_ie is considered to have no more cost that 892 the r/r alternative, which is patently untrue. */ 893enum reg_class 894{ 895 NO_REGS, 896 R0_REGS, 897 PR_REGS, 898 T_REGS, 899 MAC_REGS, 900 FPUL_REGS, 901 SIBCALL_REGS, 902 NON_SP_REGS, 903 GENERAL_REGS, 904 FP0_REGS, 905 FP_REGS, 906 DF_REGS, 907 FPSCR_REGS, 908 GENERAL_FP_REGS, 909 GENERAL_DF_REGS, 910 TARGET_REGS, 911 ALL_REGS, 912 LIM_REG_CLASSES 913}; 914 915#define N_REG_CLASSES (int) LIM_REG_CLASSES 916 917/* Give names of register classes as strings for dump file. */ 918#define REG_CLASS_NAMES \ 919{ \ 920 "NO_REGS", \ 921 "R0_REGS", \ 922 "PR_REGS", \ 923 "T_REGS", \ 924 "MAC_REGS", \ 925 "FPUL_REGS", \ 926 "SIBCALL_REGS", \ 927 "NON_SP_REGS", \ 928 "GENERAL_REGS", \ 929 "FP0_REGS", \ 930 "FP_REGS", \ 931 "DF_REGS", \ 932 "FPSCR_REGS", \ 933 "GENERAL_FP_REGS", \ 934 "GENERAL_DF_REGS", \ 935 "TARGET_REGS", \ 936 "ALL_REGS", \ 937} 938 939/* Define which registers fit in which classes. 940 This is an initializer for a vector of HARD_REG_SET 941 of length N_REG_CLASSES. */ 942#define REG_CLASS_CONTENTS \ 943{ \ 944/* NO_REGS: */ \ 945 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 946/* R0_REGS: */ \ 947 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 948/* PR_REGS: */ \ 949 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ 950/* T_REGS: */ \ 951 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ 952/* MAC_REGS: */ \ 953 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ 954/* FPUL_REGS: */ \ 955 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ 956/* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ 957 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 958/* NON_SP_REGS: */ \ 959 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 960/* GENERAL_REGS: */ \ 961 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 962/* FP0_REGS: */ \ 963 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ 964/* FP_REGS: */ \ 965 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 966/* DF_REGS: */ \ 967 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 968/* FPSCR_REGS: */ \ 969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ 970/* GENERAL_FP_REGS: */ \ 971 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ 972/* GENERAL_DF_REGS: */ \ 973 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ 974/* TARGET_REGS: */ \ 975 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ 976/* ALL_REGS: */ \ 977 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \ 978} 979 980/* The same information, inverted: 981 Return the class number of the smallest class containing 982 reg number REGNO. This could be a conditional expression 983 or could index an array. */ 984extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 985#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] 986 987/* When this hook returns true for MODE, the compiler allows 988 registers explicitly used in the rtl to be used as spill registers 989 but prevents the compiler from extending the lifetime of these 990 registers. */ 991#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 992 sh_small_register_classes_for_mode_p 993 994/* The order in which register should be allocated. */ 995/* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, 996 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be 997 spilled or used otherwise, we better have the FP_REGS allocated first. */ 998#define REG_ALLOC_ORDER \ 999 {/* Caller-saved FPRs */ \ 1000 65, 66, 67, 68, 69, 70, 71, 64, \ 1001 72, 73, 74, 75, 80, 81, 82, 83, \ 1002 84, 85, 86, 87, 88, 89, 90, 91, \ 1003 92, 93, 94, 95, 96, 97, 98, 99, \ 1004 /* Callee-saved FPRs */ \ 1005 76, 77, 78, 79,100,101,102,103, \ 1006 104,105,106,107,108,109,110,111, \ 1007 112,113,114,115,116,117,118,119, \ 1008 120,121,122,123,124,125,126,127, \ 1009 136,137,138,139,140,141,142,143, \ 1010 /* FPSCR */ 151, \ 1011 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ 1012 1, 2, 3, 7, 6, 5, 4, 0, \ 1013 8, 9, 17, 19, 20, 21, 22, 23, \ 1014 36, 37, 38, 39, 40, 41, 42, 43, \ 1015 60, 61, 62, \ 1016 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ 1017 10, 11, 12, 13, 14, 18, \ 1018 /* SH5 callee-saved GPRs */ \ 1019 28, 29, 30, 31, 32, 33, 34, 35, \ 1020 44, 45, 46, 47, 48, 49, 50, 51, \ 1021 52, 53, 54, 55, 56, 57, 58, 59, \ 1022 /* FPUL */ 150, \ 1023 /* Fixed registers */ \ 1024 15, 16, 24, 25, 26, 27, 63,144, \ 1025 145,146,147,148,149,152,153,154,155 } 1026 1027/* The class value for index registers, and the one for base regs. */ 1028#define INDEX_REG_CLASS R0_REGS 1029#define BASE_REG_CLASS GENERAL_REGS 1030 1031/* Defines for sh.md and constraints.md. */ 1032 1033#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ 1034 && ((HOST_WIDE_INT)(VALUE)) <= 127) 1035 1036#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1037 && ((HOST_WIDE_INT)(VALUE)) <= 255) 1038 1039#define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\ 1040 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX)) 1041 1042/* Return the maximum number of consecutive registers 1043 needed to represent mode MODE in a register of class CLASS. 1044 1045 If TARGET_SHMEDIA, we need two FP registers per word. 1046 Otherwise we will need at most one register per word. */ 1047#define CLASS_MAX_NREGS(CLASS, MODE) \ 1048 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1049 1050/* Stack layout; function entry, exit and calling. */ 1051 1052/* Define the number of registers that can hold parameters. 1053 These macros are used only in other macro definitions below. */ 1054#define NPARM_REGS(MODE) \ 1055 (TARGET_FPU_ANY && (MODE) == SFmode \ 1056 ? 8 \ 1057 : TARGET_FPU_DOUBLE \ 1058 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1059 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1060 ? 8 \ 1061 : 4) 1062 1063#define FIRST_PARM_REG (FIRST_GENERAL_REG + 4) 1064#define FIRST_RET_REG (FIRST_GENERAL_REG + 0) 1065 1066#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) 1067#define FIRST_FP_RET_REG FIRST_FP_REG 1068 1069/* Define this if pushing a word on the stack 1070 makes the stack pointer a smaller address. */ 1071#define STACK_GROWS_DOWNWARD 1 1072 1073/* Define this macro to nonzero if the addresses of local variable slots 1074 are at negative offsets from the frame pointer. */ 1075#define FRAME_GROWS_DOWNWARD 1 1076 1077/* If we generate an insn to push BYTES bytes, 1078 this says how many the stack pointer really advances by. */ 1079/* Don't define PUSH_ROUNDING, since the hardware doesn't do this. 1080 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to 1081 do correct alignment. */ 1082#if 0 1083#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 1084#endif 1085 1086/* Offset of first parameter from the argument pointer register value. */ 1087#define FIRST_PARM_OFFSET(FNDECL) 0 1088 1089/* Value is the number of bytes of arguments automatically popped when 1090 calling a subroutine. 1091 CUM is the accumulated argument list. */ 1092#define CALL_POPS_ARGS(CUM) (0) 1093 1094/* Some subroutine macros specific to this machine. */ 1095 1096#define BASE_RETURN_VALUE_REG(MODE) \ 1097 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ 1098 ? FIRST_FP_RET_REG \ 1099 : TARGET_FPU_ANY && (MODE) == SCmode \ 1100 ? FIRST_FP_RET_REG \ 1101 : (TARGET_FPU_DOUBLE \ 1102 && ((MODE) == DFmode || (MODE) == SFmode \ 1103 || (MODE) == DCmode || (MODE) == SCmode )) \ 1104 ? FIRST_FP_RET_REG \ 1105 : FIRST_RET_REG) 1106 1107#define BASE_ARG_REG(MODE) \ 1108 ((TARGET_SH2E && ((MODE) == SFmode)) \ 1109 ? FIRST_FP_PARM_REG \ 1110 : TARGET_FPU_DOUBLE \ 1111 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1112 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1113 ? FIRST_FP_PARM_REG \ 1114 : FIRST_PARM_REG) 1115 1116/* 1 if N is a possible register number for function argument passing. */ 1117/* ??? There are some callers that pass REGNO as int, and others that pass 1118 it as unsigned. We get warnings unless we do casts everywhere. */ 1119#define FUNCTION_ARG_REGNO_P(REGNO) \ 1120 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ 1121 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ 1122 || (TARGET_FPU_ANY \ 1123 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ 1124 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ 1125 + NPARM_REGS (SFmode)))) 1126 1127#ifdef __cplusplus 1128 1129/* Define a data type for recording info about an argument list 1130 during the scan of that argument list. This data type should 1131 hold all necessary information about the function itself 1132 and about the args processed so far, enough to enable macros 1133 such as FUNCTION_ARG to determine where the next arg should go. 1134 1135 On SH, this is a single integer, which is a number of words 1136 of arguments scanned so far (including the invisible argument, 1137 if any, which holds the structure-value-address). 1138 Thus NARGREGS or more means all following args should go on the stack. */ 1139 1140enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; 1141 1142struct sh_args 1143{ 1144 /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */ 1145 int arg_count[2]; 1146 1147 bool force_mem; 1148 1149 /* Nonzero if a prototype is available for the function. */ 1150 bool prototype_p; 1151 1152 /* The number of an odd floating-point register, that should be used 1153 for the next argument of type float. */ 1154 int free_single_fp_reg; 1155 1156 /* Whether we're processing an outgoing function call. */ 1157 bool outgoing; 1158 1159 /* This is set to nonzero when the call in question must use the Renesas ABI, 1160 even without the -mrenesas option. */ 1161 bool renesas_abi; 1162}; 1163 1164typedef sh_args CUMULATIVE_ARGS; 1165 1166/* Set when processing a function with interrupt attribute. */ 1167extern bool current_function_interrupt; 1168 1169#endif // __cplusplus 1170 1171/* Initialize a variable CUM of type CUMULATIVE_ARGS 1172 for a call to a function whose data type is FNTYPE. 1173 For a library call, FNTYPE is 0. 1174 1175 On SH, the offset always starts at 0: the first parm reg is always 1176 the same reg for a given argument class. 1177 1178 For TARGET_HITACHI, the structure value pointer is passed in memory. */ 1179#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1180 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\ 1181 (N_NAMED_ARGS), VOIDmode) 1182 1183#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1184 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) 1185 1186/* By accident we got stuck with passing SCmode on SH4 little endian 1187 in two registers that are nominally successive - which is different from 1188 two single SFmode values, where we take endianness translation into 1189 account. That does not work at all if an odd number of registers is 1190 already in use, so that got fixed, but library functions are still more 1191 likely to use complex numbers without mixing them with SFmode arguments 1192 (which in C would have to be structures), so for the sake of ABI 1193 compatibility the way SCmode values are passed when an even number of 1194 FP registers is in use remains different from a pair of SFmode values for 1195 now. 1196 I.e.: 1197 foo (double); a: fr5,fr4 1198 foo (float a, float b); a: fr5 b: fr4 1199 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, 1200 this should be the other way round... 1201 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ 1202#define FUNCTION_ARG_SCmode_WART 1 1203 1204/* Minimum alignment for an argument to be passed by callee-copy 1205 reference. We need such arguments to be aligned to 8 byte 1206 boundaries, because they'll be loaded using quad loads. */ 1207#define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) 1208 1209/* Perform any needed actions needed for a function that is receiving a 1210 variable number of arguments. */ 1211 1212/* Call the function profiler with a given profile label. 1213 We use two .aligns, so as to make sure that both the .long is aligned 1214 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) 1215 from the trapa instruction. */ 1216#define FUNCTION_PROFILER(STREAM,LABELNO) \ 1217{ \ 1218 fprintf((STREAM), "\t.align\t2\n"); \ 1219 fprintf((STREAM), "\ttrapa\t#33\n"); \ 1220 fprintf((STREAM), "\t.align\t2\n"); \ 1221 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1222} 1223 1224/* Define this macro if the code for function profiling should come 1225 before the function prologue. Normally, the profiling code comes 1226 after. */ 1227#define PROFILE_BEFORE_PROLOGUE 1228 1229/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1230 the stack pointer does not matter. The value is tested only in 1231 functions that have frame pointers. 1232 No definition is equivalent to always zero. */ 1233#define EXIT_IGNORE_STACK 1 1234 1235/* 1236 On the SH, the trampoline looks like 1237 2 0002 D202 mov.l l2,r2 1238 1 0000 D301 mov.l l1,r3 1239 3 0004 422B jmp @r2 1240 4 0006 0009 nop 1241 5 0008 00000000 l1: .long area 1242 6 000c 00000000 l2: .long function */ 1243 1244/* Length in units of the trampoline for entering a nested function. */ 1245#define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16) 1246 1247/* Alignment required for a trampoline in bits. */ 1248#define TRAMPOLINE_ALIGNMENT \ 1249 ((CACHE_LOG < 3 \ 1250 || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \ 1251 : 64) 1252 1253/* A C expression whose value is RTL representing the value of the return 1254 address for the frame COUNT steps up from the current frame. 1255 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1256 can ignore COUNT. */ 1257#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1258 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) 1259 1260/* A C expression whose value is RTL representing the location of the 1261 incoming return address at the beginning of any function, before the 1262 prologue. This RTL is either a REG, indicating that the return 1263 value is saved in REG, or a MEM representing a location in 1264 the stack. */ 1265#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG) 1266 1267/* Addressing modes, and classification of registers for them. */ 1268#define HAVE_POST_INCREMENT TARGET_SH1 1269#define HAVE_PRE_DECREMENT TARGET_SH1 1270 1271#define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1 1272#define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A 1273#define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A 1274#define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1 1275 1276/* If a memory clear move would take CLEAR_RATIO or more simple 1277 move-instruction pairs, we will do a setmem instead. */ 1278 1279#define CLEAR_RATIO(speed) ((speed) ? 15 : 3) 1280 1281/* Macros to check register numbers against specific register classes. */ 1282 1283/* These assume that REGNO is a hard or pseudo reg number. 1284 They give nonzero only if REGNO is a hard reg of the suitable class 1285 or a pseudo reg currently allocated to a suitable hard reg. 1286 Since they use reg_renumber, they are safe only once reg_renumber 1287 has been allocated, which happens in reginfo.cc during register 1288 allocation. */ 1289#define REGNO_OK_FOR_BASE_P(REGNO) \ 1290 (GENERAL_OR_AP_REGISTER_P (REGNO) \ 1291 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) 1292#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1293 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) 1294 1295/* True if SYMBOL + OFFSET constants must refer to something within 1296 SYMBOL's section. */ 1297#define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC 1298 1299/* Maximum number of registers that can appear in a valid memory 1300 address. */ 1301#define MAX_REGS_PER_ADDRESS 2 1302 1303/* Recognize any constant value that is a valid address. */ 1304#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 1305 1306/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1307 and check its validity for a certain class. 1308 The suitable hard regs are always accepted and all pseudo regs 1309 are also accepted if STRICT is not set. */ 1310 1311/* Nonzero if X is a reg that can be used as a base reg. */ 1312#define REG_OK_FOR_BASE_P(X, STRICT) \ 1313 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1314 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1315 1316/* Nonzero if X is a reg that can be used as an index. */ 1317#define REG_OK_FOR_INDEX_P(X, STRICT) \ 1318 ((REGNO (X) == R0_REG) \ 1319 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1320 1321/* Nonzero if X/OFFSET is a reg that can be used as an index. */ 1322#define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ 1323 ((REGNO (X) == R0_REG && OFFSET == 0) \ 1324 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1325 1326/* Macros for extra constraints. */ 1327 1328#define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ 1329 ((GET_CODE ((OP)) == LABEL_REF) \ 1330 || (GET_CODE ((OP)) == CONST \ 1331 && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1332 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ 1333 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) 1334 1335#define IS_NON_EXPLICIT_CONSTANT_P(OP) \ 1336 (CONSTANT_P (OP) \ 1337 && !CONST_INT_P (OP) \ 1338 && GET_CODE (OP) != CONST_DOUBLE \ 1339 && (!flag_pic \ 1340 || (LEGITIMATE_PIC_OPERAND_P (OP) \ 1341 && !PIC_ADDR_P (OP) \ 1342 && GET_CODE (OP) != LABEL_REF))) 1343 1344#define GOT_ENTRY_P(OP) \ 1345 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1346 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) 1347 1348#define GOTPLT_ENTRY_P(OP) \ 1349 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1350 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) 1351 1352#define UNSPEC_GOTOFF_P(OP) \ 1353 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) 1354 1355#define GOTOFF_P(OP) \ 1356 (GET_CODE (OP) == CONST \ 1357 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ 1358 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ 1359 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ 1360 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) 1361 1362#define PIC_ADDR_P(OP) \ 1363 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1364 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) 1365 1366#define PCREL_SYMOFF_P(OP) \ 1367 (GET_CODE (OP) == CONST \ 1368 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1369 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) 1370 1371#define NON_PIC_REFERENCE_P(OP) \ 1372 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ 1373 || (GET_CODE (OP) == CONST \ 1374 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ 1375 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \ 1376 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1377 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ 1378 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \ 1379 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) 1380 1381#define PIC_REFERENCE_P(OP) \ 1382 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ 1383 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) 1384 1385#define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ 1386 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ 1387 || (GET_CODE (X) == SUBREG \ 1388 && REG_P (SUBREG_REG (X)) \ 1389 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) 1390 1391/* Since this must be r0, which is a single register class, we must check 1392 SUBREGs more carefully, to be sure that we don't accept one that extends 1393 outside the class. */ 1394#define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ 1395 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ 1396 || (GET_CODE (X) == SUBREG \ 1397 && REG_P (SUBREG_REG (X)) \ 1398 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) 1399 1400#ifdef REG_OK_STRICT 1401#define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) 1402#define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) 1403#else 1404#define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) 1405#define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) 1406#endif 1407 1408 1409/* A C compound statement that attempts to replace X, which is an address 1410 that needs reloading, with a valid memory address for an operand of 1411 mode MODE. WIN is a C statement label elsewhere in the code. */ 1412#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1413 do { \ 1414 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ 1415 goto WIN; \ 1416 } while (0) 1417 1418/* Specify the machine mode that this machine uses 1419 for the index in the tablejump instruction. */ 1420#define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) 1421 1422#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1423((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ 1424 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1425 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1426 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1427 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ 1428 : SImode) 1429 1430/* Define as C expression which evaluates to nonzero if the tablejump 1431 instruction expects the table to contain offsets from the address of the 1432 table. 1433 Do not define this if the table should contain absolute addresses. */ 1434#define CASE_VECTOR_PC_RELATIVE 1 1435 1436/* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ 1437#define FLOAT_TYPE_SIZE 32 1438 1439/* Since the SH2e has only `float' support, it is desirable to make all 1440 floating point types equivalent to `float'. */ 1441#define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64) 1442 1443/* 'char' is signed by default. */ 1444#define DEFAULT_SIGNED_CHAR 1 1445 1446/* The type of size_t unsigned int. */ 1447#define SIZE_TYPE ("unsigned int") 1448 1449#undef PTRDIFF_TYPE 1450#define PTRDIFF_TYPE ("int") 1451 1452#define WCHAR_TYPE "short unsigned int" 1453#define WCHAR_TYPE_SIZE 16 1454 1455#define SH_ELF_WCHAR_TYPE "long int" 1456 1457/* Max number of bytes we can move from memory to memory 1458 in one reasonably fast instruction. */ 1459#define MOVE_MAX (4) 1460 1461/* Maximum value possibly taken by MOVE_MAX. Must be defined whenever 1462 MOVE_MAX is not a compile-time constant. */ 1463#define MAX_MOVE_MAX 8 1464 1465/* Max number of bytes we want move_by_pieces to be able to copy 1466 efficiently. */ 1467#define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) 1468 1469/* Define if operations between registers always perform the operation 1470 on the full register even if a narrower mode is specified. */ 1471#define WORD_REGISTER_OPERATIONS 1 1472 1473/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1474 will either zero-extend or sign-extend. The value of this macro should 1475 be the code that says which one of the two operations is implicitly 1476 done, UNKNOWN if none. */ 1477#define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN) 1478 1479/* Define if loading short immediate values into registers sign extends. */ 1480#define SHORT_IMMEDIATES_SIGN_EXTEND 1 1481 1482/* Nonzero if access to memory by bytes is no faster than for words. */ 1483#define SLOW_BYTE_ACCESS 1 1484 1485/* Nonzero if the target supports dynamic shift instructions 1486 like shad and shld. */ 1487#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) 1488 1489/* The cost of using the dynamic shift insns (shad, shld) are the same 1490 if they are available. If they are not available a library function will 1491 be emitted instead, which is more expensive. */ 1492#define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20) 1493 1494/* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like 1495 (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1496 This is not generally true when hardware dynamic shifts (shad, shld) are 1497 used, because they check the sign bit _before_ the modulo op. The sign 1498 bit determines whether it is a left shift or a right shift: 1499 if (Y < 0) 1500 return X << (Y & 31); 1501 else 1502 return X >> (-Y) & 31); 1503 1504 The dynamic shift library routines in lib1funcs.S do not use the sign bit 1505 like the hardware dynamic shifts and truncate the shift count to 31. 1506 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count 1507 truncation in the library function call patterns, as this gives slightly 1508 more compact code. */ 1509#define SHIFT_COUNT_TRUNCATED (0) 1510 1511/* Define this if addresses of constant functions 1512 shouldn't be put through pseudo regs where they can be cse'd. 1513 Desirable on machines where ordinary constants are expensive 1514 but a CALL with constant address is cheap. */ 1515/*#define NO_FUNCTION_CSE 1*/ 1516 1517/* The machine modes of pointers and functions. */ 1518#define Pmode (SImode) 1519#define FUNCTION_MODE Pmode 1520 1521/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 1522 are actually function calls with some special constraints on arguments 1523 and register usage. 1524 1525 These macros tell reorg that the references to arguments and 1526 register clobbers for insns of type sfunc do not appear to happen 1527 until after the millicode call. This allows reorg to put insns 1528 which set the argument registers into the delay slot of the millicode 1529 call -- thus they act more like traditional CALL_INSNs. 1530 1531 get_attr_is_sfunc will try to recognize the given insn, so make sure to 1532 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 1533 in particular. */ 1534 1535#define INSN_SETS_ARE_DELAYED(X) \ 1536 ((NONJUMP_INSN_P (X) \ 1537 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1538 && GET_CODE (PATTERN (X)) != USE \ 1539 && GET_CODE (PATTERN (X)) != CLOBBER \ 1540 && get_attr_is_sfunc (X))) 1541 1542#define INSN_REFERENCES_ARE_DELAYED(X) \ 1543 ((NONJUMP_INSN_P (X) \ 1544 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1545 && GET_CODE (PATTERN (X)) != USE \ 1546 && GET_CODE (PATTERN (X)) != CLOBBER \ 1547 && get_attr_is_sfunc (X))) 1548 1549 1550/* Position Independent Code. */ 1551 1552/* We can't directly access anything that contains a symbol, 1553 nor can we indirect via the constant pool. */ 1554#define LEGITIMATE_PIC_OPERAND_P(X) \ 1555 ((! nonpic_symbol_mentioned_p (X) \ 1556 && (GET_CODE (X) != SYMBOL_REF \ 1557 || ! CONSTANT_POOL_ADDRESS_P (X) \ 1558 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))) 1559 1560#define SYMBOLIC_CONST_P(X) \ 1561((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ 1562 && nonpic_symbol_mentioned_p (X)) 1563 1564/* Compute extra cost of moving data between one register class 1565 and another. */ 1566 1567/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass 1568 uses this information. Hence, the general register <-> floating point 1569 register information here is not used for SFmode. */ 1570#define REGCLASS_HAS_GENERAL_REG(CLASS) \ 1571 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ 1572 || ((CLASS) == SIBCALL_REGS)) 1573 1574#define REGCLASS_HAS_FP_REG(CLASS) \ 1575 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ 1576 || (CLASS) == DF_REGS) 1577 1578/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 1579 would be so that people with slow memory systems could generate 1580 different code that does fewer memory accesses. */ 1581 1582/* A C expression for the cost of a branch instruction. A value of 1 1583 is the default; other values are interpreted relative to that. */ 1584#define BRANCH_COST(speed_p, predictable_p) sh_branch_cost 1585 1586/* Assembler output control. */ 1587 1588/* A C string constant describing how to begin a comment in the target 1589 assembler language. The compiler assumes that the comment will end at 1590 the end of the line. */ 1591#define ASM_COMMENT_START "!" 1592 1593#define ASM_APP_ON "" 1594#define ASM_APP_OFF "" 1595#define FILE_ASM_OP "\t.file\n" 1596#define SET_ASM_OP "\t.set\t" 1597 1598/* How to change between sections. */ 1599#define TEXT_SECTION_ASM_OP "\t.text" 1600#define DATA_SECTION_ASM_OP "\t.data" 1601 1602#if defined CRT_BEGIN || defined CRT_END 1603/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ 1604#undef TEXT_SECTION_ASM_OP 1605#define TEXT_SECTION_ASM_OP "\t.text" 1606#endif 1607 1608#ifndef BSS_SECTION_ASM_OP 1609#define BSS_SECTION_ASM_OP "\t.section\t.bss" 1610#endif 1611 1612#ifndef ASM_OUTPUT_ALIGNED_BSS 1613#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1614 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 1615#endif 1616 1617/* Define this so that jump tables go in same section as the current function, 1618 which could be text or it could be a user defined section. */ 1619#define JUMP_TABLES_IN_TEXT_SECTION 1 1620 1621#undef DO_GLOBAL_CTORS_BODY 1622#define DO_GLOBAL_CTORS_BODY \ 1623{ \ 1624 typedef void (*pfunc) (void); \ 1625 extern pfunc __ctors[]; \ 1626 extern pfunc __ctors_end[]; \ 1627 pfunc *p; \ 1628 for (p = __ctors_end; p > __ctors; ) \ 1629 { \ 1630 (*--p)(); \ 1631 } \ 1632} 1633 1634#undef DO_GLOBAL_DTORS_BODY 1635#define DO_GLOBAL_DTORS_BODY \ 1636{ \ 1637 typedef void (*pfunc) (void); \ 1638 extern pfunc __dtors[]; \ 1639 extern pfunc __dtors_end[]; \ 1640 pfunc *p; \ 1641 for (p = __dtors; p < __dtors_end; p++) \ 1642 { \ 1643 (*p)(); \ 1644 } \ 1645} 1646 1647#define ASM_OUTPUT_REG_PUSH(file, v) \ 1648{ \ 1649 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ 1650} 1651 1652#define ASM_OUTPUT_REG_POP(file, v) \ 1653{ \ 1654 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ 1655} 1656 1657/* DBX register number for a given compiler register number. */ 1658/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 1659 to match gdb. */ 1660/* expand_builtin_init_dwarf_reg_sizes uses this to test if a 1661 register exists, so we should return -1 for invalid register numbers. */ 1662#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) 1663 1664#define SH_DBX_REGISTER_NUMBER(REGNO) \ 1665 (IN_RANGE ((REGNO), \ 1666 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 1667 FIRST_GENERAL_REG + 15U) \ 1668 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ 1669 : ((int) (REGNO) >= FIRST_FP_REG \ 1670 && ((int) (REGNO) \ 1671 <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \ 1672 ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ 1673 : XD_REGISTER_P (REGNO) \ 1674 ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ 1675 : (REGNO) == PR_REG \ 1676 ? (17) \ 1677 : (REGNO) == GBR_REG \ 1678 ? (18) \ 1679 : (REGNO) == MACH_REG \ 1680 ? (20) \ 1681 : (REGNO) == MACL_REG \ 1682 ? (21) \ 1683 : (REGNO) == T_REG \ 1684 ? (22) \ 1685 : (REGNO) == FPUL_REG \ 1686 ? (23) \ 1687 : (REGNO) == FPSCR_REG \ 1688 ? (24) \ 1689 : (unsigned) -1) 1690 1691/* This is how to output an assembler line 1692 that says to advance the location counter 1693 to a multiple of 2**LOG bytes. */ 1694 1695#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1696 if ((LOG) != 0) \ 1697 fprintf ((FILE), "\t.align %d\n", (LOG)) 1698 1699/* Globalizing directive for a label. */ 1700#define GLOBAL_ASM_OP "\t.global\t" 1701 1702/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1703 1704/* Output a relative address table. */ 1705#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 1706 switch (GET_MODE (BODY)) \ 1707 { \ 1708 case E_SImode: \ 1709 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1710 break; \ 1711 case E_HImode: \ 1712 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1713 break; \ 1714 case E_QImode: \ 1715 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1716 break; \ 1717 default: \ 1718 break; \ 1719 } 1720 1721/* Output an absolute table element. */ 1722#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 1723 do { \ 1724 if (! optimize || TARGET_BIGTABLE) \ 1725 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ 1726 else \ 1727 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \ 1728 } while (0) 1729 1730/* A C statement to be executed just prior to the output of 1731 assembler code for INSN, to modify the extracted operands so 1732 they will be output differently. 1733 1734 Here the argument OPVEC is the vector containing the operands 1735 extracted from INSN, and NOPERANDS is the number of elements of 1736 the vector which contain meaningful data for this insn. 1737 The contents of this vector are what will be used to convert the insn 1738 template into assembler code, so you can change the assembler output 1739 by changing the contents of the vector. */ 1740#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1741 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 1742 1743/* Which processor to schedule for. The elements of the enumeration must 1744 match exactly the cpu attribute in the sh.md file. */ 1745enum processor_type { 1746 PROCESSOR_SH1, 1747 PROCESSOR_SH2, 1748 PROCESSOR_SH2E, 1749 PROCESSOR_SH2A, 1750 PROCESSOR_SH3, 1751 PROCESSOR_SH3E, 1752 PROCESSOR_SH4, 1753 PROCESSOR_SH4A 1754}; 1755 1756#define sh_cpu_attr ((enum attr_cpu)sh_cpu) 1757extern enum processor_type sh_cpu; 1758 1759enum mdep_reorg_phase_e 1760{ 1761 SH_BEFORE_MDEP_REORG, 1762 SH_INSERT_USES_LABELS, 1763 SH_SHORTEN_BRANCHES0, 1764 SH_FIXUP_PCLOAD, 1765 SH_SHORTEN_BRANCHES1, 1766 SH_AFTER_MDEP_REORG 1767}; 1768 1769extern enum mdep_reorg_phase_e mdep_reorg_phase; 1770 1771/* Handle Renesas compiler's pragmas. */ 1772#define REGISTER_TARGET_PRAGMAS() do { \ 1773 c_register_pragma (0, "interrupt", sh_pr_interrupt); \ 1774 c_register_pragma (0, "trapa", sh_pr_trapa); \ 1775 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ 1776} while (0) 1777 1778extern tree sh_deferred_function_attributes; 1779extern tree *sh_deferred_function_attributes_tail; 1780 1781 1782 1783/* Instructions with unfilled delay slots take up an 1784 extra two bytes for the nop in the delay slot. 1785 sh-dsp parallel processing insns are four bytes long. */ 1786#define ADJUST_INSN_LENGTH(X, LENGTH) \ 1787 (LENGTH) += sh_insn_length_adjustment (X); 1788 1789/* Define this macro if it is advisable to hold scalars in registers 1790 in a wider mode than that declared by the program. In such cases, 1791 the value is constrained to be within the bounds of the declared 1792 type, but kept valid in the wider mode. The signedness of the 1793 extension may differ from that of the type. 1794 1795 Leaving the unsignedp unchanged gives better code than always setting it 1796 to 0. This is despite the fact that we have only signed char and short 1797 load instructions. */ 1798#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1799 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1800 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ 1801 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode; 1802 1803#define MAX_FIXED_MODE_SIZE (64) 1804 1805/* Better to allocate once the maximum space for outgoing args in the 1806 prologue rather than duplicate around each call. */ 1807#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1808 1809#define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } 1810 1811#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE) 1812 1813#define ACTUAL_NORMAL_MODE(ENTITY) \ 1814 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) 1815 1816#define NORMAL_MODE(ENTITY) \ 1817 (sh_cfun_interrupt_handler_p () \ 1818 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ 1819 : ACTUAL_NORMAL_MODE (ENTITY)) 1820 1821#define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG) 1822 1823#define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG)) 1824 1825#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM) 1826 1827#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM 1828#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) 1829 1830/* We have to distinguish between code and data, so that we apply 1831 datalabel where and only where appropriate. Use sdataN for data. */ 1832#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1833 ((TARGET_FDPIC \ 1834 ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ 1835 : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ 1836 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ 1837 | ((CODE) ? 0 : DW_EH_PE_sdata4)) 1838 1839/* Handle special EH pointer encodings. Absolute, pc-relative, and 1840 indirect are handled automatically. */ 1841#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1842 do { \ 1843 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ 1844 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ 1845 { \ 1846 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ 1847 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ 1848 if (0) goto DONE; \ 1849 } \ 1850 if (TARGET_FDPIC \ 1851 && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ 1852 { \ 1853 fputs ("\t.ualong ", FILE); \ 1854 output_addr_const (FILE, ADDR); \ 1855 if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ 1856 fputs ("@GOTFUNCDESC", FILE); \ 1857 else \ 1858 fputs ("@GOT", FILE); \ 1859 goto DONE; \ 1860 } \ 1861 } while (0) 1862 1863#if (defined CRT_BEGIN || defined CRT_END) 1864/* SH constant pool breaks the devices in crtstuff.c to control section 1865 in where code resides. We have to write it as asm code. */ 1866#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 1867 asm (SECTION_OP "\n\ 1868 mov.l 1f,r1\n\ 1869 mova 2f,r0\n\ 1870 braf r1\n\ 1871 lds r0,pr\n\ 18720: .p2align 2\n\ 18731: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ 18742:\n" TEXT_SECTION_ASM_OP); 1875#endif /* (defined CRT_BEGIN || defined CRT_END) */ 1876 1877#endif /* ! GCC_SH_H */ 1878