1; Generated by "genstr" from the template "loongarch.opt.in"
2; and definitions from "loongarch-strings".
3;
4; Please do not edit this file directly.
5; It will be automatically updated during a gcc build
6; if you change "loongarch.opt.in" or "loongarch-strings".
7;
8; Copyright (C) 2021-2022 Free Software Foundation, Inc.
9;
10; This file is part of GCC.
11;
12; GCC is free software; you can redistribute it and/or modify it under
13; the terms of the GNU General Public License as published by the Free
14; Software Foundation; either version 3, or (at your option) any later
15; version.
16;
17; GCC is distributed in the hope that it will be useful, but WITHOUT
18; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
20; License for more details.
21;
22; You should have received a copy of the GNU General Public License
23; along with GCC; see the file COPYING3.  If not see
24; <http://www.gnu.org/licenses/>.
25;
26
27; Variables (macros) that should be exported by loongarch.opt:
28;   la_opt_switches,
29;   la_opt_abi_base, la_opt_abi_ext,
30;   la_opt_cpu_arch, la_opt_cpu_tune,
31;   la_opt_fpu,
32;   la_cmodel.
33
34HeaderInclude
35config/loongarch/loongarch-opts.h
36
37HeaderInclude
38config/loongarch/loongarch-str.h
39
40Variable
41HOST_WIDE_INT la_opt_switches = 0
42
43; ISA related options
44;; Base ISA
45Enum
46Name(isa_base) Type(int)
47Basic ISAs of LoongArch:
48
49EnumValue
50Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
51
52
53;; ISA extensions / adjustments
54Enum
55Name(isa_ext_fpu) Type(int)
56FPU types of LoongArch:
57
58EnumValue
59Enum(isa_ext_fpu) String(none) Value(ISA_EXT_NOFPU)
60
61EnumValue
62Enum(isa_ext_fpu) String(32) Value(ISA_EXT_FPU32)
63
64EnumValue
65Enum(isa_ext_fpu) String(64) Value(ISA_EXT_FPU64)
66
67mfpu=
68Target RejectNegative Joined ToLower Enum(isa_ext_fpu) Var(la_opt_fpu) Init(M_OPTION_NOT_SEEN) Save
69-mfpu=FPU	Generate code for the given FPU.
70
71mfpu=0
72Target RejectNegative Alias(mfpu=,none)
73
74msoft-float
75Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_SOFTF) Negative(msingle-float)
76Prevent the use of all hardware floating-point instructions.
77
78msingle-float
79Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F32) Negative(mdouble-float)
80Restrict the use of hardware floating-point instructions to 32-bit operations.
81
82mdouble-float
83Target Driver RejectNegative Var(la_opt_switches) Mask(FORCE_F64) Negative(msoft-float)
84Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
85
86
87;; Base target models (implies ISA & tune parameters)
88Enum
89Name(cpu_type) Type(int)
90LoongArch CPU types:
91
92EnumValue
93Enum(cpu_type) String(native) Value(CPU_NATIVE)
94
95EnumValue
96Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
97
98EnumValue
99Enum(cpu_type) String(la464) Value(CPU_LA464)
100
101march=
102Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPTION_NOT_SEEN) Save
103-march=PROCESSOR	Generate code for the given PROCESSOR ISA.
104
105mtune=
106Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_tune) Init(M_OPTION_NOT_SEEN) Save
107-mtune=PROCESSOR	Generate optimized code for PROCESSOR.
108
109
110; ABI related options
111; (ISA constraints on ABI are handled dynamically)
112
113;; Base ABI
114Enum
115Name(abi_base) Type(int)
116Base ABI types for LoongArch:
117
118EnumValue
119Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D)
120
121EnumValue
122Enum(abi_base) String(lp64f) Value(ABI_BASE_LP64F)
123
124EnumValue
125Enum(abi_base) String(lp64s) Value(ABI_BASE_LP64S)
126
127mabi=
128Target RejectNegative Joined ToLower Enum(abi_base) Var(la_opt_abi_base) Init(M_OPTION_NOT_SEEN)
129-mabi=BASEABI	Generate code that conforms to the given BASEABI.
130
131;; ABI Extension
132Variable
133int la_opt_abi_ext = M_OPTION_NOT_SEEN
134
135
136mbranch-cost=
137Target RejectNegative Joined UInteger Var(loongarch_branch_cost) Save
138-mbranch-cost=COST	Set the cost of branches to roughly COST instructions.
139
140mcheck-zero-division
141Target Mask(CHECK_ZERO_DIV) Save
142Trap on integer divide by zero.
143
144mcond-move-int
145Target Var(TARGET_COND_MOVE_INT) Init(1) Save
146Conditional moves for integral are enabled.
147
148mcond-move-float
149Target Var(TARGET_COND_MOVE_FLOAT) Init(1) Save
150Conditional moves for float are enabled.
151
152mmemcpy
153Target Mask(MEMCPY) Save
154Prevent optimizing block moves, which is also the default behavior of -Os.
155
156mstrict-align
157Target Var(TARGET_STRICT_ALIGN) Init(0) Save
158Do not generate unaligned memory accesses.
159
160mmax-inline-memcpy-size=
161Target Joined RejectNegative UInteger Var(loongarch_max_inline_memcpy_size) Init(1024) Save
162-mmax-inline-memcpy-size=SIZE	Set the max size of memcpy to inline, default is 1024.
163
164; The code model option names for -mcmodel.
165Enum
166Name(cmodel) Type(int)
167The code model option names for -mcmodel:
168
169EnumValue
170Enum(cmodel) String(normal) Value(CMODEL_NORMAL)
171
172EnumValue
173Enum(cmodel) String(tiny) Value(CMODEL_TINY)
174
175EnumValue
176Enum(cmodel) String(tiny-static) Value(CMODEL_TINY_STATIC)
177
178EnumValue
179Enum(cmodel) String(large) Value(CMODEL_LARGE)
180
181EnumValue
182Enum(cmodel) String(extreme) Value(CMODEL_EXTREME)
183
184mcmodel=
185Target RejectNegative Joined Enum(cmodel) Var(la_opt_cmodel) Init(CMODEL_NORMAL) Save
186Specify the code model.
187
188mrelax
189Target Var(loongarch_mrelax) Init(HAVE_AS_MRELAX_OPTION && HAVE_AS_COND_BRANCH_RELAXATION)
190Take advantage of linker relaxations to reduce the number of instructions
191required to materialize symbol addresses.
192
193mpass-mrelax-to-as
194Target Var(loongarch_pass_mrelax_to_as) Init(HAVE_AS_MRELAX_OPTION)
195Pass -mrelax or -mno-relax option to the assembler.
196