1/* Subroutines for insn-output.cc for Renesas H8/300. 2 Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com), 4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify 9it under the terms of the GNU General Public License as published by 10the Free Software Foundation; either version 3, or (at your option) 11any later version. 12 13GCC is distributed in the hope that it will be useful, 14but WITHOUT ANY WARRANTY; without even the implied warranty of 15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16GNU General Public License for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22#define IN_TARGET_CODE 1 23 24#include "config.h" 25#include "system.h" 26#include "coretypes.h" 27#include "backend.h" 28#include "target.h" 29#include "rtl.h" 30#include "tree.h" 31#include "df.h" 32#include "memmodel.h" 33#include "tm_p.h" 34#include "stringpool.h" 35#include "attribs.h" 36#include "optabs.h" 37#include "regs.h" 38#include "emit-rtl.h" 39#include "recog.h" 40#include "diagnostic-core.h" 41#include "alias.h" 42#include "stor-layout.h" 43#include "varasm.h" 44#include "calls.h" 45#include "conditions.h" 46#include "output.h" 47#include "insn-attr.h" 48#include "flags.h" 49#include "explow.h" 50#include "expr.h" 51#include "tm-constrs.h" 52#include "builtins.h" 53 54/* This file should be included last. */ 55#include "target-def.h" 56 57/* Classifies a h8300_src_operand or h8300_dst_operand. 58 59 H8OP_IMMEDIATE 60 A constant operand of some sort. 61 62 H8OP_REGISTER 63 An ordinary register. 64 65 H8OP_MEM_ABSOLUTE 66 A memory reference with a constant address. 67 68 H8OP_MEM_BASE 69 A memory reference with a register as its address. 70 71 H8OP_MEM_COMPLEX 72 Some other kind of memory reference. */ 73enum h8300_operand_class 74{ 75 H8OP_IMMEDIATE, 76 H8OP_REGISTER, 77 H8OP_MEM_ABSOLUTE, 78 H8OP_MEM_BASE, 79 H8OP_MEM_COMPLEX, 80 NUM_H8OPS 81}; 82 83/* For a general two-operand instruction, element [X][Y] gives 84 the length of the opcode fields when the first operand has class 85 (X + 1) and the second has class Y. */ 86typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; 87 88/* Forward declarations. */ 89static const char *byte_reg (rtx, int); 90static int h8300_interrupt_function_p (tree); 91static int h8300_saveall_function_p (tree); 92static int h8300_monitor_function_p (tree); 93static int h8300_os_task_function_p (tree); 94static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT); 95static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); 96static unsigned int compute_saved_regs (void); 97static const char *cond_string (enum rtx_code); 98static unsigned int h8300_asm_insn_count (const char *); 99static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 100static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); 101static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); 102static void h8300_print_operand_address (FILE *, machine_mode, rtx); 103static void h8300_print_operand (FILE *, rtx, int); 104static bool h8300_print_operand_punct_valid_p (unsigned char code); 105static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t); 106static int h8300_and_costs (rtx); 107static int h8300_shift_costs (rtx); 108static void h8300_push_pop (int, int, bool, bool); 109static int h8300_stack_offset_p (rtx, int); 110static int h8300_ldm_stm_regno (rtx, int, int, int); 111static void h8300_reorg (void); 112static unsigned int h8300_constant_length (rtx); 113static unsigned int h8300_displacement_length (rtx, int); 114static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); 115static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); 116static unsigned int h8300_unary_length (rtx); 117static unsigned int h8300_short_immediate_length (rtx); 118static unsigned int h8300_bitfield_length (rtx, rtx); 119static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); 120static bool h8300_short_move_mem_p (rtx, enum rtx_code); 121static unsigned int h8300_move_length (rtx *, const h8300_length_table *); 122static bool h8300_hard_regno_scratch_ok (unsigned int); 123static rtx h8300_get_index (rtx, machine_mode mode, int *); 124 125/* CPU_TYPE, says what cpu we're compiling for. */ 126int cpu_type; 127 128/* True if a #pragma interrupt has been seen for the current function. */ 129static int pragma_interrupt; 130 131/* True if a #pragma saveall has been seen for the current function. */ 132static int pragma_saveall; 133 134static const char *const names_big[] = 135{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc" }; 136 137static const char *const names_extended[] = 138{ "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "cc" }; 139 140static const char *const names_upper_extended[] = 141{ "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "cc" }; 142 143/* Points to one of the above. */ 144/* ??? The above could be put in an array indexed by CPU_TYPE. */ 145const char * const *h8_reg_names; 146 147/* Various operations needed by the following, indexed by CPU_TYPE. */ 148 149const char *h8_push_op, *h8_pop_op, *h8_mov_op; 150 151/* Value of MOVE_RATIO. */ 152int h8300_move_ratio; 153 154/* See below where shifts are handled for explanation of this enum. */ 155 156enum shift_alg 157{ 158 SHIFT_INLINE, 159 SHIFT_ROT_AND, 160 SHIFT_SPECIAL, 161 SHIFT_LOOP 162}; 163 164/* Symbols of the various shifts which can be used as indices. */ 165 166enum shift_type 167{ 168 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 169}; 170 171/* Macros to keep the shift algorithm tables small. */ 172#define INL SHIFT_INLINE 173#define ROT SHIFT_ROT_AND 174#define LOP SHIFT_LOOP 175#define SPC SHIFT_SPECIAL 176 177/* The shift algorithms for each machine, mode, shift type, and shift 178 count are defined below. The three tables below correspond to 179 QImode, HImode, and SImode, respectively. Each table is organized 180 by, in the order of indices, machine, shift type, and shift count. */ 181 182static enum shift_alg shift_alg_qi[2][3][8] = { 183 { 184 /* TARGET_H8300H */ 185 /* 0 1 2 3 4 5 6 7 */ 186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 188 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 189 }, 190 { 191 /* TARGET_H8300S */ 192 /* 0 1 2 3 4 5 6 7 */ 193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ 194 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ 195 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ 196 } 197}; 198 199static enum shift_alg shift_alg_hi[2][3][16] = { 200 { 201 /* TARGET_H8300H */ 202 /* 0 1 2 3 4 5 6 7 */ 203 /* 8 9 10 11 12 13 14 15 */ 204 { INL, INL, INL, INL, INL, INL, INL, SPC, 205 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 206 { INL, INL, INL, INL, INL, INL, INL, SPC, 207 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 208 { INL, INL, INL, INL, INL, INL, INL, SPC, 209 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 210 }, 211 { 212 /* TARGET_H8300S */ 213 /* 0 1 2 3 4 5 6 7 */ 214 /* 8 9 10 11 12 13 14 15 */ 215 { INL, INL, INL, INL, INL, INL, INL, INL, 216 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 217 { INL, INL, INL, INL, INL, INL, INL, INL, 218 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 219 { INL, INL, INL, INL, INL, INL, INL, INL, 220 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 221 } 222}; 223 224static enum shift_alg shift_alg_si[2][3][32] = { 225 { 226 /* TARGET_H8300H */ 227 /* 0 1 2 3 4 5 6 7 */ 228 /* 8 9 10 11 12 13 14 15 */ 229 /* 16 17 18 19 20 21 22 23 */ 230 /* 24 25 26 27 28 29 30 31 */ 231 { INL, INL, INL, INL, INL, INL, INL, LOP, 232 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 233 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 234 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 235 { INL, INL, INL, INL, INL, INL, INL, LOP, 236 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 237 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 238 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 239 { INL, INL, INL, INL, INL, INL, INL, LOP, 240 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 242 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 243 }, 244 { 245 /* TARGET_H8300S */ 246 /* 0 1 2 3 4 5 6 7 */ 247 /* 8 9 10 11 12 13 14 15 */ 248 /* 16 17 18 19 20 21 22 23 */ 249 /* 24 25 26 27 28 29 30 31 */ 250 { INL, INL, INL, INL, INL, INL, INL, INL, 251 INL, INL, INL, INL, INL, INL, INL, SPC, 252 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 253 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 254 { INL, INL, INL, INL, INL, INL, INL, INL, 255 INL, INL, INL, INL, INL, INL, INL, SPC, 256 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 257 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 258 { INL, INL, INL, INL, INL, INL, INL, INL, 259 INL, INL, INL, INL, INL, INL, INL, SPC, 260 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 261 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 262 } 263}; 264 265#undef INL 266#undef ROT 267#undef LOP 268#undef SPC 269 270enum h8_cpu 271{ 272 H8_300H, 273 H8_S 274}; 275 276/* Initialize various cpu specific globals at start up. */ 277 278static void 279h8300_option_override (void) 280{ 281 static const char *const h8_push_ops[2] = { "push" , "push.l" }; 282 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; 283 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; 284 285 /* For this we treat the H8/300H and H8S the same. */ 286 cpu_type = (int) CPU_H8300H; 287 h8_reg_names = names_extended; 288 h8_push_op = h8_push_ops[cpu_type]; 289 h8_pop_op = h8_pop_ops[cpu_type]; 290 h8_mov_op = h8_mov_ops[cpu_type]; 291 292 /* If we're compiling for the H8/S, then turn off H8/300H. */ 293 if (TARGET_H8300S) 294 target_flags &= ~MASK_H8300H; 295 296 if (!TARGET_H8300S && TARGET_MAC) 297 { 298 error ("%<-ms2600%> is used without %<-ms%>"); 299 target_flags |= MASK_H8300S_1; 300 } 301 302 if (! TARGET_H8300S && TARGET_EXR) 303 { 304 error ("%<-mexr%> is used without %<-ms%>"); 305 target_flags |= MASK_H8300S_1; 306 } 307 308 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) 309 { 310 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>"); 311 target_flags |= MASK_H8300S_1; 312 } 313 314 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) 315 { 316 warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or " 317 "%<-msx%> - option ignored"); 318 } 319 320#ifdef H8300_LINUX 321 if ((TARGET_NORMAL_MODE)) 322 { 323 error ("%<-mn%> is not supported for linux targets"); 324 target_flags ^= MASK_NORMAL_MODE; 325 } 326#endif 327 328 /* Some of the shifts are optimized for speed by default. 329 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html 330 If optimizing for size, change shift_alg for those shift to 331 SHIFT_LOOP. */ 332 if (optimize_size) 333 { 334 /* H8/300H */ 335 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 336 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 337 338 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 339 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 340 341 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 342 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 343 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 344 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 345 346 shift_alg_si[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 347 shift_alg_si[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 348 shift_alg_si[H8_300H][SHIFT_ASHIFT][20] = SHIFT_LOOP; 349 shift_alg_si[H8_300H][SHIFT_ASHIFT][21] = SHIFT_LOOP; 350 shift_alg_si[H8_300H][SHIFT_ASHIFT][22] = SHIFT_LOOP; 351 shift_alg_si[H8_300H][SHIFT_ASHIFT][23] = SHIFT_LOOP; 352 shift_alg_si[H8_300H][SHIFT_ASHIFT][25] = SHIFT_LOOP; 353 shift_alg_si[H8_300H][SHIFT_ASHIFT][26] = SHIFT_LOOP; 354 shift_alg_si[H8_300H][SHIFT_ASHIFT][27] = SHIFT_LOOP; 355 356 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 357 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 358 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][20] = SHIFT_LOOP; 359 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][21] = SHIFT_LOOP; 360 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][22] = SHIFT_LOOP; 361 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][23] = SHIFT_LOOP; 362 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][25] = SHIFT_LOOP; 363 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][26] = SHIFT_LOOP; 364 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][27] = SHIFT_LOOP; 365 366 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 367 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 368 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][20] = SHIFT_LOOP; 369 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][21] = SHIFT_LOOP; 370 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][22] = SHIFT_LOOP; 371 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][23] = SHIFT_LOOP; 372 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][25] = SHIFT_LOOP; 373 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][26] = SHIFT_LOOP; 374 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][27] = SHIFT_LOOP; 375 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][28] = SHIFT_LOOP; 376 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][29] = SHIFT_LOOP; 377 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][30] = SHIFT_LOOP; 378 379 /* H8S */ 380 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 381 382 shift_alg_si[H8_S][SHIFT_ASHIFT][11] = SHIFT_LOOP; 383 shift_alg_si[H8_S][SHIFT_ASHIFT][12] = SHIFT_LOOP; 384 shift_alg_si[H8_S][SHIFT_ASHIFT][13] = SHIFT_LOOP; 385 shift_alg_si[H8_S][SHIFT_ASHIFT][14] = SHIFT_LOOP; 386 shift_alg_si[H8_S][SHIFT_ASHIFT][22] = SHIFT_LOOP; 387 shift_alg_si[H8_S][SHIFT_ASHIFT][23] = SHIFT_LOOP; 388 shift_alg_si[H8_S][SHIFT_ASHIFT][26] = SHIFT_LOOP; 389 shift_alg_si[H8_S][SHIFT_ASHIFT][27] = SHIFT_LOOP; 390 391 shift_alg_si[H8_S][SHIFT_LSHIFTRT][11] = SHIFT_LOOP; 392 shift_alg_si[H8_S][SHIFT_LSHIFTRT][12] = SHIFT_LOOP; 393 shift_alg_si[H8_S][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; 394 shift_alg_si[H8_S][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; 395 shift_alg_si[H8_S][SHIFT_LSHIFTRT][22] = SHIFT_LOOP; 396 shift_alg_si[H8_S][SHIFT_LSHIFTRT][23] = SHIFT_LOOP; 397 shift_alg_si[H8_S][SHIFT_LSHIFTRT][26] = SHIFT_LOOP; 398 shift_alg_si[H8_S][SHIFT_LSHIFTRT][27] = SHIFT_LOOP; 399 400 shift_alg_si[H8_S][SHIFT_ASHIFTRT][11] = SHIFT_LOOP; 401 shift_alg_si[H8_S][SHIFT_ASHIFTRT][12] = SHIFT_LOOP; 402 shift_alg_si[H8_S][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 403 shift_alg_si[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 404 shift_alg_si[H8_S][SHIFT_ASHIFTRT][22] = SHIFT_LOOP; 405 shift_alg_si[H8_S][SHIFT_ASHIFTRT][23] = SHIFT_LOOP; 406 shift_alg_si[H8_S][SHIFT_ASHIFTRT][26] = SHIFT_LOOP; 407 shift_alg_si[H8_S][SHIFT_ASHIFTRT][27] = SHIFT_LOOP; 408 shift_alg_si[H8_S][SHIFT_ASHIFTRT][28] = SHIFT_LOOP; 409 shift_alg_si[H8_S][SHIFT_ASHIFTRT][29] = SHIFT_LOOP; 410 shift_alg_si[H8_S][SHIFT_ASHIFTRT][30] = SHIFT_LOOP; 411 } 412 413 /* Work out a value for MOVE_RATIO. */ 414 if (!TARGET_H8300SX) 415 { 416 /* Memory-memory moves are quite expensive without the 417 h8sx instructions. */ 418 h8300_move_ratio = 3; 419 } 420 else if (flag_omit_frame_pointer) 421 { 422 /* movmd sequences are fairly cheap when er6 isn't fixed. They can 423 sometimes be as short as two individual memory-to-memory moves, 424 but since they use all the call-saved registers, it seems better 425 to allow up to three moves here. */ 426 h8300_move_ratio = 4; 427 } 428 else if (optimize_size) 429 { 430 /* In this case we don't use movmd sequences since they tend 431 to be longer than calls to memcpy(). Memory-to-memory 432 moves are cheaper than for !TARGET_H8300SX, so it makes 433 sense to have a slightly higher threshold. */ 434 h8300_move_ratio = 4; 435 } 436 else 437 { 438 /* We use movmd sequences for some moves since it can be quicker 439 than calling memcpy(). The sequences will need to save and 440 restore er6 though, so bump up the cost. */ 441 h8300_move_ratio = 6; 442 } 443 444 /* This target defaults to strict volatile bitfields. */ 445 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) 446 flag_strict_volatile_bitfields = 1; 447} 448 449/* Return the byte register name for a register rtx X. B should be 0 450 if you want a lower byte register. B should be 1 if you want an 451 upper byte register. */ 452 453static const char * 454byte_reg (rtx x, int b) 455{ 456 static const char *const names_small[] = { 457 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 458 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" 459 }; 460 461 gcc_assert (REG_P (x)); 462 463 return names_small[REGNO (x) * 2 + b]; 464} 465 466/* REGNO must be saved/restored across calls if this macro is true. */ 467 468#define WORD_REG_USED(regno) \ 469 (regno < SP_REG \ 470 /* No need to save registers if this function will not return. */ \ 471 && ! TREE_THIS_VOLATILE (current_function_decl) \ 472 && (h8300_saveall_function_p (current_function_decl) \ 473 /* Save any call saved register that was used. */ \ 474 || (df_regs_ever_live_p (regno) \ 475 && !call_used_or_fixed_reg_p (regno)) \ 476 /* Save the frame pointer if it was used. */ \ 477 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ 478 /* Save any register used in an interrupt handler. */ \ 479 || (h8300_current_function_interrupt_function_p () \ 480 && df_regs_ever_live_p (regno)) \ 481 /* Save call clobbered registers in non-leaf interrupt \ 482 handlers. */ \ 483 || (h8300_current_function_interrupt_function_p () \ 484 && call_used_or_fixed_reg_p (regno) \ 485 && !crtl->is_leaf))) 486 487/* We use this to wrap all emitted insns in the prologue. */ 488static rtx_insn * 489F (rtx_insn *x, bool set_it) 490{ 491 if (set_it) 492 RTX_FRAME_RELATED_P (x) = 1; 493 return x; 494} 495 496/* Mark all the subexpressions of the PARALLEL rtx PAR as 497 frame-related. Return PAR. 498 499 dwarf2out.cc:dwarf2out_frame_debug_expr ignores sub-expressions of a 500 PARALLEL rtx other than the first if they do not have the 501 FRAME_RELATED flag set on them. */ 502static rtx 503Fpa (rtx par) 504{ 505 int len = XVECLEN (par, 0); 506 int i; 507 508 for (i = 0; i < len; i++) 509 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1; 510 511 return par; 512} 513 514/* Output assembly language to FILE for the operation OP with operand size 515 SIZE to adjust the stack pointer. */ 516 517static void 518h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size) 519{ 520 /* If the frame size is 0, we don't have anything to do. */ 521 if (size == 0) 522 return; 523 524 /* The stack adjustment made here is further optimized by the 525 splitter. In case of H8/300, the splitter always splits the 526 addition emitted here to make the adjustment interrupt-safe. 527 FIXME: We don't always tag those, because we don't know what 528 the splitter will do. */ 529 if (Pmode == HImode) 530 { 531 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, 532 stack_pointer_rtx, 533 GEN_INT (sign * size))); 534 if (size < 4) 535 F (x, 0); 536 } 537 else 538 F (emit_insn (gen_addsi3 (stack_pointer_rtx, 539 stack_pointer_rtx, GEN_INT (sign * size))), 0); 540} 541 542/* Round up frame size SIZE. */ 543 544static HOST_WIDE_INT 545round_frame_size (HOST_WIDE_INT size) 546{ 547 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) 548 & -STACK_BOUNDARY / BITS_PER_UNIT); 549} 550 551/* Compute which registers to push/pop. 552 Return a bit vector of registers. */ 553 554static unsigned int 555compute_saved_regs (void) 556{ 557 unsigned int saved_regs = 0; 558 int regno; 559 560 /* Construct a bit vector of registers to be pushed/popped. */ 561 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 562 { 563 if (WORD_REG_USED (regno)) 564 saved_regs |= 1 << regno; 565 } 566 567 /* Don't push/pop the frame pointer as it is treated separately. */ 568 if (frame_pointer_needed) 569 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); 570 571 return saved_regs; 572} 573 574/* Emit an insn to push register RN. */ 575 576static rtx 577push (int rn) 578{ 579 rtx reg = gen_rtx_REG (word_mode, rn); 580 rtx x; 581 582 if (!TARGET_NORMAL_MODE) 583 x = gen_push_h8300hs_advanced (reg); 584 else 585 x = gen_push_h8300hs_normal (reg); 586 x = F (emit_insn (x), 0); 587 add_reg_note (x, REG_INC, stack_pointer_rtx); 588 return x; 589} 590 591/* Emit an insn to pop register RN. */ 592 593static rtx 594pop (int rn) 595{ 596 rtx reg = gen_rtx_REG (word_mode, rn); 597 rtx x; 598 599 if (!TARGET_NORMAL_MODE) 600 x = gen_pop_h8300hs_advanced (reg); 601 else 602 x = gen_pop_h8300hs_normal (reg); 603 x = emit_insn (x); 604 add_reg_note (x, REG_INC, stack_pointer_rtx); 605 return x; 606} 607 608/* Emit an instruction to push or pop NREGS consecutive registers 609 starting at register REGNO. POP_P selects a pop rather than a 610 push and RETURN_P is true if the instruction should return. 611 612 It must be possible to do the requested operation in a single 613 instruction. If NREGS == 1 && !RETURN_P, use a normal push 614 or pop insn. Otherwise emit a parallel of the form: 615 616 (parallel 617 [(return) ;; if RETURN_P 618 (save or restore REGNO) 619 (save or restore REGNO + 1) 620 ... 621 (save or restore REGNO + NREGS - 1) 622 (set sp (plus sp (const_int adjust)))] */ 623 624static void 625h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) 626{ 627 int i, j; 628 rtvec vec; 629 rtx sp, offset, x; 630 631 /* See whether we can use a simple push or pop. */ 632 if (!return_p && nregs == 1) 633 { 634 if (pop_p) 635 pop (regno); 636 else 637 push (regno); 638 return; 639 } 640 641 /* We need one element for the return insn, if present, one for each 642 register, and one for stack adjustment. */ 643 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); 644 sp = stack_pointer_rtx; 645 i = 0; 646 647 /* Add the return instruction. */ 648 if (return_p) 649 { 650 RTVEC_ELT (vec, i) = ret_rtx; 651 i++; 652 } 653 654 /* Add the register moves. */ 655 for (j = 0; j < nregs; j++) 656 { 657 rtx lhs, rhs; 658 659 if (pop_p) 660 { 661 /* Register REGNO + NREGS - 1 is popped first. Before the 662 stack adjustment, its slot is at address @sp. */ 663 lhs = gen_rtx_REG (SImode, regno + j); 664 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, 665 (nregs - j - 1) * 4)); 666 } 667 else 668 { 669 /* Register REGNO is pushed first and will be stored at @(-4,sp). */ 670 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); 671 rhs = gen_rtx_REG (SImode, regno + j); 672 } 673 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs); 674 } 675 676 /* Add the stack adjustment. */ 677 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); 678 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset)); 679 680 x = gen_rtx_PARALLEL (VOIDmode, vec); 681 if (!pop_p) 682 x = Fpa (x); 683 684 if (return_p) 685 emit_jump_insn (x); 686 else 687 emit_insn (x); 688} 689 690/* Return true if X has the value sp + OFFSET. */ 691 692static int 693h8300_stack_offset_p (rtx x, int offset) 694{ 695 if (offset == 0) 696 return x == stack_pointer_rtx; 697 698 return (GET_CODE (x) == PLUS 699 && XEXP (x, 0) == stack_pointer_rtx 700 && GET_CODE (XEXP (x, 1)) == CONST_INT 701 && INTVAL (XEXP (x, 1)) == offset); 702} 703 704/* A subroutine of h8300_ldm_stm_parallel. X is one pattern in 705 something that may be an ldm or stm instruction. If it fits 706 the required template, return the register it loads or stores, 707 otherwise return -1. 708 709 LOAD_P is true if X should be a load, false if it should be a store. 710 NREGS is the number of registers that the whole instruction is expected 711 to load or store. INDEX is the index of the register that X should 712 load or store, relative to the lowest-numbered register. */ 713 714static int 715h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) 716{ 717 int regindex, memindex, offset; 718 719 if (load_p) 720 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; 721 else 722 memindex = 0, regindex = 1, offset = (index + 1) * -4; 723 724 if (GET_CODE (x) == SET 725 && GET_CODE (XEXP (x, regindex)) == REG 726 && GET_CODE (XEXP (x, memindex)) == MEM 727 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) 728 return REGNO (XEXP (x, regindex)); 729 730 return -1; 731} 732 733/* Return true if the elements of VEC starting at FIRST describe an 734 ldm or stm instruction (LOAD_P says which). */ 735 736int 737h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) 738{ 739 rtx last; 740 int nregs, i, regno, adjust; 741 742 /* There must be a stack adjustment, a register move, and at least one 743 other operation (a return or another register move). */ 744 if (GET_NUM_ELEM (vec) < 3) 745 return false; 746 747 /* Get the range of registers to be pushed or popped. */ 748 nregs = GET_NUM_ELEM (vec) - first - 1; 749 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); 750 751 /* Check that the call to h8300_ldm_stm_regno succeeded and 752 that we're only dealing with GPRs. */ 753 if (regno < 0 || regno + nregs > 8) 754 return false; 755 756 /* 2-register h8s instructions must start with an even-numbered register. 757 3- and 4-register instructions must start with er0 or er4. */ 758 if (!TARGET_H8300SX) 759 { 760 if ((regno & 1) != 0) 761 return false; 762 if (nregs > 2 && (regno & 3) != 0) 763 return false; 764 } 765 766 /* Check the other loads or stores. */ 767 for (i = 1; i < nregs; i++) 768 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) 769 != regno + i) 770 return false; 771 772 /* Check the stack adjustment. */ 773 last = RTVEC_ELT (vec, first + nregs); 774 adjust = (load_p ? nregs : -nregs) * 4; 775 return (GET_CODE (last) == SET 776 && SET_DEST (last) == stack_pointer_rtx 777 && h8300_stack_offset_p (SET_SRC (last), adjust)); 778} 779 780/* This is what the stack looks like after the prolog of 781 a function with a frame has been set up: 782 783 <args> 784 PC 785 FP <- fp 786 <locals> 787 <saved registers> <- sp 788 789 This is what the stack looks like after the prolog of 790 a function which doesn't have a frame: 791 792 <args> 793 PC 794 <locals> 795 <saved registers> <- sp 796*/ 797 798/* Generate RTL code for the function prologue. */ 799 800void 801h8300_expand_prologue (void) 802{ 803 int regno; 804 int saved_regs; 805 int n_regs; 806 807 /* If the current function has the OS_Task attribute set, then 808 we have a naked prologue. */ 809 if (h8300_os_task_function_p (current_function_decl)) 810 return; 811 812 if (h8300_monitor_function_p (current_function_decl)) 813 /* The monitor function act as normal functions, which means it 814 can accept parameters and return values. In addition to this, 815 interrupts are masked in prologue and return with "rte" in epilogue. */ 816 emit_insn (gen_monitor_prologue ()); 817 818 if (frame_pointer_needed) 819 { 820 /* Push fp. */ 821 push (HARD_FRAME_POINTER_REGNUM); 822 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), 0); 823 } 824 825 /* Push the rest of the registers in ascending order. */ 826 saved_regs = compute_saved_regs (); 827 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) 828 { 829 n_regs = 1; 830 if (saved_regs & (1 << regno)) 831 { 832 if (TARGET_H8300S) 833 { 834 /* See how many registers we can push at the same time. */ 835 if ((TARGET_H8300SX || (regno & 3) == 0) 836 && ((saved_regs >> regno) & 0x0f) == 0x0f) 837 n_regs = 4; 838 839 else if ((TARGET_H8300SX || (regno & 3) == 0) 840 && ((saved_regs >> regno) & 0x07) == 0x07) 841 n_regs = 3; 842 843 else if ((TARGET_H8300SX || (regno & 1) == 0) 844 && ((saved_regs >> regno) & 0x03) == 0x03) 845 n_regs = 2; 846 } 847 848 h8300_push_pop (regno, n_regs, false, false); 849 } 850 } 851 852 /* Leave room for locals. */ 853 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ())); 854 855 if (flag_stack_usage_info) 856 current_function_static_stack_size 857 = round_frame_size (get_frame_size ()) 858 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD) 859 + (frame_pointer_needed ? UNITS_PER_WORD : 0); 860} 861 862/* Return nonzero if we can use "rts" for the function currently being 863 compiled. */ 864 865int 866h8300_can_use_return_insn_p (void) 867{ 868 return (reload_completed 869 && !frame_pointer_needed 870 && get_frame_size () == 0 871 && compute_saved_regs () == 0); 872} 873 874/* Generate RTL code for the function epilogue. */ 875 876void 877h8300_expand_epilogue (bool sibcall_p) 878{ 879 int regno; 880 int saved_regs; 881 int n_regs; 882 HOST_WIDE_INT frame_size; 883 bool returned_p; 884 885 if (h8300_os_task_function_p (current_function_decl)) 886 /* OS_Task epilogues are nearly naked -- they just have an 887 rts instruction. */ 888 return; 889 890 frame_size = round_frame_size (get_frame_size ()); 891 returned_p = false; 892 893 /* Deallocate locals. */ 894 h8300_emit_stack_adjustment (1, frame_size); 895 896 /* Pop the saved registers in descending order. */ 897 saved_regs = compute_saved_regs (); 898 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) 899 { 900 n_regs = 1; 901 if (saved_regs & (1 << regno)) 902 { 903 if (TARGET_H8300S) 904 { 905 /* See how many registers we can pop at the same time. */ 906 if ((TARGET_H8300SX || (regno & 3) == 3) 907 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) 908 n_regs = 4; 909 910 else if ((TARGET_H8300SX || (regno & 3) == 2) 911 && ((saved_regs << 2 >> regno) & 0x07) == 0x07) 912 n_regs = 3; 913 914 else if ((TARGET_H8300SX || (regno & 1) == 1) 915 && ((saved_regs << 1 >> regno) & 0x03) == 0x03) 916 n_regs = 2; 917 } 918 919 /* See if this pop would be the last insn before the return. 920 If so, use rte/l or rts/l instead of pop or ldm.l. */ 921 if (TARGET_H8300SX 922 && !sibcall_p 923 && !frame_pointer_needed 924 && frame_size == 0 925 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) 926 returned_p = true; 927 928 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); 929 } 930 } 931 932 /* Pop frame pointer if we had one. */ 933 if (frame_pointer_needed) 934 { 935 if (TARGET_H8300SX && !sibcall_p) 936 returned_p = true; 937 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); 938 } 939 940 if (!returned_p && !sibcall_p) 941 emit_jump_insn (ret_rtx); 942} 943 944/* Return nonzero if the current function is an interrupt 945 function. */ 946 947int 948h8300_current_function_interrupt_function_p (void) 949{ 950 return (h8300_interrupt_function_p (current_function_decl)); 951} 952 953int 954h8300_current_function_monitor_function_p () 955{ 956 return (h8300_monitor_function_p (current_function_decl)); 957} 958 959/* Output assembly code for the start of the file. */ 960 961static void 962h8300_file_start (void) 963{ 964 default_file_start (); 965 966 if (TARGET_H8300SX) 967 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); 968 else if (TARGET_H8300S) 969 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); 970 else if (TARGET_H8300H) 971 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); 972} 973 974/* Output assembly language code for the end of file. */ 975 976static void 977h8300_file_end (void) 978{ 979 fputs ("\t.end\n", asm_out_file); 980} 981 982/* Split an add of a small constant into two adds/subs insns. 983 984 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec 985 instead of adds/subs. */ 986 987void 988split_adds_subs (machine_mode mode, rtx *operands) 989{ 990 HOST_WIDE_INT val = INTVAL (operands[1]); 991 rtx reg = operands[0]; 992 HOST_WIDE_INT sign = 1; 993 HOST_WIDE_INT amount; 994 rtx (*gen_add) (rtx, rtx, rtx); 995 996 /* Force VAL to be positive so that we do not have to consider the 997 sign. */ 998 if (val < 0) 999 { 1000 val = -val; 1001 sign = -1; 1002 } 1003 1004 switch (mode) 1005 { 1006 case E_HImode: 1007 gen_add = gen_addhi3; 1008 break; 1009 1010 case E_SImode: 1011 gen_add = gen_addsi3; 1012 break; 1013 1014 default: 1015 gcc_unreachable (); 1016 } 1017 1018 /* Try different amounts in descending order. */ 1019 for (amount = 4; amount > 0; amount /= 2) 1020 { 1021 for (; val >= amount; val -= amount) 1022 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); 1023 } 1024 1025 return; 1026} 1027 1028/* Handle machine specific pragmas for compatibility with existing 1029 compilers for the H8/300. 1030 1031 pragma saveall generates prologue/epilogue code which saves and 1032 restores all the registers on function entry. 1033 1034 pragma interrupt saves and restores all registers, and exits with 1035 an rte instruction rather than an rts. A pointer to a function 1036 with this attribute may be safely used in an interrupt vector. */ 1037 1038void 1039h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1040{ 1041 pragma_interrupt = 1; 1042} 1043 1044void 1045h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1046{ 1047 pragma_saveall = 1; 1048} 1049 1050/* If the next function argument ARG is to be passed in a register, return 1051 a reg RTX for the hard register in which to pass the argument. CUM 1052 represents the state after the last argument. If the argument is to 1053 be pushed, NULL_RTX is returned. 1054 1055 On the H8/300 all normal args are pushed, unless -mquickcall in which 1056 case the first 3 arguments are passed in registers. */ 1057 1058static rtx 1059h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) 1060{ 1061 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1062 1063 static const char *const hand_list[] = { 1064 "__main", 1065 "__cmpsi2", 1066 "__divhi3", 1067 "__modhi3", 1068 "__udivhi3", 1069 "__umodhi3", 1070 "__divsi3", 1071 "__modsi3", 1072 "__udivsi3", 1073 "__umodsi3", 1074 "__mulhi3", 1075 "__mulsi3", 1076 "__reg_memcpy", 1077 "__reg_memset", 1078 "__ucmpsi2", 1079 0, 1080 }; 1081 1082 rtx result = NULL_RTX; 1083 const char *fname; 1084 int regpass = 0; 1085 1086 /* Never pass unnamed arguments in registers. */ 1087 if (!arg.named) 1088 return NULL_RTX; 1089 1090 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 1091 if (TARGET_QUICKCALL) 1092 regpass = 3; 1093 1094 /* If calling hand written assembler, use 4 regs of args. */ 1095 if (cum->libcall) 1096 { 1097 const char * const *p; 1098 1099 fname = XSTR (cum->libcall, 0); 1100 1101 /* See if this libcall is one of the hand coded ones. */ 1102 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 1103 ; 1104 1105 if (*p) 1106 regpass = 4; 1107 } 1108 1109 if (regpass) 1110 { 1111 int size = arg.promoted_size_in_bytes (); 1112 if (size + cum->nbytes <= regpass * UNITS_PER_WORD 1113 && cum->nbytes / UNITS_PER_WORD <= 3) 1114 result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD); 1115 } 1116 1117 return result; 1118} 1119 1120/* Update the data in CUM to advance over argument ARG. */ 1121 1122static void 1123h8300_function_arg_advance (cumulative_args_t cum_v, 1124 const function_arg_info &arg) 1125{ 1126 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1127 1128 cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) 1129 & -UNITS_PER_WORD); 1130} 1131 1132 1133/* Implements TARGET_REGISTER_MOVE_COST. 1134 1135 Any SI register-to-register move may need to be reloaded, 1136 so inmplement h8300_register_move_cost to return > 2 so that reload never 1137 shortcuts. */ 1138 1139static int 1140h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1141 reg_class_t from, reg_class_t to) 1142{ 1143 if (from == MAC_REGS || to == MAC_REG) 1144 return 6; 1145 else 1146 return 3; 1147} 1148 1149/* Compute the cost of an and insn. */ 1150 1151static int 1152h8300_and_costs (rtx x) 1153{ 1154 rtx operands[4]; 1155 1156 if (GET_MODE (x) == QImode) 1157 return 1; 1158 1159 if (GET_MODE (x) != HImode 1160 && GET_MODE (x) != SImode) 1161 return 100; 1162 1163 operands[0] = NULL; 1164 operands[1] = XEXP (x, 0); 1165 operands[2] = XEXP (x, 1); 1166 operands[3] = x; 1167 return compute_logical_op_length (GET_MODE (x), AND, operands, NULL) / 2; 1168} 1169 1170/* Compute the cost of a shift insn. */ 1171 1172static int 1173h8300_shift_costs (rtx x) 1174{ 1175 rtx operands[3]; 1176 1177 if (GET_MODE (x) != QImode 1178 && GET_MODE (x) != HImode 1179 && GET_MODE (x) != SImode) 1180 return 100; 1181 1182 operands[0] = gen_rtx_REG (GET_MODE (x), 0); 1183 operands[1] = NULL; 1184 operands[2] = XEXP (x, 1); 1185 return compute_a_shift_length (operands, GET_CODE (x)) / 2; 1186} 1187 1188/* Worker function for TARGET_RTX_COSTS. */ 1189 1190static bool 1191h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, 1192 int opno ATTRIBUTE_UNUSED, int *total, bool speed) 1193{ 1194 int code = GET_CODE (x); 1195 1196 if (TARGET_H8300SX && outer_code == MEM) 1197 { 1198 /* Estimate the number of execution states needed to calculate 1199 the address. */ 1200 if (register_operand (x, VOIDmode) 1201 || GET_CODE (x) == POST_INC 1202 || GET_CODE (x) == POST_DEC 1203 || CONSTANT_P (x)) 1204 *total = 0; 1205 else 1206 *total = COSTS_N_INSNS (1); 1207 return true; 1208 } 1209 1210 switch (code) 1211 { 1212 case CONST_INT: 1213 { 1214 HOST_WIDE_INT n = INTVAL (x); 1215 1216 if (TARGET_H8300SX) 1217 { 1218 /* Constant operands need the same number of processor 1219 states as register operands. Although we could try to 1220 use a size-based cost for !speed, the lack of 1221 of a mode makes the results very unpredictable. */ 1222 *total = 0; 1223 return true; 1224 } 1225 if (n >= -4 && n <= 4) 1226 { 1227 switch ((int) n) 1228 { 1229 case 0: 1230 *total = 0; 1231 return true; 1232 case 1: 1233 case 2: 1234 case -1: 1235 case -2: 1236 *total = 0 + (outer_code == SET); 1237 return true; 1238 case 4: 1239 case -4: 1240 *total = 0 + (outer_code == SET); 1241 return true; 1242 } 1243 } 1244 *total = 1; 1245 return true; 1246 } 1247 1248 case CONST: 1249 case LABEL_REF: 1250 case SYMBOL_REF: 1251 if (TARGET_H8300SX) 1252 { 1253 /* See comment for CONST_INT. */ 1254 *total = 0; 1255 return true; 1256 } 1257 *total = 3; 1258 return true; 1259 1260 case CONST_DOUBLE: 1261 *total = 20; 1262 return true; 1263 1264 case COMPARE: 1265 case NE: 1266 case EQ: 1267 case GE: 1268 case GT: 1269 case LE: 1270 case LT: 1271 case GEU: 1272 case GTU: 1273 case LEU: 1274 case LTU: 1275 if (XEXP (x, 1) == const0_rtx) 1276 *total = 0; 1277 return false; 1278 1279 case AND: 1280 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) 1281 || !h8300_src_operand (XEXP (x, 1), VOIDmode)) 1282 return false; 1283 *total = COSTS_N_INSNS (h8300_and_costs (x)); 1284 return true; 1285 1286 /* We say that MOD and DIV are so expensive because otherwise we'll 1287 generate some really horrible code for division of a power of two. */ 1288 case MOD: 1289 case DIV: 1290 case UMOD: 1291 case UDIV: 1292 if (TARGET_H8300SX) 1293 switch (GET_MODE (x)) 1294 { 1295 case E_QImode: 1296 case E_HImode: 1297 *total = COSTS_N_INSNS (!speed ? 4 : 10); 1298 return false; 1299 1300 case E_SImode: 1301 *total = COSTS_N_INSNS (!speed ? 4 : 18); 1302 return false; 1303 1304 default: 1305 break; 1306 } 1307 *total = COSTS_N_INSNS (12); 1308 return true; 1309 1310 case MULT: 1311 if (TARGET_H8300SX) 1312 switch (GET_MODE (x)) 1313 { 1314 case E_QImode: 1315 case E_HImode: 1316 *total = COSTS_N_INSNS (2); 1317 return false; 1318 1319 case E_SImode: 1320 *total = COSTS_N_INSNS (5); 1321 return false; 1322 1323 default: 1324 break; 1325 } 1326 *total = COSTS_N_INSNS (4); 1327 return true; 1328 1329 case ASHIFT: 1330 case ASHIFTRT: 1331 case LSHIFTRT: 1332 if (h8sx_binary_shift_operator (x, VOIDmode)) 1333 { 1334 *total = COSTS_N_INSNS (2); 1335 return false; 1336 } 1337 else if (h8sx_unary_shift_operator (x, VOIDmode)) 1338 { 1339 *total = COSTS_N_INSNS (1); 1340 return false; 1341 } 1342 *total = COSTS_N_INSNS (h8300_shift_costs (x)); 1343 return true; 1344 1345 case ROTATE: 1346 case ROTATERT: 1347 if (GET_MODE (x) == HImode) 1348 *total = 2; 1349 else 1350 *total = 8; 1351 return true; 1352 1353 default: 1354 *total = COSTS_N_INSNS (1); 1355 return false; 1356 } 1357} 1358 1359/* Documentation for the machine specific operand escapes: 1360 1361 'E' like s but negative. 1362 'F' like t but negative. 1363 'G' constant just the negative 1364 'R' print operand as a byte:8 address if appropriate, else fall back to 1365 'X' handling. 1366 'S' print operand as a long word 1367 'T' print operand as a word 1368 'V' find the set bit, and print its number. 1369 'W' find the clear bit, and print its number. 1370 'X' print operand as a byte 1371 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1372 If this operand isn't a register, fall back to 'R' handling. 1373 'Z' print int & 7. 1374 'c' print the opcode corresponding to rtl 1375 'e' first word of 32-bit value - if reg, then least reg. if mem 1376 then least. if const then most sig word 1377 'f' second word of 32-bit value - if reg, then biggest reg. if mem 1378 then +2. if const then least sig word 1379 'j' print operand as condition code. 1380 'k' print operand as reverse condition code. 1381 'm' convert an integer operand to a size suffix (.b, .w or .l) 1382 'o' print an integer without a leading '#' 1383 's' print as low byte of 16-bit value 1384 't' print as high byte of 16-bit value 1385 'w' print as low byte of 32-bit value 1386 'x' print as 2nd byte of 32-bit value 1387 'y' print as 3rd byte of 32-bit value 1388 'z' print as msb of 32-bit value 1389*/ 1390 1391/* Return assembly language string which identifies a comparison type. */ 1392 1393static const char * 1394cond_string (enum rtx_code code) 1395{ 1396 switch (code) 1397 { 1398 case NE: 1399 return "ne"; 1400 case EQ: 1401 return "eq"; 1402 case GE: 1403 return "ge"; 1404 case GT: 1405 return "gt"; 1406 case LE: 1407 return "le"; 1408 case LT: 1409 return "lt"; 1410 case GEU: 1411 return "hs"; 1412 case GTU: 1413 return "hi"; 1414 case LEU: 1415 return "ls"; 1416 case LTU: 1417 return "lo"; 1418 default: 1419 gcc_unreachable (); 1420 } 1421} 1422 1423/* Print operand X using operand code CODE to assembly language output file 1424 FILE. */ 1425 1426static void 1427h8300_print_operand (FILE *file, rtx x, int code) 1428{ 1429 /* This is used for communication between codes V,W,Z and Y. */ 1430 static int bitint; 1431 1432 switch (code) 1433 { 1434 case 'C': 1435 if (h8300_constant_length (x) == 2) 1436 fprintf (file, ":16"); 1437 else 1438 fprintf (file, ":32"); 1439 return; 1440 case 'E': 1441 switch (GET_CODE (x)) 1442 { 1443 case REG: 1444 fprintf (file, "%sl", names_big[REGNO (x)]); 1445 break; 1446 case CONST_INT: 1447 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); 1448 break; 1449 default: 1450 gcc_unreachable (); 1451 } 1452 break; 1453 case 'F': 1454 switch (GET_CODE (x)) 1455 { 1456 case REG: 1457 fprintf (file, "%sh", names_big[REGNO (x)]); 1458 break; 1459 case CONST_INT: 1460 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); 1461 break; 1462 default: 1463 gcc_unreachable (); 1464 } 1465 break; 1466 case 'G': 1467 gcc_assert (GET_CODE (x) == CONST_INT); 1468 fprintf (file, "#%ld", 0xff & (-INTVAL (x))); 1469 break; 1470 case 'S': 1471 if (GET_CODE (x) == REG) 1472 fprintf (file, "%s", names_extended[REGNO (x)]); 1473 else 1474 goto def; 1475 break; 1476 case 'T': 1477 if (GET_CODE (x) == REG) 1478 fprintf (file, "%s", names_big[REGNO (x)]); 1479 else 1480 goto def; 1481 break; 1482 case 'V': 1483 bitint = (INTVAL (x) & 0xffff); 1484 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) 1485 bitint = exact_log2 (bitint & 0xff); 1486 else 1487 bitint = exact_log2 ((bitint >> 8) & 0xff); 1488 gcc_assert (bitint >= 0); 1489 fprintf (file, "#%d", bitint); 1490 break; 1491 case 'W': 1492 bitint = ((~INTVAL (x)) & 0xffff); 1493 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) 1494 bitint = exact_log2 (bitint & 0xff); 1495 else 1496 bitint = (exact_log2 ((bitint >> 8) & 0xff)); 1497 gcc_assert (bitint >= 0); 1498 fprintf (file, "#%d", bitint); 1499 break; 1500 case 'R': 1501 case 'X': 1502 if (GET_CODE (x) == REG) 1503 fprintf (file, "%s", byte_reg (x, 0)); 1504 else 1505 goto def; 1506 break; 1507 case 'Y': 1508 gcc_assert (bitint >= 0); 1509 if (GET_CODE (x) == REG) 1510 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1511 else 1512 h8300_print_operand (file, x, 'R'); 1513 bitint = -1; 1514 break; 1515 case 'Z': 1516 bitint = INTVAL (x); 1517 fprintf (file, "#%d", bitint & 7); 1518 break; 1519 case 'c': 1520 switch (GET_CODE (x)) 1521 { 1522 case IOR: 1523 fprintf (file, "or"); 1524 break; 1525 case XOR: 1526 fprintf (file, "xor"); 1527 break; 1528 case AND: 1529 fprintf (file, "and"); 1530 break; 1531 default: 1532 break; 1533 } 1534 break; 1535 case 'e': 1536 switch (GET_CODE (x)) 1537 { 1538 case REG: 1539 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1540 break; 1541 case MEM: 1542 h8300_print_operand (file, x, 0); 1543 break; 1544 case CONST_INT: 1545 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); 1546 break; 1547 case CONST_DOUBLE: 1548 { 1549 long val; 1550 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1551 fprintf (file, "#%ld", ((val >> 16) & 0xffff)); 1552 break; 1553 } 1554 default: 1555 gcc_unreachable (); 1556 break; 1557 } 1558 break; 1559 case 'f': 1560 switch (GET_CODE (x)) 1561 { 1562 case REG: 1563 fprintf (file, "%s", names_big[REGNO (x)]); 1564 break; 1565 case MEM: 1566 x = adjust_address (x, HImode, 2); 1567 h8300_print_operand (file, x, 0); 1568 break; 1569 case CONST_INT: 1570 fprintf (file, "#%ld", INTVAL (x) & 0xffff); 1571 break; 1572 case CONST_DOUBLE: 1573 { 1574 long val; 1575 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1576 fprintf (file, "#%ld", (val & 0xffff)); 1577 break; 1578 } 1579 default: 1580 gcc_unreachable (); 1581 } 1582 break; 1583 case 'j': 1584 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1585 fputs ("mi", file); 1586 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1587 fputs ("pl", file); 1588 else 1589 fputs (cond_string (GET_CODE (x)), file); 1590 break; 1591 case 'k': 1592 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1593 fputs ("pl", file); 1594 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1595 fputs ("mi", file); 1596 else 1597 fputs (cond_string (reverse_condition (GET_CODE (x))), file); 1598 break; 1599 case 'm': 1600 gcc_assert (GET_CODE (x) == CONST_INT); 1601 switch (INTVAL (x)) 1602 { 1603 case 1: 1604 fputs (".b", file); 1605 break; 1606 1607 case 2: 1608 fputs (".w", file); 1609 break; 1610 1611 case 4: 1612 fputs (".l", file); 1613 break; 1614 1615 default: 1616 gcc_unreachable (); 1617 } 1618 break; 1619 case 'o': 1620 h8300_print_operand_address (file, VOIDmode, x); 1621 break; 1622 case 's': 1623 if (GET_CODE (x) == CONST_INT) 1624 fprintf (file, "#%ld", (INTVAL (x)) & 0xff); 1625 else if (GET_CODE (x) == REG) 1626 fprintf (file, "%s", byte_reg (x, 0)); 1627 else 1628 output_operand_lossage ("Expected register or constant integer."); 1629 break; 1630 case 't': 1631 if (GET_CODE (x) == CONST_INT) 1632 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1633 else if (GET_CODE (x) == REG) 1634 fprintf (file, "%s", byte_reg (x, 1)); 1635 else 1636 output_operand_lossage ("Expected register or constant integer."); 1637 break; 1638 case 'w': 1639 if (GET_CODE (x) == CONST_INT) 1640 fprintf (file, "#%ld", INTVAL (x) & 0xff); 1641 else if (GET_CODE (x) == REG) 1642 fprintf (file, "%s", byte_reg (x, 0)); 1643 else 1644 output_operand_lossage ("Expected register or constant integer."); 1645 break; 1646 case 'x': 1647 if (GET_CODE (x) == CONST_INT) 1648 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1649 else if (GET_CODE (x) == REG) 1650 fprintf (file, "%s", byte_reg (x, 1)); 1651 else 1652 output_operand_lossage ("Expected register or constant integer."); 1653 break; 1654 case 'y': 1655 if (GET_CODE (x) == CONST_INT) 1656 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); 1657 else if (GET_CODE (x) == REG) 1658 fprintf (file, "%s", byte_reg (x, 0)); 1659 else 1660 output_operand_lossage ("Expected register or constant integer."); 1661 break; 1662 case 'z': 1663 if (GET_CODE (x) == CONST_INT) 1664 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); 1665 else if (GET_CODE (x) == REG) 1666 fprintf (file, "%s", byte_reg (x, 1)); 1667 else 1668 output_operand_lossage ("Expected register or constant integer."); 1669 break; 1670 1671 default: 1672 def: 1673 switch (GET_CODE (x)) 1674 { 1675 case REG: 1676 switch (GET_MODE (x)) 1677 { 1678 case E_QImode: 1679#if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1680 fprintf (file, "%s", byte_reg (x, 0)); 1681#else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1682 fprintf (file, "%s", names_big[REGNO (x)]); 1683#endif 1684 break; 1685 case E_HImode: 1686 fprintf (file, "%s", names_big[REGNO (x)]); 1687 break; 1688 case E_SImode: 1689 case E_SFmode: 1690 fprintf (file, "%s", names_extended[REGNO (x)]); 1691 break; 1692 default: 1693 gcc_unreachable (); 1694 } 1695 break; 1696 1697 case MEM: 1698 { 1699 rtx addr = XEXP (x, 0); 1700 1701 fprintf (file, "@"); 1702 output_address (GET_MODE (x), addr); 1703 1704 /* Add a length suffix to constant addresses. Although this 1705 is often unnecessary, it helps to avoid ambiguity in the 1706 syntax of mova. If we wrote an insn like: 1707 1708 mova/w.l @(1,@foo.b),er0 1709 1710 then .b would be considered part of the symbol name. 1711 Adding a length after foo will avoid this. */ 1712 if (CONSTANT_P (addr)) 1713 switch (code) 1714 { 1715 case 'R': 1716 /* Used for mov.b and bit operations. */ 1717 if (h8300_eightbit_constant_address_p (addr)) 1718 { 1719 fprintf (file, ":8"); 1720 break; 1721 } 1722 1723 /* FALLTHRU */ 1724 1725 /* We should not get here if we are processing bit 1726 operations on H8/300 or H8/300H because 'U' 1727 constraint does not allow bit operations on the 1728 tiny area on these machines. */ 1729 1730 case 'X': 1731 case 'T': 1732 case 'S': 1733 if (h8300_constant_length (addr) == 2) 1734 fprintf (file, ":16"); 1735 else 1736 fprintf (file, ":32"); 1737 break; 1738 default: 1739 break; 1740 } 1741 } 1742 break; 1743 1744 case CONST_INT: 1745 case SYMBOL_REF: 1746 case CONST: 1747 case LABEL_REF: 1748 fprintf (file, "#"); 1749 h8300_print_operand_address (file, VOIDmode, x); 1750 break; 1751 case CONST_DOUBLE: 1752 { 1753 long val; 1754 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1755 fprintf (file, "#%ld", val); 1756 break; 1757 } 1758 default: 1759 break; 1760 } 1761 } 1762} 1763 1764/* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 1765 1766static bool 1767h8300_print_operand_punct_valid_p (unsigned char code) 1768{ 1769 return (code == '#'); 1770} 1771 1772/* Output assembly language output for the address ADDR to FILE. */ 1773 1774static void 1775h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr) 1776{ 1777 rtx index; 1778 int size; 1779 1780 switch (GET_CODE (addr)) 1781 { 1782 case REG: 1783 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1784 break; 1785 1786 case PRE_DEC: 1787 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1788 break; 1789 1790 case POST_INC: 1791 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1792 break; 1793 1794 case PRE_INC: 1795 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1796 break; 1797 1798 case POST_DEC: 1799 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); 1800 break; 1801 1802 case PLUS: 1803 fprintf (file, "("); 1804 1805 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); 1806 if (GET_CODE (index) == REG) 1807 { 1808 /* reg,foo */ 1809 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1810 fprintf (file, ","); 1811 switch (size) 1812 { 1813 case 0: 1814 h8300_print_operand_address (file, mode, index); 1815 break; 1816 1817 case 1: 1818 h8300_print_operand (file, index, 'X'); 1819 fputs (".b", file); 1820 break; 1821 1822 case 2: 1823 h8300_print_operand (file, index, 'T'); 1824 fputs (".w", file); 1825 break; 1826 1827 case 4: 1828 h8300_print_operand (file, index, 'S'); 1829 fputs (".l", file); 1830 break; 1831 } 1832 /* h8300_print_operand_address (file, XEXP (addr, 0)); */ 1833 } 1834 else 1835 { 1836 /* foo+k */ 1837 h8300_print_operand_address (file, mode, XEXP (addr, 0)); 1838 fprintf (file, "+"); 1839 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1840 } 1841 fprintf (file, ")"); 1842 break; 1843 1844 case CONST_INT: 1845 { 1846 int n = INTVAL (addr); 1847 fprintf (file, "%d", n); 1848 break; 1849 } 1850 1851 default: 1852 output_addr_const (file, addr); 1853 break; 1854 } 1855} 1856 1857/* Output all insn addresses and their sizes into the assembly language 1858 output file. This is helpful for debugging whether the length attributes 1859 in the md file are correct. This is not meant to be a user selectable 1860 option. */ 1861 1862void 1863final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, 1864 int num_operands ATTRIBUTE_UNUSED) 1865{ 1866 /* This holds the last insn address. */ 1867 static int last_insn_address = 0; 1868 1869 const int uid = INSN_UID (insn); 1870 1871 if (TARGET_ADDRESSES) 1872 { 1873 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), 1874 INSN_ADDRESSES (uid) - last_insn_address); 1875 last_insn_address = INSN_ADDRESSES (uid); 1876 } 1877} 1878 1879/* Prepare for an SI sized move. */ 1880 1881int 1882h8300_expand_movsi (rtx operands[]) 1883{ 1884 rtx src = operands[1]; 1885 rtx dst = operands[0]; 1886 if (!reload_in_progress && !reload_completed) 1887 { 1888 if (!register_operand (dst, GET_MODE (dst))) 1889 { 1890 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1891 emit_move_insn (tmp, src); 1892 operands[1] = tmp; 1893 } 1894 } 1895 return 0; 1896} 1897 1898/* Given FROM and TO register numbers, say whether this elimination is allowed. 1899 Frame pointer elimination is automatically handled. 1900 1901 For the h8300, if frame pointer elimination is being done, we would like to 1902 convert ap and rp into sp, not fp. 1903 1904 All other eliminations are valid. */ 1905 1906static bool 1907h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 1908{ 1909 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 1910} 1911 1912/* Conditionally modify register usage based on target flags. */ 1913 1914static void 1915h8300_conditional_register_usage (void) 1916{ 1917 if (!TARGET_MAC) 1918 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; 1919} 1920 1921/* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1922 Define the offset between two registers, one to be eliminated, and 1923 the other its replacement, at the start of a routine. */ 1924 1925int 1926h8300_initial_elimination_offset (int from, int to) 1927{ 1928 /* The number of bytes that the return address takes on the stack. */ 1929 int pc_size = POINTER_SIZE / BITS_PER_UNIT; 1930 1931 /* The number of bytes that the saved frame pointer takes on the stack. */ 1932 int fp_size = frame_pointer_needed * UNITS_PER_WORD; 1933 1934 /* The number of bytes that the saved registers, excluding the frame 1935 pointer, take on the stack. */ 1936 int saved_regs_size = 0; 1937 1938 /* The number of bytes that the locals takes on the stack. */ 1939 int frame_size = round_frame_size (get_frame_size ()); 1940 1941 int regno; 1942 1943 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 1944 if (WORD_REG_USED (regno)) 1945 saved_regs_size += UNITS_PER_WORD; 1946 1947 /* Adjust saved_regs_size because the above loop took the frame 1948 pointer int account. */ 1949 saved_regs_size -= fp_size; 1950 1951 switch (to) 1952 { 1953 case HARD_FRAME_POINTER_REGNUM: 1954 switch (from) 1955 { 1956 case ARG_POINTER_REGNUM: 1957 return pc_size + fp_size; 1958 case RETURN_ADDRESS_POINTER_REGNUM: 1959 return fp_size; 1960 case FRAME_POINTER_REGNUM: 1961 return -saved_regs_size; 1962 default: 1963 gcc_unreachable (); 1964 } 1965 break; 1966 case STACK_POINTER_REGNUM: 1967 switch (from) 1968 { 1969 case ARG_POINTER_REGNUM: 1970 return pc_size + saved_regs_size + frame_size; 1971 case RETURN_ADDRESS_POINTER_REGNUM: 1972 return saved_regs_size + frame_size; 1973 case FRAME_POINTER_REGNUM: 1974 return frame_size; 1975 default: 1976 gcc_unreachable (); 1977 } 1978 break; 1979 default: 1980 gcc_unreachable (); 1981 } 1982 gcc_unreachable (); 1983} 1984 1985/* Worker function for RETURN_ADDR_RTX. */ 1986 1987rtx 1988h8300_return_addr_rtx (int count, rtx frame) 1989{ 1990 rtx ret; 1991 1992 if (count == 0) 1993 ret = gen_rtx_MEM (Pmode, 1994 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); 1995 else if (flag_omit_frame_pointer) 1996 return (rtx) 0; 1997 else 1998 ret = gen_rtx_MEM (Pmode, 1999 memory_address (Pmode, 2000 plus_constant (Pmode, frame, 2001 UNITS_PER_WORD))); 2002 set_mem_alias_set (ret, get_frame_alias_set ()); 2003 return ret; 2004} 2005 2006 2007machine_mode 2008h8300_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1) 2009{ 2010 if (op1 == const0_rtx 2011 && (cond == EQ || cond == NE || cond == LT || cond == GE) 2012 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS 2013 || GET_CODE (op0) == NEG || GET_CODE (op0) == AND 2014 || GET_CODE (op0) == IOR || GET_CODE (op0) == XOR 2015 || GET_CODE (op0) == NOT || GET_CODE (op0) == ASHIFT 2016 || GET_CODE (op0) == ASHIFTRT || GET_CODE (op0) == LSHIFTRT 2017 || GET_CODE (op0) == MULT || GET_CODE (op0) == SYMBOL_REF 2018 || GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND 2019 || REG_P (op0) || MEM_P (op0))) 2020 return CCZNmode; 2021 2022 return CCmode; 2023} 2024 2025 2026/* Given that X occurs in an address of the form (plus X constant), 2027 return the part of X that is expected to be a register. There are 2028 four kinds of addressing mode to recognize: 2029 2030 @(dd,Rn) 2031 @(dd,RnL.b) 2032 @(dd,Rn.w) 2033 @(dd,ERn.l) 2034 2035 If SIZE is nonnull, and the address is one of the last three forms, 2036 set *SIZE to the index multiplication factor. Set it to 0 for 2037 plain @(dd,Rn) addresses. 2038 2039 MODE is the mode of the value being accessed. It can be VOIDmode 2040 if the address is known to be valid, but its mode is unknown. */ 2041 2042static rtx 2043h8300_get_index (rtx x, machine_mode mode, int *size) 2044{ 2045 int dummy, factor; 2046 2047 if (size == 0) 2048 size = &dummy; 2049 2050 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); 2051 if (TARGET_H8300SX 2052 && factor <= 4 2053 && (mode == VOIDmode 2054 || GET_MODE_CLASS (mode) == MODE_INT 2055 || GET_MODE_CLASS (mode) == MODE_FLOAT)) 2056 { 2057 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) 2058 { 2059 /* When accessing byte-sized values, the index can be 2060 a zero-extended QImode or HImode register. */ 2061 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); 2062 return XEXP (x, 0); 2063 } 2064 else 2065 { 2066 /* We're looking for addresses of the form: 2067 2068 (mult X I) 2069 or (mult (zero_extend X) I) 2070 2071 where I is the size of the operand being accessed. 2072 The canonical form of the second expression is: 2073 2074 (and (mult (subreg X) I) J) 2075 2076 where J == GET_MODE_MASK (GET_MODE (X)) * I. */ 2077 rtx index; 2078 2079 if (GET_CODE (x) == AND 2080 && GET_CODE (XEXP (x, 1)) == CONST_INT 2081 && (factor == 0 2082 || INTVAL (XEXP (x, 1)) == 0xff * factor 2083 || INTVAL (XEXP (x, 1)) == 0xffff * factor)) 2084 { 2085 index = XEXP (x, 0); 2086 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); 2087 } 2088 else 2089 { 2090 index = x; 2091 *size = 4; 2092 } 2093 2094 if (GET_CODE (index) == MULT 2095 && GET_CODE (XEXP (index, 1)) == CONST_INT 2096 && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) 2097 return XEXP (index, 0); 2098 } 2099 } 2100 *size = 0; 2101 return x; 2102} 2103 2104/* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. 2105 2106 On the H8/300, the predecrement and postincrement address depend thus 2107 (the amount of decrement or increment being the length of the operand). */ 2108 2109static bool 2110h8300_mode_dependent_address_p (const_rtx addr, 2111 addr_space_t as ATTRIBUTE_UNUSED) 2112{ 2113 if (GET_CODE (addr) == PLUS 2114 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) 2115 return true; 2116 2117 return false; 2118} 2119 2120static const h8300_length_table addb_length_table = 2121{ 2122 /* #xx Rs @aa @Rs @xx */ 2123 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ 2124 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ 2125 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ 2126 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ 2127}; 2128 2129static const h8300_length_table addw_length_table = 2130{ 2131 /* #xx Rs @aa @Rs @xx */ 2132 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ 2133 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ 2134 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ 2135 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ 2136}; 2137 2138static const h8300_length_table addl_length_table = 2139{ 2140 /* #xx Rs @aa @Rs @xx */ 2141 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ 2142 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ 2143 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ 2144 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ 2145}; 2146 2147#define logicb_length_table addb_length_table 2148#define logicw_length_table addw_length_table 2149 2150static const h8300_length_table logicl_length_table = 2151{ 2152 /* #xx Rs @aa @Rs @xx */ 2153 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ 2154 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ 2155 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ 2156 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ 2157}; 2158 2159static const h8300_length_table movb_length_table = 2160{ 2161 /* #xx Rs @aa @Rs @xx */ 2162 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ 2163 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ 2164 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ 2165 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ 2166}; 2167 2168#define movw_length_table movb_length_table 2169 2170static const h8300_length_table movl_length_table = 2171{ 2172 /* #xx Rs @aa @Rs @xx */ 2173 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ 2174 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ 2175 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ 2176 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ 2177}; 2178 2179/* Return the size of the given address or displacement constant. */ 2180 2181static unsigned int 2182h8300_constant_length (rtx constant) 2183{ 2184 /* Check for (@d:16,Reg). */ 2185 if (GET_CODE (constant) == CONST_INT 2186 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) 2187 return 2; 2188 2189 /* Check for (@d:16,Reg) in cases where the displacement is 2190 an absolute address. */ 2191 if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) 2192 return 2; 2193 2194 return 4; 2195} 2196 2197/* Return the size of a displacement field in address ADDR, which should 2198 have the form (plus X constant). SIZE is the number of bytes being 2199 accessed. */ 2200 2201static unsigned int 2202h8300_displacement_length (rtx addr, int size) 2203{ 2204 rtx offset; 2205 2206 offset = XEXP (addr, 1); 2207 2208 /* Check for @(d:2,Reg). */ 2209 if (register_operand (XEXP (addr, 0), VOIDmode) 2210 && GET_CODE (offset) == CONST_INT 2211 && (INTVAL (offset) == size 2212 || INTVAL (offset) == size * 2 2213 || INTVAL (offset) == size * 3)) 2214 return 0; 2215 2216 return h8300_constant_length (offset); 2217} 2218 2219/* Store the class of operand OP in *OPCLASS and return the length of any 2220 extra operand fields. SIZE is the number of bytes in OP. OPCLASS 2221 can be null if only the length is needed. */ 2222 2223static unsigned int 2224h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) 2225{ 2226 enum h8300_operand_class dummy; 2227 2228 if (opclass == 0) 2229 opclass = &dummy; 2230 2231 if (CONSTANT_P (op)) 2232 { 2233 *opclass = H8OP_IMMEDIATE; 2234 2235 /* Byte-sized immediates are stored in the opcode fields. */ 2236 if (size == 1) 2237 return 0; 2238 2239 /* If this is a 32-bit instruction, see whether the constant 2240 will fit into a 16-bit immediate field. */ 2241 if (TARGET_H8300SX 2242 && size == 4 2243 && GET_CODE (op) == CONST_INT 2244 && IN_RANGE (INTVAL (op), 0, 0xffff)) 2245 return 2; 2246 2247 return size; 2248 } 2249 else if (GET_CODE (op) == MEM) 2250 { 2251 op = XEXP (op, 0); 2252 if (CONSTANT_P (op)) 2253 { 2254 *opclass = H8OP_MEM_ABSOLUTE; 2255 return h8300_constant_length (op); 2256 } 2257 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) 2258 { 2259 *opclass = H8OP_MEM_COMPLEX; 2260 return h8300_displacement_length (op, size); 2261 } 2262 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) 2263 { 2264 *opclass = H8OP_MEM_COMPLEX; 2265 return 0; 2266 } 2267 else if (register_operand (op, VOIDmode)) 2268 { 2269 *opclass = H8OP_MEM_BASE; 2270 return 0; 2271 } 2272 } 2273 gcc_assert (register_operand (op, VOIDmode)); 2274 *opclass = H8OP_REGISTER; 2275 return 0; 2276} 2277 2278/* Return the length of the instruction described by TABLE given that 2279 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand 2280 and OP2 must be an h8300_src_operand. */ 2281 2282static unsigned int 2283h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) 2284{ 2285 enum h8300_operand_class op1_class, op2_class; 2286 unsigned int size, immediate_length; 2287 2288 size = GET_MODE_SIZE (GET_MODE (op1)); 2289 immediate_length = (h8300_classify_operand (op1, size, &op1_class) 2290 + h8300_classify_operand (op2, size, &op2_class)); 2291 return immediate_length + (*table)[op1_class - 1][op2_class]; 2292} 2293 2294/* Return the length of a unary instruction such as neg or not given that 2295 its operand is OP. */ 2296 2297unsigned int 2298h8300_unary_length (rtx op) 2299{ 2300 enum h8300_operand_class opclass; 2301 unsigned int size, operand_length; 2302 2303 size = GET_MODE_SIZE (GET_MODE (op)); 2304 operand_length = h8300_classify_operand (op, size, &opclass); 2305 switch (opclass) 2306 { 2307 case H8OP_REGISTER: 2308 return 2; 2309 2310 case H8OP_MEM_BASE: 2311 return (size == 4 ? 6 : 4); 2312 2313 case H8OP_MEM_ABSOLUTE: 2314 return operand_length + (size == 4 ? 6 : 4); 2315 2316 case H8OP_MEM_COMPLEX: 2317 return operand_length + 6; 2318 2319 default: 2320 gcc_unreachable (); 2321 } 2322} 2323 2324/* Likewise short immediate instructions such as add.w #xx:3,OP. */ 2325 2326static unsigned int 2327h8300_short_immediate_length (rtx op) 2328{ 2329 enum h8300_operand_class opclass; 2330 unsigned int size, operand_length; 2331 2332 size = GET_MODE_SIZE (GET_MODE (op)); 2333 operand_length = h8300_classify_operand (op, size, &opclass); 2334 2335 switch (opclass) 2336 { 2337 case H8OP_REGISTER: 2338 return 2; 2339 2340 case H8OP_MEM_BASE: 2341 case H8OP_MEM_ABSOLUTE: 2342 case H8OP_MEM_COMPLEX: 2343 return 4 + operand_length; 2344 2345 default: 2346 gcc_unreachable (); 2347 } 2348} 2349 2350/* Likewise bitfield load and store instructions. */ 2351 2352static unsigned int 2353h8300_bitfield_length (rtx op, rtx op2) 2354{ 2355 enum h8300_operand_class opclass; 2356 unsigned int size, operand_length; 2357 2358 if (GET_CODE (op) == REG) 2359 op = op2; 2360 gcc_assert (GET_CODE (op) != REG); 2361 2362 size = GET_MODE_SIZE (GET_MODE (op)); 2363 operand_length = h8300_classify_operand (op, size, &opclass); 2364 2365 switch (opclass) 2366 { 2367 case H8OP_MEM_BASE: 2368 case H8OP_MEM_ABSOLUTE: 2369 case H8OP_MEM_COMPLEX: 2370 return 4 + operand_length; 2371 2372 default: 2373 gcc_unreachable (); 2374 } 2375} 2376 2377/* Calculate the length of general binary instruction INSN using TABLE. */ 2378 2379static unsigned int 2380h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) 2381{ 2382 rtx set; 2383 rtx pattern; 2384 2385 if (GET_CODE (insn) != INSN) 2386 gcc_unreachable (); 2387 2388 pattern = PATTERN (insn); 2389 if (GET_CODE (pattern) == PARALLEL 2390 && GET_CODE (XVECEXP (pattern, 0, 0)) == SET 2391 && GET_CODE (SET_SRC (XVECEXP (pattern, 0, 0))) == COMPARE) 2392 set = XVECEXP (pattern, 0, 1); 2393 else 2394 set = single_set (insn); 2395 gcc_assert (set); 2396 2397 if (BINARY_P (SET_SRC (set))) 2398 return h8300_length_from_table (XEXP (SET_SRC (set), 0), 2399 XEXP (SET_SRC (set), 1), table); 2400 else 2401 { 2402 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); 2403 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), 2404 XEXP (XEXP (SET_SRC (set), 1), 1), 2405 table); 2406 } 2407} 2408 2409/* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte 2410 memory reference and either (1) it has the form @(d:16,Rn) or 2411 (2) its address has the code given by INC_CODE. */ 2412 2413static bool 2414h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) 2415{ 2416 rtx addr; 2417 unsigned int size; 2418 2419 if (GET_CODE (op) != MEM) 2420 return false; 2421 2422 addr = XEXP (op, 0); 2423 size = GET_MODE_SIZE (GET_MODE (op)); 2424 if (size != 1 && size != 2) 2425 return false; 2426 2427 return (GET_CODE (addr) == inc_code 2428 || (GET_CODE (addr) == PLUS 2429 && GET_CODE (XEXP (addr, 0)) == REG 2430 && h8300_displacement_length (addr, size) == 2)); 2431} 2432 2433/* Calculate the length of move instruction INSN using the given length 2434 table. Although the tables are correct for most cases, there is some 2435 irregularity in the length of mov.b and mov.w. The following forms: 2436 2437 mov @ERs+, Rd 2438 mov @(d:16,ERs), Rd 2439 mov Rs, @-ERd 2440 mov Rs, @(d:16,ERd) 2441 2442 are two bytes shorter than most other "mov Rs, @complex" or 2443 "mov @complex,Rd" combinations. */ 2444 2445static unsigned int 2446h8300_move_length (rtx *operands, const h8300_length_table *table) 2447{ 2448 unsigned int size; 2449 2450 size = h8300_length_from_table (operands[0], operands[1], table); 2451 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) 2452 size -= 2; 2453 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) 2454 size -= 2; 2455 return size; 2456} 2457 2458/* Return the length of a mova instruction with the given operands. 2459 DEST is the register destination, SRC is the source address and 2460 OFFSET is the 16-bit or 32-bit displacement. */ 2461 2462static unsigned int 2463h8300_mova_length (rtx dest, rtx src, rtx offset) 2464{ 2465 unsigned int size; 2466 2467 size = (2 2468 + h8300_constant_length (offset) 2469 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); 2470 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) 2471 size += 2; 2472 return size; 2473} 2474 2475/* Compute the length of INSN based on its length_table attribute. 2476 OPERANDS is the array of its operands. */ 2477 2478unsigned int 2479h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) 2480{ 2481 switch (get_attr_length_table (insn)) 2482 { 2483 case LENGTH_TABLE_NONE: 2484 gcc_unreachable (); 2485 2486 case LENGTH_TABLE_ADD: 2487 if (GET_MODE (operands[0]) == QImode) 2488 return h8300_binary_length (insn, &addb_length_table); 2489 else if (GET_MODE (operands[0]) == HImode) 2490 return h8300_binary_length (insn, &addw_length_table); 2491 else if (GET_MODE (operands[0]) == SImode) 2492 return h8300_binary_length (insn, &addl_length_table); 2493 gcc_unreachable (); 2494 2495 case LENGTH_TABLE_LOGICB: 2496 return h8300_binary_length (insn, &logicb_length_table); 2497 2498 case LENGTH_TABLE_MOVB: 2499 return h8300_move_length (operands, &movb_length_table); 2500 2501 case LENGTH_TABLE_MOVW: 2502 return h8300_move_length (operands, &movw_length_table); 2503 2504 case LENGTH_TABLE_MOVL: 2505 return h8300_move_length (operands, &movl_length_table); 2506 2507 case LENGTH_TABLE_MOVA: 2508 return h8300_mova_length (operands[0], operands[1], operands[2]); 2509 2510 case LENGTH_TABLE_MOVA_ZERO: 2511 return h8300_mova_length (operands[0], operands[1], const0_rtx); 2512 2513 case LENGTH_TABLE_UNARY: 2514 return h8300_unary_length (operands[0]); 2515 2516 case LENGTH_TABLE_MOV_IMM4: 2517 return 2 + h8300_classify_operand (operands[0], 0, 0); 2518 2519 case LENGTH_TABLE_SHORT_IMMEDIATE: 2520 return h8300_short_immediate_length (operands[0]); 2521 2522 case LENGTH_TABLE_BITFIELD: 2523 return h8300_bitfield_length (operands[0], operands[1]); 2524 2525 case LENGTH_TABLE_BITBRANCH: 2526 return h8300_bitfield_length (operands[1], operands[2]) - 2; 2527 2528 default: 2529 gcc_unreachable (); 2530 } 2531} 2532 2533/* Return true if LHS and RHS are memory references that can be mapped 2534 to the same h8sx assembly operand. LHS appears as the destination of 2535 an instruction and RHS appears as a source. 2536 2537 Three cases are allowed: 2538 2539 - RHS is @+Rn or @-Rn, LHS is @Rn 2540 - RHS is @Rn, LHS is @Rn+ or @Rn- 2541 - RHS and LHS have the same address and neither has side effects. */ 2542 2543bool 2544h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) 2545{ 2546 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) 2547 { 2548 rhs = XEXP (rhs, 0); 2549 lhs = XEXP (lhs, 0); 2550 2551 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) 2552 return rtx_equal_p (XEXP (rhs, 0), lhs); 2553 2554 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) 2555 return rtx_equal_p (rhs, XEXP (lhs, 0)); 2556 2557 if (rtx_equal_p (rhs, lhs)) 2558 return true; 2559 } 2560 return false; 2561} 2562 2563/* Return true if OPERANDS[1] can be mapped to the same assembly 2564 operand as OPERANDS[0]. */ 2565 2566bool 2567h8300_operands_match_p (rtx *operands) 2568{ 2569 if (register_operand (operands[0], VOIDmode) 2570 && register_operand (operands[1], VOIDmode)) 2571 return true; 2572 2573 if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) 2574 return true; 2575 2576 return false; 2577} 2578 2579/* Return the length of mov instruction. */ 2580 2581unsigned int 2582compute_mov_length (rtx *operands) 2583{ 2584 /* If the mov instruction involves a memory operand, we compute the 2585 length, assuming the largest addressing mode is used, and then 2586 adjust later in the function. Otherwise, we compute and return 2587 the exact length in one step. */ 2588 machine_mode mode = GET_MODE (operands[0]); 2589 rtx dest = operands[0]; 2590 rtx src = operands[1]; 2591 rtx addr; 2592 2593 if (GET_CODE (src) == MEM) 2594 addr = XEXP (src, 0); 2595 else if (GET_CODE (dest) == MEM) 2596 addr = XEXP (dest, 0); 2597 else 2598 addr = NULL_RTX; 2599 2600 unsigned int base_length; 2601 2602 switch (mode) 2603 { 2604 case E_QImode: 2605 if (addr == NULL_RTX) 2606 return 2; 2607 2608 /* The eightbit addressing is available only in QImode, so 2609 go ahead and take care of it. */ 2610 if (h8300_eightbit_constant_address_p (addr)) 2611 return 2; 2612 2613 base_length = 8; 2614 break; 2615 2616 case E_HImode: 2617 if (addr == NULL_RTX) 2618 { 2619 if (REG_P (src)) 2620 return 2; 2621 2622 if (src == const0_rtx) 2623 return 2; 2624 2625 return 4; 2626 } 2627 2628 base_length = 8; 2629 break; 2630 2631 case E_SImode: 2632 if (addr == NULL_RTX) 2633 { 2634 if (REG_P (src)) 2635 { 2636 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) 2637 return 4; 2638 else 2639 return 2; 2640 } 2641 2642 if (GET_CODE (src) == CONST_INT) 2643 { 2644 int val = INTVAL (src); 2645 2646 if (val == 0) 2647 return 2; 2648 2649 if (val == (val & 0x00ff) || val == (val & 0xff00)) 2650 return 4; 2651 2652 switch (val & 0xffffffff) 2653 { 2654 case 0xffffffff: 2655 case 0xfffffffe: 2656 case 0xfffffffc: 2657 case 0x0000ffff: 2658 case 0x0000fffe: 2659 case 0xffff0000: 2660 case 0xfffe0000: 2661 case 0x00010000: 2662 case 0x00020000: 2663 return 4; 2664 } 2665 } 2666 return 6; 2667 } 2668 2669 base_length = 10; 2670 break; 2671 2672 case E_SFmode: 2673 if (addr == NULL_RTX) 2674 { 2675 if (REG_P (src)) 2676 return 2; 2677 2678 if (satisfies_constraint_G (src)) 2679 return 2; 2680 2681 return 6; 2682 } 2683 2684 base_length = 10; 2685 break; 2686 2687 default: 2688 gcc_unreachable (); 2689 } 2690 2691 /* Adjust the length based on the addressing mode used. 2692 Specifically, we subtract the difference between the actual 2693 length and the longest one, which is @(d:24,ERs). */ 2694 2695 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ 2696 if (GET_CODE (addr) == PRE_DEC 2697 || GET_CODE (addr) == POST_INC) 2698 return base_length - 6; 2699 2700 /* @ERs and @ERd are 6 bytes shorter than the longest. */ 2701 if (GET_CODE (addr) == REG) 2702 return base_length - 6; 2703 2704 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the 2705 longest. */ 2706 if (GET_CODE (addr) == PLUS 2707 && GET_CODE (XEXP (addr, 0)) == REG 2708 && GET_CODE (XEXP (addr, 1)) == CONST_INT 2709 && INTVAL (XEXP (addr, 1)) > -32768 2710 && INTVAL (XEXP (addr, 1)) < 32767) 2711 return base_length - 4; 2712 2713 /* @aa:16 is 4 bytes shorter than the longest. */ 2714 if (h8300_tiny_constant_address_p (addr)) 2715 return base_length - 4; 2716 2717 /* @aa:24 is 2 bytes shorter than the longest. */ 2718 if (CONSTANT_P (addr)) 2719 return base_length - 2; 2720 2721 return base_length; 2722} 2723 2724/* Output an addition insn. */ 2725 2726const char * 2727output_plussi (rtx *operands, bool need_flags) 2728{ 2729 machine_mode mode = GET_MODE (operands[0]); 2730 2731 gcc_assert (mode == SImode); 2732 2733 if (GET_CODE (operands[2]) == CONST_INT 2734 && register_operand (operands[1], VOIDmode)) 2735 { 2736 HOST_WIDE_INT intval = INTVAL (operands[2]); 2737 2738 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2739 return "add.l\t%S2,%S0"; 2740 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2741 return "sub.l\t%G2,%S0"; 2742 2743 /* See if we can finish with 2 bytes. */ 2744 2745 switch ((unsigned int) intval & 0xffffffff) 2746 { 2747 /* INC/DEC set the flags, but adds/subs do not. So if we 2748 need flags, use the former and not the latter. */ 2749 case 0x00000001: 2750 if (need_flags) 2751 return "inc.l\t#1,%S0"; 2752 else 2753 return "adds\t%2,%S0"; 2754 case 0x00000002: 2755 if (need_flags) 2756 return "inc.l\t#2,%S0"; 2757 else 2758 return "adds\t%2,%S0"; 2759 case 0xffffffff: 2760 if (need_flags) 2761 return "dec.l\t#1,%S0"; 2762 else 2763 return "subs\t%G2,%S0"; 2764 case 0xfffffffe: 2765 if (need_flags) 2766 return "dec.l\t#2,%S0"; 2767 else 2768 return "subs\t%G2,%S0"; 2769 2770 /* These six cases have optimized paths when we do not 2771 need flags. Otherwise we let them fallthru. */ 2772 case 0x00000004: 2773 if (!need_flags) 2774 return "adds\t%2,%S0"; 2775 2776 /* FALLTHRU */ 2777 2778 case 0xfffffffc: 2779 if (!need_flags) 2780 return "subs\t%G2,%S0"; 2781 2782 /* FALLTHRU */ 2783 2784 case 0x00010000: 2785 case 0x00020000: 2786 if (!need_flags) 2787 { 2788 operands[2] = GEN_INT (intval >> 16); 2789 return "inc.w\t%2,%e0"; 2790 } 2791 2792 /* FALLTHRU */ 2793 2794 case 0xffff0000: 2795 case 0xfffe0000: 2796 if (!need_flags) 2797 { 2798 operands[2] = GEN_INT (intval >> 16); 2799 return "dec.w\t%G2,%e0"; 2800 } 2801 2802 /* FALLTHRU */ 2803 2804 } 2805 2806 /* See if we can finish with 4 bytes. */ 2807 if ((intval & 0xffff) == 0) 2808 { 2809 operands[2] = GEN_INT (intval >> 16); 2810 return "add.w\t%2,%e0"; 2811 } 2812 } 2813 2814 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 2815 { 2816 operands[2] = GEN_INT (-INTVAL (operands[2])); 2817 return "sub.l\t%S2,%S0"; 2818 } 2819 return "add.l\t%S2,%S0"; 2820} 2821 2822/* ??? It would be much easier to add the h8sx stuff if a single function 2823 classified the addition as either inc/dec, adds/subs, add.w or add.l. */ 2824/* Compute the length of an addition insn. */ 2825 2826unsigned int 2827compute_plussi_length (rtx *operands, bool need_flags) 2828{ 2829 machine_mode mode = GET_MODE (operands[0]); 2830 2831 gcc_assert (mode == SImode); 2832 2833 if (GET_CODE (operands[2]) == CONST_INT 2834 && register_operand (operands[1], VOIDmode)) 2835 { 2836 HOST_WIDE_INT intval = INTVAL (operands[2]); 2837 2838 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2839 return 2; 2840 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2841 return 2; 2842 2843 /* See if we can finish with 2 bytes. */ 2844 2845 switch ((unsigned int) intval & 0xffffffff) 2846 { 2847 case 0x00000001: 2848 case 0x00000002: 2849 return 2; 2850 case 0x00000004: 2851 if (need_flags) 2852 return 6; 2853 else 2854 return 2; 2855 2856 case 0xffffffff: 2857 case 0xfffffffe: 2858 return 2; 2859 case 0xfffffffc: 2860 if (need_flags) 2861 return 6; 2862 else 2863 return 2; 2864 2865 case 0x00010000: 2866 case 0x00020000: 2867 if (!need_flags) 2868 return 2; 2869 2870 /* FALLTHRU */ 2871 2872 case 0xffff0000: 2873 case 0xfffe0000: 2874 if (!need_flags) 2875 return 2; 2876 2877 /* FALLTHRU */ 2878 2879 } 2880 2881 /* See if we can finish with 4 bytes. */ 2882 if ((intval & 0xffff) == 0) 2883 return 4; 2884 } 2885 2886 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 2887 return h8300_length_from_table (operands[0], 2888 GEN_INT (-INTVAL (operands[2])), 2889 &addl_length_table); 2890 else 2891 return h8300_length_from_table (operands[0], operands[2], 2892 &addl_length_table); 2893} 2894 2895/* Compute which flag bits are valid after an addition insn. */ 2896 2897enum attr_old_cc 2898compute_plussi_cc (rtx *operands) 2899{ 2900 machine_mode mode = GET_MODE (operands[0]); 2901 2902 gcc_assert (mode == SImode); 2903 2904 if (GET_CODE (operands[2]) == CONST_INT 2905 && register_operand (operands[1], VOIDmode)) 2906 { 2907 HOST_WIDE_INT intval = INTVAL (operands[2]); 2908 2909 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2910 return OLD_CC_SET_ZN; 2911 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2912 return OLD_CC_SET_ZN; 2913 2914 /* See if we can finish with 2 bytes. */ 2915 2916 switch ((unsigned int) intval & 0xffffffff) 2917 { 2918 case 0x00000001: 2919 case 0x00000002: 2920 case 0x00000004: 2921 return OLD_CC_NONE_0HIT; 2922 2923 case 0xffffffff: 2924 case 0xfffffffe: 2925 case 0xfffffffc: 2926 return OLD_CC_NONE_0HIT; 2927 2928 case 0x00010000: 2929 case 0x00020000: 2930 return OLD_CC_CLOBBER; 2931 2932 case 0xffff0000: 2933 case 0xfffe0000: 2934 return OLD_CC_CLOBBER; 2935 } 2936 2937 /* See if we can finish with 4 bytes. */ 2938 if ((intval & 0xffff) == 0) 2939 return OLD_CC_CLOBBER; 2940 } 2941 2942 return OLD_CC_SET_ZN; 2943} 2944 2945/* Output a logical insn. */ 2946 2947const char * 2948output_logical_op (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn) 2949{ 2950 /* Pretend that every byte is affected if both operands are registers. */ 2951 const unsigned HOST_WIDE_INT intval = 2952 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 2953 /* Always use the full instruction if the 2954 first operand is in memory. It is better 2955 to use define_splits to generate the shorter 2956 sequence where valid. */ 2957 && register_operand (operands[1], VOIDmode) 2958 ? INTVAL (operands[2]) : 0x55555555); 2959 /* The determinant of the algorithm. If we perform an AND, 0 2960 affects a bit. Otherwise, 1 affects a bit. */ 2961 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 2962 /* Break up DET into pieces. */ 2963 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 2964 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 2965 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 2966 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 2967 int lower_half_easy_p = 0; 2968 int upper_half_easy_p = 0; 2969 /* The name of an insn. */ 2970 const char *opname; 2971 char insn_buf[100]; 2972 2973 /* INSN is the current insn, we examine its overall form to see if we're 2974 supposed to set or clobber the condition codes. 2975 2976 This is important to know. If we are setting condition codes, then we 2977 must do the operation in MODE and not in some smaller size. 2978 2979 The key is to look at the second object in the PARALLEL. If it is not 2980 a CLOBBER, then we care about the condition codes. */ 2981 rtx pattern = PATTERN (insn); 2982 gcc_assert (GET_CODE (pattern) == PARALLEL); 2983 rtx second_op = XVECEXP (pattern, 0, 1); 2984 bool cc_meaningful = (GET_CODE (second_op) != CLOBBER); 2985 2986 switch (code) 2987 { 2988 case AND: 2989 opname = "and"; 2990 break; 2991 case IOR: 2992 opname = "or"; 2993 break; 2994 case XOR: 2995 opname = "xor"; 2996 break; 2997 default: 2998 gcc_unreachable (); 2999 } 3000 3001 switch (mode) 3002 { 3003 case E_QImode: 3004 sprintf (insn_buf, "%s.b\t%%X2,%%X0", opname); 3005 output_asm_insn (insn_buf, operands); 3006 break; 3007 case E_HImode: 3008 /* First, see if we can (or must) finish with one insn. */ 3009 if (cc_meaningful 3010 || (b0 != 0 && b1 != 0)) 3011 { 3012 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); 3013 output_asm_insn (insn_buf, operands); 3014 } 3015 else 3016 { 3017 /* Take care of the lower byte. */ 3018 if (b0 != 0) 3019 { 3020 sprintf (insn_buf, "%s\t%%s2,%%s0", opname); 3021 output_asm_insn (insn_buf, operands); 3022 } 3023 /* Take care of the upper byte. */ 3024 if (b1 != 0) 3025 { 3026 sprintf (insn_buf, "%s\t%%t2,%%t0", opname); 3027 output_asm_insn (insn_buf, operands); 3028 } 3029 } 3030 break; 3031 case E_SImode: 3032 /* Determine if the lower half can be taken care of in no more 3033 than two bytes. */ 3034 lower_half_easy_p = (b0 == 0 3035 || b1 == 0 3036 || (code != IOR && w0 == 0xffff)); 3037 3038 /* Determine if the upper half can be taken care of in no more 3039 than two bytes. */ 3040 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3041 || (code == AND && w1 == 0xff00)); 3042 3043 /* Check if doing everything with one insn is no worse than 3044 using multiple insns. */ 3045 if (cc_meaningful 3046 || (w0 != 0 && w1 != 0 3047 && !(lower_half_easy_p && upper_half_easy_p) 3048 && !(code == IOR && w1 == 0xffff 3049 && (w0 & 0x8000) != 0 && lower_half_easy_p))) 3050 { 3051 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); 3052 output_asm_insn (insn_buf, operands); 3053 } 3054 else 3055 { 3056 /* Take care of the lower and upper words individually. For 3057 each word, we try different methods in the order of 3058 3059 1) the special insn (in case of AND or XOR), 3060 2) the word-wise insn, and 3061 3) The byte-wise insn. */ 3062 if (w0 == 0xffff && (code != IOR)) 3063 output_asm_insn ((code == AND) 3064 ? "sub.w\t%f0,%f0" : "not.w\t%f0", 3065 operands); 3066 else if ((b0 != 0) && (b1 != 0)) 3067 { 3068 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); 3069 output_asm_insn (insn_buf, operands); 3070 } 3071 else 3072 { 3073 if (b0 != 0) 3074 { 3075 sprintf (insn_buf, "%s\t%%w2,%%w0", opname); 3076 output_asm_insn (insn_buf, operands); 3077 } 3078 if (b1 != 0) 3079 { 3080 sprintf (insn_buf, "%s\t%%x2,%%x0", opname); 3081 output_asm_insn (insn_buf, operands); 3082 } 3083 } 3084 3085 if ((w1 == 0xffff) && (code != IOR)) 3086 output_asm_insn ((code == AND) 3087 ? "sub.w\t%e0,%e0" : "not.w\t%e0", 3088 operands); 3089 else if (code == IOR 3090 && w1 == 0xffff 3091 && (w0 & 0x8000) != 0) 3092 { 3093 output_asm_insn ("exts.l\t%S0", operands); 3094 } 3095 else if (code == AND 3096 && w1 == 0xff00) 3097 { 3098 output_asm_insn ("extu.w\t%e0", operands); 3099 } 3100 else 3101 { 3102 if (w1 != 0) 3103 { 3104 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); 3105 output_asm_insn (insn_buf, operands); 3106 } 3107 } 3108 } 3109 break; 3110 default: 3111 gcc_unreachable (); 3112 } 3113 return ""; 3114} 3115 3116/* Compute the length of a logical insn. */ 3117 3118unsigned int 3119compute_logical_op_length (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn) 3120{ 3121 /* Pretend that every byte is affected if both operands are registers. */ 3122 const unsigned HOST_WIDE_INT intval = 3123 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3124 /* Always use the full instruction if the 3125 first operand is in memory. It is better 3126 to use define_splits to generate the shorter 3127 sequence where valid. */ 3128 && register_operand (operands[1], VOIDmode) 3129 ? INTVAL (operands[2]) : 0x55555555); 3130 /* The determinant of the algorithm. If we perform an AND, 0 3131 affects a bit. Otherwise, 1 affects a bit. */ 3132 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3133 /* Break up DET into pieces. */ 3134 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3135 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3136 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3137 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3138 int lower_half_easy_p = 0; 3139 int upper_half_easy_p = 0; 3140 /* Insn length. */ 3141 unsigned int length = 0; 3142 3143 /* INSN is the current insn, we examine its overall form to see if we're 3144 supposed to set or clobber the condition codes. 3145 3146 This is important to know. If we are setting condition codes, then we 3147 must do the operation in MODE and not in some smaller size. 3148 3149 The key is to look at the second object in the PARALLEL. If it is not 3150 a CLOBBER, then we care about the condition codes. */ 3151 bool cc_meaningful = false; 3152 if (insn) 3153 { 3154 rtx pattern = PATTERN (insn); 3155 gcc_assert (GET_CODE (pattern) == PARALLEL); 3156 rtx second_op = XVECEXP (pattern, 0, 1); 3157 cc_meaningful = (GET_CODE (second_op) != CLOBBER); 3158 } 3159 3160 switch (mode) 3161 { 3162 case E_QImode: 3163 return 2; 3164 3165 case E_HImode: 3166 /* First, see if we can finish with one insn. */ 3167 if (cc_meaningful 3168 || (b0 != 0 && b1 != 0)) 3169 { 3170 length = h8300_length_from_table (operands[1], operands[2], 3171 &logicw_length_table); 3172 } 3173 else 3174 { 3175 /* Take care of the lower byte. */ 3176 if (b0 != 0) 3177 length += 2; 3178 3179 /* Take care of the upper byte. */ 3180 if (b1 != 0) 3181 length += 2; 3182 } 3183 break; 3184 case E_SImode: 3185 /* Determine if the lower half can be taken care of in no more 3186 than two bytes. */ 3187 lower_half_easy_p = (b0 == 0 3188 || b1 == 0 3189 || (code != IOR && w0 == 0xffff)); 3190 3191 /* Determine if the upper half can be taken care of in no more 3192 than two bytes. */ 3193 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3194 || (code == AND && w1 == 0xff00)); 3195 3196 /* Check if doing everything with one insn is no worse than 3197 using multiple insns. */ 3198 if (cc_meaningful 3199 || (w0 != 0 && w1 != 0 3200 && !(lower_half_easy_p && upper_half_easy_p) 3201 && !(code == IOR && w1 == 0xffff 3202 && (w0 & 0x8000) != 0 && lower_half_easy_p))) 3203 { 3204 length = h8300_length_from_table (operands[1], operands[2], 3205 &logicl_length_table); 3206 } 3207 else 3208 { 3209 /* Take care of the lower and upper words individually. For 3210 each word, we try different methods in the order of 3211 3212 1) the special insn (in case of AND or XOR), 3213 2) the word-wise insn, and 3214 3) The byte-wise insn. */ 3215 if (w0 == 0xffff && (code != IOR)) 3216 { 3217 length += 2; 3218 } 3219 else if ((b0 != 0) && (b1 != 0)) 3220 { 3221 length += 4; 3222 } 3223 else 3224 { 3225 if (b0 != 0) 3226 length += 2; 3227 3228 if (b1 != 0) 3229 length += 2; 3230 } 3231 3232 if (w1 == 0xffff && (code != IOR)) 3233 { 3234 length += 2; 3235 } 3236 else if (code == IOR 3237 && w1 == 0xffff 3238 && (w0 & 0x8000) != 0) 3239 { 3240 length += 2; 3241 } 3242 else if (code == AND && w1 == 0xff00) 3243 { 3244 length += 2; 3245 } 3246 else 3247 { 3248 if (w1 != 0) 3249 length += 4; 3250 } 3251 } 3252 break; 3253 default: 3254 gcc_unreachable (); 3255 } 3256 return length; 3257} 3258 3259#if 0 3260 3261/* Expand a conditional store. */ 3262 3263void 3264h8300_expand_store (rtx operands[]) 3265{ 3266 rtx dest = operands[0]; 3267 enum rtx_code code = GET_CODE (operands[1]); 3268 rtx op0 = operands[2]; 3269 rtx op1 = operands[3]; 3270 rtx tmp; 3271 3272 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3273 emit_insn (gen_rtx_SET (cc0_rtx, tmp)); 3274 3275 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); 3276 emit_insn (gen_rtx_SET (dest, tmp)); 3277} 3278#endif 3279 3280/* Shifts. 3281 3282 We devote a fair bit of code to getting efficient shifts since we 3283 can only shift one bit at a time on the H8/300 and H8/300H and only 3284 one or two bits at a time on the H8S. 3285 3286 All shift code falls into one of the following ways of 3287 implementation: 3288 3289 o SHIFT_INLINE: Emit straight line code for the shift; this is used 3290 when a straight line shift is about the same size or smaller than 3291 a loop. 3292 3293 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask 3294 off the bits we don't need. This is used when only a few of the 3295 bits in the original value will survive in the shifted value. 3296 3297 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to 3298 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline 3299 shifts can be added if the shift count is slightly more than 8 or 3300 16. This case also includes other oddballs that are not worth 3301 explaining here. 3302 3303 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. 3304 3305 For each shift count, we try to use code that has no trade-off 3306 between code size and speed whenever possible. 3307 3308 If the trade-off is unavoidable, we try to be reasonable. 3309 Specifically, the fastest version is one instruction longer than 3310 the shortest version, we take the fastest version. We also provide 3311 the use a way to switch back to the shortest version with -Os. 3312 3313 For the details of the shift algorithms for various shift counts, 3314 refer to shift_alg_[qhs]i. */ 3315 3316/* Classify a shift with the given mode and code. OP is the shift amount. */ 3317 3318enum h8sx_shift_type 3319h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op) 3320{ 3321 if (!TARGET_H8300SX) 3322 return H8SX_SHIFT_NONE; 3323 3324 switch (code) 3325 { 3326 case ASHIFT: 3327 case LSHIFTRT: 3328 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ 3329 if (GET_CODE (op) != CONST_INT) 3330 return H8SX_SHIFT_BINARY; 3331 3332 /* Reject out-of-range shift amounts. */ 3333 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) 3334 return H8SX_SHIFT_NONE; 3335 3336 /* Power-of-2 shifts are effectively unary operations. */ 3337 if (exact_log2 (INTVAL (op)) >= 0) 3338 return H8SX_SHIFT_UNARY; 3339 3340 return H8SX_SHIFT_BINARY; 3341 3342 case ASHIFTRT: 3343 if (op == const1_rtx || op == const2_rtx) 3344 return H8SX_SHIFT_UNARY; 3345 return H8SX_SHIFT_NONE; 3346 3347 case ROTATE: 3348 if (GET_CODE (op) == CONST_INT 3349 && (INTVAL (op) == 1 3350 || INTVAL (op) == 2 3351 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 3352 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) 3353 return H8SX_SHIFT_UNARY; 3354 return H8SX_SHIFT_NONE; 3355 3356 default: 3357 return H8SX_SHIFT_NONE; 3358 } 3359} 3360 3361/* Return the asm template for a single h8sx shift instruction. 3362 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] 3363 is the source and OPERANDS[3] is the shift. SUFFIX is the 3364 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand 3365 prefix for the destination operand. */ 3366 3367const char * 3368output_h8sx_shift (rtx *operands, int suffix, int optype) 3369{ 3370 static char buffer[16]; 3371 const char *stem; 3372 3373 switch (GET_CODE (operands[3])) 3374 { 3375 case ASHIFT: 3376 stem = "shll"; 3377 break; 3378 3379 case ASHIFTRT: 3380 stem = "shar"; 3381 break; 3382 3383 case LSHIFTRT: 3384 stem = "shlr"; 3385 break; 3386 3387 case ROTATE: 3388 stem = "rotl"; 3389 if (INTVAL (operands[2]) > 2) 3390 { 3391 /* This is really a right rotate. */ 3392 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) 3393 - INTVAL (operands[2])); 3394 stem = "rotr"; 3395 } 3396 break; 3397 3398 default: 3399 gcc_unreachable (); 3400 } 3401 if (operands[2] == const1_rtx) 3402 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); 3403 else 3404 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); 3405 return buffer; 3406} 3407 3408/* Emit code to do shifts. */ 3409 3410bool 3411expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[]) 3412{ 3413 switch (h8sx_classify_shift (mode, code, operands[2])) 3414 { 3415 case H8SX_SHIFT_BINARY: 3416 operands[1] = force_reg (mode, operands[1]); 3417 return false; 3418 3419 case H8SX_SHIFT_UNARY: 3420 return false; 3421 3422 case H8SX_SHIFT_NONE: 3423 break; 3424 } 3425 3426 /* Need a loop to get all the bits we want - we generate the 3427 code at emit time, but need to allocate a scratch reg now. */ 3428 emit_move_insn (copy_rtx (operands[0]), operands[1]); 3429 if (operands[2] == CONST0_RTX (QImode)) 3430 ; 3431 else if (GET_CODE (operands[2]) == CONST_INT 3432 && !h8300_shift_needs_scratch_p (INTVAL (operands[2]), mode, code)) 3433 emit_insn (gen_rtx_SET (copy_rtx (operands[0]), 3434 gen_rtx_fmt_ee (code, mode, 3435 copy_rtx (operands[1]), operands[2]))); 3436 else 3437 emit_insn (gen_rtx_PARALLEL 3438 (VOIDmode, 3439 gen_rtvec (2, 3440 gen_rtx_SET (copy_rtx (operands[0]), 3441 gen_rtx_fmt_ee (code, mode, 3442 copy_rtx (operands[0]), operands[2])), 3443 gen_rtx_CLOBBER (VOIDmode, 3444 gen_rtx_SCRATCH (QImode))))); 3445 return true; 3446} 3447 3448/* Symbols of the various modes which can be used as indices. */ 3449 3450enum shift_mode 3451{ 3452 QIshift, HIshift, SIshift 3453}; 3454 3455/* For single bit shift insns, record assembler and what bits of the 3456 condition code are valid afterwards (represented as various OLD_CC_FOO 3457 bits, 0 means CC isn't left in a usable state). */ 3458 3459struct shift_insn 3460{ 3461 const char *const assembler; 3462 const enum attr_old_cc cc_valid; 3463}; 3464 3465/* Assembler instruction shift table. 3466 3467 These tables are used to look up the basic shifts. 3468 They are indexed by cpu, shift_type, and mode. */ 3469 3470static const struct shift_insn shift_one[2][3][3] = 3471{ 3472/* H8/300 */ 3473 { 3474/* SHIFT_ASHIFT */ 3475 { 3476 { "shll\t%X0", OLD_CC_SET_ZNV }, 3477 { "add.w\t%T0,%T0", OLD_CC_SET_ZN }, 3478 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", OLD_CC_CLOBBER } 3479 }, 3480/* SHIFT_LSHIFTRT */ 3481 { 3482 { "shlr\t%X0", OLD_CC_SET_ZNV }, 3483 { "shlr\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, 3484 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } 3485 }, 3486/* SHIFT_ASHIFTRT */ 3487 { 3488 { "shar\t%X0", OLD_CC_SET_ZNV }, 3489 { "shar\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, 3490 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } 3491 } 3492 }, 3493/* H8/300H */ 3494 { 3495/* SHIFT_ASHIFT */ 3496 { 3497 { "shll.b\t%X0", OLD_CC_SET_ZNV }, 3498 { "shll.w\t%T0", OLD_CC_SET_ZNV }, 3499 { "shll.l\t%S0", OLD_CC_SET_ZNV } 3500 }, 3501/* SHIFT_LSHIFTRT */ 3502 { 3503 { "shlr.b\t%X0", OLD_CC_SET_ZNV }, 3504 { "shlr.w\t%T0", OLD_CC_SET_ZNV }, 3505 { "shlr.l\t%S0", OLD_CC_SET_ZNV } 3506 }, 3507/* SHIFT_ASHIFTRT */ 3508 { 3509 { "shar.b\t%X0", OLD_CC_SET_ZNV }, 3510 { "shar.w\t%T0", OLD_CC_SET_ZNV }, 3511 { "shar.l\t%S0", OLD_CC_SET_ZNV } 3512 } 3513 } 3514}; 3515 3516static const struct shift_insn shift_two[3][3] = 3517{ 3518/* SHIFT_ASHIFT */ 3519 { 3520 { "shll.b\t#2,%X0", OLD_CC_SET_ZNV }, 3521 { "shll.w\t#2,%T0", OLD_CC_SET_ZNV }, 3522 { "shll.l\t#2,%S0", OLD_CC_SET_ZNV } 3523 }, 3524/* SHIFT_LSHIFTRT */ 3525 { 3526 { "shlr.b\t#2,%X0", OLD_CC_SET_ZNV }, 3527 { "shlr.w\t#2,%T0", OLD_CC_SET_ZNV }, 3528 { "shlr.l\t#2,%S0", OLD_CC_SET_ZNV } 3529 }, 3530/* SHIFT_ASHIFTRT */ 3531 { 3532 { "shar.b\t#2,%X0", OLD_CC_SET_ZNV }, 3533 { "shar.w\t#2,%T0", OLD_CC_SET_ZNV }, 3534 { "shar.l\t#2,%S0", OLD_CC_SET_ZNV } 3535 } 3536}; 3537 3538/* Rotates are organized by which shift they'll be used in implementing. 3539 There's no need to record whether the cc is valid afterwards because 3540 it is the AND insn that will decide this. */ 3541 3542static const char *const rotate_one[2][3][3] = 3543{ 3544/* H8/300 */ 3545 { 3546/* SHIFT_ASHIFT */ 3547 { 3548 "rotr\t%X0", 3549 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 3550 0 3551 }, 3552/* SHIFT_LSHIFTRT */ 3553 { 3554 "rotl\t%X0", 3555 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3556 0 3557 }, 3558/* SHIFT_ASHIFTRT */ 3559 { 3560 "rotl\t%X0", 3561 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3562 0 3563 } 3564 }, 3565/* H8/300H */ 3566 { 3567/* SHIFT_ASHIFT */ 3568 { 3569 "rotr.b\t%X0", 3570 "rotr.w\t%T0", 3571 "rotr.l\t%S0" 3572 }, 3573/* SHIFT_LSHIFTRT */ 3574 { 3575 "rotl.b\t%X0", 3576 "rotl.w\t%T0", 3577 "rotl.l\t%S0" 3578 }, 3579/* SHIFT_ASHIFTRT */ 3580 { 3581 "rotl.b\t%X0", 3582 "rotl.w\t%T0", 3583 "rotl.l\t%S0" 3584 } 3585 } 3586}; 3587 3588static const char *const rotate_two[3][3] = 3589{ 3590/* SHIFT_ASHIFT */ 3591 { 3592 "rotr.b\t#2,%X0", 3593 "rotr.w\t#2,%T0", 3594 "rotr.l\t#2,%S0" 3595 }, 3596/* SHIFT_LSHIFTRT */ 3597 { 3598 "rotl.b\t#2,%X0", 3599 "rotl.w\t#2,%T0", 3600 "rotl.l\t#2,%S0" 3601 }, 3602/* SHIFT_ASHIFTRT */ 3603 { 3604 "rotl.b\t#2,%X0", 3605 "rotl.w\t#2,%T0", 3606 "rotl.l\t#2,%S0" 3607 } 3608}; 3609 3610struct shift_info { 3611 /* Shift algorithm. */ 3612 enum shift_alg alg; 3613 3614 /* The number of bits to be shifted by shift1 and shift2. Valid 3615 when ALG is SHIFT_SPECIAL. */ 3616 unsigned int remainder; 3617 3618 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ 3619 const char *special; 3620 3621 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE 3622 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3623 const char *shift1; 3624 3625 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE 3626 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3627 const char *shift2; 3628 3629 /* CC status for SHIFT_INLINE. */ 3630 enum attr_old_cc cc_inline; 3631 3632 /* CC status for SHIFT_SPECIAL. */ 3633 enum attr_old_cc cc_special; 3634}; 3635 3636static void get_shift_alg (enum shift_type, 3637 enum shift_mode, unsigned int, 3638 struct shift_info *); 3639 3640/* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the 3641 best algorithm for doing the shift. The assembler code is stored 3642 in the pointers in INFO. We achieve the maximum efficiency in most 3643 cases. 3644 3645 We first determine the strategy of the shift algorithm by a table 3646 lookup. If that tells us to use a hand crafted assembly code, we 3647 go into the big switch statement to find what that is. Otherwise, 3648 we resort to a generic way, such as inlining. In either case, the 3649 result is returned through INFO. */ 3650 3651static void 3652get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, 3653 unsigned int count, struct shift_info *info) 3654{ 3655 enum h8_cpu cpu; 3656 3657 if (TARGET_H8300S) 3658 cpu = H8_S; 3659 else 3660 cpu = H8_300H; 3661 3662 /* Find the shift algorithm. */ 3663 info->alg = SHIFT_LOOP; 3664 switch (shift_mode) 3665 { 3666 case QIshift: 3667 if (count < GET_MODE_BITSIZE (QImode)) 3668 info->alg = shift_alg_qi[cpu][shift_type][count]; 3669 break; 3670 3671 case HIshift: 3672 if (count < GET_MODE_BITSIZE (HImode)) 3673 info->alg = shift_alg_hi[cpu][shift_type][count]; 3674 break; 3675 3676 case SIshift: 3677 if (count < GET_MODE_BITSIZE (SImode)) 3678 info->alg = shift_alg_si[cpu][shift_type][count]; 3679 break; 3680 3681 default: 3682 gcc_unreachable (); 3683 } 3684 3685 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ 3686 switch (info->alg) 3687 { 3688 case SHIFT_INLINE: 3689 info->remainder = count; 3690 /* Fall through. */ 3691 3692 case SHIFT_LOOP: 3693 /* It is up to the caller to know that looping clobbers cc. */ 3694 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 3695 info->shift2 = shift_two[shift_type][shift_mode].assembler; 3696 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 3697 goto end; 3698 3699 case SHIFT_ROT_AND: 3700 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; 3701 info->shift2 = rotate_two[shift_type][shift_mode]; 3702 info->cc_inline = OLD_CC_CLOBBER; 3703 goto end; 3704 3705 case SHIFT_SPECIAL: 3706 /* REMAINDER is 0 for most cases, so initialize it to 0. */ 3707 info->remainder = 0; 3708 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 3709 info->shift2 = shift_two[shift_type][shift_mode].assembler; 3710 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 3711 info->cc_special = OLD_CC_CLOBBER; 3712 break; 3713 } 3714 3715 /* Here we only deal with SHIFT_SPECIAL. */ 3716 switch (shift_mode) 3717 { 3718 case QIshift: 3719 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 3720 through the entire value. */ 3721 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); 3722 info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; 3723 goto end; 3724 3725 case HIshift: 3726 if (count == 7) 3727 { 3728 switch (shift_type) 3729 { 3730 case SHIFT_ASHIFT: 3731 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 3732 goto end; 3733 case SHIFT_LSHIFTRT: 3734 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 3735 goto end; 3736 case SHIFT_ASHIFTRT: 3737 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 3738 goto end; 3739 } 3740 } 3741 else if ((count >= 8 && count <= 13) 3742 || (TARGET_H8300S && count == 14)) 3743 { 3744 info->remainder = count - 8; 3745 3746 switch (shift_type) 3747 { 3748 case SHIFT_ASHIFT: 3749 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 3750 goto end; 3751 case SHIFT_LSHIFTRT: 3752 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; 3753 info->cc_special = OLD_CC_SET_ZNV; 3754 goto end; 3755 case SHIFT_ASHIFTRT: 3756 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 3757 info->cc_special = OLD_CC_SET_ZNV; 3758 goto end; 3759 } 3760 } 3761 else if (count == 14) 3762 { 3763 switch (shift_type) 3764 { 3765 case SHIFT_ASHIFT: 3766 case SHIFT_LSHIFTRT: 3767 goto end; 3768 goto end; 3769 case SHIFT_ASHIFTRT: 3770 if (TARGET_H8300H) 3771 { 3772 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; 3773 info->cc_special = OLD_CC_SET_ZNV; 3774 } 3775 else /* TARGET_H8300S */ 3776 gcc_unreachable (); 3777 goto end; 3778 } 3779 } 3780 else if (count == 15) 3781 { 3782 switch (shift_type) 3783 { 3784 case SHIFT_ASHIFT: 3785 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; 3786 goto end; 3787 case SHIFT_LSHIFTRT: 3788 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; 3789 goto end; 3790 case SHIFT_ASHIFTRT: 3791 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 3792 goto end; 3793 } 3794 } 3795 gcc_unreachable (); 3796 3797 case SIshift: 3798 if (count == 8) 3799 { 3800 switch (shift_type) 3801 { 3802 case SHIFT_ASHIFT: 3803 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%s3,%t3\n\tmov.b\t%t0,%s3\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f3,%e0"; 3804 goto end; 3805 case SHIFT_LSHIFTRT: 3806 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\textu.w\t%f3\n\tmov.w\t%f3,%e0"; 3807 goto end; 3808 case SHIFT_ASHIFTRT: 3809 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\texts.w\t%f3\n\tmov.w\t%f3,%e0"; 3810 goto end; 3811 } 3812 } 3813 else if (count == 15) 3814 { 3815 /* The basic idea here is to use the shift-by-16 idiom to make things 3816 small and efficient. Of course, that loses one bit that we need, 3817 so we stuff the bit into C, shift by 16, then rotate the bit 3818 back in. */ 3819 switch (shift_type) 3820 { 3821 case SHIFT_ASHIFT: 3822 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; 3823 info->cc_special = OLD_CC_SET_ZNV; 3824 goto end; 3825 case SHIFT_LSHIFTRT: 3826 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; 3827 info->cc_special = OLD_CC_SET_ZNV; 3828 goto end; 3829 case SHIFT_ASHIFTRT: 3830 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\texts.l\t%S0\n\trotxl.l\t%S0"; 3831 info->cc_special = OLD_CC_SET_ZNV; 3832 goto end; 3833 } 3834 } 3835 else if (count >= 16 && count <= 23) 3836 { 3837 info->remainder = count - 16; 3838 3839 switch (shift_type) 3840 { 3841 case SHIFT_ASHIFT: 3842 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 3843 goto end; 3844 case SHIFT_LSHIFTRT: 3845 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; 3846 info->cc_special = OLD_CC_SET_ZNV; 3847 goto end; 3848 case SHIFT_ASHIFTRT: 3849 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 3850 info->cc_special = OLD_CC_SET_ZNV; 3851 goto end; 3852 } 3853 } 3854 else if (TARGET_H8300S && count == 27) 3855 { 3856 switch (shift_type) 3857 { 3858 case SHIFT_ASHIFT: 3859 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3860 goto end; 3861 case SHIFT_LSHIFTRT: 3862 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3863 goto end; 3864 case SHIFT_ASHIFTRT: 3865 info->remainder = count - 24; 3866 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3867 info->cc_special = OLD_CC_SET_ZNV; 3868 goto end; 3869 } 3870 } 3871 else if (count >= 24 && count <= 27) 3872 { 3873 info->remainder = count - 24; 3874 3875 switch (shift_type) 3876 { 3877 case SHIFT_ASHIFT: 3878 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 3879 goto end; 3880 case SHIFT_LSHIFTRT: 3881 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 3882 info->cc_special = OLD_CC_SET_ZNV; 3883 goto end; 3884 case SHIFT_ASHIFTRT: 3885 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3886 info->cc_special = OLD_CC_SET_ZNV; 3887 goto end; 3888 } 3889 } 3890 else if (count == 28) 3891 { 3892 switch (shift_type) 3893 { 3894 case SHIFT_ASHIFT: 3895 if (TARGET_H8300H) 3896 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3897 else 3898 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 3899 goto end; 3900 case SHIFT_LSHIFTRT: 3901 if (TARGET_H8300H) 3902 { 3903 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3904 info->cc_special = OLD_CC_SET_ZNV; 3905 } 3906 else 3907 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 3908 goto end; 3909 case SHIFT_ASHIFTRT: 3910 info->remainder = count - 24; 3911 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3912 info->cc_special = OLD_CC_SET_ZNV; 3913 goto end; 3914 } 3915 } 3916 else if (count == 29) 3917 { 3918 switch (shift_type) 3919 { 3920 case SHIFT_ASHIFT: 3921 if (TARGET_H8300H) 3922 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3923 else 3924 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3925 goto end; 3926 case SHIFT_LSHIFTRT: 3927 if (TARGET_H8300H) 3928 { 3929 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3930 info->cc_special = OLD_CC_SET_ZNV; 3931 } 3932 else 3933 { 3934 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3935 info->cc_special = OLD_CC_SET_ZNV; 3936 } 3937 goto end; 3938 case SHIFT_ASHIFTRT: 3939 info->remainder = count - 24; 3940 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3941 info->cc_special = OLD_CC_SET_ZNV; 3942 goto end; 3943 } 3944 } 3945 else if (count == 30) 3946 { 3947 switch (shift_type) 3948 { 3949 case SHIFT_ASHIFT: 3950 if (TARGET_H8300H) 3951 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3952 else 3953 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 3954 goto end; 3955 case SHIFT_LSHIFTRT: 3956 if (TARGET_H8300H) 3957 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3958 else 3959 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 3960 goto end; 3961 case SHIFT_ASHIFTRT: 3962 info->remainder = count - 24; 3963 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3964 info->cc_special = OLD_CC_SET_ZNV; 3965 goto end; 3966 } 3967 } 3968 else if (count == 31) 3969 { 3970 switch (shift_type) 3971 { 3972 case SHIFT_ASHIFT: 3973 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; 3974 info->cc_special = OLD_CC_SET_ZNV; 3975 goto end; 3976 case SHIFT_LSHIFTRT: 3977 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; 3978 info->cc_special = OLD_CC_SET_ZNV; 3979 goto end; 3980 case SHIFT_ASHIFTRT: 3981 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; 3982 info->cc_special = OLD_CC_SET_ZNV; 3983 goto end; 3984 } 3985 } 3986 gcc_unreachable (); 3987 3988 default: 3989 gcc_unreachable (); 3990 } 3991 3992 end: 3993 if (!TARGET_H8300S) 3994 info->shift2 = NULL; 3995} 3996 3997/* Given COUNT and MODE of a shift, return 1 if a scratch reg may be 3998 needed for some shift with COUNT and MODE. Return 0 otherwise. */ 3999 4000int 4001h8300_shift_needs_scratch_p (int count, machine_mode mode, enum rtx_code type) 4002{ 4003 enum h8_cpu cpu; 4004 int a, lr, ar; 4005 4006 if (GET_MODE_BITSIZE (mode) <= count) 4007 return 1; 4008 4009 /* Find out the target CPU. */ 4010 if (TARGET_H8300S) 4011 cpu = H8_S; 4012 else 4013 cpu = H8_300H; 4014 4015 /* Find the shift algorithm. */ 4016 switch (mode) 4017 { 4018 case E_QImode: 4019 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; 4020 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; 4021 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; 4022 break; 4023 4024 case E_HImode: 4025 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; 4026 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; 4027 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; 4028 break; 4029 4030 case E_SImode: 4031 a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; 4032 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; 4033 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; 4034 break; 4035 4036 default: 4037 gcc_unreachable (); 4038 } 4039 4040 /* On H8/300H, count == 8 uses a scratch register. */ 4041 if (type == CLOBBER) 4042 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP 4043 || (TARGET_H8300H && mode == SImode && count == 8)); 4044 else if (type == ASHIFT) 4045 return (a == SHIFT_LOOP 4046 || (TARGET_H8300H && mode == SImode && count == 8)); 4047 else if (type == LSHIFTRT) 4048 return (lr == SHIFT_LOOP 4049 || (TARGET_H8300H && mode == SImode && count == 8)); 4050 else if (type == ASHIFTRT) 4051 return (ar == SHIFT_LOOP 4052 || (TARGET_H8300H && mode == SImode && count == 8)); 4053 gcc_unreachable (); 4054} 4055 4056/* Output the assembler code for doing shifts. */ 4057 4058const char * 4059output_a_shift (rtx operands[4], rtx_code code) 4060{ 4061 static int loopend_lab; 4062 machine_mode mode = GET_MODE (operands[0]); 4063 enum shift_type shift_type; 4064 enum shift_mode shift_mode; 4065 struct shift_info info; 4066 int n; 4067 4068 loopend_lab++; 4069 4070 switch (mode) 4071 { 4072 case E_QImode: 4073 shift_mode = QIshift; 4074 break; 4075 case E_HImode: 4076 shift_mode = HIshift; 4077 break; 4078 case E_SImode: 4079 shift_mode = SIshift; 4080 break; 4081 default: 4082 gcc_unreachable (); 4083 } 4084 4085 switch (code) 4086 { 4087 case ASHIFTRT: 4088 shift_type = SHIFT_ASHIFTRT; 4089 break; 4090 case LSHIFTRT: 4091 shift_type = SHIFT_LSHIFTRT; 4092 break; 4093 case ASHIFT: 4094 shift_type = SHIFT_ASHIFT; 4095 break; 4096 default: 4097 gcc_unreachable (); 4098 } 4099 4100 /* This case must be taken care of by one of the two splitters 4101 that convert a variable shift into a loop. */ 4102 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4103 4104 n = INTVAL (operands[2]); 4105 4106 /* If the count is negative, make it 0. */ 4107 if (n < 0) 4108 n = 0; 4109 /* If the count is too big, truncate it. 4110 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4111 do the intuitive thing. */ 4112 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4113 n = GET_MODE_BITSIZE (mode); 4114 4115 get_shift_alg (shift_type, shift_mode, n, &info); 4116 4117 switch (info.alg) 4118 { 4119 case SHIFT_SPECIAL: 4120 output_asm_insn (info.special, operands); 4121 /* Fall through. */ 4122 4123 case SHIFT_INLINE: 4124 n = info.remainder; 4125 4126 /* Emit two bit shifts first. */ 4127 if (info.shift2 != NULL) 4128 { 4129 for (; n > 1; n -= 2) 4130 output_asm_insn (info.shift2, operands); 4131 } 4132 4133 /* Now emit one bit shifts for any residual. */ 4134 for (; n > 0; n--) 4135 output_asm_insn (info.shift1, operands); 4136 return ""; 4137 4138 case SHIFT_ROT_AND: 4139 { 4140 int m = GET_MODE_BITSIZE (mode) - n; 4141 const int mask = (shift_type == SHIFT_ASHIFT 4142 ? ((1 << m) - 1) << n 4143 : (1 << m) - 1); 4144 char insn_buf[200]; 4145 4146 /* Not all possibilities of rotate are supported. They shouldn't 4147 be generated, but let's watch for 'em. */ 4148 gcc_assert (info.shift1); 4149 4150 /* Emit two bit rotates first. */ 4151 if (info.shift2 != NULL) 4152 { 4153 for (; m > 1; m -= 2) 4154 output_asm_insn (info.shift2, operands); 4155 } 4156 4157 /* Now single bit rotates for any residual. */ 4158 for (; m > 0; m--) 4159 output_asm_insn (info.shift1, operands); 4160 4161 /* Now mask off the high bits. */ 4162 switch (mode) 4163 { 4164 case E_QImode: 4165 sprintf (insn_buf, "and\t#%d,%%X0", mask); 4166 break; 4167 4168 case E_HImode: 4169 sprintf (insn_buf, "and.w\t#%d,%%T0", mask); 4170 break; 4171 4172 default: 4173 gcc_unreachable (); 4174 } 4175 4176 output_asm_insn (insn_buf, operands); 4177 return ""; 4178 } 4179 4180 case SHIFT_LOOP: 4181 /* A loop to shift by a "large" constant value. 4182 If we have shift-by-2 insns, use them. */ 4183 if (info.shift2 != NULL) 4184 { 4185 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 4186 names_big[REGNO (operands[3])]); 4187 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4188 output_asm_insn (info.shift2, operands); 4189 output_asm_insn ("add #0xff,%X3", operands); 4190 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4191 if (n % 2) 4192 output_asm_insn (info.shift1, operands); 4193 } 4194 else 4195 { 4196 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 4197 names_big[REGNO (operands[3])]); 4198 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4199 output_asm_insn (info.shift1, operands); 4200 output_asm_insn ("add #0xff,%X3", operands); 4201 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4202 } 4203 return ""; 4204 4205 default: 4206 gcc_unreachable (); 4207 } 4208} 4209 4210/* Count the number of assembly instructions in a string TEMPL. */ 4211 4212static unsigned int 4213h8300_asm_insn_count (const char *templ) 4214{ 4215 unsigned int count = 1; 4216 4217 for (; *templ; templ++) 4218 if (*templ == '\n') 4219 count++; 4220 4221 return count; 4222} 4223 4224/* Compute the length of a shift insn. */ 4225 4226unsigned int 4227compute_a_shift_length (rtx operands[3], rtx_code code) 4228{ 4229 enum machine_mode mode = GET_MODE (operands[0]); 4230 enum shift_type shift_type; 4231 enum shift_mode shift_mode; 4232 struct shift_info info; 4233 unsigned int wlength = 0; 4234 4235 switch (mode) 4236 { 4237 case E_QImode: 4238 shift_mode = QIshift; 4239 break; 4240 case E_HImode: 4241 shift_mode = HIshift; 4242 break; 4243 case E_SImode: 4244 shift_mode = SIshift; 4245 break; 4246 default: 4247 gcc_unreachable (); 4248 } 4249 4250 switch (code) 4251 { 4252 case ASHIFTRT: 4253 shift_type = SHIFT_ASHIFTRT; 4254 break; 4255 case LSHIFTRT: 4256 shift_type = SHIFT_LSHIFTRT; 4257 break; 4258 case ASHIFT: 4259 shift_type = SHIFT_ASHIFT; 4260 break; 4261 default: 4262 gcc_unreachable (); 4263 } 4264 4265 if (GET_CODE (operands[2]) != CONST_INT) 4266 { 4267 /* Get the assembler code to do one shift. */ 4268 get_shift_alg (shift_type, shift_mode, 1, &info); 4269 4270 return (4 + h8300_asm_insn_count (info.shift1)) * 2; 4271 } 4272 else 4273 { 4274 int n = INTVAL (operands[2]); 4275 4276 /* If the count is negative, make it 0. */ 4277 if (n < 0) 4278 n = 0; 4279 /* If the count is too big, truncate it. 4280 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4281 do the intuitive thing. */ 4282 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4283 n = GET_MODE_BITSIZE (mode); 4284 4285 get_shift_alg (shift_type, shift_mode, n, &info); 4286 4287 switch (info.alg) 4288 { 4289 case SHIFT_SPECIAL: 4290 wlength += h8300_asm_insn_count (info.special); 4291 4292 /* Every assembly instruction used in SHIFT_SPECIAL case 4293 takes 2 bytes except xor.l, which takes 4 bytes, so if we 4294 see xor.l, we just pretend that xor.l counts as two insns 4295 so that the insn length will be computed correctly. */ 4296 if (strstr (info.special, "xor.l") != NULL) 4297 wlength++; 4298 4299 /* Fall through. */ 4300 4301 case SHIFT_INLINE: 4302 n = info.remainder; 4303 4304 if (info.shift2 != NULL) 4305 { 4306 wlength += h8300_asm_insn_count (info.shift2) * (n / 2); 4307 n = n % 2; 4308 } 4309 4310 wlength += h8300_asm_insn_count (info.shift1) * n; 4311 4312 return 2 * wlength; 4313 4314 case SHIFT_ROT_AND: 4315 { 4316 int m = GET_MODE_BITSIZE (mode) - n; 4317 4318 /* Not all possibilities of rotate are supported. They shouldn't 4319 be generated, but let's watch for 'em. */ 4320 gcc_assert (info.shift1); 4321 4322 if (info.shift2 != NULL) 4323 { 4324 wlength += h8300_asm_insn_count (info.shift2) * (m / 2); 4325 m = m % 2; 4326 } 4327 4328 wlength += h8300_asm_insn_count (info.shift1) * m; 4329 4330 /* Now mask off the high bits. */ 4331 switch (mode) 4332 { 4333 case E_QImode: 4334 wlength += 1; 4335 break; 4336 case E_HImode: 4337 wlength += 2; 4338 break; 4339 case E_SImode: 4340 wlength += 3; 4341 break; 4342 default: 4343 gcc_unreachable (); 4344 } 4345 return 2 * wlength; 4346 } 4347 4348 case SHIFT_LOOP: 4349 /* A loop to shift by a "large" constant value. 4350 If we have shift-by-2 insns, use them. */ 4351 if (info.shift2 != NULL) 4352 { 4353 wlength += 3 + h8300_asm_insn_count (info.shift2); 4354 if (n % 2) 4355 wlength += h8300_asm_insn_count (info.shift1); 4356 } 4357 else 4358 { 4359 wlength += 3 + h8300_asm_insn_count (info.shift1); 4360 } 4361 return 2 * wlength; 4362 4363 default: 4364 gcc_unreachable (); 4365 } 4366 } 4367} 4368 4369/* Compute which flag bits are valid after a shift insn. */ 4370 4371int 4372compute_a_shift_cc (rtx operands[3], rtx_code code) 4373{ 4374 machine_mode mode = GET_MODE (operands[0]); 4375 enum shift_type shift_type; 4376 enum shift_mode shift_mode; 4377 struct shift_info info; 4378 int n; 4379 4380 switch (mode) 4381 { 4382 case E_QImode: 4383 shift_mode = QIshift; 4384 break; 4385 case E_HImode: 4386 shift_mode = HIshift; 4387 break; 4388 case E_SImode: 4389 shift_mode = SIshift; 4390 break; 4391 default: 4392 gcc_unreachable (); 4393 } 4394 4395 switch (code) 4396 { 4397 case ASHIFTRT: 4398 shift_type = SHIFT_ASHIFTRT; 4399 break; 4400 case LSHIFTRT: 4401 shift_type = SHIFT_LSHIFTRT; 4402 break; 4403 case ASHIFT: 4404 shift_type = SHIFT_ASHIFT; 4405 break; 4406 default: 4407 gcc_unreachable (); 4408 } 4409 4410 /* This case must be taken care of by one of the two splitters 4411 that convert a variable shift into a loop. */ 4412 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4413 4414 n = INTVAL (operands[2]); 4415 4416 /* If the count is negative, make it 0. */ 4417 if (n < 0) 4418 n = 0; 4419 /* If the count is too big, truncate it. 4420 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4421 do the intuitive thing. */ 4422 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4423 n = GET_MODE_BITSIZE (mode); 4424 4425 get_shift_alg (shift_type, shift_mode, n, &info); 4426 4427 switch (info.alg) 4428 { 4429 case SHIFT_SPECIAL: 4430 if (info.remainder == 0) 4431 return (info.cc_special == OLD_CC_SET_ZN 4432 || info.cc_special == OLD_CC_SET_ZNV); 4433 4434 /* Fall through. */ 4435 4436 case SHIFT_INLINE: 4437 return (info.cc_inline == OLD_CC_SET_ZN 4438 || info.cc_inline == OLD_CC_SET_ZNV); 4439 4440 case SHIFT_ROT_AND: 4441 /* This case always ends with an and instruction. */ 4442 return true; 4443 4444 case SHIFT_LOOP: 4445 /* A loop to shift by a "large" constant value. 4446 If we have shift-by-2 insns, use them. */ 4447 if (info.shift2 != NULL) 4448 { 4449 if (n % 2) 4450 return (info.cc_inline == OLD_CC_SET_ZN 4451 || info.cc_inline == OLD_CC_SET_ZNV); 4452 4453 } 4454 return false; 4455 4456 default: 4457 gcc_unreachable (); 4458 } 4459} 4460 4461/* A rotation by a non-constant will cause a loop to be generated, in 4462 which a rotation by one bit is used. A rotation by a constant, 4463 including the one in the loop, will be taken care of by 4464 output_a_rotate () at the insn emit time. */ 4465 4466int 4467expand_a_rotate (rtx operands[]) 4468{ 4469 rtx dst = operands[0]; 4470 rtx src = operands[1]; 4471 rtx rotate_amount = operands[2]; 4472 machine_mode mode = GET_MODE (dst); 4473 4474 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) 4475 return false; 4476 4477 /* We rotate in place. */ 4478 emit_move_insn (dst, src); 4479 4480 if (GET_CODE (rotate_amount) != CONST_INT) 4481 { 4482 rtx counter = gen_reg_rtx (QImode); 4483 rtx_code_label *start_label = gen_label_rtx (); 4484 rtx_code_label *end_label = gen_label_rtx (); 4485 4486 /* If the rotate amount is less than or equal to 0, 4487 we go out of the loop. */ 4488 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, 4489 QImode, 0, end_label); 4490 4491 /* Initialize the loop counter. */ 4492 emit_move_insn (counter, rotate_amount); 4493 4494 emit_label (start_label); 4495 4496 /* Rotate by one bit. */ 4497 switch (mode) 4498 { 4499 case E_QImode: 4500 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); 4501 break; 4502 case E_HImode: 4503 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); 4504 break; 4505 case E_SImode: 4506 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); 4507 break; 4508 default: 4509 gcc_unreachable (); 4510 } 4511 4512 /* Decrement the counter by 1. */ 4513 emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); 4514 4515 /* If the loop counter is nonzero, we go back to the beginning 4516 of the loop. */ 4517 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, 4518 start_label); 4519 4520 emit_label (end_label); 4521 } 4522 else 4523 { 4524 /* Rotate by AMOUNT bits. */ 4525 switch (mode) 4526 { 4527 case E_QImode: 4528 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); 4529 break; 4530 case E_HImode: 4531 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); 4532 break; 4533 case E_SImode: 4534 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); 4535 break; 4536 default: 4537 gcc_unreachable (); 4538 } 4539 } 4540 4541 return 1; 4542} 4543 4544/* Output a rotate insn. */ 4545 4546const char * 4547output_a_rotate (enum rtx_code code, rtx *operands) 4548{ 4549 rtx dst = operands[0]; 4550 rtx rotate_amount = operands[2]; 4551 enum shift_mode rotate_mode; 4552 enum shift_type rotate_type; 4553 const char *insn_buf; 4554 int bits; 4555 int amount; 4556 machine_mode mode = GET_MODE (dst); 4557 4558 gcc_assert (GET_CODE (rotate_amount) == CONST_INT); 4559 4560 switch (mode) 4561 { 4562 case E_QImode: 4563 rotate_mode = QIshift; 4564 break; 4565 case E_HImode: 4566 rotate_mode = HIshift; 4567 break; 4568 case E_SImode: 4569 rotate_mode = SIshift; 4570 break; 4571 default: 4572 gcc_unreachable (); 4573 } 4574 4575 switch (code) 4576 { 4577 case ROTATERT: 4578 rotate_type = SHIFT_ASHIFT; 4579 break; 4580 case ROTATE: 4581 rotate_type = SHIFT_LSHIFTRT; 4582 break; 4583 default: 4584 gcc_unreachable (); 4585 } 4586 4587 amount = INTVAL (rotate_amount); 4588 4589 /* Clean up AMOUNT. */ 4590 if (amount < 0) 4591 amount = 0; 4592 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 4593 amount = GET_MODE_BITSIZE (mode); 4594 4595 /* Determine the faster direction. After this phase, amount will be 4596 at most a half of GET_MODE_BITSIZE (mode). */ 4597 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 4598 { 4599 /* Flip the direction. */ 4600 amount = GET_MODE_BITSIZE (mode) - amount; 4601 rotate_type = 4602 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 4603 } 4604 4605 /* See if a byte swap (in HImode) or a word swap (in SImode) can 4606 boost up the rotation. */ 4607 if ((mode == HImode && TARGET_H8300H && amount >= 6) 4608 || (mode == HImode && TARGET_H8300S && amount == 8) 4609 || (mode == SImode && TARGET_H8300H && amount >= 10) 4610 || (mode == SImode && TARGET_H8300S && amount >= 13)) 4611 { 4612 switch (mode) 4613 { 4614 case E_HImode: 4615 /* This code works on any family. */ 4616 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; 4617 output_asm_insn (insn_buf, operands); 4618 break; 4619 4620 case E_SImode: 4621 /* This code works on the H8/300H and H8S. */ 4622 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; 4623 output_asm_insn (insn_buf, operands); 4624 break; 4625 4626 default: 4627 gcc_unreachable (); 4628 } 4629 4630 /* Adjust AMOUNT and flip the direction. */ 4631 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 4632 rotate_type = 4633 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 4634 } 4635 4636 /* Output rotate insns. */ 4637 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) 4638 { 4639 if (bits == 2) 4640 insn_buf = rotate_two[rotate_type][rotate_mode]; 4641 else 4642 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; 4643 4644 for (; amount >= bits; amount -= bits) 4645 output_asm_insn (insn_buf, operands); 4646 } 4647 4648 return ""; 4649} 4650 4651/* Compute the length of a rotate insn. */ 4652 4653unsigned int 4654compute_a_rotate_length (rtx *operands) 4655{ 4656 rtx src = operands[1]; 4657 rtx amount_rtx = operands[2]; 4658 machine_mode mode = GET_MODE (src); 4659 int amount; 4660 unsigned int length = 0; 4661 4662 gcc_assert (GET_CODE (amount_rtx) == CONST_INT); 4663 4664 amount = INTVAL (amount_rtx); 4665 4666 /* Clean up AMOUNT. */ 4667 if (amount < 0) 4668 amount = 0; 4669 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 4670 amount = GET_MODE_BITSIZE (mode); 4671 4672 /* Determine the faster direction. After this phase, amount 4673 will be at most a half of GET_MODE_BITSIZE (mode). */ 4674 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 4675 /* Flip the direction. */ 4676 amount = GET_MODE_BITSIZE (mode) - amount; 4677 4678 /* See if a byte swap (in HImode) or a word swap (in SImode) can 4679 boost up the rotation. */ 4680 if ((mode == HImode && TARGET_H8300H && amount >= 6) 4681 || (mode == HImode && TARGET_H8300S && amount == 8) 4682 || (mode == SImode && TARGET_H8300H && amount >= 10) 4683 || (mode == SImode && TARGET_H8300S && amount >= 13)) 4684 { 4685 /* Adjust AMOUNT and flip the direction. */ 4686 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 4687 length += 6; 4688 } 4689 4690 /* We use 2-bit rotations on the H8S. */ 4691 if (TARGET_H8300S) 4692 amount = amount / 2 + amount % 2; 4693 4694 /* The H8/300 uses three insns to rotate one bit, taking 6 4695 length. */ 4696 length += amount * 2; 4697 4698 return length; 4699} 4700 4701/* Fix the operands of a gen_xxx so that it could become a bit 4702 operating insn. */ 4703 4704int 4705fix_bit_operand (rtx *operands, enum rtx_code code) 4706{ 4707 /* The bit_operand predicate accepts any memory during RTL generation, but 4708 only 'U' memory afterwards, so if this is a MEM operand, we must force 4709 it to be valid for 'U' by reloading the address. */ 4710 4711 if (code == AND 4712 ? single_zero_operand (operands[2], QImode) 4713 : single_one_operand (operands[2], QImode)) 4714 { 4715 /* OK to have a memory dest. */ 4716 if (GET_CODE (operands[0]) == MEM 4717 && !satisfies_constraint_U (operands[0])) 4718 { 4719 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), 4720 copy_to_mode_reg (Pmode, 4721 XEXP (operands[0], 0))); 4722 MEM_COPY_ATTRIBUTES (mem, operands[0]); 4723 operands[0] = mem; 4724 } 4725 4726 if (GET_CODE (operands[1]) == MEM 4727 && !satisfies_constraint_U (operands[1])) 4728 { 4729 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), 4730 copy_to_mode_reg (Pmode, 4731 XEXP (operands[1], 0))); 4732 MEM_COPY_ATTRIBUTES (mem, operands[0]); 4733 operands[1] = mem; 4734 } 4735 return 0; 4736 } 4737 4738 /* Dest and src op must be register. */ 4739 4740 operands[1] = force_reg (QImode, operands[1]); 4741 { 4742 rtx res = gen_reg_rtx (QImode); 4743 switch (code) 4744 { 4745 case AND: 4746 emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); 4747 break; 4748 case IOR: 4749 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); 4750 break; 4751 case XOR: 4752 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); 4753 break; 4754 default: 4755 gcc_unreachable (); 4756 } 4757 emit_insn (gen_movqi (operands[0], res)); 4758 } 4759 return 1; 4760} 4761 4762/* Return nonzero if FUNC is an interrupt function as specified 4763 by the "interrupt" attribute. */ 4764 4765static int 4766h8300_interrupt_function_p (tree func) 4767{ 4768 tree a; 4769 4770 if (TREE_CODE (func) != FUNCTION_DECL) 4771 return 0; 4772 4773 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 4774 return a != NULL_TREE; 4775} 4776 4777/* Return nonzero if FUNC is a saveall function as specified by the 4778 "saveall" attribute. */ 4779 4780static int 4781h8300_saveall_function_p (tree func) 4782{ 4783 tree a; 4784 4785 if (TREE_CODE (func) != FUNCTION_DECL) 4786 return 0; 4787 4788 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); 4789 return a != NULL_TREE; 4790} 4791 4792/* Return nonzero if FUNC is an OS_Task function as specified 4793 by the "OS_Task" attribute. */ 4794 4795static int 4796h8300_os_task_function_p (tree func) 4797{ 4798 tree a; 4799 4800 if (TREE_CODE (func) != FUNCTION_DECL) 4801 return 0; 4802 4803 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); 4804 return a != NULL_TREE; 4805} 4806 4807/* Return nonzero if FUNC is a monitor function as specified 4808 by the "monitor" attribute. */ 4809 4810static int 4811h8300_monitor_function_p (tree func) 4812{ 4813 tree a; 4814 4815 if (TREE_CODE (func) != FUNCTION_DECL) 4816 return 0; 4817 4818 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); 4819 return a != NULL_TREE; 4820} 4821 4822/* Return nonzero if FUNC is a function that should be called 4823 through the function vector. */ 4824 4825int 4826h8300_funcvec_function_p (tree func) 4827{ 4828 tree a; 4829 4830 if (TREE_CODE (func) != FUNCTION_DECL) 4831 return 0; 4832 4833 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); 4834 return a != NULL_TREE; 4835} 4836 4837/* Return nonzero if DECL is a variable that's in the eight bit 4838 data area. */ 4839 4840int 4841h8300_eightbit_data_p (tree decl) 4842{ 4843 tree a; 4844 4845 if (TREE_CODE (decl) != VAR_DECL) 4846 return 0; 4847 4848 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); 4849 return a != NULL_TREE; 4850} 4851 4852/* Return nonzero if DECL is a variable that's in the tiny 4853 data area. */ 4854 4855int 4856h8300_tiny_data_p (tree decl) 4857{ 4858 tree a; 4859 4860 if (TREE_CODE (decl) != VAR_DECL) 4861 return 0; 4862 4863 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); 4864 return a != NULL_TREE; 4865} 4866 4867/* Generate an 'interrupt_handler' attribute for decls. We convert 4868 all the pragmas to corresponding attributes. */ 4869 4870static void 4871h8300_insert_attributes (tree node, tree *attributes) 4872{ 4873 if (TREE_CODE (node) == FUNCTION_DECL) 4874 { 4875 if (pragma_interrupt) 4876 { 4877 pragma_interrupt = 0; 4878 4879 /* Add an 'interrupt_handler' attribute. */ 4880 *attributes = tree_cons (get_identifier ("interrupt_handler"), 4881 NULL, *attributes); 4882 } 4883 4884 if (pragma_saveall) 4885 { 4886 pragma_saveall = 0; 4887 4888 /* Add an 'saveall' attribute. */ 4889 *attributes = tree_cons (get_identifier ("saveall"), 4890 NULL, *attributes); 4891 } 4892 } 4893} 4894 4895/* Supported attributes: 4896 4897 interrupt_handler: output a prologue and epilogue suitable for an 4898 interrupt handler. 4899 4900 saveall: output a prologue and epilogue that saves and restores 4901 all registers except the stack pointer. 4902 4903 function_vector: This function should be called through the 4904 function vector. 4905 4906 eightbit_data: This variable lives in the 8-bit data area and can 4907 be referenced with 8-bit absolute memory addresses. 4908 4909 tiny_data: This variable lives in the tiny data area and can be 4910 referenced with 16-bit absolute memory references. */ 4911 4912static const struct attribute_spec h8300_attribute_table[] = 4913{ 4914 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, 4915 affects_type_identity, handler, exclude } */ 4916 { "interrupt_handler", 0, 0, true, false, false, false, 4917 h8300_handle_fndecl_attribute, NULL }, 4918 { "saveall", 0, 0, true, false, false, false, 4919 h8300_handle_fndecl_attribute, NULL }, 4920 { "OS_Task", 0, 0, true, false, false, false, 4921 h8300_handle_fndecl_attribute, NULL }, 4922 { "monitor", 0, 0, true, false, false, false, 4923 h8300_handle_fndecl_attribute, NULL }, 4924 { "function_vector", 0, 0, true, false, false, false, 4925 h8300_handle_fndecl_attribute, NULL }, 4926 { "eightbit_data", 0, 0, true, false, false, false, 4927 h8300_handle_eightbit_data_attribute, NULL }, 4928 { "tiny_data", 0, 0, true, false, false, false, 4929 h8300_handle_tiny_data_attribute, NULL }, 4930 { NULL, 0, 0, false, false, false, false, NULL, NULL } 4931}; 4932 4933 4934/* Handle an attribute requiring a FUNCTION_DECL; arguments as in 4935 struct attribute_spec.handler. */ 4936static tree 4937h8300_handle_fndecl_attribute (tree *node, tree name, 4938 tree args ATTRIBUTE_UNUSED, 4939 int flags ATTRIBUTE_UNUSED, 4940 bool *no_add_attrs) 4941{ 4942 if (TREE_CODE (*node) != FUNCTION_DECL) 4943 { 4944 warning (OPT_Wattributes, "%qE attribute only applies to functions", 4945 name); 4946 *no_add_attrs = true; 4947 } 4948 4949 return NULL_TREE; 4950} 4951 4952/* Handle an "eightbit_data" attribute; arguments as in 4953 struct attribute_spec.handler. */ 4954static tree 4955h8300_handle_eightbit_data_attribute (tree *node, tree name, 4956 tree args ATTRIBUTE_UNUSED, 4957 int flags ATTRIBUTE_UNUSED, 4958 bool *no_add_attrs) 4959{ 4960 tree decl = *node; 4961 4962 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 4963 { 4964 set_decl_section_name (decl, ".eight"); 4965 } 4966 else 4967 { 4968 warning (OPT_Wattributes, "%qE attribute ignored", 4969 name); 4970 *no_add_attrs = true; 4971 } 4972 4973 return NULL_TREE; 4974} 4975 4976/* Handle an "tiny_data" attribute; arguments as in 4977 struct attribute_spec.handler. */ 4978static tree 4979h8300_handle_tiny_data_attribute (tree *node, tree name, 4980 tree args ATTRIBUTE_UNUSED, 4981 int flags ATTRIBUTE_UNUSED, 4982 bool *no_add_attrs) 4983{ 4984 tree decl = *node; 4985 4986 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 4987 { 4988 set_decl_section_name (decl, ".tiny"); 4989 } 4990 else 4991 { 4992 warning (OPT_Wattributes, "%qE attribute ignored", 4993 name); 4994 *no_add_attrs = true; 4995 } 4996 4997 return NULL_TREE; 4998} 4999 5000/* Mark function vectors, and various small data objects. */ 5001 5002static void 5003h8300_encode_section_info (tree decl, rtx rtl, int first) 5004{ 5005 int extra_flags = 0; 5006 5007 default_encode_section_info (decl, rtl, first); 5008 5009 if (TREE_CODE (decl) == FUNCTION_DECL 5010 && h8300_funcvec_function_p (decl)) 5011 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; 5012 else if (TREE_CODE (decl) == VAR_DECL 5013 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 5014 { 5015 if (h8300_eightbit_data_p (decl)) 5016 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; 5017 else if (first && h8300_tiny_data_p (decl)) 5018 extra_flags = SYMBOL_FLAG_TINY_DATA; 5019 } 5020 5021 if (extra_flags) 5022 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 5023} 5024 5025/* Output a single-bit extraction. */ 5026 5027const char * 5028output_simode_bld (int bild, rtx operands[]) 5029{ 5030 /* Determine if we can clear the destination first. */ 5031 int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) 5032 && REGNO (operands[0]) != REGNO (operands[1])); 5033 5034 if (clear_first) 5035 output_asm_insn ("sub.l\t%S0,%S0", operands); 5036 5037 /* Output the bit load or bit inverse load. */ 5038 if (bild) 5039 output_asm_insn ("bild\t%Z2,%Y1", operands); 5040 else 5041 output_asm_insn ("bld\t%Z2,%Y1", operands); 5042 5043 if (!clear_first) 5044 output_asm_insn ("xor.l\t%S0,%S0", operands); 5045 5046 /* Perform the bit store. */ 5047 output_asm_insn ("rotxl.l\t%S0", operands); 5048 5049 /* All done. */ 5050 return ""; 5051} 5052 5053/* Delayed-branch scheduling is more effective if we have some idea 5054 how long each instruction will be. Use a shorten_branches pass 5055 to get an initial estimate. */ 5056 5057static void 5058h8300_reorg (void) 5059{ 5060 if (flag_delayed_branch) 5061 shorten_branches (get_insns ()); 5062} 5063 5064/* Nonzero if X is a constant address suitable as an 8-bit absolute, 5065 which is a special case of the 'R' operand. */ 5066 5067int 5068h8300_eightbit_constant_address_p (rtx x) 5069{ 5070 /* The ranges of the 8-bit area. */ 5071 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); 5072 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); 5073 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); 5074 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); 5075 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); 5076 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); 5077 5078 unsigned HOST_WIDE_INT addr; 5079 5080 /* We accept symbols declared with eightbit_data. */ 5081 if (GET_CODE (x) == SYMBOL_REF) 5082 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; 5083 5084 if (GET_CODE (x) == CONST 5085 && GET_CODE (XEXP (x, 0)) == PLUS 5086 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 5087 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0) 5088 return 1; 5089 5090 if (GET_CODE (x) != CONST_INT) 5091 return 0; 5092 5093 addr = INTVAL (x); 5094 5095 return (0 5096 || (TARGET_NORMAL_MODE && IN_RANGE (addr, n1, n2)) 5097 || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) 5098 || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); 5099} 5100 5101/* Nonzero if X is a constant address suitable as an 16-bit absolute 5102 on H8/300H and H8S. */ 5103 5104int 5105h8300_tiny_constant_address_p (rtx x) 5106{ 5107 /* The ranges of the 16-bit area. */ 5108 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); 5109 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); 5110 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); 5111 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); 5112 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); 5113 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); 5114 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); 5115 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); 5116 5117 unsigned HOST_WIDE_INT addr; 5118 5119 switch (GET_CODE (x)) 5120 { 5121 case SYMBOL_REF: 5122 /* In the normal mode, any symbol fits in the 16-bit absolute 5123 address range. We also accept symbols declared with 5124 tiny_data. */ 5125 return (TARGET_NORMAL_MODE 5126 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); 5127 5128 case CONST_INT: 5129 addr = INTVAL (x); 5130 return (TARGET_NORMAL_MODE 5131 || (TARGET_H8300H 5132 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) 5133 || (TARGET_H8300S 5134 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); 5135 5136 case CONST: 5137 return TARGET_NORMAL_MODE; 5138 5139 default: 5140 return 0; 5141 } 5142 5143} 5144 5145/* Return nonzero if ADDR1 and ADDR2 point to consecutive memory 5146 locations that can be accessed as a 16-bit word. */ 5147 5148int 5149byte_accesses_mergeable_p (rtx addr1, rtx addr2) 5150{ 5151 HOST_WIDE_INT offset1, offset2; 5152 rtx reg1, reg2; 5153 5154 if (REG_P (addr1)) 5155 { 5156 reg1 = addr1; 5157 offset1 = 0; 5158 } 5159 else if (GET_CODE (addr1) == PLUS 5160 && REG_P (XEXP (addr1, 0)) 5161 && GET_CODE (XEXP (addr1, 1)) == CONST_INT) 5162 { 5163 reg1 = XEXP (addr1, 0); 5164 offset1 = INTVAL (XEXP (addr1, 1)); 5165 } 5166 else 5167 return 0; 5168 5169 if (REG_P (addr2)) 5170 { 5171 reg2 = addr2; 5172 offset2 = 0; 5173 } 5174 else if (GET_CODE (addr2) == PLUS 5175 && REG_P (XEXP (addr2, 0)) 5176 && GET_CODE (XEXP (addr2, 1)) == CONST_INT) 5177 { 5178 reg2 = XEXP (addr2, 0); 5179 offset2 = INTVAL (XEXP (addr2, 1)); 5180 } 5181 else 5182 return 0; 5183 5184 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) 5185 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) 5186 && offset1 % 2 == 0 5187 && offset1 + 1 == offset2) 5188 return 1; 5189 5190 return 0; 5191} 5192 5193/* Return nonzero if we have the same comparison insn as I3 two insns 5194 before I3. I3 is assumed to be a comparison insn. */ 5195 5196int 5197same_cmp_preceding_p (rtx_insn *i3) 5198{ 5199 rtx_insn *i1, *i2; 5200 5201 /* Make sure we have a sequence of three insns. */ 5202 i2 = prev_nonnote_insn (i3); 5203 if (i2 == NULL) 5204 return 0; 5205 i1 = prev_nonnote_insn (i2); 5206 if (i1 == NULL) 5207 return 0; 5208 5209 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5210 && any_condjump_p (i2) && onlyjump_p (i2)); 5211} 5212 5213/* Return nonzero if we have the same comparison insn as I1 two insns 5214 after I1. I1 is assumed to be a comparison insn. */ 5215 5216int 5217same_cmp_following_p (rtx_insn *i1) 5218{ 5219 rtx_insn *i2, *i3; 5220 5221 /* Make sure we have a sequence of three insns. */ 5222 i2 = next_nonnote_insn (i1); 5223 if (i2 == NULL) 5224 return 0; 5225 i3 = next_nonnote_insn (i2); 5226 if (i3 == NULL) 5227 return 0; 5228 5229 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5230 && any_condjump_p (i2) && onlyjump_p (i2)); 5231} 5232 5233/* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes 5234 (or pops) N registers. OPERANDS are assumed to be an array of 5235 registers. */ 5236 5237int 5238h8300_regs_ok_for_stm (int n, rtx operands[]) 5239{ 5240 switch (n) 5241 { 5242 case 2: 5243 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) 5244 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) 5245 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); 5246 case 3: 5247 return ((REGNO (operands[0]) == 0 5248 && REGNO (operands[1]) == 1 5249 && REGNO (operands[2]) == 2) 5250 || (REGNO (operands[0]) == 4 5251 && REGNO (operands[1]) == 5 5252 && REGNO (operands[2]) == 6)); 5253 5254 case 4: 5255 return (REGNO (operands[0]) == 0 5256 && REGNO (operands[1]) == 1 5257 && REGNO (operands[2]) == 2 5258 && REGNO (operands[3]) == 3); 5259 default: 5260 gcc_unreachable (); 5261 } 5262} 5263 5264/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 5265 5266int 5267h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5268 unsigned int new_reg) 5269{ 5270 /* Interrupt functions can only use registers that have already been 5271 saved by the prologue, even if they would normally be 5272 call-clobbered. */ 5273 5274 if (h8300_current_function_interrupt_function_p () 5275 && !df_regs_ever_live_p (new_reg)) 5276 return 0; 5277 5278 return 1; 5279} 5280 5281/* Returns true if register REGNO is safe to be allocated as a scratch 5282 register in the current function. */ 5283 5284static bool 5285h8300_hard_regno_scratch_ok (unsigned int regno) 5286{ 5287 if (h8300_current_function_interrupt_function_p () 5288 && ! WORD_REG_USED (regno)) 5289 return false; 5290 5291 return true; 5292} 5293 5294 5295/* Return nonzero if X is a REG or SUBREG suitable as a base register. */ 5296 5297static int 5298h8300_rtx_ok_for_base_p (rtx x, int strict) 5299{ 5300 /* Strip off SUBREG if any. */ 5301 if (GET_CODE (x) == SUBREG) 5302 x = SUBREG_REG (x); 5303 5304 return (REG_P (x) 5305 && (strict 5306 ? REG_OK_FOR_BASE_STRICT_P (x) 5307 : REG_OK_FOR_BASE_NONSTRICT_P (x))); 5308} 5309 5310/* Return nozero if X is a legitimate address. On the H8/300, a 5311 legitimate address has the form REG, REG+CONSTANT_ADDRESS or 5312 CONSTANT_ADDRESS. */ 5313 5314static bool 5315h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict) 5316{ 5317 /* The register indirect addresses like @er0 is always valid. */ 5318 if (h8300_rtx_ok_for_base_p (x, strict)) 5319 return 1; 5320 5321 if (CONSTANT_ADDRESS_P (x)) 5322 return 1; 5323 5324 if (TARGET_H8300SX 5325 && ( GET_CODE (x) == PRE_INC 5326 || GET_CODE (x) == PRE_DEC 5327 || GET_CODE (x) == POST_INC 5328 || GET_CODE (x) == POST_DEC) 5329 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) 5330 return 1; 5331 5332 if (GET_CODE (x) == PLUS 5333 && CONSTANT_ADDRESS_P (XEXP (x, 1)) 5334 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), 5335 mode, 0), strict)) 5336 return 1; 5337 5338 return 0; 5339} 5340 5341/* Implement TARGET_HARD_REGNO_MODE_OK. */ 5342 5343static bool 5344h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 5345{ 5346 /* MAC register can only be of SImode. Otherwise, anything 5347 goes. */ 5348 return regno == MAC_REG ? mode == SImode : 1; 5349} 5350 5351/* Implement TARGET_MODES_TIEABLE_P. */ 5352 5353static bool 5354h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2) 5355{ 5356 return (mode1 == mode2 5357 || ((mode1 == QImode 5358 || mode1 == HImode 5359 || mode1 == SImode) 5360 && (mode2 == QImode 5361 || mode2 == HImode 5362 || mode2 == SImode))); 5363} 5364 5365/* Helper function for the move patterns. Make sure a move is legitimate. */ 5366 5367bool 5368h8300_move_ok (rtx dest, rtx src) 5369{ 5370 rtx addr, other; 5371 5372 /* Validate that at least one operand is a register. */ 5373 if (MEM_P (dest)) 5374 { 5375 if (MEM_P (src) || CONSTANT_P (src)) 5376 return false; 5377 addr = XEXP (dest, 0); 5378 other = src; 5379 } 5380 else if (MEM_P (src)) 5381 { 5382 addr = XEXP (src, 0); 5383 other = dest; 5384 } 5385 else 5386 return true; 5387 5388 /* Validate that auto-inc doesn't affect OTHER. */ 5389 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) 5390 return true; 5391 addr = XEXP (addr, 0); 5392 5393 if (addr == stack_pointer_rtx) 5394 return register_no_sp_elim_operand (other, VOIDmode); 5395 else 5396 return !reg_overlap_mentioned_p(other, addr); 5397} 5398 5399/* Perform target dependent optabs initialization. */ 5400static void 5401h8300_init_libfuncs (void) 5402{ 5403 set_optab_libfunc (smul_optab, HImode, "__mulhi3"); 5404 set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); 5405 set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); 5406 set_optab_libfunc (smod_optab, HImode, "__modhi3"); 5407 set_optab_libfunc (umod_optab, HImode, "__umodhi3"); 5408} 5409 5410/* Worker function for TARGET_FUNCTION_VALUE. 5411 5412 On the H8 the return value is in R0/R1. */ 5413 5414static rtx 5415h8300_function_value (const_tree ret_type, 5416 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 5417 bool outgoing ATTRIBUTE_UNUSED) 5418{ 5419 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); 5420} 5421 5422/* Worker function for TARGET_LIBCALL_VALUE. 5423 5424 On the H8 the return value is in R0/R1. */ 5425 5426static rtx 5427h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 5428{ 5429 return gen_rtx_REG (mode, R0_REG); 5430} 5431 5432/* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 5433 5434 On the H8, R0 is the only register thus used. */ 5435 5436static bool 5437h8300_function_value_regno_p (const unsigned int regno) 5438{ 5439 return (regno == R0_REG); 5440} 5441 5442/* Worker function for TARGET_RETURN_IN_MEMORY. */ 5443 5444static bool 5445h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5446{ 5447 return (TYPE_MODE (type) == BLKmode 5448 || GET_MODE_SIZE (TYPE_MODE (type)) > 8); 5449} 5450 5451/* We emit the entire trampoline here. Depending on the pointer size, 5452 we use a different trampoline. 5453 5454 Pmode == HImode 5455 vvvv context 5456 1 0000 7903xxxx mov.w #0x1234,r3 5457 2 0004 5A00xxxx jmp @0x1234 5458 ^^^^ function 5459 5460 Pmode == SImode 5461 vvvvvvvv context 5462 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 5463 3 0006 5Axxxxxx jmp @0x123456 5464 ^^^^^^ function 5465*/ 5466 5467static void 5468h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 5469{ 5470 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 5471 rtx mem; 5472 5473 if (Pmode == HImode) 5474 { 5475 mem = adjust_address (m_tramp, HImode, 0); 5476 emit_move_insn (mem, GEN_INT (0x7903)); 5477 mem = adjust_address (m_tramp, Pmode, 2); 5478 emit_move_insn (mem, cxt); 5479 mem = adjust_address (m_tramp, HImode, 4); 5480 emit_move_insn (mem, GEN_INT (0x5a00)); 5481 mem = adjust_address (m_tramp, Pmode, 6); 5482 emit_move_insn (mem, fnaddr); 5483 } 5484 else 5485 { 5486 rtx tem; 5487 5488 mem = adjust_address (m_tramp, HImode, 0); 5489 emit_move_insn (mem, GEN_INT (0x7a03)); 5490 mem = adjust_address (m_tramp, Pmode, 2); 5491 emit_move_insn (mem, cxt); 5492 5493 tem = copy_to_reg (fnaddr); 5494 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); 5495 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); 5496 mem = adjust_address (m_tramp, SImode, 6); 5497 emit_move_insn (mem, tem); 5498 } 5499} 5500 5501/* Implement PUSH_ROUNDING. 5502 5503 On the H8/300, @-sp really pushes a byte if you ask it to - but that's 5504 dangerous, so we claim that it always pushes a word, then we catch 5505 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. 5506 5507 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 5508 and doing a similar thing. */ 5509 5510poly_int64 5511h8300_push_rounding (poly_int64 bytes) 5512{ 5513 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8)); 5514} 5515 5516static bool 5517h8300_ok_for_sibcall_p (tree fndecl, tree) 5518{ 5519 /* If either the caller or target are special, then assume sibling 5520 calls are not OK. */ 5521 if (!fndecl 5522 || h8300_os_task_function_p (fndecl) 5523 || h8300_monitor_function_p (fndecl) 5524 || h8300_interrupt_function_p (fndecl) 5525 || h8300_saveall_function_p (fndecl) 5526 || h8300_os_task_function_p (current_function_decl) 5527 || h8300_monitor_function_p (current_function_decl) 5528 || h8300_interrupt_function_p (current_function_decl) 5529 || h8300_saveall_function_p (current_function_decl)) 5530 return false; 5531 5532 return 1; 5533} 5534 5535/* Initialize the GCC target structure. */ 5536#undef TARGET_ATTRIBUTE_TABLE 5537#define TARGET_ATTRIBUTE_TABLE h8300_attribute_table 5538 5539#undef TARGET_ASM_ALIGNED_HI_OP 5540#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 5541 5542#undef TARGET_ASM_FILE_START 5543#define TARGET_ASM_FILE_START h8300_file_start 5544#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 5545#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 5546 5547#undef TARGET_ASM_FILE_END 5548#define TARGET_ASM_FILE_END h8300_file_end 5549 5550#undef TARGET_PRINT_OPERAND 5551#define TARGET_PRINT_OPERAND h8300_print_operand 5552#undef TARGET_PRINT_OPERAND_ADDRESS 5553#define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address 5554#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 5555#define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p 5556 5557#undef TARGET_ENCODE_SECTION_INFO 5558#define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info 5559 5560#undef TARGET_INSERT_ATTRIBUTES 5561#define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes 5562 5563#undef TARGET_REGISTER_MOVE_COST 5564#define TARGET_REGISTER_MOVE_COST h8300_register_move_cost 5565 5566#undef TARGET_RTX_COSTS 5567#define TARGET_RTX_COSTS h8300_rtx_costs 5568 5569#undef TARGET_INIT_LIBFUNCS 5570#define TARGET_INIT_LIBFUNCS h8300_init_libfuncs 5571 5572#undef TARGET_FUNCTION_VALUE 5573#define TARGET_FUNCTION_VALUE h8300_function_value 5574 5575#undef TARGET_LIBCALL_VALUE 5576#define TARGET_LIBCALL_VALUE h8300_libcall_value 5577 5578#undef TARGET_FUNCTION_VALUE_REGNO_P 5579#define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p 5580 5581#undef TARGET_RETURN_IN_MEMORY 5582#define TARGET_RETURN_IN_MEMORY h8300_return_in_memory 5583 5584#undef TARGET_FUNCTION_ARG 5585#define TARGET_FUNCTION_ARG h8300_function_arg 5586 5587#undef TARGET_FUNCTION_ARG_ADVANCE 5588#define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance 5589 5590#undef TARGET_MACHINE_DEPENDENT_REORG 5591#define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg 5592 5593#undef TARGET_HARD_REGNO_SCRATCH_OK 5594#define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok 5595 5596#undef TARGET_HARD_REGNO_MODE_OK 5597#define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok 5598 5599#undef TARGET_MODES_TIEABLE_P 5600#define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p 5601 5602#undef TARGET_LRA_P 5603#define TARGET_LRA_P hook_bool_void_false 5604 5605#undef TARGET_LEGITIMATE_ADDRESS_P 5606#define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p 5607 5608#undef TARGET_CAN_ELIMINATE 5609#define TARGET_CAN_ELIMINATE h8300_can_eliminate 5610 5611#undef TARGET_CONDITIONAL_REGISTER_USAGE 5612#define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage 5613 5614#undef TARGET_TRAMPOLINE_INIT 5615#define TARGET_TRAMPOLINE_INIT h8300_trampoline_init 5616 5617#undef TARGET_OPTION_OVERRIDE 5618#define TARGET_OPTION_OVERRIDE h8300_option_override 5619 5620#undef TARGET_MODE_DEPENDENT_ADDRESS_P 5621#define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p 5622 5623#undef TARGET_HAVE_SPECULATION_SAFE_VALUE 5624#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 5625 5626#undef TARGET_FLAGS_REGNUM 5627#define TARGET_FLAGS_REGNUM 12 5628 5629#undef TARGET_FUNCTION_OK_FOR_SIBCALL 5630#define TARGET_FUNCTION_OK_FOR_SIBCALL h8300_ok_for_sibcall_p 5631 5632struct gcc_target targetm = TARGET_INITIALIZER; 5633