1/* Definitions of Tensilica's Xtensa target machine for GNU compiler. 2 Copyright (C) 2001-2020 Free Software Foundation, Inc. 3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify it under 8the terms of the GNU General Public License as published by the Free 9Software Foundation; either version 3, or (at your option) any later 10version. 11 12GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13WARRANTY; without even the implied warranty of MERCHANTABILITY or 14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING3. If not see 19<http://www.gnu.org/licenses/>. */ 20 21/* Get Xtensa configuration settings */ 22#include "xtensa-config.h" 23 24/* External variables defined in xtensa.c. */ 25 26/* Macros used in the machine description to select various Xtensa 27 configuration options. */ 28#ifndef XCHAL_HAVE_MUL32_HIGH 29#define XCHAL_HAVE_MUL32_HIGH 0 30#endif 31#ifndef XCHAL_HAVE_RELEASE_SYNC 32#define XCHAL_HAVE_RELEASE_SYNC 0 33#endif 34#ifndef XCHAL_HAVE_S32C1I 35#define XCHAL_HAVE_S32C1I 0 36#endif 37#ifndef XCHAL_HAVE_THREADPTR 38#define XCHAL_HAVE_THREADPTR 0 39#endif 40#ifndef XCHAL_HAVE_FP_POSTINC 41#define XCHAL_HAVE_FP_POSTINC 0 42#endif 43#define TARGET_BIG_ENDIAN XCHAL_HAVE_BE 44#define TARGET_DENSITY XCHAL_HAVE_DENSITY 45#define TARGET_MAC16 XCHAL_HAVE_MAC16 46#define TARGET_MUL16 XCHAL_HAVE_MUL16 47#define TARGET_MUL32 XCHAL_HAVE_MUL32 48#define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH 49#define TARGET_DIV32 XCHAL_HAVE_DIV32 50#define TARGET_NSA XCHAL_HAVE_NSA 51#define TARGET_MINMAX XCHAL_HAVE_MINMAX 52#define TARGET_SEXT XCHAL_HAVE_SEXT 53#define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS 54#define TARGET_HARD_FLOAT XCHAL_HAVE_FP 55#define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV 56#define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP 57#define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT 58#define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT 59#define TARGET_HARD_FLOAT_POSTINC XCHAL_HAVE_FP_POSTINC 60#define TARGET_ABS XCHAL_HAVE_ABS 61#define TARGET_ADDX XCHAL_HAVE_ADDX 62#define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC 63#define TARGET_S32C1I XCHAL_HAVE_S32C1I 64#define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS 65#define TARGET_THREADPTR XCHAL_HAVE_THREADPTR 66#define TARGET_LOOPS XCHAL_HAVE_LOOPS 67#define TARGET_WINDOWED_ABI (XSHAL_ABI == XTHAL_ABI_WINDOWED) 68#define TARGET_DEBUG XCHAL_HAVE_DEBUG 69#define TARGET_L32R XCHAL_HAVE_L32R 70 71#define TARGET_DEFAULT (MASK_SERIALIZE_VOLATILE) 72 73#ifndef HAVE_AS_TLS 74#define HAVE_AS_TLS 0 75#endif 76 77 78/* Target CPU builtins. */ 79#define TARGET_CPU_CPP_BUILTINS() \ 80 do { \ 81 builtin_assert ("cpu=xtensa"); \ 82 builtin_assert ("machine=xtensa"); \ 83 builtin_define ("__xtensa__"); \ 84 builtin_define ("__XTENSA__"); \ 85 builtin_define (TARGET_WINDOWED_ABI ? \ 86 "__XTENSA_WINDOWED_ABI__" : "__XTENSA_CALL0_ABI__");\ 87 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ 88 if (!TARGET_HARD_FLOAT) \ 89 builtin_define ("__XTENSA_SOFT_FLOAT__"); \ 90 } while (0) 91 92#define CPP_SPEC " %(subtarget_cpp_spec) " 93 94#ifndef SUBTARGET_CPP_SPEC 95#define SUBTARGET_CPP_SPEC "" 96#endif 97 98#define EXTRA_SPECS \ 99 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, 100 101/* Target machine storage layout */ 102 103/* Define this if most significant bit is lowest numbered 104 in instructions that operate on numbered bit-fields. */ 105#define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 106 107/* Define this if most significant byte of a word is the lowest numbered. */ 108#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 109 110/* Define this if most significant word of a multiword number is the lowest. */ 111#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 112 113#define MAX_BITS_PER_WORD 32 114 115/* Width of a word, in units (bytes). */ 116#define UNITS_PER_WORD 4 117#define MIN_UNITS_PER_WORD 4 118 119/* Width of a floating point register. */ 120#define UNITS_PER_FPREG 4 121 122/* Size in bits of various types on the target machine. */ 123#define INT_TYPE_SIZE 32 124#define SHORT_TYPE_SIZE 16 125#define LONG_TYPE_SIZE 32 126#define LONG_LONG_TYPE_SIZE 64 127#define FLOAT_TYPE_SIZE 32 128#define DOUBLE_TYPE_SIZE 64 129#define LONG_DOUBLE_TYPE_SIZE 64 130 131/* Allocation boundary (in *bits*) for storing pointers in memory. */ 132#define POINTER_BOUNDARY 32 133 134/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 135#define PARM_BOUNDARY 32 136 137/* Allocation boundary (in *bits*) for the code of a function. */ 138#define FUNCTION_BOUNDARY 32 139 140/* Alignment of field after 'int : 0' in a structure. */ 141#define EMPTY_FIELD_BOUNDARY 32 142 143/* Every structure's size must be a multiple of this. */ 144#define STRUCTURE_SIZE_BOUNDARY 8 145 146/* There is no point aligning anything to a rounder boundary than this. */ 147#define BIGGEST_ALIGNMENT 128 148 149/* Set this nonzero if move instructions will actually fail to work 150 when given unaligned data. */ 151#define STRICT_ALIGNMENT 1 152 153/* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP 154 for QImode, because there is no 8-bit load from memory with sign 155 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit 156 loads both with and without sign extension. */ 157#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 158 do { \ 159 if (GET_MODE_CLASS (MODE) == MODE_INT \ 160 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 161 { \ 162 if ((MODE) == QImode) \ 163 (UNSIGNEDP) = 1; \ 164 (MODE) = SImode; \ 165 } \ 166 } while (0) 167 168/* Imitate the way many other C compilers handle alignment of 169 bitfields and the structures that contain them. */ 170#define PCC_BITFIELD_TYPE_MATTERS 1 171 172/* Align arrays, unions and records to at least a word boundary. 173 One use of this macro is to increase alignment of medium-size 174 data to make it all fit in fewer cache lines. Another is to 175 cause character arrays to be word-aligned so that 'strcpy' calls 176 that copy constants to character arrays can be done inline. */ 177#undef DATA_ALIGNMENT 178#define DATA_ALIGNMENT(TYPE, ALIGN) \ 179 (!optimize_size && (((ALIGN) < BITS_PER_WORD) \ 180 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 181 || TREE_CODE (TYPE) == UNION_TYPE \ 182 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 183 184/* Operations between registers always perform the operation 185 on the full register even if a narrower mode is specified. */ 186#define WORD_REGISTER_OPERATIONS 1 187 188/* Xtensa loads are zero-extended by default. */ 189#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 190 191/* Standard register usage. */ 192 193/* Number of actual hardware registers. 194 The hardware registers are assigned numbers for the compiler 195 from 0 to just below FIRST_PSEUDO_REGISTER. 196 All registers that the compiler knows about must be given numbers, 197 even those that are not normally considered general registers. 198 199 The fake frame pointer and argument pointer will never appear in 200 the generated code, since they will always be eliminated and replaced 201 by either the stack pointer or the hard frame pointer. 202 203 0 - 15 AR[0] - AR[15] 204 16 FRAME_POINTER (fake = initial sp) 205 17 ARG_POINTER (fake = initial sp + framesize) 206 18 BR[0] for floating-point CC 207 19 - 34 FR[0] - FR[15] 208 35 MAC16 accumulator */ 209 210#define FIRST_PSEUDO_REGISTER 36 211 212/* Return the stabs register number to use for REGNO. */ 213#define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) 214 215/* 1 for registers that have pervasive standard uses 216 and are not available for the register allocator. */ 217#define FIXED_REGISTERS \ 218{ \ 219 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 220 1, 1, 0, \ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 222 0, \ 223} 224 225/* 1 for registers not available across function calls. 226 These must include the FIXED_REGISTERS and also any 227 registers that can be used without being saved. 228 The latter must include the registers where values are returned 229 and the register where structure-value addresses are passed. 230 Aside from that, you can include as many other registers as you like. 231 232 The value encoding is the following: 233 1: register is used by all ABIs; 234 bit 1 is set: register is used by windowed ABI; 235 bit 2 is set: register is used by call0 ABI. 236 237 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 238 239#define CALL_USED_REGISTERS \ 240{ \ 241 1, 1, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ 242 1, 1, 1, \ 243 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 244 1, \ 245} 246 247/* For non-leaf procedures on Xtensa processors, the allocation order 248 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we 249 want to use the lowest numbered registers first to minimize 250 register window overflows. However, local-alloc is not smart 251 enough to consider conflicts with incoming arguments. If an 252 incoming argument in a2 is live throughout the function and 253 local-alloc decides to use a2, then the incoming argument must 254 either be spilled or copied to another register. To get around 255 this, we define ADJUST_REG_ALLOC_ORDER to redefine 256 reg_alloc_order for leaf functions such that lowest numbered 257 registers are used first with the exception that the incoming 258 argument registers are not used until after other register choices 259 have been exhausted. */ 260 261#define REG_ALLOC_ORDER \ 262{ 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ 263 18, \ 264 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ 265 0, 1, 16, 17, \ 266 35, \ 267} 268 269#define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 270 271/* For Xtensa, the only point of this is to prevent GCC from otherwise 272 giving preference to call-used registers. To minimize window 273 overflows for the AR registers, we want to give preference to the 274 lower-numbered AR registers. For other register files, which are 275 not windowed, we still prefer call-used registers, if there are any. */ 276extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; 277#define LEAF_REGISTERS xtensa_leaf_regs 278 279/* For Xtensa, no remapping is necessary, but this macro must be 280 defined if LEAF_REGISTERS is defined. */ 281#define LEAF_REG_REMAP(REGNO) (REGNO) 282 283/* This must be declared if LEAF_REGISTERS is set. */ 284extern int leaf_function; 285 286/* Internal macros to classify a register number. */ 287 288/* 16 address registers + fake registers */ 289#define GP_REG_FIRST 0 290#define GP_REG_LAST 17 291#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 292 293/* Coprocessor registers */ 294#define BR_REG_FIRST 18 295#define BR_REG_LAST 18 296#define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) 297 298/* 16 floating-point registers */ 299#define FP_REG_FIRST 19 300#define FP_REG_LAST 34 301#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 302 303/* MAC16 accumulator */ 304#define ACC_REG_FIRST 35 305#define ACC_REG_LAST 35 306#define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) 307 308#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) 309#define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) 310#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) 311#define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) 312 313/* Register to use for pushing function arguments. */ 314#define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) 315 316/* Base register for access to local variables of the function. */ 317#define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + \ 318 (TARGET_WINDOWED_ABI ? 7 : 15)) 319 320/* The register number of the frame pointer register, which is used to 321 access automatic variables in the stack frame. For Xtensa, this 322 register never appears in the output. It is always eliminated to 323 either the stack pointer or the hard frame pointer. */ 324#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) 325 326/* Base register for access to arguments of the function. */ 327#define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) 328 329/* Hard frame pointer is neither frame nor arg pointer. 330 The definitions are here because actual hard frame pointer register 331 definition is not a preprocessor constant. */ 332#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 333#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 334 335/* For now we don't try to use the full set of boolean registers. Without 336 software pipelining of FP operations, there's not much to gain and it's 337 a real pain to get them reloaded. */ 338#define FPCC_REGNUM (BR_REG_FIRST + 0) 339 340/* It is as good or better to call a constant function address than to 341 call an address kept in a register. */ 342#define NO_FUNCTION_CSE 1 343 344/* Xtensa processors have "register windows". GCC does not currently 345 take advantage of the possibility for variable-sized windows; instead, 346 we use a fixed window size of 8. */ 347 348#define INCOMING_REGNO(OUT) \ 349 (TARGET_WINDOWED_ABI ? \ 350 ((GP_REG_P (OUT) && \ 351 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ 352 (OUT) - WINDOW_SIZE : (OUT)) : (OUT)) 353 354#define OUTGOING_REGNO(IN) \ 355 (TARGET_WINDOWED_ABI ? \ 356 ((GP_REG_P (IN) && \ 357 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ 358 (IN) + WINDOW_SIZE : (IN)) : (IN)) 359 360 361/* Define the classes of registers for register constraints in the 362 machine description. */ 363enum reg_class 364{ 365 NO_REGS, /* no registers in set */ 366 BR_REGS, /* coprocessor boolean registers */ 367 FP_REGS, /* floating point registers */ 368 ACC_REG, /* MAC16 accumulator */ 369 SP_REG, /* sp register (aka a1) */ 370 RL_REGS, /* preferred reload regs (not sp or fp) */ 371 GR_REGS, /* integer registers except sp */ 372 AR_REGS, /* all integer registers */ 373 ALL_REGS, /* all registers */ 374 LIM_REG_CLASSES /* max value + 1 */ 375}; 376 377#define N_REG_CLASSES (int) LIM_REG_CLASSES 378 379#define GENERAL_REGS AR_REGS 380 381/* An initializer containing the names of the register classes as C 382 string constants. These names are used in writing some of the 383 debugging dumps. */ 384#define REG_CLASS_NAMES \ 385{ \ 386 "NO_REGS", \ 387 "BR_REGS", \ 388 "FP_REGS", \ 389 "ACC_REG", \ 390 "SP_REG", \ 391 "RL_REGS", \ 392 "GR_REGS", \ 393 "AR_REGS", \ 394 "ALL_REGS" \ 395} 396 397/* Contents of the register classes. The Nth integer specifies the 398 contents of class N. The way the integer MASK is interpreted is 399 that register R is in the class if 'MASK & (1 << R)' is 1. */ 400#define REG_CLASS_CONTENTS \ 401{ \ 402 { 0x00000000, 0x00000000 }, /* no registers */ \ 403 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ 404 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ 405 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ 406 { 0x00000002, 0x00000000 }, /* stack pointer register */ \ 407 { 0x0000fffd, 0x00000000 }, /* preferred reload registers */ \ 408 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ 409 { 0x0003ffff, 0x00000000 }, /* integer registers */ \ 410 { 0xffffffff, 0x0000000f } /* all registers */ \ 411} 412 413/* A C expression whose value is a register class containing hard 414 register REGNO. In general there is more that one such class; 415 choose a class which is "minimal", meaning that no smaller class 416 also contains the register. */ 417#define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class (REGNO) 418 419/* Use the Xtensa AR register file for base registers. 420 No index registers. */ 421#define BASE_REG_CLASS AR_REGS 422#define INDEX_REG_CLASS NO_REGS 423 424/* The small_register_classes_for_mode_p hook must always return true for 425 Xtrnase, because all of the 16 AR registers may be explicitly used in 426 the RTL, as either incoming or outgoing arguments. */ 427#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 428 429/* Stack layout; function entry, exit and calling. */ 430 431#define STACK_GROWS_DOWNWARD 1 432 433#define FRAME_GROWS_DOWNWARD (flag_stack_protect \ 434 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 435 436/* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so 437 they are eliminated to either the stack pointer or hard frame pointer. */ 438#define ELIMINABLE_REGS \ 439{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 440 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 441 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 442 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 443 444/* Specify the initial difference between the specified pair of registers. */ 445#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 446 (OFFSET) = xtensa_initial_elimination_offset ((FROM), (TO)) 447 448/* If defined, the maximum amount of space required for outgoing 449 arguments will be computed and placed into the variable 450 'crtl->outgoing_args_size'. No space will be pushed 451 onto the stack for each call; instead, the function prologue 452 should increase the stack frame size by this amount. */ 453#define ACCUMULATE_OUTGOING_ARGS 1 454 455/* Offset from the argument pointer register to the first argument's 456 address. On some machines it may depend on the data type of the 457 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the 458 location above the first argument's address. */ 459#define FIRST_PARM_OFFSET(FNDECL) 0 460 461/* Align stack frames on 128 bits for Xtensa. This is necessary for 462 128-bit datatypes defined in TIE (e.g., for Vectra). */ 463#define STACK_BOUNDARY 128 464 465/* Use a fixed register window size of 8. */ 466#define WINDOW_SIZE (TARGET_WINDOWED_ABI ? 8 : 0) 467 468/* Symbolic macros for the registers used to return integer, floating 469 point, and values of coprocessor and user-defined modes. */ 470#define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) 471#define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) 472 473/* Symbolic macros for the first/last argument registers. */ 474#define GP_ARG_FIRST (GP_REG_FIRST + 2) 475#define GP_ARG_LAST (GP_REG_FIRST + 7) 476#define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) 477#define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) 478 479#define MAX_ARGS_IN_REGISTERS 6 480 481/* Don't worry about compatibility with PCC. */ 482#define DEFAULT_PCC_STRUCT_RETURN 0 483 484/* A C expression that is nonzero if REGNO is the number of a hard 485 register in which function arguments are sometimes passed. This 486 does *not* include implicit arguments such as the static chain and 487 the structure-value address. On many machines, no registers can be 488 used for this purpose since all function arguments are pushed on 489 the stack. */ 490#define FUNCTION_ARG_REGNO_P(N) \ 491 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) 492 493/* Record the number of argument words seen so far, along with a flag to 494 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG 495 is used for both incoming and outgoing args, so a separate flag is 496 needed. */ 497typedef struct xtensa_args 498{ 499 int arg_words; 500 int incoming; 501} CUMULATIVE_ARGS; 502 503#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 504 init_cumulative_args (&CUM, 0) 505 506#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 507 init_cumulative_args (&CUM, 1) 508 509/* Profiling Xtensa code is typically done with the built-in profiling 510 feature of Tensilica's instruction set simulator, which does not 511 require any compiler support. Profiling code on a real (i.e., 512 non-simulated) Xtensa processor is currently only supported by 513 GNU/Linux with glibc. The glibc version of _mcount doesn't require 514 counter variables. The _mcount function needs the current PC and 515 the current return address to identify an arc in the call graph. 516 Pass the current return address as the first argument; the current 517 PC is available as a0 in _mcount's register window. Both of these 518 values contain window size information in the two most significant 519 bits; we assume that _mcount will mask off those bits. The call to 520 _mcount uses a window size of 8 to make sure that it doesn't clobber 521 any incoming argument values. */ 522 523#define NO_PROFILE_COUNTERS 1 524 525#define FUNCTION_PROFILER(FILE, LABELNO) \ 526 do { \ 527 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ 528 if (flag_pic) \ 529 { \ 530 fprintf (FILE, "\tmovi\ta%d, _mcount@PLT\n", WINDOW_SIZE); \ 531 fprintf (FILE, "\tcallx%d\ta%d\n", WINDOW_SIZE, WINDOW_SIZE); \ 532 } \ 533 else \ 534 fprintf (FILE, "\tcall%d\t_mcount\n", WINDOW_SIZE); \ 535 } while (0) 536 537/* Stack pointer value doesn't matter at exit. */ 538#define EXIT_IGNORE_STACK 1 539 540/* Size in bytes of the trampoline, as an integer. Make sure this is 541 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */ 542#define TRAMPOLINE_SIZE (TARGET_WINDOWED_ABI ? \ 543 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \ 544 60 : 52) : \ 545 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \ 546 32 : 24)) 547 548/* Alignment required for trampolines, in bits. */ 549#define TRAMPOLINE_ALIGNMENT 32 550 551/* If defined, a C expression that produces the machine-specific code 552 to setup the stack so that arbitrary frames can be accessed. 553 554 On Xtensa, a stack back-trace must always begin from the stack pointer, 555 so that the register overflow save area can be located. However, the 556 stack-walking code in GCC always begins from the hard_frame_pointer 557 register, not the stack pointer. The frame pointer is usually equal 558 to the stack pointer, but the __builtin_return_address and 559 __builtin_frame_address functions will not work if count > 0 and 560 they are called from a routine that uses alloca. These functions 561 are not guaranteed to work at all if count > 0 so maybe that is OK. 562 563 A nicer solution would be to allow the architecture-specific files to 564 specify whether to start from the stack pointer or frame pointer. That 565 would also allow us to skip the machine->accesses_prev_frame stuff that 566 we currently need to ensure that there is a frame pointer when these 567 builtin functions are used. */ 568 569#define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses 570 571/* A C expression whose value is RTL representing the address in a 572 stack frame where the pointer to the caller's frame is stored. 573 Assume that FRAMEADDR is an RTL expression for the address of the 574 stack frame itself. 575 576 For Xtensa, there is no easy way to get the frame pointer if it is 577 not equivalent to the stack pointer. Moreover, the result of this 578 macro is used for continuing to walk back up the stack, so it must 579 return the stack pointer address. Thus, there is some inconsistency 580 here in that __builtin_frame_address will return the frame pointer 581 when count == 0 and the stack pointer when count > 0. */ 582 583#define DYNAMIC_CHAIN_ADDRESS(frame) \ 584 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD)) 585 586/* Define this if the return address of a particular stack frame is 587 accessed from the frame pointer of the previous stack frame. */ 588#define RETURN_ADDR_IN_PREVIOUS_FRAME TARGET_WINDOWED_ABI 589 590/* A C expression whose value is RTL representing the value of the 591 return address for the frame COUNT steps up from the current 592 frame, after the prologue. */ 593#define RETURN_ADDR_RTX xtensa_return_addr 594 595/* Addressing modes, and classification of registers for them. */ 596 597/* C expressions which are nonzero if register number NUM is suitable 598 for use as a base or index register in operand addresses. */ 599 600#define REGNO_OK_FOR_INDEX_P(NUM) 0 601#define REGNO_OK_FOR_BASE_P(NUM) \ 602 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) 603 604/* C expressions that are nonzero if X (assumed to be a `reg' RTX) is 605 valid for use as a base or index register. */ 606 607#ifdef REG_OK_STRICT 608#define REG_OK_STRICT_FLAG 1 609#else 610#define REG_OK_STRICT_FLAG 0 611#endif 612 613#define BASE_REG_P(X, STRICT) \ 614 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 615 || REGNO_OK_FOR_BASE_P (REGNO (X))) 616 617#define REG_OK_FOR_INDEX_P(X) 0 618#define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG) 619 620/* Maximum number of registers that can appear in a valid memory address. */ 621#define MAX_REGS_PER_ADDRESS 1 622 623/* A C expression that is 1 if the RTX X is a constant which is a 624 valid address. This is defined to be the same as 'CONSTANT_P (X)', 625 but rejecting CONST_DOUBLE. */ 626#define CONSTANT_ADDRESS_P(X) \ 627 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 628 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 629 || (GET_CODE (X) == CONST))) 630 631/* A C expression that is nonzero if X is a legitimate immediate 632 operand on the target machine when generating position independent 633 code. */ 634#define LEGITIMATE_PIC_OPERAND_P(X) \ 635 ((GET_CODE (X) != SYMBOL_REF \ 636 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ 637 && GET_CODE (X) != LABEL_REF \ 638 && GET_CODE (X) != CONST) 639 640/* Specify the machine mode that this machine uses 641 for the index in the tablejump instruction. */ 642#define CASE_VECTOR_MODE (SImode) 643 644/* Define this as 1 if 'char' should by default be signed; else as 0. */ 645#define DEFAULT_SIGNED_CHAR 0 646 647/* Max number of bytes we can move from memory to memory 648 in one reasonably fast instruction. */ 649#define MOVE_MAX 4 650#define MAX_MOVE_MAX 4 651 652/* Prefer word-sized loads. */ 653#define SLOW_BYTE_ACCESS 1 654 655/* Shift instructions ignore all but the low-order few bits. */ 656#define SHIFT_COUNT_TRUNCATED 1 657 658#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 659#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 660 661/* Specify the machine mode that pointers have. 662 After generation of rtl, the compiler makes no further distinction 663 between pointers and any other objects of this machine mode. */ 664#define Pmode SImode 665 666/* A function address in a call instruction is a word address (for 667 indexing purposes) so give the MEM rtx a words's mode. */ 668#define FUNCTION_MODE SImode 669 670#define BRANCH_COST(speed_p, predictable_p) 3 671 672/* How to refer to registers in assembler output. 673 This sequence is indexed by compiler's hard-register-number (see above). */ 674#define REGISTER_NAMES \ 675{ \ 676 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ 677 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ 678 "fp", "argp", "b0", \ 679 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 680 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 681 "acc" \ 682} 683 684/* If defined, a C initializer for an array of structures containing a 685 name and a register number. This macro defines additional names 686 for hard registers, thus allowing the 'asm' option in declarations 687 to refer to registers using alternate names. */ 688#define ADDITIONAL_REGISTER_NAMES \ 689{ \ 690 { "a1", 1 + GP_REG_FIRST } \ 691} 692 693#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 694#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 695 696/* Globalizing directive for a label. */ 697#define GLOBAL_ASM_OP "\t.global\t" 698 699/* Declare an uninitialized external linkage data object. */ 700#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 701 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 702 703/* This is how to output an element of a case-vector that is absolute. */ 704#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 705 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ 706 LOCAL_LABEL_PREFIX, VALUE) 707 708/* This is how to output an element of a case-vector that is relative. 709 This is used for pc-relative code. */ 710#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 711 do { \ 712 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ 713 LOCAL_LABEL_PREFIX, (VALUE), \ 714 LOCAL_LABEL_PREFIX, (REL)); \ 715 } while (0) 716 717/* This is how to output an assembler line that says to advance the 718 location counter to a multiple of 2**LOG bytes. */ 719#define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 720 do { \ 721 if ((LOG) != 0) \ 722 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ 723 } while (0) 724 725/* Indicate that jump tables go in the text section. This is 726 necessary when compiling PIC code. */ 727#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 728 729 730/* Define the strings to put out for each section in the object file. */ 731#define TEXT_SECTION_ASM_OP "\t.text" 732#define DATA_SECTION_ASM_OP "\t.data" 733#define BSS_SECTION_ASM_OP "\t.section\t.bss" 734 735 736/* Define output to appear before the constant pool. */ 737#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ 738 do { \ 739 if ((SIZE) > 0 || !TARGET_WINDOWED_ABI) \ 740 { \ 741 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ 742 switch_to_section (function_section (FUNDECL)); \ 743 fprintf (FILE, "\t.literal_position\n"); \ 744 } \ 745 } while (0) 746 747 748/* A C statement (with or without semicolon) to output a constant in 749 the constant pool, if it needs special treatment. */ 750#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ 751 do { \ 752 xtensa_output_literal (FILE, X, MODE, LABELNO); \ 753 goto JUMPTO; \ 754 } while (0) 755 756/* How to start an assembler comment. */ 757#define ASM_COMMENT_START "#" 758 759/* Exception handling. Xtensa uses much of the standard DWARF2 unwinding 760 machinery, but the variable size register window save areas are too 761 complicated to efficiently describe with CFI entries. The CFA must 762 still be specified in DWARF so that DW_AT_frame_base is set correctly 763 for debugging. */ 764#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) 765#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) 766#define DWARF_ALT_FRAME_RETURN_COLUMN 16 767#define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN \ 768 + (TARGET_WINDOWED_ABI ? 0 : 1)) 769#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM) 770#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 771 (flag_pic \ 772 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \ 773 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 774 : DW_EH_PE_absptr) 775 776#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 10) 777 778/* Emit a PC-relative relocation. */ 779#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 780 do { \ 781 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 782 assemble_name (FILE, LABEL); \ 783 fputs ("@pcrel", FILE); \ 784 } while (0) 785 786/* Xtensa constant pool breaks the devices in crtstuff.c to control 787 section in where code resides. We have to write it as asm code. Use 788 a MOVI and let the assembler relax it -- for the .init and .fini 789 sections, the assembler knows to put the literal in the right 790 place. */ 791#if defined(__XTENSA_WINDOWED_ABI__) 792#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 793 asm (SECTION_OP "\n\ 794 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ 795 callx8\ta8\n" \ 796 TEXT_SECTION_ASM_OP); 797#elif defined(__XTENSA_CALL0_ABI__) 798#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 799 asm (SECTION_OP "\n\ 800 movi\ta0, " USER_LABEL_PREFIX #FUNC "\n\ 801 callx0\ta0\n" \ 802 TEXT_SECTION_ASM_OP); 803#endif 804