1;; Scheduling description for z900 (cpu 2064). 2;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com). 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it under 9;; the terms of the GNU General Public License as published by the Free 10;; Software Foundation; either version 3, or (at your option) any later 11;; version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 15;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16;; for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22;; 23;; References: 24;; The microarchitecture of the IBM eServer z900 processor. 25;; E.M. Schwarz et al. 26;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. 27;; 28;; z900 (cpu 2064) pipeline 29;; 30;; dec 31;; --> | <--- 32;; LA bypass | agen | 33;; | | | 34;; --- c1 | Load bypass 35;; | | 36;; c2---- 37;; | 38;; e1 39;; | 40;; wr 41 42(define_automaton "z_ipu") 43(define_cpu_unit "z_e1" "z_ipu") 44(define_cpu_unit "z_wr" "z_ipu") 45 46 47(define_insn_reservation "z_la" 1 48 (and (eq_attr "cpu" "z900") 49 (eq_attr "type" "la")) 50 "z_e1,z_wr") 51 52(define_insn_reservation "z_larl" 1 53 (and (eq_attr "cpu" "z900") 54 (eq_attr "type" "larl")) 55 "z_e1,z_wr") 56 57(define_insn_reservation "z_load" 1 58 (and (eq_attr "cpu" "z900") 59 (eq_attr "type" "load")) 60 "z_e1,z_wr") 61 62(define_insn_reservation "z_store" 1 63 (and (eq_attr "cpu" "z900") 64 (eq_attr "type" "store")) 65 "z_e1,z_wr") 66 67(define_insn_reservation "z_sem" 2 68 (and (eq_attr "cpu" "z900") 69 (eq_attr "type" "sem")) 70 "z_e1*2,z_wr") 71 72(define_insn_reservation "z_call" 5 73 (and (eq_attr "cpu" "z900") 74 (eq_attr "type" "jsr")) 75 "z_e1*5,z_wr") 76 77(define_insn_reservation "z_mul" 5 78 (and (eq_attr "cpu" "z900") 79 (eq_attr "type" "imulsi,imulhi")) 80 "z_e1*5,z_wr") 81 82(define_insn_reservation "z_inf" 10 83 (and (eq_attr "cpu" "z900") 84 (eq_attr "type" "idiv,imuldi")) 85 "z_e1*10,z_wr") 86 87;; For everything else we check the atype flag. 88 89(define_insn_reservation "z_int" 1 90 (and (eq_attr "cpu" "z900") 91 (and (not (eq_attr "type" "la,larl,load,store,jsr")) 92 (eq_attr "atype" "reg"))) 93 "z_e1,z_wr") 94 95(define_insn_reservation "z_agen" 1 96 (and (eq_attr "cpu" "z900") 97 (and (not (eq_attr "type" "la,larl,load,store,jsr")) 98 (eq_attr "atype" "agen"))) 99 "z_e1,z_wr") 100 101;; 102;; s390_agen_dep_p returns 1, if a register is set in the 103;; first insn and used in the dependent insn to form a address. 104;; 105 106;; 107;; If an instruction uses a register to address memory, it needs 108;; to be set 5 cycles in advance. 109;; 110 111(define_bypass 5 "z_int,z_agen" 112 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 113 114;; 115;; A load type instruction uses a bypass to feed the result back 116;; to the address generation pipeline stage. 117;; 118 119(define_bypass 3 "z_load" 120 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 121 122;; 123;; A load address type instruction uses a bypass to feed the 124;; result back to the address generation pipeline stage. 125;; 126 127(define_bypass 2 "z_larl,z_la" 128 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 129 130 131 132 133 134