1;; Pipeline description for the AppliedMicro Titan core.
2;;   Copyright (C) 2010-2020 Free Software Foundation, Inc.
3;;   Contributed by Theobroma Systems Design und Consulting GmbH
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; AppliedMicro Titan core complex
22
23(define_automaton "titan_core,titan_fpu,titan_fxu,titan_bpu,titan_lsu")
24(define_cpu_unit "titan_issue_0,titan_issue_1" "titan_core")
25
26;; Some useful abbreviations.
27(define_reservation "titan_issue" "titan_issue_0|titan_issue_1")
28
29;; === FXU scheduling ===
30
31(define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
32
33;; The 1-cycle adder executes add, addi, subf, neg, compare and trap
34;; instructions. It provides its own, dedicated result-bus, so we
35;; don't need the titan_fxu_wb reservation to complete.
36(define_insn_reservation "titan_fxu_adder" 1
37  (and (ior (eq_attr "type" "cmp,trap")
38	    (and (eq_attr "type" "add,logical")
39		 (eq_attr "dot" "yes")))
40       (eq_attr "cpu" "titan"))
41  "titan_issue,titan_fxu_sh")
42
43(define_insn_reservation "titan_imul" 5
44  (and (eq_attr "type" "mul")
45       (eq_attr "cpu" "titan"))       
46  "titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")  
47
48(define_insn_reservation "titan_mulhw" 4
49  (and (eq_attr "type" "halfmul")
50       (eq_attr "cpu" "titan"))
51  "titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")
52
53(define_bypass 2 "titan_mulhw" "titan_mulhw")
54
55(define_insn_reservation "titan_fxu_shift_and_rotate" 2
56  (and (eq_attr "type" "insert,shift,cntlz")
57       (eq_attr "cpu" "titan"))
58  "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")
59
60;; We model the divider for the worst-case (i.e. a full 32-bit
61;; divide).  To model the bypass for byte-wise completion, a
62;; define_bypass with a guard-function could be used... however, this
63;; would be an optimization of doubtful value, as a large number of
64;; divides will operate on 32-bit variables.
65
66;; To avoid an unmanagably large automata (generating the automata
67;; would require well over 2GB in memory), we don't model the shared
68;; result bus on this one. The divider-pipeline is thus modeled
69;; through its latency and initial disptach bottlenecks (i.e. issue
70;; slots and fxu scheduler availability)
71(define_insn_reservation "titan_fxu_div" 34
72  (and (eq_attr "type" "div")
73       (eq_attr "cpu" "titan"))
74  "titan_issue,titan_fxu_sh")
75
76(define_insn_reservation "titan_fxu_alu" 1
77  (and (ior (eq_attr "type" "integer,exts")
78	    (and (eq_attr "type" "add,logical")
79		 (eq_attr "dot" "no")))
80       (eq_attr "cpu" "titan"))
81  "titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")
82
83;; === BPU scheduling ===
84
85(define_cpu_unit "titan_bpu_sh" "titan_bpu")
86
87(define_insn_reservation "titan_bpu" 2
88  (and (eq_attr "type" "branch,jmpreg,cr_logical")
89       (eq_attr "cpu" "titan"))
90  "titan_issue,titan_bpu_sh")
91
92;; === LSU scheduling ===
93
94(define_cpu_unit "titan_lsu_sh" "titan_lsu")
95
96;; Loads.
97(define_insn_reservation "titan_lsu_load" 3
98  (and (eq_attr "type" "load,load_l,sync")
99       (eq_attr "cpu" "titan"))
100  "titan_issue,titan_lsu_sh")
101
102(define_insn_reservation "titan_lsu_fpload" 12
103  (and (eq_attr "type" "fpload")
104       (eq_attr "cpu" "titan"))
105  "titan_issue,titan_lsu_sh")
106
107;; Note that the isync is not clearly placed within any execution
108;; unit. We've made the assumption that it will be running out of the
109;; LSU, as msync is also executed within the LSU.
110(define_insn_reservation "titan_lsu_sync" 20
111  (and (eq_attr "type" "sync")
112       (eq_attr "cpu" "titan"))
113  "titan_issue,titan_lsu_sh*20")
114
115;; Stores.
116(define_insn_reservation "titan_lsu_store" 12
117  (and (eq_attr "type" "store,store_c")
118       (eq_attr "cpu" "titan"))
119  "titan_issue,titan_lsu_sh")
120
121(define_insn_reservation "titan_lsu_fpstore" 12
122  (and (eq_attr "type" "fpstore")
123       (eq_attr "cpu" "titan"))
124  "titan_issue,titan_lsu_sh")
125
126;; === FPU scheduling ===
127
128;; In order to keep the automaton for the Titan FPU efficient and
129;; maintainable, we've kept in as concise as possible and created a
130;; mapping for the main "choke points" only instead of modelling the
131;; overall flow of instructions through the FP-pipeline(s).
132
133;; The key elements modelled are:
134;;  * each FP-instruction takes up one of the two issue slots 
135;;  * the FPU runs at half the core frequency
136;;  * divides are not pipelined (but execute in a separate unit)
137;;  * the FPU has a shared result bus for all its units
138
139(define_cpu_unit "titan_fp0,titan_fpdiv,titan_fpwb" "titan_fpu")
140
141(define_insn_reservation "titan_fp_div_double" 72
142  (and (eq_attr "type" "ddiv")
143       (eq_attr "cpu" "titan"))
144  "titan_issue,titan_fpdiv*72,titan_fpwb")
145
146(define_insn_reservation "titan_fp_div_single" 46
147  (and (eq_attr "type" "sdiv")
148       (eq_attr "cpu" "titan"))
149  "titan_issue,titan_fpdiv*46,titan_fpwb")
150
151;; Make sure the "titan_fp" rule stays last, as it's a catch all for
152;; double-precision and unclassified (e.g. fsel) FP-instructions
153(define_insn_reservation "titan_fp" 10
154  (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul")
155       (eq_attr "cpu" "titan"))
156  "titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
157
158;; Please note, that the non-pipelined FP-instructions "mcrfs",
159;; "mtfsb0[.]", "mtfsb1[.]", "mtfsf[.]", "mtfsfi[.]" are not
160;; accessible from regular language constructs (i.e. they are not used
161;; by the code generator, except for special purpose sequences defined
162;; in rs6000.md), no special provisions are made for these.
163
164