rs6000.opt revision 1.7
1; Options for the rs6000 port of the compiler 2; 3; Copyright (C) 2005-2016 Free Software Foundation, Inc. 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>. 5; 6; This file is part of GCC. 7; 8; GCC is free software; you can redistribute it and/or modify it under 9; the terms of the GNU General Public License as published by the Free 10; Software Foundation; either version 3, or (at your option) any later 11; version. 12; 13; GCC is distributed in the hope that it will be useful, but WITHOUT 14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16; License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with GCC; see the file COPYING3. If not see 20; <http://www.gnu.org/licenses/>. 21 22HeaderInclude 23config/rs6000/rs6000-opts.h 24 25;; ISA flag bits (on/off) 26Variable 27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT 28 29TargetSave 30HOST_WIDE_INT x_rs6000_isa_flags 31 32;; Miscellaneous flag bits that were set explicitly by the user 33Variable 34HOST_WIDE_INT rs6000_isa_flags_explicit 35 36TargetSave 37HOST_WIDE_INT x_rs6000_isa_flags_explicit 38 39;; Current processor 40TargetVariable 41enum processor_type rs6000_cpu = PROCESSOR_PPC603 42 43;; Always emit branch hint bits. 44TargetVariable 45unsigned char rs6000_always_hint 46 47;; Schedule instructions for group formation. 48TargetVariable 49unsigned char rs6000_sched_groups 50 51;; Align branch targets. 52TargetVariable 53unsigned char rs6000_align_branch_targets 54 55;; Support for -msched-costly-dep option. 56TargetVariable 57enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly 58 59;; Support for -minsert-sched-nops option. 60TargetVariable 61enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none 62 63;; Non-zero to allow overriding loop alignment. 64TargetVariable 65unsigned char can_override_loop_align 66 67;; Which small data model to use (for System V targets only) 68TargetVariable 69enum rs6000_sdata_type rs6000_sdata = SDATA_DATA 70 71;; Bit size of immediate TLS offsets and string from which it is decoded. 72TargetVariable 73int rs6000_tls_size = 32 74 75;; ABI enumeration available for subtarget to use. 76TargetVariable 77enum rs6000_abi rs6000_current_abi = ABI_NONE 78 79;; Type of traceback to use. 80TargetVariable 81enum rs6000_traceback_type rs6000_traceback = traceback_default 82 83;; Control alignment for fields within structures. 84TargetVariable 85unsigned char rs6000_alignment_flags 86 87;; Code model for 64-bit linux. 88TargetVariable 89enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL 90 91;; What type of reciprocal estimation instructions to generate 92TargetVariable 93unsigned int rs6000_recip_control 94 95;; Mask of what builtin functions are allowed 96TargetVariable 97HOST_WIDE_INT rs6000_builtin_mask 98 99;; Debug flags 100TargetVariable 101unsigned int rs6000_debug 102 103;; This option existed in the past, but now is always on. 104mpowerpc 105Target RejectNegative Undocumented Ignore 106 107mpowerpc64 108Target Report Mask(POWERPC64) Var(rs6000_isa_flags) 109Use PowerPC-64 instruction set. 110 111mpowerpc-gpopt 112Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) 113Use PowerPC General Purpose group optional instructions. 114 115mpowerpc-gfxopt 116Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) 117Use PowerPC Graphics group optional instructions. 118 119mmfcrf 120Target Report Mask(MFCRF) Var(rs6000_isa_flags) 121Use PowerPC V2.01 single field mfcr instruction. 122 123mpopcntb 124Target Report Mask(POPCNTB) Var(rs6000_isa_flags) 125Use PowerPC V2.02 popcntb instruction. 126 127mfprnd 128Target Report Mask(FPRND) Var(rs6000_isa_flags) 129Use PowerPC V2.02 floating point rounding instructions. 130 131mcmpb 132Target Report Mask(CMPB) Var(rs6000_isa_flags) 133Use PowerPC V2.05 compare bytes instruction. 134 135mmfpgpr 136Target Report Mask(MFPGPR) Var(rs6000_isa_flags) 137Use extended PowerPC V2.05 move floating point to/from GPR instructions. 138 139maltivec 140Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) 141Use AltiVec instructions. 142 143maltivec=le 144Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save 145Generate AltiVec instructions using little-endian element order. 146 147maltivec=be 148Target Report RejectNegative Var(rs6000_altivec_element_order, 2) 149Generate AltiVec instructions using big-endian element order. 150 151mhard-dfp 152Target Report Mask(DFP) Var(rs6000_isa_flags) 153Use decimal floating point instructions. 154 155mmulhw 156Target Report Mask(MULHW) Var(rs6000_isa_flags) 157Use 4xx half-word multiply instructions. 158 159mdlmzb 160Target Report Mask(DLMZB) Var(rs6000_isa_flags) 161Use 4xx string-search dlmzb instruction. 162 163mmultiple 164Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) 165Generate load/store multiple instructions. 166 167mstring 168Target Report Mask(STRING) Var(rs6000_isa_flags) 169Generate string instructions for block moves. 170 171msoft-float 172Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) 173Do not use hardware floating point. 174 175mhard-float 176Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) 177Use hardware floating point. 178 179mpopcntd 180Target Report Mask(POPCNTD) Var(rs6000_isa_flags) 181Use PowerPC V2.06 popcntd instruction. 182 183mfriz 184Target Report Var(TARGET_FRIZ) Init(-1) Save 185Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. 186 187mveclibabi= 188Target RejectNegative Joined Var(rs6000_veclibabi_name) 189Vector library ABI to use. 190 191mvsx 192Target Report Mask(VSX) Var(rs6000_isa_flags) 193Use vector/scalar (VSX) instructions. 194 195mvsx-scalar-float 196Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1) 197; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default) 198 199mvsx-scalar-double 200Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1) 201; If -mvsx, use VSX arithmetic instructions for DFmode (on by default) 202 203mvsx-scalar-memory 204Target Undocumented Report Alias(mupper-regs-df) 205 206mvsx-align-128 207Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save 208; If -mvsx, set alignment to 128 bits instead of 32/64 209 210mallow-movmisalign 211Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save 212; Allow/disallow the movmisalign in DF/DI vectors 213 214mefficient-unaligned-vector 215Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) 216; Consider unaligned VSX accesses to be efficient/inefficient 217 218mallow-df-permute 219Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save 220; Allow/disallow permutation of DF/DI vectors 221 222msched-groups 223Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save 224; Explicitly set/unset whether rs6000_sched_groups is set 225 226malways-hint 227Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save 228; Explicitly set/unset whether rs6000_always_hint is set 229 230malign-branch-targets 231Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save 232; Explicitly set/unset whether rs6000_align_branch_targets is set 233 234mvectorize-builtins 235Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save 236; Explicitly control whether we vectorize the builtins or not. 237 238mno-update 239Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) 240Do not generate load/store with update instructions. 241 242mupdate 243Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) 244Generate load/store with update instructions. 245 246msingle-pic-base 247Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) 248Do not load the PIC register in function prologues. 249 250mavoid-indexed-addresses 251Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save 252Avoid generation of indexed load/store instructions when possible. 253 254mtls-markers 255Target Report Var(tls_markers) Init(1) Save 256Mark __tls_get_addr calls with argument info. 257 258msched-epilog 259Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save 260 261msched-prolog 262Target Report Var(TARGET_SCHED_PROLOG) Save 263Schedule the start and end of the procedure. 264 265maix-struct-return 266Target Report RejectNegative Var(aix_struct_return) Save 267Return all structures in memory (AIX default). 268 269msvr4-struct-return 270Target Report RejectNegative Var(aix_struct_return,0) Save 271Return small structures in registers (SVR4 default). 272 273mxl-compat 274Target Report Var(TARGET_XL_COMPAT) Save 275Conform more closely to IBM XLC semantics. 276 277mrecip 278Target Report 279Generate software reciprocal divide and square root for better throughput. 280 281mrecip= 282Target Report RejectNegative Joined Var(rs6000_recip_name) 283Generate software reciprocal divide and square root for better throughput. 284 285mrecip-precision 286Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) 287Assume that the reciprocal estimate instructions provide more accuracy. 288 289mno-fp-in-toc 290Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save 291Do not place floating point constants in TOC. 292 293mfp-in-toc 294Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save 295Place floating point constants in TOC. 296 297mno-sum-in-toc 298Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save 299Do not place symbol+offset constants in TOC. 300 301msum-in-toc 302Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save 303Place symbol+offset constants in TOC. 304 305; Output only one TOC entry per module. Normally linking fails if 306; there are more than 16K unique variables/constants in an executable. With 307; this option, linking fails only if there are more than 16K modules, or 308; if there are more than 16K unique variables/constant in a single module. 309; 310; This is at the cost of having 2 extra loads and one extra store per 311; function, and one less allocable register. 312mminimal-toc 313Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) 314Use only one TOC entry per procedure. 315 316mfull-toc 317Target Report 318Put everything in the regular TOC. 319 320mvrsave 321Target Report Var(TARGET_ALTIVEC_VRSAVE) Save 322Generate VRSAVE instructions when generating AltiVec code. 323 324mvrsave=no 325Target RejectNegative Alias(mvrsave) NegativeAlias 326Deprecated option. Use -mno-vrsave instead. 327 328mvrsave=yes 329Target RejectNegative Alias(mvrsave) 330Deprecated option. Use -mvrsave instead. 331 332mblock-move-inline-limit= 333Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save 334Specify how many bytes should be moved inline before calling out to memcpy/memmove. 335 336misel 337Target Report Mask(ISEL) Var(rs6000_isa_flags) 338Generate isel instructions. 339 340misel=no 341Target RejectNegative Alias(misel) NegativeAlias 342Deprecated option. Use -mno-isel instead. 343 344misel=yes 345Target RejectNegative Alias(misel) 346Deprecated option. Use -misel instead. 347 348mspe 349Target Var(rs6000_spe) Save 350Generate SPE SIMD instructions on E500. 351 352mpaired 353Target Var(rs6000_paired_float) Save 354Generate PPC750CL paired-single instructions. 355 356mspe=no 357Target RejectNegative Alias(mspe) NegativeAlias 358Deprecated option. Use -mno-spe instead. 359 360mspe=yes 361Target RejectNegative Alias(mspe) 362Deprecated option. Use -mspe instead. 363 364mdebug= 365Target RejectNegative Joined 366-mdebug= Enable debug output. 367 368mabi=altivec 369Target RejectNegative Var(rs6000_altivec_abi) Save 370Use the AltiVec ABI extensions. 371 372mabi=no-altivec 373Target RejectNegative Var(rs6000_altivec_abi, 0) 374Do not use the AltiVec ABI extensions. 375 376mabi=spe 377Target RejectNegative Var(rs6000_spe_abi) Save 378Use the SPE ABI extensions. 379 380mabi=no-spe 381Target RejectNegative Var(rs6000_spe_abi, 0) 382Do not use the SPE ABI extensions. 383 384mabi=elfv1 385Target RejectNegative Var(rs6000_elf_abi, 1) Save 386Use the ELFv1 ABI. 387 388mabi=elfv2 389Target RejectNegative Var(rs6000_elf_abi, 2) 390Use the ELFv2 ABI. 391 392; These are here for testing during development only, do not document 393; in the manual please. 394 395; If we want Darwin's struct-by-value-in-regs ABI. 396mabi=d64 397Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save 398 399mabi=d32 400Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) 401 402mabi=ieeelongdouble 403Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save 404 405mabi=ibmlongdouble 406Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0) 407 408mcpu= 409Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 410-mcpu= Use features of and schedule code for given CPU. 411 412mtune= 413Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 414-mtune= Schedule code for given CPU. 415 416mtraceback= 417Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) 418-mtraceback= Select full, part, or no traceback table. 419 420Enum 421Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) 422 423EnumValue 424Enum(rs6000_traceback_type) String(full) Value(traceback_full) 425 426EnumValue 427Enum(rs6000_traceback_type) String(part) Value(traceback_part) 428 429EnumValue 430Enum(rs6000_traceback_type) String(no) Value(traceback_none) 431 432mlongcall 433Target Report Var(rs6000_default_long_calls) Save 434Avoid all range limits on call instructions. 435 436mgen-cell-microcode 437Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save 438Generate Cell microcode. 439 440mwarn-cell-microcode 441Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save 442Warn when a Cell microcoded instruction is emitted. 443 444mwarn-altivec-long 445Target Var(rs6000_warn_altivec_long) Init(1) Save 446Warn about deprecated 'vector long ...' AltiVec type usage. 447 448mfloat-gprs= 449Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save 450-mfloat-gprs= Select GPR floating point method. 451 452Enum 453Name(rs6000_float_gprs) Type(unsigned char) 454Valid arguments to -mfloat-gprs=: 455 456EnumValue 457Enum(rs6000_float_gprs) String(yes) Value(1) 458 459EnumValue 460Enum(rs6000_float_gprs) String(single) Value(1) 461 462EnumValue 463Enum(rs6000_float_gprs) String(double) Value(2) 464 465EnumValue 466Enum(rs6000_float_gprs) String(no) Value(0) 467 468mlong-double- 469Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save 470-mlong-double-<n> Specify size of long double (64 or 128 bits). 471 472mlra 473Target Report Mask(LRA) Var(rs6000_isa_flags) 474Enable Local Register Allocation. 475 476msched-costly-dep= 477Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) 478Determine which dependences between insns are considered costly. 479 480minsert-sched-nops= 481Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) 482Specify which post scheduling nop insertion scheme to apply. 483 484malign- 485Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) 486Specify alignment of structure fields default/natural. 487 488Enum 489Name(rs6000_alignment_flags) Type(unsigned char) 490Valid arguments to -malign-: 491 492EnumValue 493Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER) 494 495EnumValue 496Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) 497 498mprioritize-restricted-insns= 499Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save 500Specify scheduling priority for dispatch slot restricted insns. 501 502msingle-float 503Target RejectNegative Var(rs6000_single_float) Save 504Single-precision floating point unit. 505 506mdouble-float 507Target RejectNegative Var(rs6000_double_float) Save 508Double-precision floating point unit. 509 510msimple-fpu 511Target RejectNegative Var(rs6000_simple_fpu) Save 512Floating point unit does not support divide & sqrt. 513 514mfpu= 515Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) 516-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu). 517 518Enum 519Name(fpu_type_t) Type(enum fpu_type_t) 520 521EnumValue 522Enum(fpu_type_t) String(none) Value(FPU_NONE) 523 524EnumValue 525Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE) 526 527EnumValue 528Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE) 529 530EnumValue 531Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL) 532 533EnumValue 534Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) 535 536mxilinx-fpu 537Target Var(rs6000_xilinx_fpu) Save 538Specify Xilinx FPU. 539 540mpointers-to-nested-functions 541Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save 542Use/do not use r11 to hold the static link in calls to functions via pointers. 543 544msave-toc-indirect 545Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) 546Control whether we save the TOC in the prologue for indirect calls or generate the save inline. 547 548mvsx-timode 549Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) 550Allow 128-bit integers in VSX registers. 551 552mpower8-fusion 553Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) 554Fuse certain integer operations together for better performance on power8. 555 556mpower8-fusion-sign 557Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) 558Allow sign extension in fusion operations. 559 560mpower8-vector 561Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) 562Use/do not use vector and scalar instructions added in ISA 2.07. 563 564mcrypto 565Target Report Mask(CRYPTO) Var(rs6000_isa_flags) 566Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. 567 568mdirect-move 569Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) 570Use ISA 2.07 direct move between GPR & VSX register instructions. 571 572mhtm 573Target Report Mask(HTM) Var(rs6000_isa_flags) 574Use ISA 2.07 transactional memory (HTM) instructions. 575 576mquad-memory 577Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) 578Generate the quad word memory instructions (lq/stq). 579 580mquad-memory-atomic 581Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) 582Generate the quad word memory atomic instructions (lqarx/stqcx). 583 584mcompat-align-parm 585Target Report Var(rs6000_compat_align_parm) Init(0) Save 586Generate aggregate parameter passing code with at most 64-bit alignment. 587 588mupper-regs-df 589Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) 590Allow double variables in upper registers with -mcpu=power7 or -mvsx. 591 592mupper-regs-sf 593Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) 594Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector. 595 596mupper-regs 597Target Report Var(TARGET_UPPER_REGS) Init(-1) Save 598Allow float/double variables in upper registers if cpu allows it. 599 600moptimize-swaps 601Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save 602Analyze and remove doubleword swaps from VSX computations. 603 604mpower9-fusion 605Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags) 606Fuse certain operations together for better performance on power9. 607 608mpower9-misc 609Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) 610Use/do not use certain scalar instructions added in ISA 3.0. 611 612mpower9-vector 613Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) 614Use/do not use vector instructions added in ISA 3.0. 615 616mpower9-dform-scalar 617Target Undocumented Mask(P9_DFORM_SCALAR) Var(rs6000_isa_flags) 618Use/do not use scalar register+offset memory instructions added in ISA 3.0. 619 620mpower9-dform-vector 621Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs6000_isa_flags) 622Use/do not use vector register+offset memory instructions added in ISA 3.0. 623 624mpower9-dform 625Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save 626Use/do not use register+offset memory instructions added in ISA 3.0. 627 628mpower9-minmax 629Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags) 630Use/do not use the new min/max instructions defined in ISA 3.0. 631 632mtoc-fusion 633Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) 634Fuse medium/large code model toc references with the memory instruction. 635 636mmodulo 637Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) 638Generate the integer modulo instructions. 639 640mfloat128 641Target Report Mask(FLOAT128) Var(rs6000_isa_flags) 642Enable/disable IEEE 128-bit floating point via the __float128 keyword. 643 644mfloat128-hardware 645Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) 646Enable/disable using IEEE 128-bit floating point instructions. 647 648mfloat128-convert 649Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) 650Enable/disable default conversions between __float128 & long double. 651