1; Options for the rs6000 port of the compiler
2;
3; Copyright (C) 2005-2020 Free Software Foundation, Inc.
4; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
5;
6; This file is part of GCC.
7;
8; GCC is free software; you can redistribute it and/or modify it under
9; the terms of the GNU General Public License as published by the Free
10; Software Foundation; either version 3, or (at your option) any later
11; version.
12;
13; GCC is distributed in the hope that it will be useful, but WITHOUT
14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16; License for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with GCC; see the file COPYING3.  If not see
20; <http://www.gnu.org/licenses/>.
21
22HeaderInclude
23config/rs6000/rs6000-opts.h
24
25;; ISA flag bits (on/off)
26Variable
27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
28
29TargetSave
30HOST_WIDE_INT x_rs6000_isa_flags
31
32;; Miscellaneous flag bits that were set explicitly by the user
33Variable
34HOST_WIDE_INT rs6000_isa_flags_explicit
35
36TargetSave
37HOST_WIDE_INT x_rs6000_isa_flags_explicit
38
39;; Current processor
40TargetVariable
41enum processor_type rs6000_cpu = PROCESSOR_PPC603
42
43;; Current tuning
44TargetVariable
45enum processor_type rs6000_tune = PROCESSOR_PPC603
46
47;; Always emit branch hint bits.
48TargetVariable
49unsigned char rs6000_always_hint
50
51;; Schedule instructions for group formation.
52TargetVariable
53unsigned char rs6000_sched_groups
54
55;; Align branch targets.
56TargetVariable
57unsigned char rs6000_align_branch_targets
58
59;; Support for -msched-costly-dep option.
60TargetVariable
61enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
62
63;; Support for -minsert-sched-nops option.
64TargetVariable
65enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
66
67;; Non-zero to allow overriding loop alignment.
68TargetVariable
69unsigned char can_override_loop_align
70
71;; Which small data model to use (for System V targets only)
72TargetVariable
73enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
74
75;; Bit size of immediate TLS offsets and string from which it is decoded.
76TargetVariable
77int rs6000_tls_size = 32
78
79;; ABI enumeration available for subtarget to use.
80TargetVariable
81enum rs6000_abi rs6000_current_abi = ABI_NONE
82
83;; Type of traceback to use.
84TargetVariable
85enum rs6000_traceback_type rs6000_traceback = traceback_default
86
87;; Control alignment for fields within structures.
88TargetVariable
89unsigned char rs6000_alignment_flags
90
91;; Code model for 64-bit linux.
92TargetVariable
93enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
94
95;; What type of reciprocal estimation instructions to generate
96TargetVariable
97unsigned int rs6000_recip_control
98
99;; Mask of what builtin functions are allowed
100TargetVariable
101HOST_WIDE_INT rs6000_builtin_mask
102
103;; Debug flags
104TargetVariable
105unsigned int rs6000_debug
106
107;; Whether to enable the -mfloat128 stuff without necessarily enabling the
108;; __float128 keyword.
109TargetSave
110unsigned char x_TARGET_FLOAT128_TYPE
111
112Variable
113unsigned char TARGET_FLOAT128_TYPE
114
115;; This option existed in the past, but now is always on.
116mpowerpc
117Target RejectNegative Undocumented Ignore
118
119mpowerpc64
120Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
121Use PowerPC-64 instruction set.
122
123mpowerpc-gpopt
124Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
125Use PowerPC General Purpose group optional instructions.
126
127mpowerpc-gfxopt
128Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
129Use PowerPC Graphics group optional instructions.
130
131mmfcrf
132Target Report Mask(MFCRF) Var(rs6000_isa_flags)
133Use PowerPC V2.01 single field mfcr instruction.
134
135mpopcntb
136Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
137Use PowerPC V2.02 popcntb instruction.
138
139mfprnd
140Target Report Mask(FPRND) Var(rs6000_isa_flags)
141Use PowerPC V2.02 floating point rounding instructions.
142
143mcmpb
144Target Report Mask(CMPB) Var(rs6000_isa_flags)
145Use PowerPC V2.05 compare bytes instruction.
146
147;; This option existed in the past, but now is always off.
148mno-mfpgpr
149Target RejectNegative Undocumented Ignore
150
151mmfpgpr
152Target RejectNegative Undocumented WarnRemoved
153
154maltivec
155Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
156Use AltiVec instructions.
157
158mfold-gimple
159Target Report Var(rs6000_fold_gimple) Init(1)
160Enable early gimple folding of builtins.
161
162mhard-dfp
163Target Report Mask(DFP) Var(rs6000_isa_flags)
164Use decimal floating point instructions.
165
166mmulhw
167Target Report Mask(MULHW) Var(rs6000_isa_flags)
168Use 4xx half-word multiply instructions.
169
170mdlmzb
171Target Report Mask(DLMZB) Var(rs6000_isa_flags)
172Use 4xx string-search dlmzb instruction.
173
174mmultiple
175Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
176Generate load/store multiple instructions.
177
178;; This option existed in the past, but now is always off.
179mno-string
180Target RejectNegative Undocumented Ignore
181
182mstring
183Target RejectNegative Undocumented WarnRemoved
184
185msoft-float
186Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
187Do not use hardware floating point.
188
189mhard-float
190Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
191Use hardware floating point.
192
193mpopcntd
194Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
195Use PowerPC V2.06 popcntd instruction.
196
197mfriz
198Target Report Var(TARGET_FRIZ) Init(-1) Save
199Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
200
201mveclibabi=
202Target RejectNegative Joined Var(rs6000_veclibabi_name)
203Vector library ABI to use.
204
205mvsx
206Target Report Mask(VSX) Var(rs6000_isa_flags)
207Use vector/scalar (VSX) instructions.
208
209mvsx-align-128
210Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
211; If -mvsx, set alignment to 128 bits instead of 32/64
212
213mallow-movmisalign
214Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
215; Allow the movmisalign in DF/DI vectors
216
217mefficient-unaligned-vsx
218Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
219; Consider unaligned VSX vector and fp accesses to be efficient
220
221msched-groups
222Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
223; Explicitly set rs6000_sched_groups
224
225malways-hint
226Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
227; Explicitly set rs6000_always_hint
228
229malign-branch-targets
230Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
231; Explicitly set rs6000_align_branch_targets
232
233mno-update
234Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
235Do not generate load/store with update instructions.
236
237mupdate
238Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
239Generate load/store with update instructions.
240
241msingle-pic-base
242Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
243Do not load the PIC register in function prologues.
244
245mavoid-indexed-addresses
246Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
247Avoid generation of indexed load/store instructions when possible.
248
249msched-epilog
250Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
251
252msched-prolog
253Target Report Var(TARGET_SCHED_PROLOG) Save
254Schedule the start and end of the procedure.
255
256maix-struct-return
257Target Report RejectNegative Var(aix_struct_return) Save
258Return all structures in memory (AIX default).
259
260msvr4-struct-return
261Target Report RejectNegative Var(aix_struct_return,0) Save
262Return small structures in registers (SVR4 default).
263
264mxl-compat
265Target Report Var(TARGET_XL_COMPAT) Save
266Conform more closely to IBM XLC semantics.
267
268mrecip
269Target Report
270Generate software reciprocal divide and square root for better throughput.
271
272mrecip=
273Target Report RejectNegative Joined Var(rs6000_recip_name)
274Generate software reciprocal divide and square root for better throughput.
275
276mrecip-precision
277Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
278Assume that the reciprocal estimate instructions provide more accuracy.
279
280mno-fp-in-toc
281Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
282Do not place floating point constants in TOC.
283
284mfp-in-toc
285Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
286Place floating point constants in TOC.
287
288mno-sum-in-toc
289Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
290Do not place symbol+offset constants in TOC.
291
292msum-in-toc
293Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
294Place symbol+offset constants in TOC.
295
296;  Output only one TOC entry per module.  Normally linking fails if
297;   there are more than 16K unique variables/constants in an executable.  With
298;   this option, linking fails only if there are more than 16K modules, or
299;   if there are more than 16K unique variables/constant in a single module.
300;
301;   This is at the cost of having 2 extra loads and one extra store per
302;   function, and one less allocable register.
303mminimal-toc
304Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
305Use only one TOC entry per procedure.
306
307mfull-toc
308Target Report
309Put everything in the regular TOC.
310
311mvrsave
312Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
313Generate VRSAVE instructions when generating AltiVec code.
314
315mvrsave=no
316Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead)
317Deprecated option.  Use -mno-vrsave instead.
318
319mvrsave=yes
320Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead)
321Deprecated option.  Use -mvrsave instead.
322
323mblock-move-inline-limit=
324Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
325Max number of bytes to move inline.
326
327mblock-compare-inline-limit=
328Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
329Max number of bytes to compare without loops.
330
331mblock-compare-inline-loop-limit=
332Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
333Max number of bytes to compare with loops.
334
335mstring-compare-inline-limit=
336Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
337Max number of bytes to compare.
338
339misel
340Target Report Mask(ISEL) Var(rs6000_isa_flags)
341Generate isel instructions.
342
343mdebug=
344Target RejectNegative Joined
345-mdebug=	Enable debug output.
346
347; Altivec ABI
348mabi=altivec
349Target RejectNegative Var(rs6000_altivec_abi) Save
350Use the AltiVec ABI extensions.
351
352mabi=no-altivec
353Target RejectNegative Var(rs6000_altivec_abi, 0)
354Do not use the AltiVec ABI extensions.
355
356; AIX Extended vector ABI
357mabi=vec-extabi
358Target RejectNegative Var(rs6000_aix_extabi, 1) Save
359Use the AIX Vector Extended ABI.
360
361mabi=vec-default
362Target RejectNegative Var(rs6000_aix_extabi, 0)
363Do not use the AIX Vector Extended ABI.
364
365; PPC64 Linux ELF ABI
366mabi=elfv1
367Target RejectNegative Var(rs6000_elf_abi, 1) Save
368Use the ELFv1 ABI.
369
370mabi=elfv2
371Target RejectNegative Var(rs6000_elf_abi, 2)
372Use the ELFv2 ABI.
373
374; These are here for testing during development only, do not document
375; in the manual please.
376
377; If we want Darwin's struct-by-value-in-regs ABI.
378mabi=d64
379Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
380
381mabi=d32
382Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
383
384mabi=ieeelongdouble
385Target RejectNegative Var(rs6000_ieeequad) Save
386
387mabi=ibmlongdouble
388Target RejectNegative Var(rs6000_ieeequad, 0)
389
390mcpu=
391Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
392-mcpu=	Use features of and schedule code for given CPU.
393
394mtune=
395Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
396-mtune=	Schedule code for given CPU.
397
398mtraceback=
399Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
400-mtraceback=[full,part,no]	Select type of traceback table.
401
402Enum
403Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
404
405EnumValue
406Enum(rs6000_traceback_type) String(full) Value(traceback_full)
407
408EnumValue
409Enum(rs6000_traceback_type) String(part) Value(traceback_part)
410
411EnumValue
412Enum(rs6000_traceback_type) String(no) Value(traceback_none)
413
414mlongcall
415Target Report Var(rs6000_default_long_calls) Save
416Avoid all range limits on call instructions.
417
418; This option existed in the past, but now is always on.
419mgen-cell-microcode
420Target RejectNegative Undocumented Ignore
421
422mwarn-altivec-long
423Target Var(rs6000_warn_altivec_long) Init(1) Save
424Warn about deprecated 'vector long ...' AltiVec type usage.
425
426mlong-double-
427Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
428Use -mlong-double-64 for 64-bit IEEE floating point format.  Use
429-mlong-double-128 for 128-bit floating point format (either IEEE or IBM).
430
431; This option existed in the past, but now is always on.
432mlra
433Target RejectNegative Undocumented Ignore
434
435msched-costly-dep=
436Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
437Determine which dependences between insns are considered costly.
438
439minsert-sched-nops=
440Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
441Specify which post scheduling nop insertion scheme to apply.
442
443malign-
444Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
445Specify alignment of structure fields default/natural.
446
447Enum
448Name(rs6000_alignment_flags) Type(unsigned char)
449Valid arguments to -malign-:
450
451EnumValue
452Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
453
454EnumValue
455Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
456
457mprioritize-restricted-insns=
458Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
459Specify scheduling priority for dispatch slot restricted insns.
460
461mpointers-to-nested-functions
462Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
463Use r11 to hold the static link in calls to functions via pointers.
464
465msave-toc-indirect
466Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
467Save the TOC in the prologue for indirect calls rather than inline.
468
469; This option existed in the past, but now is always the same as -mvsx.
470mvsx-timode
471Target RejectNegative Undocumented Ignore
472
473mpower8-fusion
474Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
475Fuse certain integer operations together for better performance on power8.
476
477mpower8-fusion-sign
478Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
479Allow sign extension in fusion operations.
480
481mpower8-vector
482Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
483Use vector and scalar instructions added in ISA 2.07.
484
485mcrypto
486Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
487Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
488
489mdirect-move
490Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved
491
492mhtm
493Target Report Mask(HTM) Var(rs6000_isa_flags)
494Use ISA 2.07 transactional memory (HTM) instructions.
495
496mquad-memory
497Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
498Generate the quad word memory instructions (lq/stq).
499
500mquad-memory-atomic
501Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
502Generate the quad word memory atomic instructions (lqarx/stqcx).
503
504mcompat-align-parm
505Target Report Var(rs6000_compat_align_parm) Init(0) Save
506Generate aggregate parameter passing code with at most 64-bit alignment.
507
508moptimize-swaps
509Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
510Analyze and remove doubleword swaps from VSX computations.
511
512munroll-only-small-loops
513Target Undocumented Var(unroll_only_small_loops) Init(0) Save
514; Use conservative small loop unrolling.
515
516mpower9-misc
517Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
518Use certain scalar instructions added in ISA 3.0.
519
520mpower9-vector
521Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
522Use vector instructions added in ISA 3.0.
523
524mpower9-minmax
525Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
526Use the new min/max instructions defined in ISA 3.0.
527
528mtoc-fusion
529Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
530Fuse medium/large code model toc references with the memory instruction.
531
532mmodulo
533Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
534Generate the integer modulo instructions.
535
536mfloat128
537Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
538Enable IEEE 128-bit floating point via the __float128 keyword.
539
540mfloat128-hardware
541Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
542Enable using IEEE 128-bit floating point instructions.
543
544mfloat128-convert
545Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
546Enable default conversions between __float128 & long double.
547
548mstack-protector-guard=
549Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
550Use given stack-protector guard.
551
552Enum
553Name(stack_protector_guard) Type(enum stack_protector_guard)
554Valid arguments to -mstack-protector-guard=:
555
556EnumValue
557Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
558
559EnumValue
560Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
561
562mstack-protector-guard-reg=
563Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
564Use the given base register for addressing the stack-protector guard.
565
566TargetVariable
567int rs6000_stack_protector_guard_reg = 0
568
569mstack-protector-guard-offset=
570Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
571Use the given offset for addressing the stack-protector guard.
572
573TargetVariable
574long rs6000_stack_protector_guard_offset = 0
575
576;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
577;; branches via the CTR.
578mspeculate-indirect-jumps
579Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
580
581mpower10
582Target Report Mask(POWER10) Var(rs6000_isa_flags)
583Use instructions added in ISA 3.1.
584
585mprefixed
586Target Report Mask(PREFIXED) Var(rs6000_isa_flags)
587Generate (do not generate) prefixed memory instructions.
588
589mpcrel
590Target Report Mask(PCREL) Var(rs6000_isa_flags)
591Generate (do not generate) pc-relative memory addressing.
592
593mmma
594Target Report Mask(MMA) Var(rs6000_isa_flags)
595Generate (do not generate) MMA instructions.
596