config/rs6000/rs6000.opt

; Options for the rs6000 port of the compiler
;
; Copyright (C) 2005-2015 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/rs6000/rs6000-opts.h

;; ISA flag bits (on/off)
Variable
HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT

TargetSave
HOST_WIDE_INT x_rs6000_isa_flags

;; Miscellaneous flag bits that were set explicitly by the user
Variable
HOST_WIDE_INT rs6000_isa_flags_explicit

TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit

;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603

;; Always emit branch hint bits.
TargetVariable
unsigned char rs6000_always_hint

;; Schedule instructions for group formation.
TargetVariable
unsigned char rs6000_sched_groups

;; Align branch targets.
TargetVariable
unsigned char rs6000_align_branch_targets

;; Support for -msched-costly-dep option.
TargetVariable
enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly

;; Support for -minsert-sched-nops option.
TargetVariable
enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none

;; Non-zero to allow overriding loop alignment.
TargetVariable
unsigned char can_override_loop_align

;; Which small data model to use (for System V targets only)
TargetVariable
enum rs6000_sdata_type rs6000_sdata = SDATA_DATA

;; Bit size of immediate TLS offsets and string from which it is decoded.
TargetVariable
int rs6000_tls_size = 32

;; ABI enumeration available for subtarget to use.
TargetVariable
enum rs6000_abi rs6000_current_abi = ABI_NONE

;; Type of traceback to use.
TargetVariable
enum rs6000_traceback_type rs6000_traceback = traceback_default

;; Control alignment for fields within structures.
TargetVariable
unsigned char rs6000_alignment_flags

;; Code model for 64-bit linux.
TargetVariable
enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL

;; What type of reciprocal estimation instructions to generate
TargetVariable
unsigned int rs6000_recip_control

;; Mask of what builtin functions are allowed
TargetVariable
HOST_WIDE_INT rs6000_builtin_mask

;; Debug flags
TargetVariable
unsigned int rs6000_debug

;; This option existed in the past, but now is always on.
mpowerpc
Target RejectNegative Undocumented Ignore

mpowerpc64
Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set

mpowerpc-gpopt
Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions

mpowerpc-gfxopt
Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions

mmfcrf
Target Report Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction

mpopcntb
Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction

mfprnd
Target Report Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions

mcmpb
Target Report Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction

mmfpgpr
Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
Use extended PowerPC V2.05 move floating point to/from GPR instructions

maltivec
Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions

maltivec=le
Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save
Generate AltiVec instructions using little-endian element order

maltivec=be
Target Report RejectNegative Var(rs6000_altivec_element_order, 2)
Generate AltiVec instructions using big-endian element order

mhard-dfp
Target Report Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions

mmulhw
Target Report Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions

mdlmzb
Target Report Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction

mmultiple
Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions

mstring
Target Report Mask(STRING) Var(rs6000_isa_flags)
Generate string instructions for block moves

msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point

mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point

mpopcntd
Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction

mfriz
Target Report Var(TARGET_FRIZ) Init(-1) Save
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions

mveclibabi=
Target RejectNegative Joined Var(rs6000_veclibabi_name)
Vector library ABI to use

mvsx
Target Report Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions

mvsx-scalar-float
Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1)
; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default)

mvsx-scalar-double
Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1)
; If -mvsx, use VSX arithmetic instructions for DFmode (on by default)

mvsx-scalar-memory
Target Undocumented Report Alias(mupper-regs-df)

mvsx-align-128
Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64

mallow-movmisalign
Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow/disallow the movmisalign in DF/DI vectors

mefficient-unaligned-vector
Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX accesses to be efficient/inefficient

mallow-df-permute
Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save
; Allow/disallow permutation of DF/DI vectors

msched-groups
Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set/unset whether rs6000_sched_groups is set

malways-hint
Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set/unset whether rs6000_always_hint is set

malign-branch-targets
Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set/unset whether rs6000_align_branch_targets is set

mvectorize-builtins
Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save
; Explicitly control whether we vectorize the builtins or not.

mno-update
Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions

mupdate
Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions

msingle-pic-base
Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
Do not load the PIC register in function prologues

mavoid-indexed-addresses
Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
Avoid generation of indexed load/store instructions when possible

mtls-markers
Target Report Var(tls_markers) Init(1) Save
Mark __tls_get_addr calls with argument info

msched-epilog
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save

msched-prolog
Target Report Var(TARGET_SCHED_PROLOG) Save
Schedule the start and end of the procedure

maix-struct-return
Target Report RejectNegative Var(aix_struct_return) Save
Return all structures in memory (AIX default)

msvr4-struct-return
Target Report RejectNegative Var(aix_struct_return,0) Save
Return small structures in registers (SVR4 default)

mxl-compat
Target Report Var(TARGET_XL_COMPAT) Save
Conform more closely to IBM XLC semantics

mrecip
Target Report
Generate software reciprocal divide and square root for better throughput.

mrecip=
Target Report RejectNegative Joined Var(rs6000_recip_name)
Generate software reciprocal divide and square root for better throughput.

mrecip-precision
Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy.

mno-fp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
Do not place floating point constants in TOC

mfp-in-toc
Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
Place floating point constants in TOC

mno-sum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
Do not place symbol+offset constants in TOC

msum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
Place symbol+offset constants in TOC

;  Output only one TOC entry per module.  Normally linking fails if
;   there are more than 16K unique variables/constants in an executable.  With
;   this option, linking fails only if there are more than 16K modules, or
;   if there are more than 16K unique variables/constant in a single module.
;
;   This is at the cost of having 2 extra loads and one extra store per
;   function, and one less allocable register.
mminimal-toc
Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure

mfull-toc
Target Report
Put everything in the regular TOC

mvrsave
Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
Generate VRSAVE instructions when generating AltiVec code

mvrsave=no
Target RejectNegative Alias(mvrsave) NegativeAlias
Deprecated option.  Use -mno-vrsave instead

mvrsave=yes
Target RejectNegative Alias(mvrsave)
Deprecated option.  Use -mvrsave instead

mblock-move-inline-limit=
Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
Specify how many bytes should be moved inline before calling out to memcpy/memmove

misel
Target Report Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions

misel=no
Target RejectNegative Alias(misel) NegativeAlias
Deprecated option.  Use -mno-isel instead

misel=yes
Target RejectNegative Alias(misel)
Deprecated option.  Use -misel instead

mspe
Target Var(rs6000_spe) Save
Generate SPE SIMD instructions on E500

mpaired
Target Var(rs6000_paired_float) Save
Generate PPC750CL paired-single instructions

mspe=no
Target RejectNegative Alias(mspe) NegativeAlias
Deprecated option.  Use -mno-spe instead

mspe=yes
Target RejectNegative Alias(mspe)
Deprecated option.  Use -mspe instead

mdebug=
Target RejectNegative Joined
-mdebug=	Enable debug output

mabi=altivec
Target RejectNegative Var(rs6000_altivec_abi) Save
Use the AltiVec ABI extensions

mabi=no-altivec
Target RejectNegative Var(rs6000_altivec_abi, 0)
Do not use the AltiVec ABI extensions

mabi=spe
Target RejectNegative Var(rs6000_spe_abi) Save
Use the SPE ABI extensions

mabi=no-spe
Target RejectNegative Var(rs6000_spe_abi, 0)
Do not use the SPE ABI extensions

mabi=elfv1
Target RejectNegative Var(rs6000_elf_abi, 1) Save
Use the ELFv1 ABI

mabi=elfv2
Target RejectNegative Var(rs6000_elf_abi, 2)
Use the ELFv2 ABI

; These are here for testing during development only, do not document
; in the manual please.

; If we want Darwin's struct-by-value-in-regs ABI.
mabi=d64
Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save

mabi=d32
Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)

mabi=ieeelongdouble
Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save

mabi=ibmlongdouble
Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0)

mcpu=
Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mcpu=	Use features of and schedule code for given CPU

mtune=
Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mtune=	Schedule code for given CPU

mtraceback=
Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
-mtraceback=	Select full, part, or no traceback table

Enum
Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)

EnumValue
Enum(rs6000_traceback_type) String(full) Value(traceback_full)

EnumValue
Enum(rs6000_traceback_type) String(part) Value(traceback_part)

EnumValue
Enum(rs6000_traceback_type) String(no) Value(traceback_none)

mlongcall
Target Report Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions

mgen-cell-microcode
Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
Generate Cell microcode

mwarn-cell-microcode
Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
Warn when a Cell microcoded instruction is emitted

mwarn-altivec-long
Target Var(rs6000_warn_altivec_long) Init(1) Save
Warn about deprecated 'vector long ...' AltiVec type usage

mfloat-gprs=
Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save
-mfloat-gprs=	Select GPR floating point method

Enum
Name(rs6000_float_gprs) Type(unsigned char)
Valid arguments to -mfloat-gprs=:

EnumValue
Enum(rs6000_float_gprs) String(yes) Value(1)

EnumValue
Enum(rs6000_float_gprs) String(single) Value(1)

EnumValue
Enum(rs6000_float_gprs) String(double) Value(2)

EnumValue
Enum(rs6000_float_gprs) String(no) Value(0)

mlong-double-
Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
-mlong-double-<n>	Specify size of long double (64 or 128 bits)

mlra
Target Report Var(rs6000_lra_flag) Init(0) Save
Use LRA instead of reload

msched-costly-dep=
Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
Determine which dependences between insns are considered costly

minsert-sched-nops=
Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
Specify which post scheduling nop insertion scheme to apply

malign-
Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
Specify alignment of structure fields default/natural

Enum
Name(rs6000_alignment_flags) Type(unsigned char)
Valid arguments to -malign-:

EnumValue
Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)

EnumValue
Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)

mprioritize-restricted-insns=
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
Specify scheduling priority for dispatch slot restricted insns

msingle-float
Target RejectNegative Var(rs6000_single_float) Save
Single-precision floating point unit

mdouble-float
Target RejectNegative Var(rs6000_double_float) Save
Double-precision floating point unit

msimple-fpu
Target RejectNegative Var(rs6000_simple_fpu) Save
Floating point unit does not support divide & sqrt

mfpu=
Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
-mfpu=	Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu)

Enum
Name(fpu_type_t) Type(enum fpu_type_t)

EnumValue
Enum(fpu_type_t) String(none) Value(FPU_NONE)

EnumValue
Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)

EnumValue
Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)

EnumValue
Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)

EnumValue
Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)

mxilinx-fpu
Target Var(rs6000_xilinx_fpu) Save
Specify Xilinx FPU.

mpointers-to-nested-functions
Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use/do not use r11 to hold the static link in calls to functions via pointers.

msave-toc-indirect
Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Control whether we save the TOC in the prologue for indirect calls or generate the save inline

mvsx-timode
Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags)
Allow 128-bit integers in VSX registers

mpower8-fusion
Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8

mpower8-fusion-sign
Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
Allow sign extension in fusion operations

mpower8-vector
Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use/do not use vector and scalar instructions added in ISA 2.07.

mcrypto
Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions

mdirect-move
Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags)
Use ISA 2.07 direct move between GPR & VSX register instructions

mhtm
Target Report Mask(HTM) Var(rs6000_isa_flags)
Use ISA 2.07 transactional memory (HTM) instructions

mquad-memory
Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
Generate the quad word memory instructions (lq/stq).

mquad-memory-atomic
Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
Generate the quad word memory atomic instructions (lqarx/stqcx).

mcompat-align-parm
Target Report Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.

mupper-regs-df
Target Report Mask(UPPER_REGS_DF) Var(rs6000_isa_flags)
Allow double variables in upper registers with -mcpu=power7 or -mvsx

mupper-regs-sf
Target Report Mask(UPPER_REGS_SF) Var(rs6000_isa_flags)
Allow float variables in upper registers with -mcpu=power8 or -mpower8-vector

mupper-regs
Target Report Var(TARGET_UPPER_REGS) Init(-1) Save
Allow float/double variables in upper registers if cpu allows it

moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.