rs6000.opt revision 1.1.1.1
1; Options for the rs6000 port of the compiler 2; 3; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>. 5; 6; This file is part of GCC. 7; 8; GCC is free software; you can redistribute it and/or modify it under 9; the terms of the GNU General Public License as published by the Free 10; Software Foundation; either version 3, or (at your option) any later 11; version. 12; 13; GCC is distributed in the hope that it will be useful, but WITHOUT 14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16; License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with GCC; see the file COPYING3. If not see 20; <http://www.gnu.org/licenses/>. 21 22mpower 23Target Report RejectNegative Mask(POWER) 24Use POWER instruction set 25 26mno-power 27Target Report RejectNegative 28Do not use POWER instruction set 29 30mpower2 31Target Report Mask(POWER2) 32Use POWER2 instruction set 33 34mpowerpc 35Target Report RejectNegative Mask(POWERPC) 36Use PowerPC instruction set 37 38mno-powerpc 39Target Report RejectNegative 40Do not use PowerPC instruction set 41 42mpowerpc64 43Target Report Mask(POWERPC64) 44Use PowerPC-64 instruction set 45 46mpowerpc-gpopt 47Target Report Mask(PPC_GPOPT) 48Use PowerPC General Purpose group optional instructions 49 50mpowerpc-gfxopt 51Target Report Mask(PPC_GFXOPT) 52Use PowerPC Graphics group optional instructions 53 54mmfcrf 55Target Report Mask(MFCRF) 56Use PowerPC V2.01 single field mfcr instruction 57 58mpopcntb 59Target Report Mask(POPCNTB) 60Use PowerPC V2.02 popcntb instruction 61 62mfprnd 63Target Report Mask(FPRND) 64Use PowerPC V2.02 floating point rounding instructions 65 66mcmpb 67Target Report Mask(CMPB) 68Use PowerPC V2.05 compare bytes instruction 69 70mmfpgpr 71Target Report Mask(MFPGPR) 72Use extended PowerPC V2.05 move floating point to/from GPR instructions 73 74maltivec 75Target Report Mask(ALTIVEC) 76Use AltiVec instructions 77 78mhard-dfp 79Target Report Mask(DFP) 80Use decimal floating point instructions 81 82mmulhw 83Target Report Mask(MULHW) 84Use 4xx half-word multiply instructions 85 86mdlmzb 87Target Report Mask(DLMZB) 88Use 4xx string-search dlmzb instruction 89 90mmultiple 91Target Report Mask(MULTIPLE) 92Generate load/store multiple instructions 93 94mstring 95Target Report Mask(STRING) 96Generate string instructions for block moves 97 98mnew-mnemonics 99Target Report RejectNegative Mask(NEW_MNEMONICS) 100Use new mnemonics for PowerPC architecture 101 102mold-mnemonics 103Target Report RejectNegative InverseMask(NEW_MNEMONICS) 104Use old mnemonics for PowerPC architecture 105 106msoft-float 107Target Report RejectNegative Mask(SOFT_FLOAT) 108Do not use hardware floating point 109 110mhard-float 111Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) 112Use hardware floating point 113 114mpopcntd 115Target Report Mask(POPCNTD) 116Use PowerPC V2.06 popcntd instruction 117 118mvsx 119Target Report Mask(VSX) 120Use vector/scalar (VSX) instructions 121 122mvsx-scalar-double 123Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) 124; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) 125 126mvsx-scalar-memory 127Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) 128; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) 129 130mvsx-align-128 131Target Undocumented Report Var(TARGET_VSX_ALIGN_128) 132; If -mvsx, set alignment to 128 bits instead of 32/64 133 134mallow-movmisalign 135Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) 136; Allow/disallow the movmisalign in DF/DI vectors 137 138mallow-df-permute 139Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) 140; Allow/disallow permutation of DF/DI vectors 141 142msched-groups 143Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) 144; Explicitly set/unset whether rs6000_sched_groups is set 145 146malways-hint 147Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) 148; Explicitly set/unset whether rs6000_always_hint is set 149 150malign-branch-targets 151Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) 152; Explicitly set/unset whether rs6000_align_branch_targets is set 153 154mvectorize-builtins 155Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) 156; Explicitly control whether we vectorize the builtins or not. 157 158mno-update 159Target Report RejectNegative Mask(NO_UPDATE) 160Do not generate load/store with update instructions 161 162mupdate 163Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) 164Generate load/store with update instructions 165 166mavoid-indexed-addresses 167Target Report Var(TARGET_AVOID_XFORM) Init(-1) 168Avoid generation of indexed load/store instructions when possible 169 170mfused-madd 171Target Report Var(TARGET_FUSED_MADD) Init(1) 172Generate fused multiply/add instructions 173 174mtls-markers 175Target Report Var(tls_markers) Init(1) 176Mark __tls_get_addr calls with argument info 177 178msched-epilog 179Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) 180 181msched-prolog 182Target Report Var(TARGET_SCHED_PROLOG) VarExists 183Schedule the start and end of the procedure 184 185maix-struct-return 186Target Report RejectNegative Var(aix_struct_return) 187Return all structures in memory (AIX default) 188 189msvr4-struct-return 190Target Report RejectNegative Var(aix_struct_return,0) VarExists 191Return small structures in registers (SVR4 default) 192 193mxl-compat 194Target Report Var(TARGET_XL_COMPAT) 195Conform more closely to IBM XLC semantics 196 197mrecip 198Target Report Var(TARGET_RECIP) 199Generate software reciprocal sqrt for better throughput 200 201mno-fp-in-toc 202Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) 203Do not place floating point constants in TOC 204 205mfp-in-toc 206Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) 207Place floating point constants in TOC 208 209mno-sum-in-toc 210Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) 211Do not place symbol+offset constants in TOC 212 213msum-in-toc 214Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists 215Place symbol+offset constants in TOC 216 217; Output only one TOC entry per module. Normally linking fails if 218; there are more than 16K unique variables/constants in an executable. With 219; this option, linking fails only if there are more than 16K modules, or 220; if there are more than 16K unique variables/constant in a single module. 221; 222; This is at the cost of having 2 extra loads and one extra store per 223; function, and one less allocable register. 224mminimal-toc 225Target Report Mask(MINIMAL_TOC) 226Use only one TOC entry per procedure 227 228mfull-toc 229Target Report 230Put everything in the regular TOC 231 232mvrsave 233Target Report Var(TARGET_ALTIVEC_VRSAVE) 234Generate VRSAVE instructions when generating AltiVec code 235 236mvrsave= 237Target RejectNegative Joined 238-mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead 239 240misel 241Target Report Mask(ISEL) 242Generate isel instructions 243 244misel= 245Target RejectNegative Joined 246-misel=yes/no Deprecated option. Use -misel/-mno-isel instead 247 248mspe 249Target 250Generate SPE SIMD instructions on E500 251 252mpaired 253Target Var(rs6000_paired_float) 254Generate PPC750CL paired-single instructions 255 256mspe= 257Target RejectNegative Joined 258-mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead 259 260mdebug= 261Target RejectNegative Joined 262-mdebug= Enable debug output 263 264mabi= 265Target RejectNegative Joined 266-mabi= Specify ABI to use 267 268mcpu= 269Target RejectNegative Joined 270-mcpu= Use features of and schedule code for given CPU 271 272mtune= 273Target RejectNegative Joined 274-mtune= Schedule code for given CPU 275 276mtraceback= 277Target RejectNegative Joined 278-mtraceback= Select full, part, or no traceback table 279 280mlongcall 281Target Report Var(rs6000_default_long_calls) 282Avoid all range limits on call instructions 283 284mgen-cell-microcode 285Target Report Var(rs6000_gen_cell_microcode) Init(-1) 286Generate Cell microcode 287 288mwarn-cell-microcode 289Target Var(rs6000_warn_cell_microcode) Init(0) Warning 290Warn when a Cell microcoded instruction is emitted 291 292mwarn-altivec-long 293Target Var(rs6000_warn_altivec_long) Init(1) 294Warn about deprecated 'vector long ...' AltiVec type usage 295 296mfloat-gprs= 297Target RejectNegative Joined 298-mfloat-gprs= Select GPR floating point method 299 300mlong-double- 301Target RejectNegative Joined UInteger 302-mlong-double-<n> Specify size of long double (64 or 128 bits) 303 304msched-costly-dep= 305Target RejectNegative Joined 306Determine which dependences between insns are considered costly 307 308minsert-sched-nops= 309Target RejectNegative Joined 310Specify which post scheduling nop insertion scheme to apply 311 312malign- 313Target RejectNegative Joined 314Specify alignment of structure fields default/natural 315 316mprioritize-restricted-insns= 317Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) 318Specify scheduling priority for dispatch slot restricted insns 319 320msingle-float 321Target RejectNegative Var(rs6000_single_float) 322Single-precision floating point unit 323 324mdouble-float 325Target RejectNegative Var(rs6000_double_float) 326Double-precision floating point unit 327 328msimple-fpu 329Target RejectNegative Var(rs6000_simple_fpu) 330Floating point unit does not support divide & sqrt 331 332mfpu= 333Target RejectNegative Joined 334-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu) 335 336mxilinx-fpu 337Target Var(rs6000_xilinx_fpu) 338Specify Xilinx FPU. 339 340 341