1/* IBM RS/6000 CPU names..
2   Copyright (C) 1991-2020 Free Software Foundation, Inc.
3   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5   This file is part of GCC.
6
7   GCC is free software; you can redistribute it and/or modify it
8   under the terms of the GNU General Public License as published
9   by the Free Software Foundation; either version 3, or (at your
10   option) any later version.
11
12   GCC is distributed in the hope that it will be useful, but WITHOUT
13   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15   License for more details.
16
17   You should have received a copy of the GNU General Public License
18   along with GCC; see the file COPYING3.  If not see
19   <http://www.gnu.org/licenses/>.  */
20
21/* ISA masks.  */
22#ifndef ISA_2_1_MASKS
23#define ISA_2_1_MASKS		OPTION_MASK_MFCRF
24#define ISA_2_2_MASKS		(ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
25#define ISA_2_4_MASKS		(ISA_2_2_MASKS | OPTION_MASK_FPRND)
26
27  /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
28     power6.  In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
29     as optional.  Group masks by server and embedded. */
30#define ISA_2_5_MASKS_EMBEDDED	(ISA_2_4_MASKS				\
31				 | OPTION_MASK_CMPB			\
32				 | OPTION_MASK_RECIP_PRECISION		\
33				 | OPTION_MASK_PPC_GFXOPT		\
34				 | OPTION_MASK_PPC_GPOPT)
35
36#define ISA_2_5_MASKS_SERVER	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
37
38  /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
39     altivec is a win so enable it.  */
40#define ISA_2_6_MASKS_EMBEDDED	(ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
41#define ISA_2_6_MASKS_SERVER	(ISA_2_5_MASKS_SERVER			\
42				 | OPTION_MASK_POPCNTD			\
43				 | OPTION_MASK_ALTIVEC			\
44				 | OPTION_MASK_VSX)
45
46/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
47   fusion here, instead set it in rs6000.c if we are tuning for a power8
48   system.  */
49#define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
50				 | OPTION_MASK_P8_VECTOR		\
51				 | OPTION_MASK_CRYPTO			\
52				 | OPTION_MASK_DIRECT_MOVE		\
53				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
54				 | OPTION_MASK_HTM			\
55				 | OPTION_MASK_QUAD_MEMORY		\
56				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
57
58/* ISA masks setting fusion options.  */
59#define OTHER_FUSION_MASKS	(OPTION_MASK_P8_FUSION			\
60				 | OPTION_MASK_P8_FUSION_SIGN)
61
62/* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
63   FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
64#define ISA_3_0_MASKS_SERVER	((ISA_2_7_MASKS_SERVER			\
65				  | OPTION_MASK_ISEL			\
66				  | OPTION_MASK_MODULO			\
67				  | OPTION_MASK_P9_MINMAX		\
68				  | OPTION_MASK_P9_MISC			\
69				  | OPTION_MASK_P9_VECTOR)		\
70				 & ~OTHER_FUSION_MASKS)
71
72/* Support for the IEEE 128-bit floating point hardware requires a lot of the
73   VSX instructions that are part of ISA 3.0.  */
74#define ISA_3_0_MASKS_IEEE	(OPTION_MASK_VSX			\
75				 | OPTION_MASK_P8_VECTOR		\
76				 | OPTION_MASK_P9_VECTOR)
77
78/* Flags that need to be turned off if -mno-power10.  */
79#define OTHER_POWER10_MASKS	(OPTION_MASK_MMA			\
80				 | OPTION_MASK_PCREL			\
81				 | OPTION_MASK_PREFIXED)
82
83#define ISA_3_1_MASKS_SERVER	(ISA_3_0_MASKS_SERVER			\
84				 | OPTION_MASK_POWER10			\
85				 | OTHER_POWER10_MASKS)
86
87/* Flags that need to be turned off if -mno-power9-vector.  */
88#define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
89				 | OPTION_MASK_P9_MINMAX)
90
91/* Flags that need to be turned off if -mno-power8-vector.  */
92#define OTHER_P8_VECTOR_MASKS	(OTHER_P9_VECTOR_MASKS			\
93				 | OPTION_MASK_P9_VECTOR		\
94				 | OPTION_MASK_DIRECT_MOVE		\
95				 | OPTION_MASK_CRYPTO)
96
97/* Flags that need to be turned off if -mno-vsx.  */
98#define OTHER_VSX_VECTOR_MASKS	(OTHER_P8_VECTOR_MASKS			\
99				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
100				 | OPTION_MASK_FLOAT128_KEYWORD		\
101				 | OPTION_MASK_P8_VECTOR)
102
103/* Flags that need to be turned off if -mno-altivec.  */
104#define OTHER_ALTIVEC_MASKS	(OTHER_VSX_VECTOR_MASKS			\
105				 | OPTION_MASK_VSX)
106
107#define POWERPC_7400_MASK	(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
108
109/* Deal with ports that do not have -mstrict-align.  */
110#ifdef OPTION_MASK_STRICT_ALIGN
111#define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
112#else
113#define OPTION_MASK_STRICT_ALIGN 0
114#define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
115#ifndef MASK_STRICT_ALIGN
116#define MASK_STRICT_ALIGN 0
117#endif
118#endif
119
120/* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
121#define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
122				 | OPTION_MASK_CMPB			\
123				 | OPTION_MASK_CRYPTO			\
124				 | OPTION_MASK_DFP			\
125				 | OPTION_MASK_DIRECT_MOVE		\
126				 | OPTION_MASK_DLMZB			\
127				 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX	\
128				 | OPTION_MASK_FLOAT128_HW		\
129				 | OPTION_MASK_FLOAT128_KEYWORD		\
130				 | OPTION_MASK_FPRND			\
131				 | OPTION_MASK_POWER10			\
132				 | OPTION_MASK_HTM			\
133				 | OPTION_MASK_ISEL			\
134				 | OPTION_MASK_MFCRF			\
135				 | OPTION_MASK_MMA			\
136				 | OPTION_MASK_MODULO			\
137				 | OPTION_MASK_MULHW			\
138				 | OPTION_MASK_NO_UPDATE		\
139				 | OPTION_MASK_P8_FUSION		\
140				 | OPTION_MASK_P8_VECTOR		\
141				 | OPTION_MASK_P9_MINMAX		\
142				 | OPTION_MASK_P9_MISC			\
143				 | OPTION_MASK_P9_VECTOR		\
144				 | OPTION_MASK_PCREL			\
145				 | OPTION_MASK_POPCNTB			\
146				 | OPTION_MASK_POPCNTD			\
147				 | OPTION_MASK_POWERPC64		\
148				 | OPTION_MASK_PPC_GFXOPT		\
149				 | OPTION_MASK_PPC_GPOPT		\
150				 | OPTION_MASK_PREFIXED			\
151				 | OPTION_MASK_QUAD_MEMORY		\
152				 | OPTION_MASK_QUAD_MEMORY_ATOMIC	\
153				 | OPTION_MASK_RECIP_PRECISION		\
154				 | OPTION_MASK_SOFT_FLOAT		\
155				 | OPTION_MASK_STRICT_ALIGN_OPTIONAL	\
156				 | OPTION_MASK_VSX)
157
158#endif
159
160/* This table occasionally claims that a processor does not support a
161   particular feature even though it does, but the feature is slower than the
162   alternative.  Thus, it shouldn't be relied on as a complete description of
163   the processor's support.
164
165   Please keep this list in order, and don't forget to update the documentation
166   in invoke.texi when adding a new processor or flag.
167
168   Before including this file, define a macro:
169
170   RS6000_CPU (NAME, CPU, FLAGS)
171
172   where the arguments are the fields of struct rs6000_ptt.  */
173
174RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
175RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
176RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
177RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
178RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
179RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
180RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
181RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
182RS6000_CPU ("476", PROCESSOR_PPC476,
183	    MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
184	    | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
185RS6000_CPU ("476fp", PROCESSOR_PPC476,
186	    MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
187	    | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
188RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
189RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
190RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
191RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
192RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
193RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
194RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
195RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
196RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
197RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
198RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
199RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
200RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
201RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
202RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
203RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
204RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
205RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
206RS6000_CPU ("a2", PROCESSOR_PPCA2,
207	    MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
208	    | MASK_NO_UPDATE)
209RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
210RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
211RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
212RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
213	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
214RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
215	    MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
216RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
217	    | MASK_MFCRF | MASK_ISEL)
218RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
219RS6000_CPU ("970", PROCESSOR_POWER4,
220	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
221RS6000_CPU ("cell", PROCESSOR_CELL,
222	    POWERPC_7400_MASK  | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
223RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
224RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
225RS6000_CPU ("G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK)
226RS6000_CPU ("G5", PROCESSOR_POWER4,
227	    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
228RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
229RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
230RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
231	    | MASK_PPC_GFXOPT | MASK_MFCRF)
232RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
233	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
234RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
235	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
236RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
237	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
238	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
239RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
240	    | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
241	    | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
242RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
243RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
244RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
245RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER)
246RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
247RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
248RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
249RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
250