1/* Subroutines used to generate function calls and handle built-in 2 instructions on IBM RS/6000. 3 Copyright (C) 1991-2020 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21#define IN_TARGET_CODE 1 22 23#include "config.h" 24#include "system.h" 25#include "coretypes.h" 26#include "backend.h" 27#include "rtl.h" 28#include "tree.h" 29#include "memmodel.h" 30#include "gimple.h" 31#include "cfghooks.h" 32#include "cfgloop.h" 33#include "df.h" 34#include "tm_p.h" 35#include "stringpool.h" 36#include "expmed.h" 37#include "optabs.h" 38#include "regs.h" 39#include "ira.h" 40#include "recog.h" 41#include "cgraph.h" 42#include "diagnostic-core.h" 43#include "insn-attr.h" 44#include "flags.h" 45#include "alias.h" 46#include "fold-const.h" 47#include "attribs.h" 48#include "stor-layout.h" 49#include "calls.h" 50#include "print-tree.h" 51#include "varasm.h" 52#include "explow.h" 53#include "expr.h" 54#include "output.h" 55#include "common/common-target.h" 56#include "langhooks.h" 57#include "gimplify.h" 58#include "gimple-fold.h" 59#include "gimple-iterator.h" 60#include "gimple-ssa.h" 61#include "builtins.h" 62#include "tree-vector-builder.h" 63#if TARGET_XCOFF 64#include "xcoffout.h" /* get declarations of xcoff_*_section_name */ 65#endif 66#include "ppc-auxv.h" 67#include "tree-ssa-propagate.h" 68#include "tree-vrp.h" 69#include "tree-ssanames.h" 70#include "targhooks.h" 71#include "opts.h" 72 73#include "rs6000-internal.h" 74 75#if TARGET_MACHO 76#include "gstab.h" /* for N_SLINE */ 77#include "dbxout.h" /* dbxout_ */ 78#endif 79 80#ifndef TARGET_PROFILE_KERNEL 81#define TARGET_PROFILE_KERNEL 0 82#endif 83 84#ifdef HAVE_AS_GNU_ATTRIBUTE 85# ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 86# define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0 87# endif 88#endif 89 90#ifndef TARGET_NO_PROTOTYPE 91#define TARGET_NO_PROTOTYPE 0 92#endif 93 94struct builtin_compatibility 95{ 96 const enum rs6000_builtins code; 97 const char *const name; 98}; 99 100struct builtin_description 101{ 102 const HOST_WIDE_INT mask; 103 const enum insn_code icode; 104 const char *const name; 105 const enum rs6000_builtins code; 106}; 107 108/* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */ 109static const struct 110{ 111 const char *cpu; 112 unsigned int cpuid; 113} cpu_is_info[] = { 114 { "power10", PPC_PLATFORM_POWER10 }, 115 { "power9", PPC_PLATFORM_POWER9 }, 116 { "power8", PPC_PLATFORM_POWER8 }, 117 { "power7", PPC_PLATFORM_POWER7 }, 118 { "power6x", PPC_PLATFORM_POWER6X }, 119 { "power6", PPC_PLATFORM_POWER6 }, 120 { "power5+", PPC_PLATFORM_POWER5_PLUS }, 121 { "power5", PPC_PLATFORM_POWER5 }, 122 { "ppc970", PPC_PLATFORM_PPC970 }, 123 { "power4", PPC_PLATFORM_POWER4 }, 124 { "ppca2", PPC_PLATFORM_PPCA2 }, 125 { "ppc476", PPC_PLATFORM_PPC476 }, 126 { "ppc464", PPC_PLATFORM_PPC464 }, 127 { "ppc440", PPC_PLATFORM_PPC440 }, 128 { "ppc405", PPC_PLATFORM_PPC405 }, 129 { "ppc-cell-be", PPC_PLATFORM_CELL_BE } 130}; 131 132/* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */ 133static const struct 134{ 135 const char *hwcap; 136 int mask; 137 unsigned int id; 138} cpu_supports_info[] = { 139 /* AT_HWCAP masks. */ 140 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 }, 141 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 }, 142 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 }, 143 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 }, 144 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 }, 145 { "booke", PPC_FEATURE_BOOKE, 0 }, 146 { "cellbe", PPC_FEATURE_CELL_BE, 0 }, 147 { "dfp", PPC_FEATURE_HAS_DFP, 0 }, 148 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 }, 149 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 }, 150 { "fpu", PPC_FEATURE_HAS_FPU, 0 }, 151 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 }, 152 { "mmu", PPC_FEATURE_HAS_MMU, 0 }, 153 { "notb", PPC_FEATURE_NO_TB, 0 }, 154 { "pa6t", PPC_FEATURE_PA6T, 0 }, 155 { "power4", PPC_FEATURE_POWER4, 0 }, 156 { "power5", PPC_FEATURE_POWER5, 0 }, 157 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 }, 158 { "power6x", PPC_FEATURE_POWER6_EXT, 0 }, 159 { "ppc32", PPC_FEATURE_32, 0 }, 160 { "ppc601", PPC_FEATURE_601_INSTR, 0 }, 161 { "ppc64", PPC_FEATURE_64, 0 }, 162 { "ppcle", PPC_FEATURE_PPC_LE, 0 }, 163 { "smt", PPC_FEATURE_SMT, 0 }, 164 { "spe", PPC_FEATURE_HAS_SPE, 0 }, 165 { "true_le", PPC_FEATURE_TRUE_LE, 0 }, 166 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 }, 167 { "vsx", PPC_FEATURE_HAS_VSX, 0 }, 168 169 /* AT_HWCAP2 masks. */ 170 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 }, 171 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 }, 172 { "ebb", PPC_FEATURE2_HAS_EBB, 1 }, 173 { "htm", PPC_FEATURE2_HAS_HTM, 1 }, 174 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 }, 175 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 }, 176 { "isel", PPC_FEATURE2_HAS_ISEL, 1 }, 177 { "tar", PPC_FEATURE2_HAS_TAR, 1 }, 178 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 }, 179 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 }, 180 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 }, 181 { "darn", PPC_FEATURE2_DARN, 1 }, 182 { "scv", PPC_FEATURE2_SCV, 1 }, 183 { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 }, 184 { "mma", PPC_FEATURE2_MMA, 1 }, 185}; 186 187static void altivec_init_builtins (void); 188static tree builtin_function_type (machine_mode, machine_mode, 189 machine_mode, machine_mode, 190 enum rs6000_builtins, const char *name); 191static void rs6000_common_init_builtins (void); 192static void htm_init_builtins (void); 193static void mma_init_builtins (void); 194 195 196/* Hash table to keep track of the argument types for builtin functions. */ 197 198struct GTY((for_user)) builtin_hash_struct 199{ 200 tree type; 201 machine_mode mode[4]; /* return value + 3 arguments. */ 202 unsigned char uns_p[4]; /* and whether the types are unsigned. */ 203}; 204 205struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct> 206{ 207 static hashval_t hash (builtin_hash_struct *); 208 static bool equal (builtin_hash_struct *, builtin_hash_struct *); 209}; 210 211static GTY (()) hash_table<builtin_hasher> *builtin_hash_table; 212 213/* Hash function for builtin functions with up to 3 arguments and a return 214 type. */ 215hashval_t 216builtin_hasher::hash (builtin_hash_struct *bh) 217{ 218 unsigned ret = 0; 219 int i; 220 221 for (i = 0; i < 4; i++) 222 { 223 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]); 224 ret = (ret * 2) + bh->uns_p[i]; 225 } 226 227 return ret; 228} 229 230/* Compare builtin hash entries H1 and H2 for equivalence. */ 231bool 232builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2) 233{ 234 return ((p1->mode[0] == p2->mode[0]) 235 && (p1->mode[1] == p2->mode[1]) 236 && (p1->mode[2] == p2->mode[2]) 237 && (p1->mode[3] == p2->mode[3]) 238 && (p1->uns_p[0] == p2->uns_p[0]) 239 && (p1->uns_p[1] == p2->uns_p[1]) 240 && (p1->uns_p[2] == p2->uns_p[2]) 241 && (p1->uns_p[3] == p2->uns_p[3])); 242} 243 244 245/* Table that classifies rs6000 builtin functions (pure, const, etc.). */ 246#undef RS6000_BUILTIN_0 247#undef RS6000_BUILTIN_1 248#undef RS6000_BUILTIN_2 249#undef RS6000_BUILTIN_3 250#undef RS6000_BUILTIN_A 251#undef RS6000_BUILTIN_D 252#undef RS6000_BUILTIN_H 253#undef RS6000_BUILTIN_M 254#undef RS6000_BUILTIN_P 255#undef RS6000_BUILTIN_X 256 257#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ 258 { NAME, ICODE, MASK, ATTR }, 259 260#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ 261 { NAME, ICODE, MASK, ATTR }, 262 263#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \ 264 { NAME, ICODE, MASK, ATTR }, 265 266#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \ 267 { NAME, ICODE, MASK, ATTR }, 268 269#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \ 270 { NAME, ICODE, MASK, ATTR }, 271 272#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ 273 { NAME, ICODE, MASK, ATTR }, 274 275#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ 276 { NAME, ICODE, MASK, ATTR }, 277 278#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \ 279 { NAME, ICODE, MASK, ATTR }, 280 281#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ 282 { NAME, ICODE, MASK, ATTR }, 283 284#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \ 285 { NAME, ICODE, MASK, ATTR }, 286 287struct rs6000_builtin_info_type { 288 const char *name; 289 const enum insn_code icode; 290 const HOST_WIDE_INT mask; 291 const unsigned attr; 292}; 293 294static const struct rs6000_builtin_info_type rs6000_builtin_info[] = 295{ 296#include "rs6000-builtin.def" 297}; 298 299#undef RS6000_BUILTIN_0 300#undef RS6000_BUILTIN_1 301#undef RS6000_BUILTIN_2 302#undef RS6000_BUILTIN_3 303#undef RS6000_BUILTIN_A 304#undef RS6000_BUILTIN_D 305#undef RS6000_BUILTIN_H 306#undef RS6000_BUILTIN_M 307#undef RS6000_BUILTIN_P 308#undef RS6000_BUILTIN_X 309 310const struct altivec_builtin_types altivec_overloaded_builtins[] = { 311 /* Unary AltiVec/VSX builtins. */ 312 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI, 313 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 314 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI, 315 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 316 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, 317 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 318 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, 319 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 320 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, 321 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 322 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, 323 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 324 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI, 325 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 326 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI, 327 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 328 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI, 329 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 330 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP, 331 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 332 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP, 333 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 334 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP, 335 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 336 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM, 337 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 338 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM, 339 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 340 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP, 341 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 342 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 343 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 }, 344 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 345 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 }, 346 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 347 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 }, 348 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 349 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 }, 350 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 351 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 }, 352 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 353 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 }, 354 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 355 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 }, 356 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 357 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 }, 358 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 359 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, 360 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 361 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, 362 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, 363 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 364 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, 365 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 366 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, 367 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 368 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, 369 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 370 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, 371 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 372 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, 373 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 374 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, 375 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 376 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF, 377 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 378 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, 379 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 380 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, 381 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 382 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, 383 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 384 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, 385 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 386 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 387 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 388 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 389 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 390 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 391 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 392 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 393 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 394 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 395 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 396 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 397 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 398 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, 399 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 400 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF, 401 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 402 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 403 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 404 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 405 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 406 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 407 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 408 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 409 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 410 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 411 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 412 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 413 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 414 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 415 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 416 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 417 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 418 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 419 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 420 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 421 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 422 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, 423 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 424 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 425 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 426 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 427 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 428 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 429 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 430 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 431 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 432 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF, 433 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 434 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 435 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 436 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 437 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 438 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 439 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 440 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 441 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 442 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 443 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 444 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 445 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 446 447 /* Binary AltiVec/VSX builtins. */ 448 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 449 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 450 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 451 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 452 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 453 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 454 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 456 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 457 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 458 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 459 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 460 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 461 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 462 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 463 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 464 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 465 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 466 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 467 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 468 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 469 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 470 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 471 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 472 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 473 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 474 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 475 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 476 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 477 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 478 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 479 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 480 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 481 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 482 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 484 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 485 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 486 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 487 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 488 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 489 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 490 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 492 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 493 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 494 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 496 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, 497 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 498 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, 499 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 500 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 501 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 502 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 503 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 504 RS6000_BTI_unsigned_V1TI, 0 }, 505 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, 506 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 507 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 508 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 509 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 510 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 511 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 512 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 513 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 514 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 515 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 516 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 517 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 518 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 519 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 520 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 521 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 522 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 523 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 524 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 525 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 526 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 527 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 528 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 529 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 530 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 531 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 532 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 533 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 534 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 535 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 536 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 537 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 538 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 539 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 540 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 541 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 542 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 543 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 544 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 545 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 546 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 547 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 548 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 549 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 550 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 551 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 552 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 553 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 554 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 555 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, 556 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 557 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, 558 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 559 RS6000_BTI_unsigned_V4SI, 0 }, 560 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, 561 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 562 RS6000_BTI_unsigned_V1TI, 0 }, 563 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, 564 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 565 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, 566 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 567 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 568 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, 569 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 570 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 571 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 572 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 573 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 574 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 575 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 576 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 577 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 578 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 579 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 580 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 581 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 582 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 583 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 584 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 585 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 586 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 587 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 588 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 589 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 590 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 591 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 592 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 593 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 594 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 595 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 596 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 597 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 598 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 599 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 600 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 601 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 602 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 603 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 604 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 605 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 606 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 607 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 608 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 609 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 610 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 611 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 612 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 613 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 614 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 615 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 616 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 617 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 618 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 619 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 620 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 621 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 622 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 623 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 624 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 625 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 626 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 627 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 628 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 629 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 630 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 631 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 632 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 634 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 635 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 636 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 637 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 638 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 639 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 640 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 641 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 642 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 643 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 644 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 645 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 646 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 647 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 648 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 649 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 650 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 651 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 652 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 653 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 654 655 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, 656 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 657 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, 658 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 659 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, 660 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 661 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, 662 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 663 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, 664 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 665 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, 666 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 667 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, 668 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 669 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, 670 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 671 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, 672 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 673 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, 674 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 675 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, 676 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 677 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, 678 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 679 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, 680 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 681 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, 682 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 683 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, 684 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 685 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, 686 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 687 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, 688 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 689 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, 690 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 691 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, 692 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 693 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, 694 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 695 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, 696 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 697 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, 698 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 699 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, 700 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 701 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, 702 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 703 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, 704 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 705 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, 706 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 707 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, 708 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 709 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, 710 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 711 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, 712 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 713 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, 714 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 715 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, 716 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 717 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, 718 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 719 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, 720 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 721 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, 722 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 723 724 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, 725 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 726 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, 727 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 728 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, 729 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 730 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, 731 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 732 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, 733 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 734 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, 735 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 736 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, 737 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 738 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, 739 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 740 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, 741 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 742 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, 743 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 744 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, 745 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 746 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, 747 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 748 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, 749 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 750 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, 751 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 752 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, 753 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 754 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, 755 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 756 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, 757 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 758 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, 759 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 760 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, 761 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 762 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, 763 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 764 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, 765 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 766 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, 767 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 768 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, 769 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 770 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, 771 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 772 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, 773 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 774 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, 775 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 776 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, 777 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 778 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, 779 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 780 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, 781 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 782 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, 783 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 784 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, 785 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 786 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, 787 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 788 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, 789 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 790 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, 791 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 792 793 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, 794 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 795 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, 796 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 797 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH, 798 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 799 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH, 800 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 801 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW, 802 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 803 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW, 804 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 805 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW, 806 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 807 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW, 808 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 809 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH, 810 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 811 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH, 812 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 813 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB, 814 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 815 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB, 816 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 817 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP, 818 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 819 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 820 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 821 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 822 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 823 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 824 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 825 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 826 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 827 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 828 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 829 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 830 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 831 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 832 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 833 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 834 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 835 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 836 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 837 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 838 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 839 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 840 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 841 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 842 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 843 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, 844 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 845 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, 846 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 847 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP, 848 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 849 850 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 851 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 852 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 853 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 854 855 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 856 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 857 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 858 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 859 860 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 861 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 862 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 863 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 864 865 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP, 866 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 867 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP, 868 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 869 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI, 870 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, 871 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI, 872 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 873 RS6000_BTI_unsigned_V16QI, 0}, 874 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI, 875 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, 876 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI, 877 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 878 RS6000_BTI_unsigned_V8HI, 0}, 879 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI, 880 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, 881 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI, 882 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 883 RS6000_BTI_unsigned_V4SI, 0}, 884 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI, 885 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, 886 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI, 887 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 888 RS6000_BTI_unsigned_V2DI, 0}, 889 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB, 890 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 891 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB, 892 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 893 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH, 894 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 895 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH, 896 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 897 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW, 898 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 899 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, 900 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 901 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, 902 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 903 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, 904 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 905 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, 906 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 907 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, 908 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 909 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, 910 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 911 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, 912 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 913 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, 914 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 915 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, 916 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 917 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, 918 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 919 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, 920 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 921 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, 922 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 923 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, 924 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 925 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, 926 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 927 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI, 928 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, 929 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI, 930 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 931 RS6000_BTI_unsigned_V16QI, 0}, 932 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI, 933 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, 934 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI, 935 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 936 RS6000_BTI_unsigned_V8HI, 0}, 937 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI, 938 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, 939 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI, 940 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 941 RS6000_BTI_unsigned_V4SI, 0}, 942 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI, 943 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, 944 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI, 945 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 946 RS6000_BTI_unsigned_V2DI, 0}, 947 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB, 948 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 949 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB, 950 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 951 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH, 952 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 953 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH, 954 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 955 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW, 956 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 957 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, 958 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 959 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, 960 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 961 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, 962 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 963 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, 964 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 965 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, 966 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 967 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP, 968 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 969 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF, 970 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 971 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX, 972 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 973 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, 974 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 975 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, 976 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, 977 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, 978 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, 979 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, 980 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 981 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, 982 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 983 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, 984 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 985 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, 986 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 987 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, 988 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 989 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, 990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 991 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, 992 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 993 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, 994 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 995 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, 996 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 997 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, 998 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 999 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, 1000 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, 1001 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, 1002 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1003 1004 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI, 1005 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1006 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI, 1007 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1008 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF, 1009 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1010 1011 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI, 1012 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1013 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI, 1014 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1015 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF, 1016 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1017 1018 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI, 1019 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1020 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI, 1021 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1022 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF, 1023 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1024 1025 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI, 1026 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1027 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI, 1028 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1029 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF, 1030 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1031 1032 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, 1033 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, 1034 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, 1035 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1036 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF, 1037 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1038 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI, 1039 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1040 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI, 1041 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 1042 RS6000_BTI_unsigned_V2DI, 0 }, 1043 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, 1044 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1045 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, 1046 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, 1047 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI, 1048 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1049 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF, 1050 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1051 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, 1052 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, 1053 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, 1054 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1055 1056 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1057 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, 1058 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1059 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 }, 1060 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1061 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 1062 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1063 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 1064 1065 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1066 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1067 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1068 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1069 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1070 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1071 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1072 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1073 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1074 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1075 ~RS6000_BTI_unsigned_V2DI, 0 }, 1076 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1077 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1078 ~RS6000_BTI_unsigned_long_long, 0 }, 1079 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1080 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1081 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1082 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1083 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1084 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1085 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1086 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1087 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1088 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1089 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1090 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1091 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1092 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1093 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1094 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1095 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1096 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1097 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1098 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1099 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1100 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1101 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1102 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1103 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1104 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1105 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1106 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1107 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1108 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1109 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1110 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1111 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1112 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1113 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1114 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1115 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1116 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1117 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1118 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1119 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1120 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1121 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1122 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1123 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1124 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1125 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1126 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1127 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1128 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1129 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1130 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1131 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1132 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1133 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1134 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1135 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1136 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1137 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1138 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1139 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1140 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1141 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1142 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1143 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1144 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1145 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1146 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1147 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1148 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1149 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1150 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1151 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1152 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1153 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1154 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1155 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1156 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1157 1158 /* vector float vec_ldl (int, vector float *); 1159 vector float vec_ldl (int, float *); */ 1160 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1161 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1162 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1163 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1164 1165 /* vector bool int vec_ldl (int, vector bool int *); 1166 vector bool int vec_ldl (int, bool int *); 1167 vector int vec_ldl (int, vector int *); 1168 vector int vec_ldl (int, int *); 1169 vector unsigned int vec_ldl (int, vector unsigned int *); 1170 vector unsigned int vec_ldl (int, unsigned int *); */ 1171 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1172 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1173 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1174 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 }, 1175 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1176 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1177 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1178 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1179 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1180 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1181 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1182 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1183 1184 /* vector bool short vec_ldl (int, vector bool short *); 1185 vector bool short vec_ldl (int, bool short *); 1186 vector pixel vec_ldl (int, vector pixel *); 1187 vector short vec_ldl (int, vector short *); 1188 vector short vec_ldl (int, short *); 1189 vector unsigned short vec_ldl (int, vector unsigned short *); 1190 vector unsigned short vec_ldl (int, unsigned short *); */ 1191 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1192 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1193 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1194 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 }, 1195 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1196 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1197 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1198 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1199 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1200 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1201 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1202 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1203 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1204 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1205 1206 /* vector bool char vec_ldl (int, vector bool char *); 1207 vector bool char vec_ldl (int, bool char *); 1208 vector char vec_ldl (int, vector char *); 1209 vector char vec_ldl (int, char *); 1210 vector unsigned char vec_ldl (int, vector unsigned char *); 1211 vector unsigned char vec_ldl (int, unsigned char *); */ 1212 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1213 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1214 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1215 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 }, 1216 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1217 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1218 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1219 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1220 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1221 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1222 ~RS6000_BTI_unsigned_V16QI, 0 }, 1223 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1224 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1225 1226 /* vector double vec_ldl (int, vector double *); 1227 vector double vec_ldl (int, double *); */ 1228 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1229 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1230 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1231 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1232 1233 /* vector long long vec_ldl (int, vector long long *); 1234 vector long long vec_ldl (int, long long *); 1235 vector unsigned long long vec_ldl (int, vector unsigned long long *); 1236 vector unsigned long long vec_ldl (int, unsigned long long *); 1237 vector bool long long vec_ldl (int, vector bool long long *); 1238 vector bool long long vec_ldl (int, bool long long *); */ 1239 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1240 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1241 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1242 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1243 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1244 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1245 ~RS6000_BTI_unsigned_V2DI, 0 }, 1246 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1247 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1248 ~RS6000_BTI_unsigned_long_long, 0 }, 1249 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1250 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1251 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1252 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 }, 1253 1254 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1255 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1256 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1258 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1259 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1260 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1261 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1262 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1263 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1264 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1265 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1266 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1267 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1268 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1269 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1270 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1271 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1272 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1274 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1275 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1276 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1277 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1278 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1279 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1280 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1281 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1282 ~RS6000_BTI_unsigned_long_long, 0 }, 1283 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1284 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1285 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1286 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1287 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1288 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1289 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1290 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1291 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1292 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1293 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1294 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1295 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1296 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1297 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1298 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1299 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1300 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1301 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1302 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1303 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1304 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1305 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1306 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1307 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1308 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1309 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1310 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1311 ~RS6000_BTI_unsigned_long_long, 0 }, 1312 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1313 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1314 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1315 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1316 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1317 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1318 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1319 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1320 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1321 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1322 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1323 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1324 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1325 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1326 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1327 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1328 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1329 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1330 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1331 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1332 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1333 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1334 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1335 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1336 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1337 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1338 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1339 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1340 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1341 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1342 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1343 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1344 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1345 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1346 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1347 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1348 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1349 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1350 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1351 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1352 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1353 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1354 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1355 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1356 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1357 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1358 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1359 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1360 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1361 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1362 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1363 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1364 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1365 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1366 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1367 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1368 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1369 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1370 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1371 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1372 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1373 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1374 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1375 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1376 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1377 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1378 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1379 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1380 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1381 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1382 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1383 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1384 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1385 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1386 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1387 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1388 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1389 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1390 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1391 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1392 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1393 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1394 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1395 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1396 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1397 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1398 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1399 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1400 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1401 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1402 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1403 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1404 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1405 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1406 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1407 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1408 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1409 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1410 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1411 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1412 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1413 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1414 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1415 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1416 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1417 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1418 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1419 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1420 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1421 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1422 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1423 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1424 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1425 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1426 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1427 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1428 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1429 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1430 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1431 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1432 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1433 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1434 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1435 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1436 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1437 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1438 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1439 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1440 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1441 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1442 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1443 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1444 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1445 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1446 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1447 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1448 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1449 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1450 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1451 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1452 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1453 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1454 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1456 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1457 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1458 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1459 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1460 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1461 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1462 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1463 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1464 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1465 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1466 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1467 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1468 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1469 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1470 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1471 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1472 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1473 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1474 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1475 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1476 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1477 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1478 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1479 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1480 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1481 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1482 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1484 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1485 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1486 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1487 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1488 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1489 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1490 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1491 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1492 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1493 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1494 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1496 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1497 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1498 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1499 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1500 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1501 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1502 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1503 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1504 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, 1505 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1506 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, 1507 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1508 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP, 1509 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1510 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1511 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1512 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1513 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1514 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1515 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1516 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1517 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1518 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1519 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1520 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1521 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1522 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1523 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1524 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1525 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1526 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1527 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1528 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1529 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1530 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1531 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1532 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1533 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1534 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1535 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 1536 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1537 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1538 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1539 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1540 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1541 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1542 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1543 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1544 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1545 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1546 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1547 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1548 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1550 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1551 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1552 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1553 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1554 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1555 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1556 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1557 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1558 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1559 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1560 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1561 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1562 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1563 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1564 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1565 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1566 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1567 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1568 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1569 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1570 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1571 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1572 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1573 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1574 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1575 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1576 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1577 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1578 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1579 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1580 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF, 1581 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1582 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1583 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1584 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1585 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1586 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1587 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1588 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1589 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1590 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1591 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1592 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1593 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1594 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1595 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1596 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1597 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1598 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1599 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1600 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1601 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1602 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1603 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1604 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1605 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1606 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1607 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1608 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1609 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1610 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1611 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1612 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1613 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1614 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1615 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1616 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1617 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1618 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1619 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1620 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1621 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1622 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1623 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1624 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1625 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1626 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1627 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1628 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1629 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1630 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1631 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1632 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1633 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1634 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1635 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1636 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1637 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1638 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1639 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1640 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF, 1641 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1642 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1643 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1644 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1645 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1646 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1647 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1648 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1649 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1650 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1651 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1652 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1653 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1654 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1655 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1656 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1657 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1658 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1659 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1660 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1661 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1662 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1663 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1664 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1665 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1666 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1667 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1668 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1669 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1670 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1671 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1672 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1673 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1674 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1675 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1676 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1677 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1678 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1679 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1680 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1681 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1682 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1683 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1684 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1685 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1686 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1687 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1688 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1689 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1690 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1691 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1692 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1693 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1694 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1695 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1696 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1697 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1698 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1699 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1700 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1701 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1702 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1703 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1704 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1705 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1706 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1707 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1708 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1709 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1710 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1711 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1712 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1713 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1714 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1715 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1716 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1717 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1718 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1719 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1720 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1721 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1722 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1723 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1724 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1725 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1726 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, 1727 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1728 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, 1729 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1730 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP, 1731 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1732 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1733 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1734 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1735 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1736 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1737 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1738 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1739 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1740 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1741 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1742 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1743 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1744 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1745 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1746 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1747 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1748 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1749 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1750 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1751 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1752 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1753 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1754 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1755 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1756 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1757 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1758 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1759 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1760 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1761 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1762 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 1764 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1765 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1766 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1767 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1768 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1769 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1770 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1771 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1772 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1773 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1774 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1776 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1777 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1778 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1779 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1780 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, 1781 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1782 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, 1783 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1784 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, 1785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1786 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, 1787 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1788 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW, 1789 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1790 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW, 1791 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 1792 RS6000_BTI_unsigned_V4SI, 0 }, 1793 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, 1794 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1795 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, 1796 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1797 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, 1798 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1799 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, 1800 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1801 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW, 1802 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1803 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW, 1804 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1805 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, 1806 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1807 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, 1808 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1809 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, 1810 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1811 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW, 1812 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1813 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW, 1814 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 1815 RS6000_BTI_unsigned_V4SI, 0 }, 1816 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, 1817 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1818 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, 1819 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1820 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH, 1821 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1822 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, 1823 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1824 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, 1825 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1826 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW, 1827 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1828 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW, 1829 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1830 1831 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI, 1832 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 1833 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI, 1834 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 1835 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI, 1836 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 1837 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI, 1838 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 1839 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF, 1840 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 1841 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP, 1842 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 1843 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, 1844 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 1845 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, 1846 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 1847 1848 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF, 1849 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1850 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF, 1851 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1852 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, 1853 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1854 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, 1855 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1856 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, 1857 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1858 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, 1859 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1860 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, 1861 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1862 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, 1863 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1864 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, 1865 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1866 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI, 1867 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1868 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, 1869 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1870 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, 1871 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1872 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI, 1873 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1874 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, 1875 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1876 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, 1877 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1878 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI, 1879 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1880 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, 1881 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1882 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, 1883 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1884 1885 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, 1886 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1887 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, 1888 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 1889 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, 1890 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 1891 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, 1892 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1893 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, 1894 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 1895 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, 1896 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 1897 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, 1898 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1899 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, 1900 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1901 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, 1902 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1903 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, 1904 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1905 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, 1906 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1907 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, 1908 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1909 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, 1910 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1911 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, 1912 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1913 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, 1914 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1915 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, 1916 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1917 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, 1918 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1919 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, 1920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1921 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, 1922 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1923 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, 1924 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1925 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, 1926 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1927 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, 1928 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1929 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, 1930 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1931 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, 1932 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1933 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, 1934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1935 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, 1936 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1937 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, 1938 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1939 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, 1940 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1941 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, 1942 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1943 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, 1944 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1945 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, 1946 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1947 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, 1948 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1949 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, 1950 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1951 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, 1952 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1953 1954 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 1955 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1956 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 1957 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1958 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 1959 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1960 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 1961 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1962 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 1963 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1964 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 1965 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1966 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 1967 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1968 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 1969 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1970 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 1971 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1972 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF, 1973 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1974 1975 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI, 1976 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 1977 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI, 1978 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 1979 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI, 1980 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 1981 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI, 1982 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 1983 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF, 1984 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 1985 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF, 1986 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 1987 1988 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, 1989 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1990 { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16, 1991 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1992 1993 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, 1994 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1995 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, 1996 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1997 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, 1998 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1999 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, 2000 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2001 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, 2002 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2003 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, 2004 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2005 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, 2006 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2007 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, 2008 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2009 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, 2010 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2011 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, 2012 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2013 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, 2014 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2015 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, 2016 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2017 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, 2018 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2019 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, 2020 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2021 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, 2022 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2023 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, 2024 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2025 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, 2026 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2027 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, 2028 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2029 2030 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2031 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, 2032 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2033 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2034 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI, 2035 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2036 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2037 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, 2038 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2039 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2040 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, 2041 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2042 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2043 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, 2044 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2045 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2046 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, 2047 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2048 2049 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2050 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2051 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2052 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2053 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2054 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2055 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2056 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2057 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2058 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2059 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2060 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2061 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX, 2062 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2063 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS, 2064 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2065 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS, 2066 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2067 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS, 2068 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2069 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, 2070 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2071 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, 2072 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2073 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, 2074 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2075 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, 2076 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2077 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, 2078 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2079 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, 2080 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2081 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, 2082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2083 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS, 2084 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2085 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS, 2086 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2087 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS, 2088 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2089 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, 2090 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2091 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2092 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2093 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS, 2094 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2095 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, 2096 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2097 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, 2098 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2099 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC, 2100 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2101 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC, 2102 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2103 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2104 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2105 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2106 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2107 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2108 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2109 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2110 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2111 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2112 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2113 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2114 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2115 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2116 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2117 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2118 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2119 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2120 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2121 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2122 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2123 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2124 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2125 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2126 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2127 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2128 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2129 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2130 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2131 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI, 2132 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 2133 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 2134 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI, 2135 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 2136 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 2137 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM, 2138 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 2139 RS6000_BTI_unsigned_V4SI, 0 }, 2140 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM, 2141 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 2142 RS6000_BTI_unsigned_V2DI, 0 }, 2143 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2144 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2145 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2146 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2147 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2148 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2149 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2150 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2151 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2152 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2153 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2154 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2155 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2156 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2157 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2158 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2159 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, 2160 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2161 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, 2162 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2163 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2164 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2165 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2166 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2167 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2168 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2169 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2170 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2171 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2172 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2173 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2174 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2175 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2176 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2177 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2178 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2179 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2180 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2181 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2182 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2183 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2184 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2185 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2186 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2187 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2188 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2189 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2190 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2191 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2192 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2193 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2194 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2195 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2196 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2197 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2198 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2199 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2200 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2201 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2202 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2203 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2204 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2205 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2206 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2207 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2208 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2209 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2210 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2211 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2212 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2213 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2214 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2215 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2216 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2217 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2218 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2219 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2220 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2221 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2222 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2223 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2224 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2225 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2226 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2227 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2228 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2229 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2230 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2231 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2232 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2233 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2234 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2235 2236 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2237 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2238 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2239 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2240 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2241 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2242 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2243 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2244 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2245 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 }, 2246 2247 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2248 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2249 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2250 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2251 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2252 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2253 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2254 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2255 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2256 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2257 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2258 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2259 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2260 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2261 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2262 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2263 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2264 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2265 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2266 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2267 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2268 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2269 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2270 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2271 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2272 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2273 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2274 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2275 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2276 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2277 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2278 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2279 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2280 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, 2281 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2282 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2283 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2284 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, 2285 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2286 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2287 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2288 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2289 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2290 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2291 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2292 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2293 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2294 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2295 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2296 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2297 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2298 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2299 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2300 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2301 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2302 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2303 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2304 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2305 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2306 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2307 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2308 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2309 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, 2310 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 2311 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2312 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, 2313 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2314 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, 2315 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2316 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, 2317 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2318 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2319 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2320 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2321 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2322 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2323 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2324 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2325 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2326 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2327 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2328 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2329 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2330 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2331 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2332 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2333 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2334 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2335 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2336 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2337 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2338 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2339 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2340 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2341 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2342 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2343 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2344 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2345 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2346 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2347 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2348 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2349 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2350 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2351 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2352 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2353 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2354 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2355 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2356 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2357 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2358 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2359 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2360 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2361 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2362 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2363 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2364 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2365 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2366 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2367 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2368 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2369 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2370 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2371 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2372 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2373 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2374 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2375 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2376 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2377 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2378 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2379 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2380 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2381 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2382 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2383 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2384 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2385 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2386 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2387 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2388 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2389 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2390 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2391 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2392 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2393 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2395 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2396 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2397 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2398 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2399 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2400 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2401 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2402 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2403 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2404 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2405 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2406 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2407 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2408 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2409 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2410 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2411 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2412 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2413 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2414 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2415 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2416 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2417 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2418 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2419 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2420 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2421 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2422 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2423 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2424 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2425 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2426 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2427 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2428 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2429 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2430 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2431 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2432 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2433 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2434 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2435 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2436 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2437 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2438 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2439 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2440 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2441 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2442 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2443 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2444 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2445 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2446 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2447 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2448 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2449 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2450 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2451 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2452 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2453 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2454 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2455 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2456 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2457 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2458 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2459 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2460 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2461 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2462 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2463 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2464 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2465 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2466 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2467 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2468 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2469 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2470 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2471 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2472 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2473 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2474 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2475 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2476 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2477 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2478 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2479 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2480 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2481 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2482 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2483 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2484 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2485 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2486 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2487 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2488 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2489 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2490 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2491 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2492 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, 2493 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2494 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2495 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2496 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, 2497 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2498 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2499 2500 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2501 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2502 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2503 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2504 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2505 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2506 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2507 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2508 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2509 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2510 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2511 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2512 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2513 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2514 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2515 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2516 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2517 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2518 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2519 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2520 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2521 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2522 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2523 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2524 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2525 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2526 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2527 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2528 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2529 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2530 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2531 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2532 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2533 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2534 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2535 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2536 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2537 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2538 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2539 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2540 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2541 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2542 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2543 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2544 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2545 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2546 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2547 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2548 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, 2549 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2550 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, 2551 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2552 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 2553 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 2554 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 2555 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 2556 RS6000_BTI_unsigned_V1TI, 0 }, 2557 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, 2558 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2559 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2560 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2561 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2562 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2563 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2564 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2565 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2566 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2567 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2568 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2569 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2570 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2571 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2572 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 2573 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2574 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2575 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2576 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2577 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2578 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2579 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2580 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2581 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2582 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2583 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2584 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2585 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2586 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2587 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2588 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2589 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2590 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2591 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2592 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2593 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2594 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2595 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2596 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2597 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2598 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2599 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2600 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2601 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2602 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2603 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2605 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2606 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2607 2608 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, 2609 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2610 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, 2611 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2612 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, 2613 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 2614 RS6000_BTI_unsigned_V1TI, 0 }, 2615 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, 2616 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 2617 2618 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2619 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2620 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2621 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2622 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2623 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2624 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2625 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2626 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2627 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2628 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2629 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2630 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2631 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2632 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2634 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2635 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2636 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2637 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2638 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2639 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2640 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2641 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2642 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2643 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2644 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2645 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2646 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2647 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2648 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2649 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2650 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2651 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2652 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2653 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2654 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2655 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2656 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2657 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2658 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2659 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2660 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2661 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2662 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2663 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 2664 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2665 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2666 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2667 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2668 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2669 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2670 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2671 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2672 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2673 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2674 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2675 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2676 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2677 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2678 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2679 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2680 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2681 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2682 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2683 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2684 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2685 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2686 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2687 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2688 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2689 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2690 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2691 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2692 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2693 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2694 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2695 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2696 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2697 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2698 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2699 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2700 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2701 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2702 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS, 2703 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2704 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS, 2705 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 2706 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS, 2707 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 2708 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS, 2709 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 2710 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS, 2711 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 2712 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS, 2713 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2714 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS, 2715 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2716 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, 2717 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2718 2719 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, 2720 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 2721 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, 2722 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 2723 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 2724 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 2725 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 2726 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, 2727 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 2728 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 2729 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2730 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 2731 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2732 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 2733 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2734 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 2735 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2736 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 2737 ~RS6000_BTI_unsigned_V2DI, 0 }, 2738 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2739 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 2740 ~RS6000_BTI_unsigned_long_long, 0 }, 2741 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 2742 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 2743 2744 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, 2745 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 2746 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, 2747 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 2748 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 2749 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 2750 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 2751 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 2752 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 2753 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 2754 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 2755 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 2756 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 2757 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 2758 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 2759 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 2760 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 2761 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 2762 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 2763 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 2764 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 2765 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 2766 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 2767 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 2768 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 2769 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 2770 ~RS6000_BTI_unsigned_V16QI, 0 }, 2771 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 2772 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 2773 2774 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, 2775 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 2776 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, 2777 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 2778 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, 2779 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 2780 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, 2781 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 2782 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 2783 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 2784 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 2785 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 2786 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 2787 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 2788 ~RS6000_BTI_unsigned_V2DI, 0 }, 2789 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 2790 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 2791 ~RS6000_BTI_unsigned_long_long, 0 }, 2792 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, 2793 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 2794 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, 2795 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 2796 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 2797 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 2798 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 2799 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 2800 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 2801 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 2802 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 2803 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 2804 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 2805 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 2806 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 2807 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 2808 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 2809 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 2810 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 2811 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 2812 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 2813 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 2814 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 2815 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 2816 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 2817 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 2818 ~RS6000_BTI_unsigned_V16QI, 0 }, 2819 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 2820 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 2821 2822 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, 2823 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2824 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, 2825 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 2826 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, 2827 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 2828 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, 2829 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2830 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, 2831 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 2832 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, 2833 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 2834 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, 2835 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2836 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, 2837 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2838 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, 2839 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2840 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, 2841 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2842 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, 2843 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2844 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, 2845 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2846 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, 2847 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2848 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, 2849 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2850 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, 2851 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2852 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, 2853 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2854 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, 2855 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2856 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, 2857 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2858 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, 2859 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2860 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, 2861 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2862 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, 2863 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2864 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, 2865 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2866 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, 2867 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2868 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, 2869 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2870 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, 2871 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2872 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, 2873 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2874 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, 2875 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2876 2877 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, 2878 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2879 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, 2880 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2881 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, 2882 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2883 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2884 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2885 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2886 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2887 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2888 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2889 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2890 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2891 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2892 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2893 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, 2894 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2895 2896 /* Ternary AltiVec/VSX builtins. */ 2897 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2898 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2899 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2900 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2901 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2902 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2903 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2904 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2905 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2906 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2907 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2908 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2909 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2910 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2911 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2912 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2913 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2914 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2915 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2916 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2917 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2918 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2919 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2920 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2921 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2922 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2923 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2924 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2925 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2926 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2927 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2928 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2929 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2930 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2931 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2932 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2933 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2934 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2935 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2936 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2937 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2938 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2939 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2940 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2941 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2942 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2943 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2944 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2945 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2946 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2947 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2948 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2949 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2950 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2951 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2952 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2953 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2954 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2955 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2956 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2957 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2958 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2959 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2960 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2961 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2962 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2963 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2964 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2965 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2966 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2967 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2968 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2969 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2970 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2971 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2972 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2973 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2974 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2975 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2976 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2977 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2978 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2979 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2980 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2981 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2982 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2983 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2984 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2985 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2986 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2987 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2988 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2989 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2990 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2991 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2992 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2993 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2994 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2995 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2996 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2997 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2998 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2999 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3000 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3001 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3002 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3003 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3004 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3005 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3006 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3007 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3008 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3009 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3010 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3011 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3012 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3013 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3014 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3015 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3016 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3017 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3018 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3019 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3020 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3021 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3022 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3023 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3024 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3025 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3026 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3027 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3028 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3029 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3030 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3031 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3032 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3033 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3034 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3035 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3036 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3037 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3038 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3039 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3040 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3041 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3042 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3043 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3044 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3045 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3046 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3047 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3048 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3049 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3050 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3051 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3052 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3053 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3054 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3055 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3056 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3057 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP, 3058 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3059 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP, 3060 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3061 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3062 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3063 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3064 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3065 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3066 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3067 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3068 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3069 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS, 3070 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3071 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3072 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3073 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3074 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3075 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3076 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3077 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3078 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3079 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS, 3080 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3081 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP, 3082 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3083 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP, 3084 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3085 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM, 3086 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 3087 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM, 3088 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 3089 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM, 3090 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3091 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM, 3092 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3093 3094 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM, 3095 RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V1TI }, 3096 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM, 3097 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI }, 3098 3099 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM, 3100 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3101 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM, 3102 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3103 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM, 3104 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 3105 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM, 3106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 3107 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS, 3108 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3109 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS, 3110 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3111 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS, 3112 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3113 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS, 3114 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3115 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP, 3116 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3117 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP, 3118 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3119 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP, 3120 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3121 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP, 3122 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3123 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF, 3124 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, 3125 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3126 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, 3127 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3128 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, 3129 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3130 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3131 RS6000_BTI_unsigned_V16QI }, 3132 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, 3133 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, 3134 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3135 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI }, 3136 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3137 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI }, 3138 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3139 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI }, 3140 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3141 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI }, 3142 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3143 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI }, 3144 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3145 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI }, 3146 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3147 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI }, 3148 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3149 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 3150 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3151 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3152 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3153 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3154 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3155 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3156 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3157 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3158 3159 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3160 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 3161 RS6000_BTI_bool_V16QI }, 3162 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3163 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3164 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3165 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3166 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3167 3168 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3169 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, 3170 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3171 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, 3172 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3173 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI }, 3174 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3175 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3176 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3177 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 3178 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3179 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, 3180 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3181 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 3182 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3183 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3184 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3185 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 3186 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3187 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, 3188 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3189 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3190 RS6000_BTI_bool_V2DI }, 3191 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3192 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3193 RS6000_BTI_unsigned_V2DI }, 3194 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 3195 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, 3196 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 3197 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI }, 3198 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3199 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3200 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3201 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI }, 3202 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3203 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3204 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3205 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI }, 3206 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3207 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3208 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3209 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3210 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3211 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 3212 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3213 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3214 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3215 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3216 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3217 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI }, 3218 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3219 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3220 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3221 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3222 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3223 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 3224 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3225 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3226 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3227 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3228 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3229 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 3230 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3231 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3232 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3233 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3234 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3235 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3236 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3237 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3238 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, 3239 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 3240 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3241 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 3242 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3243 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI }, 3244 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3245 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, 3246 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3247 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 3248 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3249 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, 3250 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3251 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI }, 3252 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3253 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI }, 3254 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3255 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 3256 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 3258 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3259 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI }, 3260 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, 3261 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 3262 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3263 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI }, 3264 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3265 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 3266 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3267 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, 3268 3269 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3270 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 3271 RS6000_BTI_INTSI }, 3272 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3274 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 3275 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3276 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 3277 RS6000_BTI_INTSI }, 3278 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3279 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3280 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, 3281 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3282 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 3283 RS6000_BTI_INTSI }, 3284 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3285 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3286 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, 3287 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3288 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 3289 RS6000_BTI_INTSI }, 3290 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3291 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3292 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, 3293 3294 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3295 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3296 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3297 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3298 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3299 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3300 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3301 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, 3302 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3303 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3304 ~RS6000_BTI_unsigned_V2DI }, 3305 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3306 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3307 ~RS6000_BTI_unsigned_long_long }, 3308 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3309 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3310 ~RS6000_BTI_bool_V2DI }, 3311 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3312 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3313 ~RS6000_BTI_long_long }, 3314 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3315 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3316 ~RS6000_BTI_unsigned_long_long }, 3317 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3318 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3319 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3320 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3321 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3322 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3323 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3324 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3325 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3326 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3327 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3328 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3329 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3330 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3331 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3332 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3333 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3334 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3335 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3336 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3337 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3338 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3339 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3340 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3341 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3342 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3343 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3344 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3345 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3346 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3347 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3348 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3349 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3350 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3351 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3352 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3353 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3354 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3355 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3356 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3357 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3358 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3359 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3360 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3361 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3362 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3363 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3364 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3365 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3366 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3367 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3368 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3369 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3370 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3371 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3372 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3373 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3374 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3375 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3376 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3377 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3378 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3379 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3380 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3381 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3382 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3383 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3384 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3385 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3386 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3387 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3388 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3389 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3390 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3391 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3392 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3393 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3394 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3395 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3396 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3397 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3398 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3399 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3400 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3401 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3402 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3403 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3404 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3405 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3406 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3407 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3408 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3409 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3410 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3411 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3412 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3413 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3414 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3415 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3416 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3417 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3418 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3419 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3420 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3421 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3422 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3423 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3424 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3425 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3426 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3427 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3428 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3429 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3430 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3431 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3432 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3433 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3434 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3435 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3436 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3437 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3438 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3439 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3440 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3441 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3442 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3443 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3444 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3445 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3446 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3447 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3448 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3449 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3450 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3451 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3452 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3453 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3454 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3455 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3456 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3457 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3458 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3459 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3460 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3461 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3462 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3463 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3464 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3465 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3466 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3467 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3468 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3469 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3470 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3471 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3472 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3473 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3474 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3475 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3476 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3477 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3478 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3479 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3480 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3481 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3482 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3483 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3484 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3485 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3486 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3487 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3488 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3489 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3490 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3491 ~RS6000_BTI_unsigned_V2DI }, 3492 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3493 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3494 ~RS6000_BTI_bool_V2DI }, 3495 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3496 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3497 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3498 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3499 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3500 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3501 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3502 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3503 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3504 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3505 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3506 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3507 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3508 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3509 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3510 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3511 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3512 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3513 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3514 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3515 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3516 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3517 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3518 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3519 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3520 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3521 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3522 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3523 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3524 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3525 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3526 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3527 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3528 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3529 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3530 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3531 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3532 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3533 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3534 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3535 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3536 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3537 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3538 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3539 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3540 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3541 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3542 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3543 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3544 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3545 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3546 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3547 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3548 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3549 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3550 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3551 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3552 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3553 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3554 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3555 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3556 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3557 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3558 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3559 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3560 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3561 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3562 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3563 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3564 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3565 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3566 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3567 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3568 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3569 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3570 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3571 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3572 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3573 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3574 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3575 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3576 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3577 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3578 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3579 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3580 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3581 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3582 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3583 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3584 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3585 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3586 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3587 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3588 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3589 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3590 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3591 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3592 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3593 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3594 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3595 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3596 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3597 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3598 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3599 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3600 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3601 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3602 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3603 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3604 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3605 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3606 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3607 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3608 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3609 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3610 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3611 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3612 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3613 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3614 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3615 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3616 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3617 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3618 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3619 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3620 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3621 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3622 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3623 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3624 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3625 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3626 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3627 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3628 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3629 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3630 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3631 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3632 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3633 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3634 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3635 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3636 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3637 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3638 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3639 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, 3640 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3641 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, 3642 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3643 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 3644 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3645 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 3646 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, 3647 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, 3648 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long }, 3649 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 3650 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3651 ~RS6000_BTI_unsigned_V2DI }, 3652 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 3653 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3654 ~RS6000_BTI_bool_V2DI }, 3655 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, 3656 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3657 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, 3658 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3659 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3660 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3661 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3662 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3663 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3664 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3665 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3666 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3667 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3668 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3669 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3670 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3671 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 3672 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3673 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3674 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3675 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3676 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3677 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3678 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3679 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3680 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3681 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3682 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3683 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3684 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3685 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3686 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3687 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3688 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3689 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3690 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3691 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3692 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3693 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3694 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3695 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3696 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3697 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3698 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3699 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 3700 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3701 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 3702 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3703 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, 3704 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3705 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, 3706 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3707 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, 3708 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI }, 3709 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, 3710 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI }, 3711 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 3712 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3713 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 3714 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 3715 ~RS6000_BTI_long_long }, 3716 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 3717 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3718 ~RS6000_BTI_unsigned_V2DI }, 3719 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 3720 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3721 ~RS6000_BTI_unsigned_long_long }, 3722 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, 3723 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3724 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, 3725 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3726 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 3727 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3728 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 3729 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3730 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 3731 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3732 ~RS6000_BTI_unsigned_V4SI }, 3733 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 3734 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3735 ~RS6000_BTI_UINTSI }, 3736 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 3737 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3738 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 3739 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3740 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 3741 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3742 ~RS6000_BTI_unsigned_V8HI }, 3743 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 3744 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3745 ~RS6000_BTI_UINTHI }, 3746 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 3747 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3748 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 3749 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3750 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 3751 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3752 ~RS6000_BTI_unsigned_V16QI }, 3753 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 3754 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3755 ~RS6000_BTI_UINTQI }, 3756 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 3757 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 3758 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 3759 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3760 RS6000_BTI_INTSI }, 3761 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 3762 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 3763 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 3764 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3765 RS6000_BTI_INTSI }, 3766 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 3767 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 3768 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 3769 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3770 RS6000_BTI_INTSI }, 3771 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 3772 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 3773 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 3774 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3775 RS6000_BTI_INTSI }, 3776 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, 3777 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 3778 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, 3779 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 3780 3781 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, 3782 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 3783 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 3784 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 3785 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 3786 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3787 RS6000_BTI_INTSI }, 3788 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, 3789 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 3790 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 3791 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 3792 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 3793 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3794 RS6000_BTI_INTSI }, 3795 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 3796 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 3797 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 3798 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3799 RS6000_BTI_INTSI }, 3800 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 3801 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 3802 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 3803 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3804 RS6000_BTI_INTSI }, 3805 3806 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 3807 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 3808 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 3809 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 3810 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3811 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 3812 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3813 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 3814 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3815 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 3816 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3817 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 3818 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3819 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3820 ~RS6000_BTI_unsigned_V2DI, 0 }, 3821 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3822 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 }, 3823 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3824 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 3825 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 3826 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 3827 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 3828 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 3829 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3830 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 3831 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3832 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 3833 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3834 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 3835 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3836 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 3837 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3838 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3839 ~RS6000_BTI_unsigned_V4SI, 0 }, 3840 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3841 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 3842 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3843 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3844 ~RS6000_BTI_unsigned_long, 0 }, 3845 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3846 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 3847 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3848 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 3849 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3850 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 3851 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3852 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 3853 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3854 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3855 ~RS6000_BTI_unsigned_V8HI, 0 }, 3856 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3857 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 3858 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3859 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 3860 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3861 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 3862 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3863 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 3864 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3865 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3866 ~RS6000_BTI_unsigned_V16QI, 0 }, 3867 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3868 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3869 3870 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 3871 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3872 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 3873 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3874 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3875 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI, 3876 ~RS6000_BTI_long_long }, 3877 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3878 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI, 3879 ~RS6000_BTI_unsigned_long_long }, 3880 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, 3881 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI }, 3882 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, 3883 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI }, 3884 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3885 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3886 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3887 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3888 ~RS6000_BTI_unsigned_V2DI }, 3889 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3890 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3891 ~RS6000_BTI_bool_V2DI }, 3892 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 3893 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3894 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 3895 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3896 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3897 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3898 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3899 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3900 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3901 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3902 ~RS6000_BTI_unsigned_V4SI }, 3903 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3904 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3905 ~RS6000_BTI_UINTSI }, 3906 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3907 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3908 ~RS6000_BTI_bool_V4SI }, 3909 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3910 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3911 ~RS6000_BTI_UINTSI }, 3912 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3913 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3914 ~RS6000_BTI_INTSI }, 3915 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3916 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3917 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3918 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3919 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3920 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3921 ~RS6000_BTI_unsigned_V8HI }, 3922 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3923 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3924 ~RS6000_BTI_UINTHI }, 3925 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3926 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3927 ~RS6000_BTI_bool_V8HI }, 3928 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3929 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3930 ~RS6000_BTI_UINTHI }, 3931 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3932 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3933 ~RS6000_BTI_INTHI }, 3934 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3935 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3936 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3937 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3938 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3939 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3940 ~RS6000_BTI_unsigned_V16QI }, 3941 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3942 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3943 ~RS6000_BTI_UINTQI }, 3944 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3945 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3946 ~RS6000_BTI_bool_V16QI }, 3947 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3948 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3949 ~RS6000_BTI_UINTQI }, 3950 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3951 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3952 ~RS6000_BTI_INTQI }, 3953 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3954 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 3955 ~RS6000_BTI_pixel_V8HI }, 3956 3957 /* Predicates. */ 3958 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3959 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3960 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3961 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3962 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3963 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3964 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3965 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 3966 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3967 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3968 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3969 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3970 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3971 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3972 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3973 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3974 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3975 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3976 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3977 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3978 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3979 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 3980 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3981 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3982 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3983 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3984 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3985 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3986 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3987 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3988 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3989 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 3990 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3991 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3992 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3993 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 3994 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3995 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 3996 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3997 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3998 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3999 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4000 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4001 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4002 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4003 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4004 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4005 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4006 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, 4007 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4008 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, 4009 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4010 4011 4012 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4013 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 4014 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4015 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 4016 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4017 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4018 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4019 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 4020 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4021 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 4022 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4023 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4024 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4025 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 4026 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4027 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 4028 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4029 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 4030 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4031 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4032 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4033 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4034 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4035 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 4036 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4037 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 4038 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4039 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 4040 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4041 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI }, 4042 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4043 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 4044 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4045 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 4046 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4047 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4048 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4049 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 4050 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4051 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 4052 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4053 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 4054 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4055 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 4056 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4057 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 4058 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4059 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 4060 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4061 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4062 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4063 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4064 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4065 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4066 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4067 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4068 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4069 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, 4070 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, 4071 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4072 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, 4073 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4074 4075 4076 /* cmpge is the same as cmpgt for all cases except floating point. 4077 There is further code to deal with this special case in 4078 altivec_build_resolved_builtin. */ 4079 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4080 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 4081 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4082 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 4083 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4084 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4085 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4086 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 4087 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4088 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 4089 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4090 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4091 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4092 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 4093 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4094 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 4095 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4096 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4097 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4098 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4099 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4100 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 4101 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4102 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 4103 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4104 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 4105 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4106 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 4107 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4108 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4109 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4110 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 4111 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4112 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 4113 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4114 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 4115 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4116 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 4117 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4118 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 4119 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4120 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4121 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4122 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4123 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4124 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4125 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4126 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4127 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, 4128 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4129 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, 4130 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4131 4132 /* Power8 vector overloaded functions. */ 4133 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4134 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4135 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4136 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4137 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4138 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4139 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, 4140 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4141 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, 4142 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4143 RS6000_BTI_unsigned_V16QI, 0 }, 4144 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, 4145 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4146 RS6000_BTI_bool_V16QI, 0 }, 4147 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, 4148 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4149 RS6000_BTI_unsigned_V16QI, 0 }, 4150 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4151 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4152 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4153 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4154 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4155 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4156 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, 4157 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4158 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, 4159 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4160 RS6000_BTI_unsigned_V8HI, 0 }, 4161 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, 4162 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4163 RS6000_BTI_bool_V8HI, 0 }, 4164 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, 4165 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4166 RS6000_BTI_unsigned_V8HI, 0 }, 4167 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4168 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4169 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4170 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4171 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4172 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4173 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, 4174 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4175 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, 4176 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4177 RS6000_BTI_unsigned_V4SI, 0 }, 4178 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, 4179 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4180 RS6000_BTI_bool_V4SI, 0 }, 4181 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, 4182 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4183 RS6000_BTI_unsigned_V4SI, 0 }, 4184 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4185 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4186 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4187 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4188 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4189 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4190 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, 4191 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4192 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, 4193 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4194 RS6000_BTI_unsigned_V2DI, 0 }, 4195 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, 4196 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4197 RS6000_BTI_bool_V2DI, 0 }, 4198 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, 4199 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4200 RS6000_BTI_unsigned_V2DI, 0 }, 4201 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, 4202 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4203 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, 4204 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4205 4206 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4207 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4208 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4209 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4210 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4211 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4212 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, 4213 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4214 RS6000_BTI_unsigned_V16QI, 0 }, 4215 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, 4216 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4217 RS6000_BTI_bool_V16QI, 0 }, 4218 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, 4219 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4220 RS6000_BTI_unsigned_V16QI, 0 }, 4221 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, 4222 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4223 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4224 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4225 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4226 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4227 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4228 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4229 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, 4230 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4231 RS6000_BTI_unsigned_V8HI, 0 }, 4232 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, 4233 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4234 RS6000_BTI_bool_V8HI, 0 }, 4235 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, 4236 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4237 RS6000_BTI_unsigned_V8HI, 0 }, 4238 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, 4239 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4240 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4241 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4242 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4243 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4244 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4245 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4246 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, 4247 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4248 RS6000_BTI_unsigned_V4SI, 0 }, 4249 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, 4250 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4251 RS6000_BTI_bool_V4SI, 0 }, 4252 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, 4253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4254 RS6000_BTI_unsigned_V4SI, 0 }, 4255 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, 4256 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4257 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4258 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4259 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4260 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4261 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4262 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4263 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, 4264 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4265 RS6000_BTI_unsigned_V2DI, 0 }, 4266 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, 4267 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4268 RS6000_BTI_bool_V2DI, 0 }, 4269 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, 4270 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4271 RS6000_BTI_unsigned_V2DI, 0 }, 4272 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, 4273 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4274 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, 4275 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4276 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, 4277 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4278 4279 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4280 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4281 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4282 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4283 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4284 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4285 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, 4286 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4287 RS6000_BTI_unsigned_V16QI, 0 }, 4288 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, 4289 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4290 RS6000_BTI_bool_V16QI, 0 }, 4291 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, 4292 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4293 RS6000_BTI_unsigned_V16QI, 0 }, 4294 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, 4295 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4296 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4297 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4298 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4299 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4300 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4301 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4302 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, 4303 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4304 RS6000_BTI_unsigned_V8HI, 0 }, 4305 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, 4306 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4307 RS6000_BTI_bool_V8HI, 0 }, 4308 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, 4309 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4310 RS6000_BTI_unsigned_V8HI, 0 }, 4311 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, 4312 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4313 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4314 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4315 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4316 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4317 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4318 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4319 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, 4320 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4321 RS6000_BTI_unsigned_V4SI, 0 }, 4322 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, 4323 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4324 RS6000_BTI_bool_V4SI, 0 }, 4325 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, 4326 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4327 RS6000_BTI_unsigned_V4SI, 0 }, 4328 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, 4329 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4330 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4331 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4332 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4333 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4334 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4335 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4336 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, 4337 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4338 RS6000_BTI_unsigned_V2DI, 0 }, 4339 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, 4340 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4341 RS6000_BTI_bool_V2DI, 0 }, 4342 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, 4343 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4344 RS6000_BTI_unsigned_V2DI, 0 }, 4345 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, 4346 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4347 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, 4348 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4349 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, 4350 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4351 4352 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 4353 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4354 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 4355 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4356 RS6000_BTI_unsigned_V1TI, 0 }, 4357 4358 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4359 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4360 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4361 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4362 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4363 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4364 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4365 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4366 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4367 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4368 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4369 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4370 4371 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 4372 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4373 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 4374 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4375 RS6000_BTI_unsigned_V1TI, 0 }, 4376 4377 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD, 4378 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4379 RS6000_BTI_unsigned_V16QI, 0 }, 4380 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ, 4381 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, 4382 RS6000_BTI_unsigned_V16QI, 0 }, 4383 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2, 4384 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4385 RS6000_BTI_unsigned_V16QI, 0 }, 4386 4387 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4388 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4389 RS6000_BTI_unsigned_V16QI, 0 }, 4390 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4391 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4392 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4393 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 4394 RS6000_BTI_unsigned_V16QI, 0 }, 4395 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4396 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, 4397 RS6000_BTI_unsigned_V16QI, 0 }, 4398 4399 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 4400 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4401 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 4402 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4403 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 4404 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4405 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 4406 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4407 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 4408 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4409 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 4410 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4411 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 4412 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4413 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 4414 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4415 4416 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 4417 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4418 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 4419 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4420 4421 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 4422 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4423 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 4424 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4425 4426 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4427 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4428 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4429 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4430 4431 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4432 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4433 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4434 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4435 4436 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD, 4437 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4438 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD, 4439 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4440 4441 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD, 4442 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4443 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD, 4444 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4445 4446 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD, 4447 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4448 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD, 4449 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4450 4451 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD, 4452 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4453 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD, 4454 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4455 4456 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD, 4457 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4458 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD, 4459 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4460 4461 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD, 4462 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4463 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD, 4464 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4465 4466 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD, 4467 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4468 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD, 4469 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4470 4471 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD, 4472 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4473 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD, 4474 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4475 4476 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, 4477 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4478 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, 4479 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4480 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, 4481 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4482 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, 4483 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4484 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, 4485 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4486 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, 4487 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4488 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, 4489 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4490 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, 4491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4492 4493 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, 4494 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4495 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, 4496 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4497 4498 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, 4499 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4500 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, 4501 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4502 4503 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, 4504 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4505 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, 4506 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4507 4508 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, 4509 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4510 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, 4511 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4512 4513 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB, 4514 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4515 RS6000_BTI_unsigned_V16QI, 0 }, 4516 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH, 4517 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4518 RS6000_BTI_unsigned_V8HI, 0 }, 4519 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW, 4520 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4521 RS6000_BTI_unsigned_V4SI, 0 }, 4522 4523 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB, 4524 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4525 RS6000_BTI_unsigned_V16QI, 0 }, 4526 4527 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH, 4528 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4529 RS6000_BTI_unsigned_V8HI, 0 }, 4530 4531 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW, 4532 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4533 RS6000_BTI_unsigned_V4SI, 0 }, 4534 4535 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP, 4536 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4537 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP, 4538 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4539 4540 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP, 4541 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4542 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP, 4543 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4544 4545 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP, 4546 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4547 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP, 4548 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4549 4550 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP, 4551 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4552 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP, 4553 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4554 4555 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP, 4556 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 4557 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP, 4558 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 4559 4560 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP, 4561 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 4562 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP, 4563 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 4564 4565 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, 4566 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 4567 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, 4568 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, 4569 4570 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, 4571 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4572 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, 4573 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, 4574 4575 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, 4576 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 4577 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, 4578 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, 4579 4580 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, 4581 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4582 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, 4583 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, 4584 4585 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP, 4586 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, 4587 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP, 4588 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, 4589 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, 4590 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, 4591 4592 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, 4593 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, 4594 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP, 4595 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, 4596 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, 4597 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, 4598 4599 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, 4600 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, 4601 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP, 4602 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, 4603 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, 4604 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, 4605 4606 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, 4607 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, 4608 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP, 4609 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, 4610 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, 4611 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, 4612 4613 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, 4614 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, 4615 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, 4616 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, 4617 4618 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, 4619 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, 4620 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, 4621 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, 4622 4623 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, 4624 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, 4625 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF, 4626 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 }, 4627 4628 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, 4629 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, 4630 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, 4631 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, 4632 4633 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, 4634 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 4635 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, 4636 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 4637 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, 4638 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 4639 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, 4640 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 4641 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, 4642 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 4643 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, 4644 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 4645 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, 4646 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 4647 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, 4648 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 4649 4650 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, 4651 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 4652 RS6000_BTI_unsigned_long_long, 0 }, 4653 4654 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4655 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, 4656 RS6000_BTI_unsigned_long_long, 0 }, 4657 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4658 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 4659 RS6000_BTI_unsigned_long_long, 0 }, 4660 4661 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4662 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, 4663 RS6000_BTI_unsigned_long_long, 0 }, 4664 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4665 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, 4666 RS6000_BTI_unsigned_long_long, 0 }, 4667 4668 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4669 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, 4670 RS6000_BTI_unsigned_long_long, 0 }, 4671 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4672 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, 4673 RS6000_BTI_unsigned_long_long, 0 }, 4674 4675 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4676 RS6000_BTI_V2DI, ~RS6000_BTI_long_long, 4677 RS6000_BTI_unsigned_long_long, 0 }, 4678 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4679 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, 4680 RS6000_BTI_unsigned_long_long, 0 }, 4681 4682 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4683 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, 4684 RS6000_BTI_unsigned_long_long, 0 }, 4685 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4686 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, 4687 RS6000_BTI_unsigned_long_long, 0 }, 4688 4689 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4690 RS6000_BTI_V2DF, ~RS6000_BTI_double, 4691 RS6000_BTI_unsigned_long_long, 0 }, 4692 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 4693 RS6000_BTI_V4SF, ~RS6000_BTI_float, 4694 RS6000_BTI_unsigned_long_long, 0 }, 4695 /* At an appropriate future time, add support for the 4696 RS6000_BTI_Float16 (exact name to be determined) type here. */ 4697 4698 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R, 4699 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 4700 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long}, 4701 4702 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4703 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, 4704 RS6000_BTI_unsigned_long_long }, 4705 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4706 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 4707 RS6000_BTI_unsigned_long_long }, 4708 4709 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4710 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, 4711 RS6000_BTI_unsigned_long_long }, 4712 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4713 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, 4714 RS6000_BTI_unsigned_long_long }, 4715 4716 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4717 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, 4718 RS6000_BTI_unsigned_long_long }, 4719 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4720 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, 4721 RS6000_BTI_unsigned_long_long }, 4722 4723 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4724 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long, 4725 RS6000_BTI_unsigned_long_long }, 4726 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4727 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, 4728 RS6000_BTI_unsigned_long_long }, 4729 4730 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4731 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, 4732 RS6000_BTI_unsigned_long_long }, 4733 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4734 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, 4735 RS6000_BTI_unsigned_long_long }, 4736 4737 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4738 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double, 4739 RS6000_BTI_unsigned_long_long }, 4740 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 4741 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float, 4742 RS6000_BTI_unsigned_long_long }, 4743 /* At an appropriate future time, add support for the 4744 RS6000_BTI_Float16 (exact name to be determined) type here. */ 4745 4746 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 4747 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 4748 RS6000_BTI_bool_V16QI, 0 }, 4749 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 4750 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 4751 RS6000_BTI_V16QI, 0 }, 4752 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 4753 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 4754 RS6000_BTI_unsigned_V16QI, 0 }, 4755 4756 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 4757 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 4758 RS6000_BTI_bool_V8HI, 0 }, 4759 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 4760 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 4761 RS6000_BTI_V8HI, 0 }, 4762 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 4763 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 4764 RS6000_BTI_unsigned_V8HI, 0 }, 4765 4766 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 4767 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 4768 RS6000_BTI_bool_V4SI, 0 }, 4769 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 4770 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 4771 RS6000_BTI_V4SI, 0 }, 4772 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 4773 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 4774 RS6000_BTI_unsigned_V4SI, 0 }, 4775 4776 /* The following 2 entries have been deprecated. */ 4777 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4778 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4779 RS6000_BTI_unsigned_V16QI, 0 }, 4780 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4781 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 4782 RS6000_BTI_bool_V16QI, 0 }, 4783 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4784 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 4785 RS6000_BTI_unsigned_V16QI, 0 }, 4786 4787 /* The following 2 entries have been deprecated. */ 4788 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4789 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4790 RS6000_BTI_V16QI, 0 }, 4791 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4792 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 4793 RS6000_BTI_bool_V16QI, 0 }, 4794 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4795 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4796 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 4797 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4798 RS6000_BTI_bool_V16QI, 0 }, 4799 4800 /* The following 2 entries have been deprecated. */ 4801 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4802 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4803 RS6000_BTI_unsigned_V8HI, 0 }, 4804 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4805 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 4806 RS6000_BTI_bool_V8HI, 0 }, 4807 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4808 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 4809 RS6000_BTI_unsigned_V8HI, 0 }, 4810 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4811 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4812 4813 /* The following 2 entries have been deprecated. */ 4814 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4815 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4816 RS6000_BTI_V8HI, 0 }, 4817 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4818 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 4819 RS6000_BTI_bool_V8HI, 0 }, 4820 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4821 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4822 RS6000_BTI_bool_V8HI, 0 }, 4823 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 4824 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, 4825 RS6000_BTI_pixel_V8HI, 0 }, 4826 4827 /* The following 2 entries have been deprecated. */ 4828 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4829 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4830 RS6000_BTI_unsigned_V4SI, 0 }, 4831 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4832 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 4833 RS6000_BTI_bool_V4SI, 0 }, 4834 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4835 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 4836 RS6000_BTI_unsigned_V4SI, 0 }, 4837 4838 /* The following 2 entries have been deprecated. */ 4839 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4840 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4841 RS6000_BTI_V4SI, 0 }, 4842 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4843 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 4844 RS6000_BTI_bool_V4SI, 0 }, 4845 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4846 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4847 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 4848 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4849 RS6000_BTI_bool_V4SI, 0 }, 4850 4851 /* The following 2 entries have been deprecated. */ 4852 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4853 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4854 RS6000_BTI_unsigned_V2DI, 0 }, 4855 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4856 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 4857 RS6000_BTI_bool_V2DI, 0 }, 4858 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4859 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 4860 RS6000_BTI_unsigned_V2DI, 0 4861 }, 4862 4863 /* The following 2 entries have been deprecated. */ 4864 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4865 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4866 RS6000_BTI_V2DI, 0 }, 4867 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4868 RS6000_BTI_INTSI, RS6000_BTI_V2DI, 4869 RS6000_BTI_bool_V2DI, 0 }, 4870 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4871 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4872 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 4873 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4874 RS6000_BTI_bool_V2DI, 0 }, 4875 4876 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P, 4877 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4878 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P, 4879 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4880 4881 /* The following 2 entries have been deprecated. */ 4882 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4883 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4884 RS6000_BTI_unsigned_V16QI, 0 }, 4885 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4886 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 4887 RS6000_BTI_bool_V16QI, 0 }, 4888 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4889 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 4890 RS6000_BTI_unsigned_V16QI, 0 }, 4891 4892 /* The following 2 entries have been deprecated. */ 4893 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4894 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4895 RS6000_BTI_V16QI, 0 }, 4896 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4897 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 4898 RS6000_BTI_bool_V16QI, 0 }, 4899 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4900 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4901 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 4902 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 4903 RS6000_BTI_bool_V16QI, 0 }, 4904 4905 /* The following 2 entries have been deprecated. */ 4906 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4907 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4908 RS6000_BTI_unsigned_V8HI, 0 }, 4909 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4910 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 4911 RS6000_BTI_bool_V8HI, 0 }, 4912 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4913 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 4914 RS6000_BTI_unsigned_V8HI, 0 }, 4915 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4916 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4917 4918 /* The following 2 entries have been deprecated. */ 4919 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4920 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4921 RS6000_BTI_V8HI, 0 }, 4922 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4923 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 4924 RS6000_BTI_bool_V8HI, 0 }, 4925 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4926 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 4927 RS6000_BTI_bool_V8HI, 0 }, 4928 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 4929 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, 4930 RS6000_BTI_pixel_V8HI, 0 }, 4931 4932 /* The following 2 entries have been deprecated. */ 4933 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4934 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4935 RS6000_BTI_unsigned_V4SI, 0 }, 4936 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4937 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 4938 RS6000_BTI_bool_V4SI, 0 }, 4939 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4940 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 4941 RS6000_BTI_unsigned_V4SI, 0 }, 4942 4943 /* The following 2 entries have been deprecated. */ 4944 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4945 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4946 RS6000_BTI_V4SI, 0 }, 4947 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4948 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 4949 RS6000_BTI_bool_V4SI, 0 }, 4950 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4951 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4952 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 4953 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 4954 RS6000_BTI_bool_V4SI, 0 }, 4955 4956 /* The following 2 entries have been deprecated. */ 4957 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4958 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4959 RS6000_BTI_unsigned_V2DI, 0 }, 4960 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4961 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 4962 RS6000_BTI_bool_V2DI, 0 }, 4963 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4964 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 4965 RS6000_BTI_unsigned_V2DI, 0 4966 }, 4967 4968 /* The following 2 entries have been deprecated. */ 4969 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4970 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4971 RS6000_BTI_V2DI, 0 }, 4972 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4973 RS6000_BTI_INTSI, RS6000_BTI_V2DI, 4974 RS6000_BTI_bool_V2DI, 0 }, 4975 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4976 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4977 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 4978 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 4979 RS6000_BTI_bool_V2DI, 0 }, 4980 4981 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P, 4982 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4983 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P, 4984 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4985 4986 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, 4987 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 4988 RS6000_BTI_unsigned_V16QI }, 4989 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, 4990 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4991 4992 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, 4993 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 4994 RS6000_BTI_unsigned_V8HI }, 4995 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, 4996 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4997 4998 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, 4999 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5000 RS6000_BTI_unsigned_V4SI }, 5001 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, 5002 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 5003 5004 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, 5005 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 5006 RS6000_BTI_V16QI, 0 }, 5007 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, 5008 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 5009 RS6000_BTI_unsigned_V16QI, 0 }, 5010 5011 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, 5012 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 5013 RS6000_BTI_V8HI, 0 }, 5014 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, 5015 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 5016 RS6000_BTI_unsigned_V8HI, 0 }, 5017 5018 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, 5019 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 5020 RS6000_BTI_V4SI, 0 }, 5021 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, 5022 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 5023 RS6000_BTI_unsigned_V4SI, 0 }, 5024 5025 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, 5026 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5027 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, 5028 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5029 5030 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, 5031 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5032 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, 5033 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5034 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI, 5035 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, 5036 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI, 5037 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 }, 5038 5039 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B, 5040 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 5041 5042 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH, 5043 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5044 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL, 5045 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5046 5047 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, 5048 RS6000_BTI_INTQI, RS6000_BTI_UINTSI, 5049 RS6000_BTI_V16QI, 0 }, 5050 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, 5051 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 5052 RS6000_BTI_unsigned_V16QI, 0 }, 5053 5054 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, 5055 RS6000_BTI_INTHI, RS6000_BTI_UINTSI, 5056 RS6000_BTI_V8HI, 0 }, 5057 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, 5058 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, 5059 RS6000_BTI_unsigned_V8HI, 0 }, 5060 5061 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5062 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, 5063 RS6000_BTI_V4SI, 0 }, 5064 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5065 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 5066 RS6000_BTI_unsigned_V4SI, 0 }, 5067 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5068 RS6000_BTI_float, RS6000_BTI_UINTSI, 5069 RS6000_BTI_V4SF, 0 }, 5070 5071 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, 5072 RS6000_BTI_INTQI, RS6000_BTI_UINTSI, 5073 RS6000_BTI_V16QI, 0 }, 5074 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, 5075 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 5076 RS6000_BTI_unsigned_V16QI, 0 }, 5077 5078 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, 5079 RS6000_BTI_INTHI, RS6000_BTI_UINTSI, 5080 RS6000_BTI_V8HI, 0 }, 5081 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, 5082 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, 5083 RS6000_BTI_unsigned_V8HI, 0 }, 5084 5085 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5086 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, 5087 RS6000_BTI_V4SI, 0 }, 5088 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5089 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 5090 RS6000_BTI_unsigned_V4SI, 0 }, 5091 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5092 RS6000_BTI_float, RS6000_BTI_UINTSI, 5093 RS6000_BTI_V4SF, 0 }, 5094 5095 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5096 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5097 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5098 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5099 5100 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, 5101 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI, 5102 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 5103 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, 5104 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 5105 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 5106 5107 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5108 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5109 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5110 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5111 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5112 5113 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 5114 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5115 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 5116 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5117 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5118 5119 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 5120 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5121 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 5122 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5123 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5124 5125 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 5126 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5127 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 5128 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5129 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5130 5131 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5132 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5133 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5134 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5135 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5136 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5137 5138 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5139 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5140 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5141 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5142 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5143 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5144 5145 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5146 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 5147 RS6000_BTI_unsigned_V2DI, 0 }, 5148 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5149 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5150 RS6000_BTI_bool_V2DI, 0 }, 5151 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5152 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5153 RS6000_BTI_unsigned_V2DI, 0 }, 5154 5155 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5156 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 5157 RS6000_BTI_unsigned_V2DI, 0 }, 5158 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5159 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5160 RS6000_BTI_bool_V2DI, 0 }, 5161 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5162 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5163 RS6000_BTI_unsigned_V2DI, 0 }, 5164 5165 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5166 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5167 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5168 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5169 RS6000_BTI_unsigned_V2DI, 0 }, 5170 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5171 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5172 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF, 5173 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5174 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF, 5175 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5176 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5177 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5178 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5179 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5180 RS6000_BTI_unsigned_V4SI, 0 }, 5181 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5182 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5183 5184 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5185 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5186 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5187 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5188 RS6000_BTI_unsigned_V4SI, 0 }, 5189 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5190 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5191 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5192 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5193 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5194 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5195 RS6000_BTI_unsigned_V2DI, 0 }, 5196 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5197 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5198 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF, 5199 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5200 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF, 5201 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5202 5203 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB, 5204 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 5205 RS6000_BTI_unsigned_V16QI, 0 }, 5206 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH, 5207 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 5208 RS6000_BTI_unsigned_V8HI, 0 }, 5209 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW, 5210 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 5211 RS6000_BTI_unsigned_V4SI, 0 }, 5212 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD, 5213 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, 5214 RS6000_BTI_unsigned_V2DI, 0 }, 5215 5216 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 5217 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5218 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 5219 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5220 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 5221 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5222 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 5223 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5224 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 5225 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5226 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 5227 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5228 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 5229 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5230 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 5231 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5232 5233 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 5234 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5235 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 5236 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5237 5238 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, 5239 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5240 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, 5241 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5242 5243 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, 5244 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5245 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, 5246 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5247 5248 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, 5249 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5250 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, 5251 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5252 5253 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, 5254 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5255 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, 5256 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5257 5258 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 5259 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5260 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 5261 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5262 5263 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 5264 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5265 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 5266 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5267 5268 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 5269 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5270 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 5271 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5272 5273 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, 5274 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5275 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, 5276 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5277 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, 5278 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5279 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, 5280 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5281 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5282 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5283 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5284 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5285 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5286 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, 5287 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5288 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, 5289 5290 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, 5291 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5292 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, 5293 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5294 5295 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, 5296 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5297 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, 5298 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5299 5300 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5301 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5302 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5303 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5304 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5305 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, 5306 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5307 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, 5308 5309 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, 5310 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5311 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, 5312 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5313 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, 5314 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5315 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, 5316 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5317 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, 5318 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5319 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, 5320 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5321 5322 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB, 5323 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, 5324 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2, 5325 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, 5326 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB, 5327 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 }, 5328 5329 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5330 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5331 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5332 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5333 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5334 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5335 5336 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, 5337 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5338 5339 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, 5340 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5341 5342 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, 5343 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5344 5345 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 5346 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5347 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 5348 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5349 5350 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 5351 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5352 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 5353 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5354 5355 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 5356 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5357 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 5358 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5359 5360 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 5361 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5362 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 5363 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5364 5365 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 5366 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 5367 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 5368 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5369 RS6000_BTI_unsigned_V1TI, 0 }, 5370 5371 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5372 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5373 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5374 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5375 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5376 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5377 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5378 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5379 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5380 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5381 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5382 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5383 5384 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 5385 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 5386 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 5387 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5388 RS6000_BTI_unsigned_V1TI, 0 }, 5389 5390 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32, 5391 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 }, 5392 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB, 5393 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, 5394 5395 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 5396 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 5397 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 5398 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 5399 5400 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 5401 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 5402 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 5403 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 5404 5405 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV, 5406 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5407 RS6000_BTI_unsigned_V16QI, 0 }, 5408 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV, 5409 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5410 RS6000_BTI_unsigned_V16QI, 0 }, 5411 5412 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, 5413 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5414 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, 5415 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5416 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5417 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, 5418 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5419 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5420 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5421 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5422 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5423 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, 5424 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5425 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5426 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5427 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5428 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5429 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, 5430 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5431 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5432 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5433 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5434 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5435 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, 5436 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5437 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5438 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5439 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5440 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF, 5441 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 5442 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF, 5443 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 5444 5445 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5446 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5447 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5448 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5449 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5450 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5451 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5452 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5453 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5454 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, 5455 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5456 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, 5457 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5458 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, 5459 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5460 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, 5461 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF, 5462 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 5463 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF, 5464 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 5465 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5466 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5467 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5468 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5469 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5470 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5471 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5472 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5473 5474 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF, 5475 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5476 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF, 5477 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5478 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF, 5479 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5480 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, 5481 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5482 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF, 5483 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5484 5485 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, 5486 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5487 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF, 5488 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5489 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF, 5490 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5491 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, 5492 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5493 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF, 5494 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 5495 RS6000_BTI_V2DF, 0 }, 5496 5497 /* Crypto builtins. */ 5498 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, 5499 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5500 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 5501 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, 5502 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 5503 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 5504 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, 5505 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5506 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 5507 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, 5508 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5509 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 5510 5511 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, 5512 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5513 RS6000_BTI_unsigned_V16QI, 0 }, 5514 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, 5515 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 5516 RS6000_BTI_unsigned_V8HI, 0 }, 5517 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, 5518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5519 RS6000_BTI_unsigned_V4SI, 0 }, 5520 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, 5521 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5522 RS6000_BTI_unsigned_V2DI, 0 }, 5523 5524 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, 5525 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5526 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 5527 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, 5528 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5529 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 5530 5531 { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 } 5532}; 5533 5534/* Nonzero if we can use a floating-point register to pass this arg. */ 5535#define USE_FP_FOR_ARG_P(CUM,MODE) \ 5536 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \ 5537 && (CUM)->fregno <= FP_ARG_MAX_REG \ 5538 && TARGET_HARD_FLOAT) 5539 5540/* Nonzero if we can use an AltiVec register to pass this arg. */ 5541#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \ 5542 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \ 5543 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \ 5544 && TARGET_ALTIVEC_ABI \ 5545 && (NAMED)) 5546 5547/* Walk down the type tree of TYPE counting consecutive base elements. 5548 If *MODEP is VOIDmode, then set it to the first valid floating point 5549 or vector type. If a non-floating point or vector type is found, or 5550 if a floating point or vector type that doesn't match a non-VOIDmode 5551 *MODEP is found, then return -1, otherwise return the count in the 5552 sub-tree. */ 5553 5554static int 5555rs6000_aggregate_candidate (const_tree type, machine_mode *modep, 5556 int *empty_base_seen) 5557{ 5558 machine_mode mode; 5559 HOST_WIDE_INT size; 5560 5561 switch (TREE_CODE (type)) 5562 { 5563 case REAL_TYPE: 5564 mode = TYPE_MODE (type); 5565 if (!SCALAR_FLOAT_MODE_P (mode)) 5566 return -1; 5567 5568 if (*modep == VOIDmode) 5569 *modep = mode; 5570 5571 if (*modep == mode) 5572 return 1; 5573 5574 break; 5575 5576 case COMPLEX_TYPE: 5577 mode = TYPE_MODE (TREE_TYPE (type)); 5578 if (!SCALAR_FLOAT_MODE_P (mode)) 5579 return -1; 5580 5581 if (*modep == VOIDmode) 5582 *modep = mode; 5583 5584 if (*modep == mode) 5585 return 2; 5586 5587 break; 5588 5589 case VECTOR_TYPE: 5590 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC) 5591 return -1; 5592 5593 /* Use V4SImode as representative of all 128-bit vector types. */ 5594 size = int_size_in_bytes (type); 5595 switch (size) 5596 { 5597 case 16: 5598 mode = V4SImode; 5599 break; 5600 default: 5601 return -1; 5602 } 5603 5604 if (*modep == VOIDmode) 5605 *modep = mode; 5606 5607 /* Vector modes are considered to be opaque: two vectors are 5608 equivalent for the purposes of being homogeneous aggregates 5609 if they are the same size. */ 5610 if (*modep == mode) 5611 return 1; 5612 5613 break; 5614 5615 case ARRAY_TYPE: 5616 { 5617 int count; 5618 tree index = TYPE_DOMAIN (type); 5619 5620 /* Can't handle incomplete types nor sizes that are not 5621 fixed. */ 5622 if (!COMPLETE_TYPE_P (type) 5623 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) 5624 return -1; 5625 5626 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep, 5627 empty_base_seen); 5628 if (count == -1 5629 || !index 5630 || !TYPE_MAX_VALUE (index) 5631 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index)) 5632 || !TYPE_MIN_VALUE (index) 5633 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index)) 5634 || count < 0) 5635 return -1; 5636 5637 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index)) 5638 - tree_to_uhwi (TYPE_MIN_VALUE (index))); 5639 5640 /* There must be no padding. */ 5641 if (wi::to_wide (TYPE_SIZE (type)) 5642 != count * GET_MODE_BITSIZE (*modep)) 5643 return -1; 5644 5645 return count; 5646 } 5647 5648 case RECORD_TYPE: 5649 { 5650 int count = 0; 5651 int sub_count; 5652 tree field; 5653 5654 /* Can't handle incomplete types nor sizes that are not 5655 fixed. */ 5656 if (!COMPLETE_TYPE_P (type) 5657 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) 5658 return -1; 5659 5660 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5661 { 5662 if (TREE_CODE (field) != FIELD_DECL) 5663 continue; 5664 5665 if (DECL_FIELD_ABI_IGNORED (field)) 5666 { 5667 if (lookup_attribute ("no_unique_address", 5668 DECL_ATTRIBUTES (field))) 5669 *empty_base_seen |= 2; 5670 else 5671 *empty_base_seen |= 1; 5672 continue; 5673 } 5674 5675 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep, 5676 empty_base_seen); 5677 if (sub_count < 0) 5678 return -1; 5679 count += sub_count; 5680 } 5681 5682 /* There must be no padding. */ 5683 if (wi::to_wide (TYPE_SIZE (type)) 5684 != count * GET_MODE_BITSIZE (*modep)) 5685 return -1; 5686 5687 return count; 5688 } 5689 5690 case UNION_TYPE: 5691 case QUAL_UNION_TYPE: 5692 { 5693 /* These aren't very interesting except in a degenerate case. */ 5694 int count = 0; 5695 int sub_count; 5696 tree field; 5697 5698 /* Can't handle incomplete types nor sizes that are not 5699 fixed. */ 5700 if (!COMPLETE_TYPE_P (type) 5701 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) 5702 return -1; 5703 5704 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 5705 { 5706 if (TREE_CODE (field) != FIELD_DECL) 5707 continue; 5708 5709 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep, 5710 empty_base_seen); 5711 if (sub_count < 0) 5712 return -1; 5713 count = count > sub_count ? count : sub_count; 5714 } 5715 5716 /* There must be no padding. */ 5717 if (wi::to_wide (TYPE_SIZE (type)) 5718 != count * GET_MODE_BITSIZE (*modep)) 5719 return -1; 5720 5721 return count; 5722 } 5723 5724 default: 5725 break; 5726 } 5727 5728 return -1; 5729} 5730 5731/* If an argument, whose type is described by TYPE and MODE, is a homogeneous 5732 float or vector aggregate that shall be passed in FP/vector registers 5733 according to the ELFv2 ABI, return the homogeneous element mode in 5734 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE. 5735 5736 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */ 5737 5738bool 5739rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type, 5740 machine_mode *elt_mode, 5741 int *n_elts) 5742{ 5743 /* Note that we do not accept complex types at the top level as 5744 homogeneous aggregates; these types are handled via the 5745 targetm.calls.split_complex_arg mechanism. Complex types 5746 can be elements of homogeneous aggregates, however. */ 5747 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type 5748 && AGGREGATE_TYPE_P (type)) 5749 { 5750 machine_mode field_mode = VOIDmode; 5751 int empty_base_seen = 0; 5752 int field_count = rs6000_aggregate_candidate (type, &field_mode, 5753 &empty_base_seen); 5754 5755 if (field_count > 0) 5756 { 5757 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8; 5758 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size); 5759 5760 /* The ELFv2 ABI allows homogeneous aggregates to occupy 5761 up to AGGR_ARG_NUM_REG registers. */ 5762 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size) 5763 { 5764 if (elt_mode) 5765 *elt_mode = field_mode; 5766 if (n_elts) 5767 *n_elts = field_count; 5768 if (empty_base_seen && warn_psabi) 5769 { 5770 static unsigned last_reported_type_uid; 5771 unsigned uid = TYPE_UID (TYPE_MAIN_VARIANT (type)); 5772 if (uid != last_reported_type_uid) 5773 { 5774 const char *url 5775 = CHANGES_ROOT_URL "gcc-10/changes.html#empty_base"; 5776 if (empty_base_seen & 1) 5777 inform (input_location, 5778 "parameter passing for argument of type %qT " 5779 "when C++17 is enabled changed to match C++14 " 5780 "%{in GCC 10.1%}", type, url); 5781 else 5782 inform (input_location, 5783 "parameter passing for argument of type %qT " 5784 "with %<[[no_unique_address]]%> members " 5785 "changed %{in GCC 10.1%}", type, url); 5786 last_reported_type_uid = uid; 5787 } 5788 } 5789 return true; 5790 } 5791 } 5792 } 5793 5794 if (elt_mode) 5795 *elt_mode = mode; 5796 if (n_elts) 5797 *n_elts = 1; 5798 return false; 5799} 5800 5801/* Return a nonzero value to say to return the function value in 5802 memory, just as large structures are always returned. TYPE will be 5803 the data type of the value, and FNTYPE will be the type of the 5804 function doing the returning, or @code{NULL} for libcalls. 5805 5806 The AIX ABI for the RS/6000 specifies that all structures are 5807 returned in memory. The Darwin ABI does the same. 5808 5809 For the Darwin 64 Bit ABI, a function result can be returned in 5810 registers or in memory, depending on the size of the return data 5811 type. If it is returned in registers, the value occupies the same 5812 registers as it would if it were the first and only function 5813 argument. Otherwise, the function places its result in memory at 5814 the location pointed to by GPR3. 5815 5816 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4, 5817 but a draft put them in memory, and GCC used to implement the draft 5818 instead of the final standard. Therefore, aix_struct_return 5819 controls this instead of DEFAULT_ABI; V.4 targets needing backward 5820 compatibility can change DRAFT_V4_STRUCT_RET to override the 5821 default, and -m switches get the final word. See 5822 rs6000_option_override_internal for more details. 5823 5824 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit 5825 long double support is enabled. These values are returned in memory. 5826 5827 int_size_in_bytes returns -1 for variable size objects, which go in 5828 memory always. The cast to unsigned makes -1 > 8. */ 5829 5830bool 5831rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5832{ 5833 /* For the Darwin64 ABI, test if we can fit the return value in regs. */ 5834 if (TARGET_MACHO 5835 && rs6000_darwin64_abi 5836 && TREE_CODE (type) == RECORD_TYPE 5837 && int_size_in_bytes (type) > 0) 5838 { 5839 CUMULATIVE_ARGS valcum; 5840 rtx valret; 5841 5842 valcum.words = 0; 5843 valcum.fregno = FP_ARG_MIN_REG; 5844 valcum.vregno = ALTIVEC_ARG_MIN_REG; 5845 /* Do a trial code generation as if this were going to be passed 5846 as an argument; if any part goes in memory, we return NULL. */ 5847 valret = rs6000_darwin64_record_arg (&valcum, type, true, true); 5848 if (valret) 5849 return false; 5850 /* Otherwise fall through to more conventional ABI rules. */ 5851 } 5852 5853 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */ 5854 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type, 5855 NULL, NULL)) 5856 return false; 5857 5858 /* The ELFv2 ABI returns aggregates up to 16B in registers */ 5859 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type) 5860 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16) 5861 return false; 5862 5863 if (AGGREGATE_TYPE_P (type) 5864 && (aix_struct_return 5865 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) 5866 return true; 5867 5868 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector 5869 modes only exist for GCC vector types if -maltivec. */ 5870 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI 5871 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type))) 5872 return false; 5873 5874 /* Return synthetic vectors in memory. */ 5875 if (TREE_CODE (type) == VECTOR_TYPE 5876 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) 5877 { 5878 static bool warned_for_return_big_vectors = false; 5879 if (!warned_for_return_big_vectors) 5880 { 5881 warning (OPT_Wpsabi, "GCC vector returned by reference: " 5882 "non-standard ABI extension with no compatibility " 5883 "guarantee"); 5884 warned_for_return_big_vectors = true; 5885 } 5886 return true; 5887 } 5888 5889 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD 5890 && FLOAT128_IEEE_P (TYPE_MODE (type))) 5891 return true; 5892 5893 return false; 5894} 5895 5896/* Specify whether values returned in registers should be at the most 5897 significant end of a register. We want aggregates returned by 5898 value to match the way aggregates are passed to functions. */ 5899 5900bool 5901rs6000_return_in_msb (const_tree valtype) 5902{ 5903 return (DEFAULT_ABI == ABI_ELFv2 5904 && BYTES_BIG_ENDIAN 5905 && AGGREGATE_TYPE_P (valtype) 5906 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype) 5907 == PAD_UPWARD)); 5908} 5909 5910#ifdef HAVE_AS_GNU_ATTRIBUTE 5911/* Return TRUE if a call to function FNDECL may be one that 5912 potentially affects the function calling ABI of the object file. */ 5913 5914static bool 5915call_ABI_of_interest (tree fndecl) 5916{ 5917 if (rs6000_gnu_attr && symtab->state == EXPANSION) 5918 { 5919 struct cgraph_node *c_node; 5920 5921 /* Libcalls are always interesting. */ 5922 if (fndecl == NULL_TREE) 5923 return true; 5924 5925 /* Any call to an external function is interesting. */ 5926 if (DECL_EXTERNAL (fndecl)) 5927 return true; 5928 5929 /* Interesting functions that we are emitting in this object file. */ 5930 c_node = cgraph_node::get (fndecl); 5931 c_node = c_node->ultimate_alias_target (); 5932 return !c_node->only_called_directly_p (); 5933 } 5934 return false; 5935} 5936#endif 5937 5938/* Initialize a variable CUM of type CUMULATIVE_ARGS 5939 for a call to a function whose data type is FNTYPE. 5940 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode. 5941 5942 For incoming args we set the number of arguments in the prototype large 5943 so we never return a PARALLEL. */ 5944 5945void 5946init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, 5947 rtx libname ATTRIBUTE_UNUSED, int incoming, 5948 int libcall, int n_named_args, 5949 tree fndecl, 5950 machine_mode return_mode ATTRIBUTE_UNUSED) 5951{ 5952 static CUMULATIVE_ARGS zero_cumulative; 5953 5954 *cum = zero_cumulative; 5955 cum->words = 0; 5956 cum->fregno = FP_ARG_MIN_REG; 5957 cum->vregno = ALTIVEC_ARG_MIN_REG; 5958 cum->prototype = (fntype && prototype_p (fntype)); 5959 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) 5960 ? CALL_LIBCALL : CALL_NORMAL); 5961 cum->sysv_gregno = GP_ARG_MIN_REG; 5962 cum->stdarg = stdarg_p (fntype); 5963 cum->libcall = libcall; 5964 5965 cum->nargs_prototype = 0; 5966 if (incoming || cum->prototype) 5967 cum->nargs_prototype = n_named_args; 5968 5969 /* Check for a longcall attribute. */ 5970 if ((!fntype && rs6000_default_long_calls) 5971 || (fntype 5972 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) 5973 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))) 5974 cum->call_cookie |= CALL_LONG; 5975 else if (DEFAULT_ABI != ABI_DARWIN) 5976 { 5977 bool is_local = (fndecl 5978 && !DECL_EXTERNAL (fndecl) 5979 && !DECL_WEAK (fndecl) 5980 && (*targetm.binds_local_p) (fndecl)); 5981 if (is_local) 5982 ; 5983 else if (flag_plt) 5984 { 5985 if (fntype 5986 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype))) 5987 cum->call_cookie |= CALL_LONG; 5988 } 5989 else 5990 { 5991 if (!(fntype 5992 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype)))) 5993 cum->call_cookie |= CALL_LONG; 5994 } 5995 } 5996 5997 if (TARGET_DEBUG_ARG) 5998 { 5999 fprintf (stderr, "\ninit_cumulative_args:"); 6000 if (fntype) 6001 { 6002 tree ret_type = TREE_TYPE (fntype); 6003 fprintf (stderr, " ret code = %s,", 6004 get_tree_code_name (TREE_CODE (ret_type))); 6005 } 6006 6007 if (cum->call_cookie & CALL_LONG) 6008 fprintf (stderr, " longcall,"); 6009 6010 fprintf (stderr, " proto = %d, nargs = %d\n", 6011 cum->prototype, cum->nargs_prototype); 6012 } 6013 6014#ifdef HAVE_AS_GNU_ATTRIBUTE 6015 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)) 6016 { 6017 cum->escapes = call_ABI_of_interest (fndecl); 6018 if (cum->escapes) 6019 { 6020 tree return_type; 6021 6022 if (fntype) 6023 { 6024 return_type = TREE_TYPE (fntype); 6025 return_mode = TYPE_MODE (return_type); 6026 } 6027 else 6028 return_type = lang_hooks.types.type_for_mode (return_mode, 0); 6029 6030 if (return_type != NULL) 6031 { 6032 if (TREE_CODE (return_type) == RECORD_TYPE 6033 && TYPE_TRANSPARENT_AGGR (return_type)) 6034 { 6035 return_type = TREE_TYPE (first_field (return_type)); 6036 return_mode = TYPE_MODE (return_type); 6037 } 6038 if (AGGREGATE_TYPE_P (return_type) 6039 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type) 6040 <= 8)) 6041 rs6000_returns_struct = true; 6042 } 6043 if (SCALAR_FLOAT_MODE_P (return_mode)) 6044 { 6045 rs6000_passes_float = true; 6046 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT) 6047 && (FLOAT128_IBM_P (return_mode) 6048 || FLOAT128_IEEE_P (return_mode) 6049 || (return_type != NULL 6050 && (TYPE_MAIN_VARIANT (return_type) 6051 == long_double_type_node)))) 6052 rs6000_passes_long_double = true; 6053 6054 /* Note if we passed or return a IEEE 128-bit type. We changed 6055 the mangling for these types, and we may need to make an alias 6056 with the old mangling. */ 6057 if (FLOAT128_IEEE_P (return_mode)) 6058 rs6000_passes_ieee128 = true; 6059 } 6060 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)) 6061 rs6000_passes_vector = true; 6062 } 6063 } 6064#endif 6065 6066 if (fntype 6067 && !TARGET_ALTIVEC 6068 && TARGET_ALTIVEC_ABI 6069 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype)))) 6070 { 6071 error ("cannot return value in vector register because" 6072 " altivec instructions are disabled, use %qs" 6073 " to enable them", "-maltivec"); 6074 } 6075} 6076 6077 6078/* On rs6000, function arguments are promoted, as are function return 6079 values. */ 6080 6081machine_mode 6082rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 6083 machine_mode mode, 6084 int *punsignedp ATTRIBUTE_UNUSED, 6085 const_tree, int for_return) 6086{ 6087 /* Warning: this is a static local variable and not always NULL! 6088 This function is called multiple times for the same function 6089 and return value. PREV_FUNC is used to keep track of the 6090 first time we encounter a function's return value in order 6091 to not report an error with that return value multiple times. */ 6092 static struct function *prev_func = NULL; 6093 6094 /* We do not allow MMA types being used as return values. Only report 6095 the invalid return value usage the first time we encounter it. */ 6096 if (for_return 6097 && prev_func != cfun 6098 && (mode == POImode || mode == PXImode)) 6099 { 6100 /* Record we have now handled function CFUN, so the next time we 6101 are called, we do not re-report the same error. */ 6102 prev_func = cfun; 6103 if (TYPE_CANONICAL (type) != NULL_TREE) 6104 type = TYPE_CANONICAL (type); 6105 error ("invalid use of MMA type %qs as a function return value", 6106 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)))); 6107 } 6108 6109 PROMOTE_MODE (mode, *punsignedp, type); 6110 6111 return mode; 6112} 6113 6114/* Return true if TYPE must be passed on the stack and not in registers. */ 6115 6116bool 6117rs6000_must_pass_in_stack (const function_arg_info &arg) 6118{ 6119 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT) 6120 return must_pass_in_stack_var_size (arg); 6121 else 6122 return must_pass_in_stack_var_size_or_pad (arg); 6123} 6124 6125static inline bool 6126is_complex_IBM_long_double (machine_mode mode) 6127{ 6128 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode)); 6129} 6130 6131/* Whether ABI_V4 passes MODE args to a function in floating point 6132 registers. */ 6133 6134static bool 6135abi_v4_pass_in_fpr (machine_mode mode, bool named) 6136{ 6137 if (!TARGET_HARD_FLOAT) 6138 return false; 6139 if (mode == DFmode) 6140 return true; 6141 if (mode == SFmode && named) 6142 return true; 6143 /* ABI_V4 passes complex IBM long double in 8 gprs. 6144 Stupid, but we can't change the ABI now. */ 6145 if (is_complex_IBM_long_double (mode)) 6146 return false; 6147 if (FLOAT128_2REG_P (mode)) 6148 return true; 6149 if (DECIMAL_FLOAT_MODE_P (mode)) 6150 return true; 6151 return false; 6152} 6153 6154/* Implement TARGET_FUNCTION_ARG_PADDING. 6155 6156 For the AIX ABI structs are always stored left shifted in their 6157 argument slot. */ 6158 6159pad_direction 6160rs6000_function_arg_padding (machine_mode mode, const_tree type) 6161{ 6162#ifndef AGGREGATE_PADDING_FIXED 6163#define AGGREGATE_PADDING_FIXED 0 6164#endif 6165#ifndef AGGREGATES_PAD_UPWARD_ALWAYS 6166#define AGGREGATES_PAD_UPWARD_ALWAYS 0 6167#endif 6168 6169 if (!AGGREGATE_PADDING_FIXED) 6170 { 6171 /* GCC used to pass structures of the same size as integer types as 6172 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING. 6173 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were 6174 passed padded downward, except that -mstrict-align further 6175 muddied the water in that multi-component structures of 2 and 4 6176 bytes in size were passed padded upward. 6177 6178 The following arranges for best compatibility with previous 6179 versions of gcc, but removes the -mstrict-align dependency. */ 6180 if (BYTES_BIG_ENDIAN) 6181 { 6182 HOST_WIDE_INT size = 0; 6183 6184 if (mode == BLKmode) 6185 { 6186 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST) 6187 size = int_size_in_bytes (type); 6188 } 6189 else 6190 size = GET_MODE_SIZE (mode); 6191 6192 if (size == 1 || size == 2 || size == 4) 6193 return PAD_DOWNWARD; 6194 } 6195 return PAD_UPWARD; 6196 } 6197 6198 if (AGGREGATES_PAD_UPWARD_ALWAYS) 6199 { 6200 if (type != 0 && AGGREGATE_TYPE_P (type)) 6201 return PAD_UPWARD; 6202 } 6203 6204 /* Fall back to the default. */ 6205 return default_function_arg_padding (mode, type); 6206} 6207 6208/* If defined, a C expression that gives the alignment boundary, in bits, 6209 of an argument with the specified mode and type. If it is not defined, 6210 PARM_BOUNDARY is used for all arguments. 6211 6212 V.4 wants long longs and doubles to be double word aligned. Just 6213 testing the mode size is a boneheaded way to do this as it means 6214 that other types such as complex int are also double word aligned. 6215 However, we're stuck with this because changing the ABI might break 6216 existing library interfaces. 6217 6218 Quadword align Altivec/VSX vectors. 6219 Quadword align large synthetic vector types. */ 6220 6221unsigned int 6222rs6000_function_arg_boundary (machine_mode mode, const_tree type) 6223{ 6224 machine_mode elt_mode; 6225 int n_elts; 6226 6227 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts); 6228 6229 if (DEFAULT_ABI == ABI_V4 6230 && (GET_MODE_SIZE (mode) == 8 6231 || (TARGET_HARD_FLOAT 6232 && !is_complex_IBM_long_double (mode) 6233 && FLOAT128_2REG_P (mode)))) 6234 return 64; 6235 else if (FLOAT128_VECTOR_P (mode)) 6236 return 128; 6237 else if (type && TREE_CODE (type) == VECTOR_TYPE 6238 && int_size_in_bytes (type) >= 8 6239 && int_size_in_bytes (type) < 16) 6240 return 64; 6241 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode) 6242 || (type && TREE_CODE (type) == VECTOR_TYPE 6243 && int_size_in_bytes (type) >= 16)) 6244 return 128; 6245 6246 /* Aggregate types that need > 8 byte alignment are quadword-aligned 6247 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless 6248 -mcompat-align-parm is used. */ 6249 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm) 6250 || DEFAULT_ABI == ABI_ELFv2) 6251 && type && TYPE_ALIGN (type) > 64) 6252 { 6253 /* "Aggregate" means any AGGREGATE_TYPE except for single-element 6254 or homogeneous float/vector aggregates here. We already handled 6255 vector aggregates above, but still need to check for float here. */ 6256 bool aggregate_p = (AGGREGATE_TYPE_P (type) 6257 && !SCALAR_FLOAT_MODE_P (elt_mode)); 6258 6259 /* We used to check for BLKmode instead of the above aggregate type 6260 check. Warn when this results in any difference to the ABI. */ 6261 if (aggregate_p != (mode == BLKmode)) 6262 { 6263 static bool warned; 6264 if (!warned && warn_psabi) 6265 { 6266 warned = true; 6267 inform (input_location, 6268 "the ABI of passing aggregates with %d-byte alignment" 6269 " has changed in GCC 5", 6270 (int) TYPE_ALIGN (type) / BITS_PER_UNIT); 6271 } 6272 } 6273 6274 if (aggregate_p) 6275 return 128; 6276 } 6277 6278 /* Similar for the Darwin64 ABI. Note that for historical reasons we 6279 implement the "aggregate type" check as a BLKmode check here; this 6280 means certain aggregate types are in fact not aligned. */ 6281 if (TARGET_MACHO && rs6000_darwin64_abi 6282 && mode == BLKmode 6283 && type && TYPE_ALIGN (type) > 64) 6284 return 128; 6285 6286 return PARM_BOUNDARY; 6287} 6288 6289/* The offset in words to the start of the parameter save area. */ 6290 6291static unsigned int 6292rs6000_parm_offset (void) 6293{ 6294 return (DEFAULT_ABI == ABI_V4 ? 2 6295 : DEFAULT_ABI == ABI_ELFv2 ? 4 6296 : 6); 6297} 6298 6299/* For a function parm of MODE and TYPE, return the starting word in 6300 the parameter area. NWORDS of the parameter area are already used. */ 6301 6302static unsigned int 6303rs6000_parm_start (machine_mode mode, const_tree type, 6304 unsigned int nwords) 6305{ 6306 unsigned int align; 6307 6308 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1; 6309 return nwords + (-(rs6000_parm_offset () + nwords) & align); 6310} 6311 6312/* Compute the size (in words) of a function argument. */ 6313 6314static unsigned long 6315rs6000_arg_size (machine_mode mode, const_tree type) 6316{ 6317 unsigned long size; 6318 6319 if (mode != BLKmode) 6320 size = GET_MODE_SIZE (mode); 6321 else 6322 size = int_size_in_bytes (type); 6323 6324 if (TARGET_32BIT) 6325 return (size + 3) >> 2; 6326 else 6327 return (size + 7) >> 3; 6328} 6329 6330/* Use this to flush pending int fields. */ 6331 6332static void 6333rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum, 6334 HOST_WIDE_INT bitpos, int final) 6335{ 6336 unsigned int startbit, endbit; 6337 int intregs, intoffset; 6338 6339 /* Handle the situations where a float is taking up the first half 6340 of the GPR, and the other half is empty (typically due to 6341 alignment restrictions). We can detect this by a 8-byte-aligned 6342 int field, or by seeing that this is the final flush for this 6343 argument. Count the word and continue on. */ 6344 if (cum->floats_in_gpr == 1 6345 && (cum->intoffset % 64 == 0 6346 || (cum->intoffset == -1 && final))) 6347 { 6348 cum->words++; 6349 cum->floats_in_gpr = 0; 6350 } 6351 6352 if (cum->intoffset == -1) 6353 return; 6354 6355 intoffset = cum->intoffset; 6356 cum->intoffset = -1; 6357 cum->floats_in_gpr = 0; 6358 6359 if (intoffset % BITS_PER_WORD != 0) 6360 { 6361 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD; 6362 if (!int_mode_for_size (bits, 0).exists ()) 6363 { 6364 /* We couldn't find an appropriate mode, which happens, 6365 e.g., in packed structs when there are 3 bytes to load. 6366 Back intoffset back to the beginning of the word in this 6367 case. */ 6368 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD); 6369 } 6370 } 6371 6372 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD); 6373 endbit = ROUND_UP (bitpos, BITS_PER_WORD); 6374 intregs = (endbit - startbit) / BITS_PER_WORD; 6375 cum->words += intregs; 6376 /* words should be unsigned. */ 6377 if ((unsigned)cum->words < (endbit/BITS_PER_WORD)) 6378 { 6379 int pad = (endbit/BITS_PER_WORD) - cum->words; 6380 cum->words += pad; 6381 } 6382} 6383 6384/* The darwin64 ABI calls for us to recurse down through structs, 6385 looking for elements passed in registers. Unfortunately, we have 6386 to track int register count here also because of misalignments 6387 in powerpc alignment mode. */ 6388 6389static void 6390rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum, 6391 const_tree type, 6392 HOST_WIDE_INT startbitpos) 6393{ 6394 tree f; 6395 6396 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f)) 6397 if (TREE_CODE (f) == FIELD_DECL) 6398 { 6399 HOST_WIDE_INT bitpos = startbitpos; 6400 tree ftype = TREE_TYPE (f); 6401 machine_mode mode; 6402 if (ftype == error_mark_node) 6403 continue; 6404 mode = TYPE_MODE (ftype); 6405 6406 if (DECL_SIZE (f) != 0 6407 && tree_fits_uhwi_p (bit_position (f))) 6408 bitpos += int_bit_position (f); 6409 6410 /* ??? FIXME: else assume zero offset. */ 6411 6412 if (TREE_CODE (ftype) == RECORD_TYPE) 6413 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); 6414 else if (USE_FP_FOR_ARG_P (cum, mode)) 6415 { 6416 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3; 6417 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); 6418 cum->fregno += n_fpregs; 6419 /* Single-precision floats present a special problem for 6420 us, because they are smaller than an 8-byte GPR, and so 6421 the structure-packing rules combined with the standard 6422 varargs behavior mean that we want to pack float/float 6423 and float/int combinations into a single register's 6424 space. This is complicated by the arg advance flushing, 6425 which works on arbitrarily large groups of int-type 6426 fields. */ 6427 if (mode == SFmode) 6428 { 6429 if (cum->floats_in_gpr == 1) 6430 { 6431 /* Two floats in a word; count the word and reset 6432 the float count. */ 6433 cum->words++; 6434 cum->floats_in_gpr = 0; 6435 } 6436 else if (bitpos % 64 == 0) 6437 { 6438 /* A float at the beginning of an 8-byte word; 6439 count it and put off adjusting cum->words until 6440 we see if a arg advance flush is going to do it 6441 for us. */ 6442 cum->floats_in_gpr++; 6443 } 6444 else 6445 { 6446 /* The float is at the end of a word, preceded 6447 by integer fields, so the arg advance flush 6448 just above has already set cum->words and 6449 everything is taken care of. */ 6450 } 6451 } 6452 else 6453 cum->words += n_fpregs; 6454 } 6455 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1)) 6456 { 6457 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); 6458 cum->vregno++; 6459 cum->words += 2; 6460 } 6461 else if (cum->intoffset == -1) 6462 cum->intoffset = bitpos; 6463 } 6464} 6465 6466/* Check for an item that needs to be considered specially under the darwin 64 6467 bit ABI. These are record types where the mode is BLK or the structure is 6468 8 bytes in size. */ 6469int 6470rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type) 6471{ 6472 return rs6000_darwin64_abi 6473 && ((mode == BLKmode 6474 && TREE_CODE (type) == RECORD_TYPE 6475 && int_size_in_bytes (type) > 0) 6476 || (type && TREE_CODE (type) == RECORD_TYPE 6477 && int_size_in_bytes (type) == 8)) ? 1 : 0; 6478} 6479 6480/* Update the data in CUM to advance over an argument 6481 of mode MODE and data type TYPE. 6482 (TYPE is null for libcalls where that information may not be available.) 6483 6484 Note that for args passed by reference, function_arg will be called 6485 with MODE and TYPE set to that of the pointer to the arg, not the arg 6486 itself. */ 6487 6488static void 6489rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, 6490 const_tree type, bool named, int depth) 6491{ 6492 machine_mode elt_mode; 6493 int n_elts; 6494 6495 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts); 6496 6497 /* Only tick off an argument if we're not recursing. */ 6498 if (depth == 0) 6499 cum->nargs_prototype--; 6500 6501#ifdef HAVE_AS_GNU_ATTRIBUTE 6502 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4) 6503 && cum->escapes) 6504 { 6505 if (SCALAR_FLOAT_MODE_P (mode)) 6506 { 6507 rs6000_passes_float = true; 6508 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT) 6509 && (FLOAT128_IBM_P (mode) 6510 || FLOAT128_IEEE_P (mode) 6511 || (type != NULL 6512 && TYPE_MAIN_VARIANT (type) == long_double_type_node))) 6513 rs6000_passes_long_double = true; 6514 6515 /* Note if we passed or return a IEEE 128-bit type. We changed the 6516 mangling for these types, and we may need to make an alias with 6517 the old mangling. */ 6518 if (FLOAT128_IEEE_P (mode)) 6519 rs6000_passes_ieee128 = true; 6520 } 6521 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode)) 6522 rs6000_passes_vector = true; 6523 } 6524#endif 6525 6526 if (TARGET_ALTIVEC_ABI 6527 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode) 6528 || (type && TREE_CODE (type) == VECTOR_TYPE 6529 && int_size_in_bytes (type) == 16))) 6530 { 6531 bool stack = false; 6532 6533 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named)) 6534 { 6535 cum->vregno += n_elts; 6536 6537 /* If we are not splitting Complex IEEE128 args then account for the 6538 fact that they are passed in 2 VSX regs. */ 6539 if (!targetm.calls.split_complex_arg && type 6540 && TREE_CODE (type) == COMPLEX_TYPE && elt_mode == KCmode) 6541 cum->vregno++; 6542 6543 if (!TARGET_ALTIVEC) 6544 error ("cannot pass argument in vector register because" 6545 " altivec instructions are disabled, use %qs" 6546 " to enable them", "-maltivec"); 6547 6548 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument 6549 even if it is going to be passed in a vector register. 6550 Darwin does the same for variable-argument functions. */ 6551 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 6552 && TARGET_64BIT) 6553 || (cum->stdarg && DEFAULT_ABI != ABI_V4)) 6554 stack = true; 6555 } 6556 else 6557 stack = true; 6558 6559 if (stack) 6560 { 6561 int align; 6562 6563 /* Vector parameters must be 16-byte aligned. In 32-bit 6564 mode this means we need to take into account the offset 6565 to the parameter save area. In 64-bit mode, they just 6566 have to start on an even word, since the parameter save 6567 area is 16-byte aligned. */ 6568 if (TARGET_32BIT) 6569 align = -(rs6000_parm_offset () + cum->words) & 3; 6570 else 6571 align = cum->words & 1; 6572 cum->words += align + rs6000_arg_size (mode, type); 6573 6574 if (TARGET_DEBUG_ARG) 6575 { 6576 fprintf (stderr, "function_adv: words = %2d, align=%d, ", 6577 cum->words, align); 6578 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n", 6579 cum->nargs_prototype, cum->prototype, 6580 GET_MODE_NAME (mode)); 6581 } 6582 } 6583 } 6584 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) 6585 { 6586 int size = int_size_in_bytes (type); 6587 /* Variable sized types have size == -1 and are 6588 treated as if consisting entirely of ints. 6589 Pad to 16 byte boundary if needed. */ 6590 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD 6591 && (cum->words % 2) != 0) 6592 cum->words++; 6593 /* For varargs, we can just go up by the size of the struct. */ 6594 if (!named) 6595 cum->words += (size + 7) / 8; 6596 else 6597 { 6598 /* It is tempting to say int register count just goes up by 6599 sizeof(type)/8, but this is wrong in a case such as 6600 { int; double; int; } [powerpc alignment]. We have to 6601 grovel through the fields for these too. */ 6602 cum->intoffset = 0; 6603 cum->floats_in_gpr = 0; 6604 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0); 6605 rs6000_darwin64_record_arg_advance_flush (cum, 6606 size * BITS_PER_UNIT, 1); 6607 } 6608 if (TARGET_DEBUG_ARG) 6609 { 6610 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d", 6611 cum->words, TYPE_ALIGN (type), size); 6612 fprintf (stderr, 6613 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n", 6614 cum->nargs_prototype, cum->prototype, 6615 GET_MODE_NAME (mode)); 6616 } 6617 } 6618 else if (DEFAULT_ABI == ABI_V4) 6619 { 6620 if (abi_v4_pass_in_fpr (mode, named)) 6621 { 6622 /* _Decimal128 must use an even/odd register pair. This assumes 6623 that the register number is odd when fregno is odd. */ 6624 if (mode == TDmode && (cum->fregno % 2) == 1) 6625 cum->fregno++; 6626 6627 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0) 6628 <= FP_ARG_V4_MAX_REG) 6629 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3; 6630 else 6631 { 6632 cum->fregno = FP_ARG_V4_MAX_REG + 1; 6633 if (mode == DFmode || FLOAT128_IBM_P (mode) 6634 || mode == DDmode || mode == TDmode) 6635 cum->words += cum->words & 1; 6636 cum->words += rs6000_arg_size (mode, type); 6637 } 6638 } 6639 else 6640 { 6641 int n_words = rs6000_arg_size (mode, type); 6642 int gregno = cum->sysv_gregno; 6643 6644 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10). 6645 As does any other 2 word item such as complex int due to a 6646 historical mistake. */ 6647 if (n_words == 2) 6648 gregno += (1 - gregno) & 1; 6649 6650 /* Multi-reg args are not split between registers and stack. */ 6651 if (gregno + n_words - 1 > GP_ARG_MAX_REG) 6652 { 6653 /* Long long is aligned on the stack. So are other 2 word 6654 items such as complex int due to a historical mistake. */ 6655 if (n_words == 2) 6656 cum->words += cum->words & 1; 6657 cum->words += n_words; 6658 } 6659 6660 /* Note: continuing to accumulate gregno past when we've started 6661 spilling to the stack indicates the fact that we've started 6662 spilling to the stack to expand_builtin_saveregs. */ 6663 cum->sysv_gregno = gregno + n_words; 6664 } 6665 6666 if (TARGET_DEBUG_ARG) 6667 { 6668 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", 6669 cum->words, cum->fregno); 6670 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ", 6671 cum->sysv_gregno, cum->nargs_prototype, cum->prototype); 6672 fprintf (stderr, "mode = %4s, named = %d\n", 6673 GET_MODE_NAME (mode), named); 6674 } 6675 } 6676 else 6677 { 6678 int n_words = rs6000_arg_size (mode, type); 6679 int start_words = cum->words; 6680 int align_words = rs6000_parm_start (mode, type, start_words); 6681 6682 cum->words = align_words + n_words; 6683 6684 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT) 6685 { 6686 /* _Decimal128 must be passed in an even/odd float register pair. 6687 This assumes that the register number is odd when fregno is 6688 odd. */ 6689 if (elt_mode == TDmode && (cum->fregno % 2) == 1) 6690 cum->fregno++; 6691 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3); 6692 } 6693 6694 if (TARGET_DEBUG_ARG) 6695 { 6696 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ", 6697 cum->words, cum->fregno); 6698 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ", 6699 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode)); 6700 fprintf (stderr, "named = %d, align = %d, depth = %d\n", 6701 named, align_words - start_words, depth); 6702 } 6703 } 6704} 6705 6706void 6707rs6000_function_arg_advance (cumulative_args_t cum, 6708 const function_arg_info &arg) 6709{ 6710 rs6000_function_arg_advance_1 (get_cumulative_args (cum), 6711 arg.mode, arg.type, arg.named, 0); 6712} 6713 6714/* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the 6715 structure between cum->intoffset and bitpos to integer registers. */ 6716 6717static void 6718rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum, 6719 HOST_WIDE_INT bitpos, rtx rvec[], int *k) 6720{ 6721 machine_mode mode; 6722 unsigned int regno; 6723 unsigned int startbit, endbit; 6724 int this_regno, intregs, intoffset; 6725 rtx reg; 6726 6727 if (cum->intoffset == -1) 6728 return; 6729 6730 intoffset = cum->intoffset; 6731 cum->intoffset = -1; 6732 6733 /* If this is the trailing part of a word, try to only load that 6734 much into the register. Otherwise load the whole register. Note 6735 that in the latter case we may pick up unwanted bits. It's not a 6736 problem at the moment but may wish to revisit. */ 6737 6738 if (intoffset % BITS_PER_WORD != 0) 6739 { 6740 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD; 6741 if (!int_mode_for_size (bits, 0).exists (&mode)) 6742 { 6743 /* We couldn't find an appropriate mode, which happens, 6744 e.g., in packed structs when there are 3 bytes to load. 6745 Back intoffset back to the beginning of the word in this 6746 case. */ 6747 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD); 6748 mode = word_mode; 6749 } 6750 } 6751 else 6752 mode = word_mode; 6753 6754 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD); 6755 endbit = ROUND_UP (bitpos, BITS_PER_WORD); 6756 intregs = (endbit - startbit) / BITS_PER_WORD; 6757 this_regno = cum->words + intoffset / BITS_PER_WORD; 6758 6759 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno) 6760 cum->use_stack = 1; 6761 6762 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno); 6763 if (intregs <= 0) 6764 return; 6765 6766 intoffset /= BITS_PER_UNIT; 6767 do 6768 { 6769 regno = GP_ARG_MIN_REG + this_regno; 6770 reg = gen_rtx_REG (mode, regno); 6771 rvec[(*k)++] = 6772 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 6773 6774 this_regno += 1; 6775 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 6776 mode = word_mode; 6777 intregs -= 1; 6778 } 6779 while (intregs > 0); 6780} 6781 6782/* Recursive workhorse for the following. */ 6783 6784static void 6785rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type, 6786 HOST_WIDE_INT startbitpos, rtx rvec[], 6787 int *k) 6788{ 6789 tree f; 6790 6791 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f)) 6792 if (TREE_CODE (f) == FIELD_DECL) 6793 { 6794 HOST_WIDE_INT bitpos = startbitpos; 6795 tree ftype = TREE_TYPE (f); 6796 machine_mode mode; 6797 if (ftype == error_mark_node) 6798 continue; 6799 mode = TYPE_MODE (ftype); 6800 6801 if (DECL_SIZE (f) != 0 6802 && tree_fits_uhwi_p (bit_position (f))) 6803 bitpos += int_bit_position (f); 6804 6805 /* ??? FIXME: else assume zero offset. */ 6806 6807 if (TREE_CODE (ftype) == RECORD_TYPE) 6808 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); 6809 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode)) 6810 { 6811 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; 6812#if 0 6813 switch (mode) 6814 { 6815 case E_SCmode: mode = SFmode; break; 6816 case E_DCmode: mode = DFmode; break; 6817 case E_TCmode: mode = TFmode; break; 6818 default: break; 6819 } 6820#endif 6821 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); 6822 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1) 6823 { 6824 gcc_assert (cum->fregno == FP_ARG_MAX_REG 6825 && (mode == TFmode || mode == TDmode)); 6826 /* Long double or _Decimal128 split over regs and memory. */ 6827 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode; 6828 cum->use_stack=1; 6829 } 6830 rvec[(*k)++] 6831 = gen_rtx_EXPR_LIST (VOIDmode, 6832 gen_rtx_REG (mode, cum->fregno++), 6833 GEN_INT (bitpos / BITS_PER_UNIT)); 6834 if (FLOAT128_2REG_P (mode)) 6835 cum->fregno++; 6836 } 6837 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1)) 6838 { 6839 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); 6840 rvec[(*k)++] 6841 = gen_rtx_EXPR_LIST (VOIDmode, 6842 gen_rtx_REG (mode, cum->vregno++), 6843 GEN_INT (bitpos / BITS_PER_UNIT)); 6844 } 6845 else if (cum->intoffset == -1) 6846 cum->intoffset = bitpos; 6847 } 6848} 6849 6850/* For the darwin64 ABI, we want to construct a PARALLEL consisting of 6851 the register(s) to be used for each field and subfield of a struct 6852 being passed by value, along with the offset of where the 6853 register's value may be found in the block. FP fields go in FP 6854 register, vector fields go in vector registers, and everything 6855 else goes in int registers, packed as in memory. 6856 6857 This code is also used for function return values. RETVAL indicates 6858 whether this is the case. 6859 6860 Much of this is taken from the SPARC V9 port, which has a similar 6861 calling convention. */ 6862 6863rtx 6864rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type, 6865 bool named, bool retval) 6866{ 6867 rtx rvec[FIRST_PSEUDO_REGISTER]; 6868 int k = 1, kbase = 1; 6869 HOST_WIDE_INT typesize = int_size_in_bytes (type); 6870 /* This is a copy; modifications are not visible to our caller. */ 6871 CUMULATIVE_ARGS copy_cum = *orig_cum; 6872 CUMULATIVE_ARGS *cum = ©_cum; 6873 6874 /* Pad to 16 byte boundary if needed. */ 6875 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD 6876 && (cum->words % 2) != 0) 6877 cum->words++; 6878 6879 cum->intoffset = 0; 6880 cum->use_stack = 0; 6881 cum->named = named; 6882 6883 /* Put entries into rvec[] for individual FP and vector fields, and 6884 for the chunks of memory that go in int regs. Note we start at 6885 element 1; 0 is reserved for an indication of using memory, and 6886 may or may not be filled in below. */ 6887 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k); 6888 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k); 6889 6890 /* If any part of the struct went on the stack put all of it there. 6891 This hack is because the generic code for 6892 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register 6893 parts of the struct are not at the beginning. */ 6894 if (cum->use_stack) 6895 { 6896 if (retval) 6897 return NULL_RTX; /* doesn't go in registers at all */ 6898 kbase = 0; 6899 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 6900 } 6901 if (k > 1 || cum->use_stack) 6902 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase])); 6903 else 6904 return NULL_RTX; 6905} 6906 6907/* Determine where to place an argument in 64-bit mode with 32-bit ABI. */ 6908 6909static rtx 6910rs6000_mixed_function_arg (machine_mode mode, const_tree type, 6911 int align_words) 6912{ 6913 int n_units; 6914 int i, k; 6915 rtx rvec[GP_ARG_NUM_REG + 1]; 6916 6917 if (align_words >= GP_ARG_NUM_REG) 6918 return NULL_RTX; 6919 6920 n_units = rs6000_arg_size (mode, type); 6921 6922 /* Optimize the simple case where the arg fits in one gpr, except in 6923 the case of BLKmode due to assign_parms assuming that registers are 6924 BITS_PER_WORD wide. */ 6925 if (n_units == 0 6926 || (n_units == 1 && mode != BLKmode)) 6927 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 6928 6929 k = 0; 6930 if (align_words + n_units > GP_ARG_NUM_REG) 6931 /* Not all of the arg fits in gprs. Say that it goes in memory too, 6932 using a magic NULL_RTX component. 6933 This is not strictly correct. Only some of the arg belongs in 6934 memory, not all of it. However, the normal scheme using 6935 function_arg_partial_nregs can result in unusual subregs, eg. 6936 (subreg:SI (reg:DF) 4), which are not handled well. The code to 6937 store the whole arg to memory is often more efficient than code 6938 to store pieces, and we know that space is available in the right 6939 place for the whole arg. */ 6940 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 6941 6942 i = 0; 6943 do 6944 { 6945 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words); 6946 rtx off = GEN_INT (i++ * 4); 6947 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 6948 } 6949 while (++align_words < GP_ARG_NUM_REG && --n_units != 0); 6950 6951 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); 6952} 6953 6954/* We have an argument of MODE and TYPE that goes into FPRs or VRs, 6955 but must also be copied into the parameter save area starting at 6956 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding 6957 to the GPRs and/or memory. Return the number of elements used. */ 6958 6959static int 6960rs6000_psave_function_arg (machine_mode mode, const_tree type, 6961 int align_words, rtx *rvec) 6962{ 6963 int k = 0; 6964 6965 if (align_words < GP_ARG_NUM_REG) 6966 { 6967 int n_words = rs6000_arg_size (mode, type); 6968 6969 if (align_words + n_words > GP_ARG_NUM_REG 6970 || mode == BLKmode 6971 || (TARGET_32BIT && TARGET_POWERPC64)) 6972 { 6973 /* If this is partially on the stack, then we only 6974 include the portion actually in registers here. */ 6975 machine_mode rmode = TARGET_32BIT ? SImode : DImode; 6976 int i = 0; 6977 6978 if (align_words + n_words > GP_ARG_NUM_REG) 6979 { 6980 /* Not all of the arg fits in gprs. Say that it goes in memory 6981 too, using a magic NULL_RTX component. Also see comment in 6982 rs6000_mixed_function_arg for why the normal 6983 function_arg_partial_nregs scheme doesn't work in this case. */ 6984 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 6985 } 6986 6987 do 6988 { 6989 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words); 6990 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode)); 6991 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 6992 } 6993 while (++align_words < GP_ARG_NUM_REG && --n_words != 0); 6994 } 6995 else 6996 { 6997 /* The whole arg fits in gprs. */ 6998 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 6999 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx); 7000 } 7001 } 7002 else 7003 { 7004 /* It's entirely in memory. */ 7005 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 7006 } 7007 7008 return k; 7009} 7010 7011/* RVEC is a vector of K components of an argument of mode MODE. 7012 Construct the final function_arg return value from it. */ 7013 7014static rtx 7015rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k) 7016{ 7017 gcc_assert (k >= 1); 7018 7019 /* Avoid returning a PARALLEL in the trivial cases. */ 7020 if (k == 1) 7021 { 7022 if (XEXP (rvec[0], 0) == NULL_RTX) 7023 return NULL_RTX; 7024 7025 if (GET_MODE (XEXP (rvec[0], 0)) == mode) 7026 return XEXP (rvec[0], 0); 7027 } 7028 7029 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); 7030} 7031 7032/* Determine where to put an argument to a function. 7033 Value is zero to push the argument on the stack, 7034 or a hard register in which to store the argument. 7035 7036 CUM is a variable of type CUMULATIVE_ARGS which gives info about 7037 the preceding args and about the function being called. It is 7038 not modified in this routine. 7039 ARG is a description of the argument. 7040 7041 On RS/6000 the first eight words of non-FP are normally in registers 7042 and the rest are pushed. Under AIX, the first 13 FP args are in registers. 7043 Under V.4, the first 8 FP args are in registers. 7044 7045 If this is floating-point and no prototype is specified, we use 7046 both an FP and integer register (or possibly FP reg and stack). Library 7047 functions (when CALL_LIBCALL is set) always have the proper types for args, 7048 so we can pass the FP value just in one register. emit_library_function 7049 doesn't support PARALLEL anyway. 7050 7051 Note that for args passed by reference, function_arg will be called 7052 with ARG describing the pointer to the arg, not the arg itself. */ 7053 7054rtx 7055rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) 7056{ 7057 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 7058 tree type = arg.type; 7059 machine_mode mode = arg.mode; 7060 bool named = arg.named; 7061 enum rs6000_abi abi = DEFAULT_ABI; 7062 machine_mode elt_mode; 7063 int n_elts; 7064 7065 /* We do not allow MMA types being used as function arguments. */ 7066 if (mode == POImode || mode == PXImode) 7067 { 7068 if (TYPE_CANONICAL (type) != NULL_TREE) 7069 type = TYPE_CANONICAL (type); 7070 error ("invalid use of MMA operand of type %qs as a function parameter", 7071 IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)))); 7072 return NULL_RTX; 7073 } 7074 7075 /* Return a marker to indicate whether CR1 needs to set or clear the 7076 bit that V.4 uses to say fp args were passed in registers. 7077 Assume that we don't need the marker for software floating point, 7078 or compiler generated library calls. */ 7079 if (arg.end_marker_p ()) 7080 { 7081 if (abi == ABI_V4 7082 && (cum->call_cookie & CALL_LIBCALL) == 0 7083 && (cum->stdarg 7084 || (cum->nargs_prototype < 0 7085 && (cum->prototype || TARGET_NO_PROTOTYPE))) 7086 && TARGET_HARD_FLOAT) 7087 return GEN_INT (cum->call_cookie 7088 | ((cum->fregno == FP_ARG_MIN_REG) 7089 ? CALL_V4_SET_FP_ARGS 7090 : CALL_V4_CLEAR_FP_ARGS)); 7091 7092 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL); 7093 } 7094 7095 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts); 7096 7097 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) 7098 { 7099 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false); 7100 if (rslt != NULL_RTX) 7101 return rslt; 7102 /* Else fall through to usual handling. */ 7103 } 7104 7105 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named)) 7106 { 7107 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1]; 7108 rtx r, off; 7109 int i, k = 0; 7110 7111 /* Do we also need to pass this argument in the parameter save area? 7112 Library support functions for IEEE 128-bit are assumed to not need the 7113 value passed both in GPRs and in vector registers. */ 7114 if (TARGET_64BIT && !cum->prototype 7115 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode))) 7116 { 7117 int align_words = ROUND_UP (cum->words, 2); 7118 k = rs6000_psave_function_arg (mode, type, align_words, rvec); 7119 } 7120 7121 /* Describe where this argument goes in the vector registers. */ 7122 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++) 7123 { 7124 r = gen_rtx_REG (elt_mode, cum->vregno + i); 7125 off = GEN_INT (i * GET_MODE_SIZE (elt_mode)); 7126 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 7127 } 7128 7129 return rs6000_finish_function_arg (mode, rvec, k); 7130 } 7131 else if (TARGET_ALTIVEC_ABI 7132 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode) 7133 || (type && TREE_CODE (type) == VECTOR_TYPE 7134 && int_size_in_bytes (type) == 16))) 7135 { 7136 if (named || abi == ABI_V4) 7137 return NULL_RTX; 7138 else 7139 { 7140 /* Vector parameters to varargs functions under AIX or Darwin 7141 get passed in memory and possibly also in GPRs. */ 7142 int align, align_words, n_words; 7143 machine_mode part_mode; 7144 7145 /* Vector parameters must be 16-byte aligned. In 32-bit 7146 mode this means we need to take into account the offset 7147 to the parameter save area. In 64-bit mode, they just 7148 have to start on an even word, since the parameter save 7149 area is 16-byte aligned. */ 7150 if (TARGET_32BIT) 7151 align = -(rs6000_parm_offset () + cum->words) & 3; 7152 else 7153 align = cum->words & 1; 7154 align_words = cum->words + align; 7155 7156 /* Out of registers? Memory, then. */ 7157 if (align_words >= GP_ARG_NUM_REG) 7158 return NULL_RTX; 7159 7160 if (TARGET_32BIT && TARGET_POWERPC64) 7161 return rs6000_mixed_function_arg (mode, type, align_words); 7162 7163 /* The vector value goes in GPRs. Only the part of the 7164 value in GPRs is reported here. */ 7165 part_mode = mode; 7166 n_words = rs6000_arg_size (mode, type); 7167 if (align_words + n_words > GP_ARG_NUM_REG) 7168 /* Fortunately, there are only two possibilities, the value 7169 is either wholly in GPRs or half in GPRs and half not. */ 7170 part_mode = DImode; 7171 7172 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words); 7173 } 7174 } 7175 7176 else if (abi == ABI_V4) 7177 { 7178 if (abi_v4_pass_in_fpr (mode, named)) 7179 { 7180 /* _Decimal128 must use an even/odd register pair. This assumes 7181 that the register number is odd when fregno is odd. */ 7182 if (mode == TDmode && (cum->fregno % 2) == 1) 7183 cum->fregno++; 7184 7185 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0) 7186 <= FP_ARG_V4_MAX_REG) 7187 return gen_rtx_REG (mode, cum->fregno); 7188 else 7189 return NULL_RTX; 7190 } 7191 else 7192 { 7193 int n_words = rs6000_arg_size (mode, type); 7194 int gregno = cum->sysv_gregno; 7195 7196 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10). 7197 As does any other 2 word item such as complex int due to a 7198 historical mistake. */ 7199 if (n_words == 2) 7200 gregno += (1 - gregno) & 1; 7201 7202 /* Multi-reg args are not split between registers and stack. */ 7203 if (gregno + n_words - 1 > GP_ARG_MAX_REG) 7204 return NULL_RTX; 7205 7206 if (TARGET_32BIT && TARGET_POWERPC64) 7207 return rs6000_mixed_function_arg (mode, type, 7208 gregno - GP_ARG_MIN_REG); 7209 return gen_rtx_REG (mode, gregno); 7210 } 7211 } 7212 else 7213 { 7214 int align_words = rs6000_parm_start (mode, type, cum->words); 7215 7216 /* _Decimal128 must be passed in an even/odd float register pair. 7217 This assumes that the register number is odd when fregno is odd. */ 7218 if (elt_mode == TDmode && (cum->fregno % 2) == 1) 7219 cum->fregno++; 7220 7221 if (USE_FP_FOR_ARG_P (cum, elt_mode) 7222 && !(TARGET_AIX && !TARGET_ELF 7223 && type != NULL && AGGREGATE_TYPE_P (type))) 7224 { 7225 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1]; 7226 rtx r, off; 7227 int i, k = 0; 7228 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3; 7229 int fpr_words; 7230 7231 /* Do we also need to pass this argument in the parameter 7232 save area? */ 7233 if (type && (cum->nargs_prototype <= 0 7234 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 7235 && TARGET_XL_COMPAT 7236 && align_words >= GP_ARG_NUM_REG))) 7237 k = rs6000_psave_function_arg (mode, type, align_words, rvec); 7238 7239 /* Describe where this argument goes in the fprs. */ 7240 for (i = 0; i < n_elts 7241 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++) 7242 { 7243 /* Check if the argument is split over registers and memory. 7244 This can only ever happen for long double or _Decimal128; 7245 complex types are handled via split_complex_arg. */ 7246 machine_mode fmode = elt_mode; 7247 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1) 7248 { 7249 gcc_assert (FLOAT128_2REG_P (fmode)); 7250 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode; 7251 } 7252 7253 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg); 7254 off = GEN_INT (i * GET_MODE_SIZE (elt_mode)); 7255 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 7256 } 7257 7258 /* If there were not enough FPRs to hold the argument, the rest 7259 usually goes into memory. However, if the current position 7260 is still within the register parameter area, a portion may 7261 actually have to go into GPRs. 7262 7263 Note that it may happen that the portion of the argument 7264 passed in the first "half" of the first GPR was already 7265 passed in the last FPR as well. 7266 7267 For unnamed arguments, we already set up GPRs to cover the 7268 whole argument in rs6000_psave_function_arg, so there is 7269 nothing further to do at this point. */ 7270 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8); 7271 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG 7272 && cum->nargs_prototype > 0) 7273 { 7274 static bool warned; 7275 7276 machine_mode rmode = TARGET_32BIT ? SImode : DImode; 7277 int n_words = rs6000_arg_size (mode, type); 7278 7279 align_words += fpr_words; 7280 n_words -= fpr_words; 7281 7282 do 7283 { 7284 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words); 7285 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode)); 7286 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off); 7287 } 7288 while (++align_words < GP_ARG_NUM_REG && --n_words != 0); 7289 7290 if (!warned && warn_psabi) 7291 { 7292 warned = true; 7293 inform (input_location, 7294 "the ABI of passing homogeneous %<float%> aggregates" 7295 " has changed in GCC 5"); 7296 } 7297 } 7298 7299 return rs6000_finish_function_arg (mode, rvec, k); 7300 } 7301 else if (align_words < GP_ARG_NUM_REG) 7302 { 7303 if (TARGET_32BIT && TARGET_POWERPC64) 7304 return rs6000_mixed_function_arg (mode, type, align_words); 7305 7306 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); 7307 } 7308 else 7309 return NULL_RTX; 7310 } 7311} 7312 7313/* For an arg passed partly in registers and partly in memory, this is 7314 the number of bytes passed in registers. For args passed entirely in 7315 registers or entirely in memory, zero. When an arg is described by a 7316 PARALLEL, perhaps using more than one register type, this function 7317 returns the number of bytes used by the first element of the PARALLEL. */ 7318 7319int 7320rs6000_arg_partial_bytes (cumulative_args_t cum_v, 7321 const function_arg_info &arg) 7322{ 7323 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 7324 bool passed_in_gprs = true; 7325 int ret = 0; 7326 int align_words; 7327 machine_mode elt_mode; 7328 int n_elts; 7329 7330 rs6000_discover_homogeneous_aggregate (arg.mode, arg.type, 7331 &elt_mode, &n_elts); 7332 7333 if (DEFAULT_ABI == ABI_V4) 7334 return 0; 7335 7336 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, arg.named)) 7337 { 7338 /* If we are passing this arg in the fixed parameter save area (gprs or 7339 memory) as well as VRs, we do not use the partial bytes mechanism; 7340 instead, rs6000_function_arg will return a PARALLEL including a memory 7341 element as necessary. Library support functions for IEEE 128-bit are 7342 assumed to not need the value passed both in GPRs and in vector 7343 registers. */ 7344 if (TARGET_64BIT && !cum->prototype 7345 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode))) 7346 return 0; 7347 7348 /* Otherwise, we pass in VRs only. Check for partial copies. */ 7349 passed_in_gprs = false; 7350 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1) 7351 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16; 7352 } 7353 7354 /* In this complicated case we just disable the partial_nregs code. */ 7355 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (arg.mode, arg.type)) 7356 return 0; 7357 7358 align_words = rs6000_parm_start (arg.mode, arg.type, cum->words); 7359 7360 if (USE_FP_FOR_ARG_P (cum, elt_mode) 7361 && !(TARGET_AIX && !TARGET_ELF && arg.aggregate_type_p ())) 7362 { 7363 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3; 7364 7365 /* If we are passing this arg in the fixed parameter save area 7366 (gprs or memory) as well as FPRs, we do not use the partial 7367 bytes mechanism; instead, rs6000_function_arg will return a 7368 PARALLEL including a memory element as necessary. */ 7369 if (arg.type 7370 && (cum->nargs_prototype <= 0 7371 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 7372 && TARGET_XL_COMPAT 7373 && align_words >= GP_ARG_NUM_REG))) 7374 return 0; 7375 7376 /* Otherwise, we pass in FPRs only. Check for partial copies. */ 7377 passed_in_gprs = false; 7378 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1) 7379 { 7380 /* Compute number of bytes / words passed in FPRs. If there 7381 is still space available in the register parameter area 7382 *after* that amount, a part of the argument will be passed 7383 in GPRs. In that case, the total amount passed in any 7384 registers is equal to the amount that would have been passed 7385 in GPRs if everything were passed there, so we fall back to 7386 the GPR code below to compute the appropriate value. */ 7387 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno) 7388 * MIN (8, GET_MODE_SIZE (elt_mode))); 7389 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8); 7390 7391 if (align_words + fpr_words < GP_ARG_NUM_REG) 7392 passed_in_gprs = true; 7393 else 7394 ret = fpr; 7395 } 7396 } 7397 7398 if (passed_in_gprs 7399 && align_words < GP_ARG_NUM_REG 7400 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (arg.mode, arg.type)) 7401 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); 7402 7403 if (ret != 0 && TARGET_DEBUG_ARG) 7404 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret); 7405 7406 return ret; 7407} 7408 7409/* A C expression that indicates when an argument must be passed by 7410 reference. If nonzero for an argument, a copy of that argument is 7411 made in memory and a pointer to the argument is passed instead of 7412 the argument itself. The pointer is passed in whatever way is 7413 appropriate for passing a pointer to that type. 7414 7415 Under V.4, aggregates and long double are passed by reference. 7416 7417 As an extension to all 32-bit ABIs, AltiVec vectors are passed by 7418 reference unless the AltiVec vector extension ABI is in force. 7419 7420 As an extension to all ABIs, variable sized types are passed by 7421 reference. */ 7422 7423bool 7424rs6000_pass_by_reference (cumulative_args_t, const function_arg_info &arg) 7425{ 7426 if (!arg.type) 7427 return 0; 7428 7429 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD 7430 && FLOAT128_IEEE_P (TYPE_MODE (arg.type))) 7431 { 7432 if (TARGET_DEBUG_ARG) 7433 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n"); 7434 return 1; 7435 } 7436 7437 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (arg.type)) 7438 { 7439 if (TARGET_DEBUG_ARG) 7440 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n"); 7441 return 1; 7442 } 7443 7444 if (int_size_in_bytes (arg.type) < 0) 7445 { 7446 if (TARGET_DEBUG_ARG) 7447 fprintf (stderr, "function_arg_pass_by_reference: variable size\n"); 7448 return 1; 7449 } 7450 7451 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector 7452 modes only exist for GCC vector types if -maltivec. */ 7453 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (arg.mode)) 7454 { 7455 if (TARGET_DEBUG_ARG) 7456 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n"); 7457 return 1; 7458 } 7459 7460 /* Pass synthetic vectors in memory. */ 7461 if (TREE_CODE (arg.type) == VECTOR_TYPE 7462 && int_size_in_bytes (arg.type) > (TARGET_ALTIVEC_ABI ? 16 : 8)) 7463 { 7464 static bool warned_for_pass_big_vectors = false; 7465 if (TARGET_DEBUG_ARG) 7466 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n"); 7467 if (!warned_for_pass_big_vectors) 7468 { 7469 warning (OPT_Wpsabi, "GCC vector passed by reference: " 7470 "non-standard ABI extension with no compatibility " 7471 "guarantee"); 7472 warned_for_pass_big_vectors = true; 7473 } 7474 return 1; 7475 } 7476 7477 return 0; 7478} 7479 7480/* Process parameter of type TYPE after ARGS_SO_FAR parameters were 7481 already processes. Return true if the parameter must be passed 7482 (fully or partially) on the stack. */ 7483 7484static bool 7485rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type) 7486{ 7487 int unsignedp; 7488 rtx entry_parm; 7489 7490 /* Catch errors. */ 7491 if (type == NULL || type == error_mark_node) 7492 return true; 7493 7494 /* Handle types with no storage requirement. */ 7495 if (TYPE_MODE (type) == VOIDmode) 7496 return false; 7497 7498 /* Handle complex types. */ 7499 if (TREE_CODE (type) == COMPLEX_TYPE) 7500 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)) 7501 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))); 7502 7503 /* Handle transparent aggregates. */ 7504 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE) 7505 && TYPE_TRANSPARENT_AGGR (type)) 7506 type = TREE_TYPE (first_field (type)); 7507 7508 /* See if this arg was passed by invisible reference. */ 7509 function_arg_info arg (type, /*named=*/true); 7510 apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg); 7511 7512 /* Find mode as it is passed by the ABI. */ 7513 unsignedp = TYPE_UNSIGNED (type); 7514 arg.mode = promote_mode (arg.type, arg.mode, &unsignedp); 7515 7516 /* If we must pass in stack, we need a stack. */ 7517 if (rs6000_must_pass_in_stack (arg)) 7518 return true; 7519 7520 /* If there is no incoming register, we need a stack. */ 7521 entry_parm = rs6000_function_arg (args_so_far, arg); 7522 if (entry_parm == NULL) 7523 return true; 7524 7525 /* Likewise if we need to pass both in registers and on the stack. */ 7526 if (GET_CODE (entry_parm) == PARALLEL 7527 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX) 7528 return true; 7529 7530 /* Also true if we're partially in registers and partially not. */ 7531 if (rs6000_arg_partial_bytes (args_so_far, arg) != 0) 7532 return true; 7533 7534 /* Update info on where next arg arrives in registers. */ 7535 rs6000_function_arg_advance (args_so_far, arg); 7536 return false; 7537} 7538 7539/* Return true if FUN has no prototype, has a variable argument 7540 list, or passes any parameter in memory. */ 7541 7542static bool 7543rs6000_function_parms_need_stack (tree fun, bool incoming) 7544{ 7545 tree fntype, result; 7546 CUMULATIVE_ARGS args_so_far_v; 7547 cumulative_args_t args_so_far; 7548 7549 if (!fun) 7550 /* Must be a libcall, all of which only use reg parms. */ 7551 return false; 7552 7553 fntype = fun; 7554 if (!TYPE_P (fun)) 7555 fntype = TREE_TYPE (fun); 7556 7557 /* Varargs functions need the parameter save area. */ 7558 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype)) 7559 return true; 7560 7561 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX); 7562 args_so_far = pack_cumulative_args (&args_so_far_v); 7563 7564 /* When incoming, we will have been passed the function decl. 7565 It is necessary to use the decl to handle K&R style functions, 7566 where TYPE_ARG_TYPES may not be available. */ 7567 if (incoming) 7568 { 7569 gcc_assert (DECL_P (fun)); 7570 result = DECL_RESULT (fun); 7571 } 7572 else 7573 result = TREE_TYPE (fntype); 7574 7575 if (result && aggregate_value_p (result, fntype)) 7576 { 7577 if (!TYPE_P (result)) 7578 result = TREE_TYPE (result); 7579 result = build_pointer_type (result); 7580 rs6000_parm_needs_stack (args_so_far, result); 7581 } 7582 7583 if (incoming) 7584 { 7585 tree parm; 7586 7587 for (parm = DECL_ARGUMENTS (fun); 7588 parm && parm != void_list_node; 7589 parm = TREE_CHAIN (parm)) 7590 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm))) 7591 return true; 7592 } 7593 else 7594 { 7595 function_args_iterator args_iter; 7596 tree arg_type; 7597 7598 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter) 7599 if (rs6000_parm_needs_stack (args_so_far, arg_type)) 7600 return true; 7601 } 7602 7603 return false; 7604} 7605 7606/* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is 7607 usually a constant depending on the ABI. However, in the ELFv2 ABI 7608 the register parameter area is optional when calling a function that 7609 has a prototype is scope, has no variable argument list, and passes 7610 all parameters in registers. */ 7611 7612int 7613rs6000_reg_parm_stack_space (tree fun, bool incoming) 7614{ 7615 int reg_parm_stack_space; 7616 7617 switch (DEFAULT_ABI) 7618 { 7619 default: 7620 reg_parm_stack_space = 0; 7621 break; 7622 7623 case ABI_AIX: 7624 case ABI_DARWIN: 7625 reg_parm_stack_space = TARGET_64BIT ? 64 : 32; 7626 break; 7627 7628 case ABI_ELFv2: 7629 /* ??? Recomputing this every time is a bit expensive. Is there 7630 a place to cache this information? */ 7631 if (rs6000_function_parms_need_stack (fun, incoming)) 7632 reg_parm_stack_space = TARGET_64BIT ? 64 : 32; 7633 else 7634 reg_parm_stack_space = 0; 7635 break; 7636 } 7637 7638 return reg_parm_stack_space; 7639} 7640 7641static void 7642rs6000_move_block_from_reg (int regno, rtx x, int nregs) 7643{ 7644 int i; 7645 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode; 7646 7647 if (nregs == 0) 7648 return; 7649 7650 for (i = 0; i < nregs; i++) 7651 { 7652 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode)); 7653 if (reload_completed) 7654 { 7655 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0))) 7656 tem = NULL_RTX; 7657 else 7658 tem = simplify_gen_subreg (reg_mode, x, BLKmode, 7659 i * GET_MODE_SIZE (reg_mode)); 7660 } 7661 else 7662 tem = replace_equiv_address (tem, XEXP (tem, 0)); 7663 7664 gcc_assert (tem); 7665 7666 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i)); 7667 } 7668} 7669 7670/* Perform any needed actions needed for a function that is receiving a 7671 variable number of arguments. 7672 7673 CUM is as above. 7674 7675 ARG is the last named argument. 7676 7677 PRETEND_SIZE is a variable that should be set to the amount of stack 7678 that must be pushed by the prolog to pretend that our caller pushed 7679 it. 7680 7681 Normally, this macro will push all remaining incoming registers on the 7682 stack and set PRETEND_SIZE to the length of the registers pushed. */ 7683 7684void 7685setup_incoming_varargs (cumulative_args_t cum, 7686 const function_arg_info &arg, 7687 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) 7688{ 7689 CUMULATIVE_ARGS next_cum; 7690 int reg_size = TARGET_32BIT ? 4 : 8; 7691 rtx save_area = NULL_RTX, mem; 7692 int first_reg_offset; 7693 alias_set_type set; 7694 7695 /* Skip the last named argument. */ 7696 next_cum = *get_cumulative_args (cum); 7697 rs6000_function_arg_advance_1 (&next_cum, arg.mode, arg.type, arg.named, 0); 7698 7699 if (DEFAULT_ABI == ABI_V4) 7700 { 7701 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG; 7702 7703 if (! no_rtl) 7704 { 7705 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0; 7706 HOST_WIDE_INT offset = 0; 7707 7708 /* Try to optimize the size of the varargs save area. 7709 The ABI requires that ap.reg_save_area is doubleword 7710 aligned, but we don't need to allocate space for all 7711 the bytes, only those to which we actually will save 7712 anything. */ 7713 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG) 7714 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset; 7715 if (TARGET_HARD_FLOAT 7716 && next_cum.fregno <= FP_ARG_V4_MAX_REG 7717 && cfun->va_list_fpr_size) 7718 { 7719 if (gpr_reg_num) 7720 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG) 7721 * UNITS_PER_FP_WORD; 7722 if (cfun->va_list_fpr_size 7723 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) 7724 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD; 7725 else 7726 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno) 7727 * UNITS_PER_FP_WORD; 7728 } 7729 if (gpr_reg_num) 7730 { 7731 offset = -((first_reg_offset * reg_size) & ~7); 7732 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size) 7733 { 7734 gpr_reg_num = cfun->va_list_gpr_size; 7735 if (reg_size == 4 && (first_reg_offset & 1)) 7736 gpr_reg_num++; 7737 } 7738 gpr_size = (gpr_reg_num * reg_size + 7) & ~7; 7739 } 7740 else if (fpr_size) 7741 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG) 7742 * UNITS_PER_FP_WORD 7743 - (int) (GP_ARG_NUM_REG * reg_size); 7744 7745 if (gpr_size + fpr_size) 7746 { 7747 rtx reg_save_area 7748 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64); 7749 gcc_assert (MEM_P (reg_save_area)); 7750 reg_save_area = XEXP (reg_save_area, 0); 7751 if (GET_CODE (reg_save_area) == PLUS) 7752 { 7753 gcc_assert (XEXP (reg_save_area, 0) 7754 == virtual_stack_vars_rtx); 7755 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1))); 7756 offset += INTVAL (XEXP (reg_save_area, 1)); 7757 } 7758 else 7759 gcc_assert (reg_save_area == virtual_stack_vars_rtx); 7760 } 7761 7762 cfun->machine->varargs_save_offset = offset; 7763 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset); 7764 } 7765 } 7766 else 7767 { 7768 first_reg_offset = next_cum.words; 7769 save_area = crtl->args.internal_arg_pointer; 7770 7771 if (targetm.calls.must_pass_in_stack (arg)) 7772 first_reg_offset += rs6000_arg_size (TYPE_MODE (arg.type), arg.type); 7773 } 7774 7775 set = get_varargs_alias_set (); 7776 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG 7777 && cfun->va_list_gpr_size) 7778 { 7779 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset; 7780 7781 if (va_list_gpr_counter_field) 7782 /* V4 va_list_gpr_size counts number of registers needed. */ 7783 n_gpr = cfun->va_list_gpr_size; 7784 else 7785 /* char * va_list instead counts number of bytes needed. */ 7786 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size; 7787 7788 if (nregs > n_gpr) 7789 nregs = n_gpr; 7790 7791 mem = gen_rtx_MEM (BLKmode, 7792 plus_constant (Pmode, save_area, 7793 first_reg_offset * reg_size)); 7794 MEM_NOTRAP_P (mem) = 1; 7795 set_mem_alias_set (mem, set); 7796 set_mem_align (mem, BITS_PER_WORD); 7797 7798 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem, 7799 nregs); 7800 } 7801 7802 /* Save FP registers if needed. */ 7803 if (DEFAULT_ABI == ABI_V4 7804 && TARGET_HARD_FLOAT 7805 && ! no_rtl 7806 && next_cum.fregno <= FP_ARG_V4_MAX_REG 7807 && cfun->va_list_fpr_size) 7808 { 7809 int fregno = next_cum.fregno, nregs; 7810 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO); 7811 rtx lab = gen_label_rtx (); 7812 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) 7813 * UNITS_PER_FP_WORD); 7814 7815 emit_jump_insn 7816 (gen_rtx_SET (pc_rtx, 7817 gen_rtx_IF_THEN_ELSE (VOIDmode, 7818 gen_rtx_NE (VOIDmode, cr1, 7819 const0_rtx), 7820 gen_rtx_LABEL_REF (VOIDmode, lab), 7821 pc_rtx))); 7822 7823 for (nregs = 0; 7824 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; 7825 fregno++, off += UNITS_PER_FP_WORD, nregs++) 7826 { 7827 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode, 7828 plus_constant (Pmode, save_area, off)); 7829 MEM_NOTRAP_P (mem) = 1; 7830 set_mem_alias_set (mem, set); 7831 set_mem_align (mem, GET_MODE_ALIGNMENT ( 7832 TARGET_HARD_FLOAT ? DFmode : SFmode)); 7833 emit_move_insn (mem, gen_rtx_REG ( 7834 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno)); 7835 } 7836 7837 emit_label (lab); 7838 } 7839} 7840 7841/* Create the va_list data type. */ 7842 7843tree 7844rs6000_build_builtin_va_list (void) 7845{ 7846 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl; 7847 7848 /* For AIX, prefer 'char *' because that's what the system 7849 header files like. */ 7850 if (DEFAULT_ABI != ABI_V4) 7851 return build_pointer_type (char_type_node); 7852 7853 record = (*lang_hooks.types.make_type) (RECORD_TYPE); 7854 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL, 7855 get_identifier ("__va_list_tag"), record); 7856 7857 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"), 7858 unsigned_char_type_node); 7859 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"), 7860 unsigned_char_type_node); 7861 /* Give the two bytes of padding a name, so that -Wpadded won't warn on 7862 every user file. */ 7863 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL, 7864 get_identifier ("reserved"), short_unsigned_type_node); 7865 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL, 7866 get_identifier ("overflow_arg_area"), 7867 ptr_type_node); 7868 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL, 7869 get_identifier ("reg_save_area"), 7870 ptr_type_node); 7871 7872 va_list_gpr_counter_field = f_gpr; 7873 va_list_fpr_counter_field = f_fpr; 7874 7875 DECL_FIELD_CONTEXT (f_gpr) = record; 7876 DECL_FIELD_CONTEXT (f_fpr) = record; 7877 DECL_FIELD_CONTEXT (f_res) = record; 7878 DECL_FIELD_CONTEXT (f_ovf) = record; 7879 DECL_FIELD_CONTEXT (f_sav) = record; 7880 7881 TYPE_STUB_DECL (record) = type_decl; 7882 TYPE_NAME (record) = type_decl; 7883 TYPE_FIELDS (record) = f_gpr; 7884 DECL_CHAIN (f_gpr) = f_fpr; 7885 DECL_CHAIN (f_fpr) = f_res; 7886 DECL_CHAIN (f_res) = f_ovf; 7887 DECL_CHAIN (f_ovf) = f_sav; 7888 7889 layout_type (record); 7890 7891 /* The correct type is an array type of one element. */ 7892 return build_array_type (record, build_index_type (size_zero_node)); 7893} 7894 7895/* Implement va_start. */ 7896 7897void 7898rs6000_va_start (tree valist, rtx nextarg) 7899{ 7900 HOST_WIDE_INT words, n_gpr, n_fpr; 7901 tree f_gpr, f_fpr, f_res, f_ovf, f_sav; 7902 tree gpr, fpr, ovf, sav, t; 7903 7904 /* Only SVR4 needs something special. */ 7905 if (DEFAULT_ABI != ABI_V4) 7906 { 7907 std_expand_builtin_va_start (valist, nextarg); 7908 return; 7909 } 7910 7911 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 7912 f_fpr = DECL_CHAIN (f_gpr); 7913 f_res = DECL_CHAIN (f_fpr); 7914 f_ovf = DECL_CHAIN (f_res); 7915 f_sav = DECL_CHAIN (f_ovf); 7916 7917 valist = build_simple_mem_ref (valist); 7918 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 7919 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist), 7920 f_fpr, NULL_TREE); 7921 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist), 7922 f_ovf, NULL_TREE); 7923 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist), 7924 f_sav, NULL_TREE); 7925 7926 /* Count number of gp and fp argument registers used. */ 7927 words = crtl->args.info.words; 7928 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG, 7929 GP_ARG_NUM_REG); 7930 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG, 7931 FP_ARG_NUM_REG); 7932 7933 if (TARGET_DEBUG_ARG) 7934 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = " 7935 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n", 7936 words, n_gpr, n_fpr); 7937 7938 if (cfun->va_list_gpr_size) 7939 { 7940 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, 7941 build_int_cst (NULL_TREE, n_gpr)); 7942 TREE_SIDE_EFFECTS (t) = 1; 7943 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7944 } 7945 7946 if (cfun->va_list_fpr_size) 7947 { 7948 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, 7949 build_int_cst (NULL_TREE, n_fpr)); 7950 TREE_SIDE_EFFECTS (t) = 1; 7951 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7952 7953#ifdef HAVE_AS_GNU_ATTRIBUTE 7954 if (call_ABI_of_interest (cfun->decl)) 7955 rs6000_passes_float = true; 7956#endif 7957 } 7958 7959 /* Find the overflow area. */ 7960 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer); 7961 if (words != 0) 7962 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD); 7963 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); 7964 TREE_SIDE_EFFECTS (t) = 1; 7965 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7966 7967 /* If there were no va_arg invocations, don't set up the register 7968 save area. */ 7969 if (!cfun->va_list_gpr_size 7970 && !cfun->va_list_fpr_size 7971 && n_gpr < GP_ARG_NUM_REG 7972 && n_fpr < FP_ARG_V4_MAX_REG) 7973 return; 7974 7975 /* Find the register save area. */ 7976 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx); 7977 if (cfun->machine->varargs_save_offset) 7978 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset); 7979 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); 7980 TREE_SIDE_EFFECTS (t) = 1; 7981 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 7982} 7983 7984/* Implement va_arg. */ 7985 7986tree 7987rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, 7988 gimple_seq *post_p) 7989{ 7990 tree f_gpr, f_fpr, f_res, f_ovf, f_sav; 7991 tree gpr, fpr, ovf, sav, reg, t, u; 7992 int size, rsize, n_reg, sav_ofs, sav_scale; 7993 tree lab_false, lab_over, addr; 7994 int align; 7995 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true); 7996 int regalign = 0; 7997 gimple *stmt; 7998 7999 if (pass_va_arg_by_reference (type)) 8000 { 8001 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p); 8002 return build_va_arg_indirect_ref (t); 8003 } 8004 8005 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an 8006 earlier version of gcc, with the property that it always applied alignment 8007 adjustments to the va-args (even for zero-sized types). The cheapest way 8008 to deal with this is to replicate the effect of the part of 8009 std_gimplify_va_arg_expr that carries out the align adjust, for the case 8010 of relevance. 8011 We don't need to check for pass-by-reference because of the test above. 8012 We can return a simplifed answer, since we know there's no offset to add. */ 8013 8014 if (((TARGET_MACHO 8015 && rs6000_darwin64_abi) 8016 || DEFAULT_ABI == ABI_ELFv2 8017 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) 8018 && integer_zerop (TYPE_SIZE (type))) 8019 { 8020 unsigned HOST_WIDE_INT align, boundary; 8021 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL); 8022 align = PARM_BOUNDARY / BITS_PER_UNIT; 8023 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type); 8024 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT) 8025 boundary = MAX_SUPPORTED_STACK_ALIGNMENT; 8026 boundary /= BITS_PER_UNIT; 8027 if (boundary > align) 8028 { 8029 tree t ; 8030 /* This updates arg ptr by the amount that would be necessary 8031 to align the zero-sized (but not zero-alignment) item. */ 8032 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, 8033 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1)); 8034 gimplify_and_add (t, pre_p); 8035 8036 t = fold_convert (sizetype, valist_tmp); 8037 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp, 8038 fold_convert (TREE_TYPE (valist), 8039 fold_build2 (BIT_AND_EXPR, sizetype, t, 8040 size_int (-boundary)))); 8041 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t); 8042 gimplify_and_add (t, pre_p); 8043 } 8044 /* Since it is zero-sized there's no increment for the item itself. */ 8045 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp); 8046 return build_va_arg_indirect_ref (valist_tmp); 8047 } 8048 8049 if (DEFAULT_ABI != ABI_V4) 8050 { 8051 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE) 8052 { 8053 tree elem_type = TREE_TYPE (type); 8054 machine_mode elem_mode = TYPE_MODE (elem_type); 8055 int elem_size = GET_MODE_SIZE (elem_mode); 8056 8057 if (elem_size < UNITS_PER_WORD) 8058 { 8059 tree real_part, imag_part; 8060 gimple_seq post = NULL; 8061 8062 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, 8063 &post); 8064 /* Copy the value into a temporary, lest the formal temporary 8065 be reused out from under us. */ 8066 real_part = get_initialized_tmp_var (real_part, pre_p, &post); 8067 gimple_seq_add_seq (pre_p, post); 8068 8069 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p, 8070 post_p); 8071 8072 return build2 (COMPLEX_EXPR, type, real_part, imag_part); 8073 } 8074 } 8075 8076 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); 8077 } 8078 8079 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); 8080 f_fpr = DECL_CHAIN (f_gpr); 8081 f_res = DECL_CHAIN (f_fpr); 8082 f_ovf = DECL_CHAIN (f_res); 8083 f_sav = DECL_CHAIN (f_ovf); 8084 8085 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); 8086 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist), 8087 f_fpr, NULL_TREE); 8088 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist), 8089 f_ovf, NULL_TREE); 8090 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist), 8091 f_sav, NULL_TREE); 8092 8093 size = int_size_in_bytes (type); 8094 rsize = (size + 3) / 4; 8095 int pad = 4 * rsize - size; 8096 align = 1; 8097 8098 machine_mode mode = TYPE_MODE (type); 8099 if (abi_v4_pass_in_fpr (mode, false)) 8100 { 8101 /* FP args go in FP registers, if present. */ 8102 reg = fpr; 8103 n_reg = (size + 7) / 8; 8104 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4; 8105 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4); 8106 if (mode != SFmode && mode != SDmode) 8107 align = 8; 8108 } 8109 else 8110 { 8111 /* Otherwise into GP registers. */ 8112 reg = gpr; 8113 n_reg = rsize; 8114 sav_ofs = 0; 8115 sav_scale = 4; 8116 if (n_reg == 2) 8117 align = 8; 8118 } 8119 8120 /* Pull the value out of the saved registers.... */ 8121 8122 lab_over = NULL; 8123 addr = create_tmp_var (ptr_type_node, "addr"); 8124 8125 /* AltiVec vectors never go in registers when -mabi=altivec. */ 8126 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) 8127 align = 16; 8128 else 8129 { 8130 lab_false = create_artificial_label (input_location); 8131 lab_over = create_artificial_label (input_location); 8132 8133 /* Long long is aligned in the registers. As are any other 2 gpr 8134 item such as complex int due to a historical mistake. */ 8135 u = reg; 8136 if (n_reg == 2 && reg == gpr) 8137 { 8138 regalign = 1; 8139 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg), 8140 build_int_cst (TREE_TYPE (reg), n_reg - 1)); 8141 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), 8142 unshare_expr (reg), u); 8143 } 8144 /* _Decimal128 is passed in even/odd fpr pairs; the stored 8145 reg number is 0 for f1, so we want to make it odd. */ 8146 else if (reg == fpr && mode == TDmode) 8147 { 8148 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg), 8149 build_int_cst (TREE_TYPE (reg), 1)); 8150 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t); 8151 } 8152 8153 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1)); 8154 t = build2 (GE_EXPR, boolean_type_node, u, t); 8155 u = build1 (GOTO_EXPR, void_type_node, lab_false); 8156 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); 8157 gimplify_and_add (t, pre_p); 8158 8159 t = sav; 8160 if (sav_ofs) 8161 t = fold_build_pointer_plus_hwi (sav, sav_ofs); 8162 8163 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg), 8164 build_int_cst (TREE_TYPE (reg), n_reg)); 8165 u = fold_convert (sizetype, u); 8166 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale)); 8167 t = fold_build_pointer_plus (t, u); 8168 8169 /* _Decimal32 varargs are located in the second word of the 64-bit 8170 FP register for 32-bit binaries. */ 8171 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode) 8172 t = fold_build_pointer_plus_hwi (t, size); 8173 8174 /* Args are passed right-aligned. */ 8175 if (BYTES_BIG_ENDIAN) 8176 t = fold_build_pointer_plus_hwi (t, pad); 8177 8178 gimplify_assign (addr, t, pre_p); 8179 8180 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); 8181 8182 stmt = gimple_build_label (lab_false); 8183 gimple_seq_add_stmt (pre_p, stmt); 8184 8185 if ((n_reg == 2 && !regalign) || n_reg > 2) 8186 { 8187 /* Ensure that we don't find any more args in regs. 8188 Alignment has taken care of for special cases. */ 8189 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p); 8190 } 8191 } 8192 8193 /* ... otherwise out of the overflow area. */ 8194 8195 /* Care for on-stack alignment if needed. */ 8196 t = ovf; 8197 if (align != 1) 8198 { 8199 t = fold_build_pointer_plus_hwi (t, align - 1); 8200 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, 8201 build_int_cst (TREE_TYPE (t), -align)); 8202 } 8203 8204 /* Args are passed right-aligned. */ 8205 if (BYTES_BIG_ENDIAN) 8206 t = fold_build_pointer_plus_hwi (t, pad); 8207 8208 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); 8209 8210 gimplify_assign (unshare_expr (addr), t, pre_p); 8211 8212 t = fold_build_pointer_plus_hwi (t, size); 8213 gimplify_assign (unshare_expr (ovf), t, pre_p); 8214 8215 if (lab_over) 8216 { 8217 stmt = gimple_build_label (lab_over); 8218 gimple_seq_add_stmt (pre_p, stmt); 8219 } 8220 8221 if (STRICT_ALIGNMENT 8222 && (TYPE_ALIGN (type) 8223 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align))) 8224 { 8225 /* The value (of type complex double, for example) may not be 8226 aligned in memory in the saved registers, so copy via a 8227 temporary. (This is the same code as used for SPARC.) */ 8228 tree tmp = create_tmp_var (type, "va_arg_tmp"); 8229 tree dest_addr = build_fold_addr_expr (tmp); 8230 8231 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY), 8232 3, dest_addr, addr, size_int (rsize * 4)); 8233 TREE_ADDRESSABLE (tmp) = 1; 8234 8235 gimplify_and_add (copy, pre_p); 8236 addr = dest_addr; 8237 } 8238 8239 addr = fold_convert (ptrtype, addr); 8240 return build_va_arg_indirect_ref (addr); 8241} 8242 8243/* Builtins. */ 8244 8245static void 8246def_builtin (const char *name, tree type, enum rs6000_builtins code) 8247{ 8248 tree t; 8249 unsigned classify = rs6000_builtin_info[(int)code].attr; 8250 const char *attr_string = ""; 8251 8252 /* Don't define the builtin if it doesn't have a type. See PR92661. */ 8253 if (type == NULL_TREE) 8254 return; 8255 8256 gcc_assert (name != NULL); 8257 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT)); 8258 8259 if (rs6000_builtin_decls[(int)code]) 8260 fatal_error (input_location, 8261 "internal error: builtin function %qs already processed", 8262 name); 8263 8264 rs6000_builtin_decls[(int)code] = t = 8265 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE); 8266 8267 /* Set any special attributes. */ 8268 if ((classify & RS6000_BTC_CONST) != 0) 8269 { 8270 /* const function, function only depends on the inputs. */ 8271 TREE_READONLY (t) = 1; 8272 TREE_NOTHROW (t) = 1; 8273 attr_string = ", const"; 8274 } 8275 else if ((classify & RS6000_BTC_PURE) != 0) 8276 { 8277 /* pure function, function can read global memory, but does not set any 8278 external state. */ 8279 DECL_PURE_P (t) = 1; 8280 TREE_NOTHROW (t) = 1; 8281 attr_string = ", pure"; 8282 } 8283 else if ((classify & RS6000_BTC_FP) != 0) 8284 { 8285 /* Function is a math function. If rounding mode is on, then treat the 8286 function as not reading global memory, but it can have arbitrary side 8287 effects. If it is off, then assume the function is a const function. 8288 This mimics the ATTR_MATHFN_FPROUNDING attribute in 8289 builtin-attribute.def that is used for the math functions. */ 8290 TREE_NOTHROW (t) = 1; 8291 if (flag_rounding_math) 8292 { 8293 DECL_PURE_P (t) = 1; 8294 DECL_IS_NOVOPS (t) = 1; 8295 attr_string = ", fp, pure"; 8296 } 8297 else 8298 { 8299 TREE_READONLY (t) = 1; 8300 attr_string = ", fp, const"; 8301 } 8302 } 8303 else if ((classify & (RS6000_BTC_QUAD | RS6000_BTC_PAIR)) != 0) 8304 /* The function uses a register quad and/or pair. Nothing to do. */ 8305 ; 8306 else if ((classify & RS6000_BTC_ATTR_MASK) != 0) 8307 gcc_unreachable (); 8308 8309 if (TARGET_DEBUG_BUILTIN) 8310 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n", 8311 (int)code, name, attr_string); 8312} 8313 8314static const struct builtin_compatibility bdesc_compat[] = 8315{ 8316#define RS6000_BUILTIN_COMPAT 8317#include "rs6000-builtin.def" 8318}; 8319#undef RS6000_BUILTIN_COMPAT 8320 8321/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ 8322 8323#undef RS6000_BUILTIN_0 8324#undef RS6000_BUILTIN_1 8325#undef RS6000_BUILTIN_2 8326#undef RS6000_BUILTIN_3 8327#undef RS6000_BUILTIN_A 8328#undef RS6000_BUILTIN_D 8329#undef RS6000_BUILTIN_H 8330#undef RS6000_BUILTIN_M 8331#undef RS6000_BUILTIN_P 8332#undef RS6000_BUILTIN_X 8333 8334#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8335#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8336#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8337#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \ 8338 { MASK, ICODE, NAME, ENUM }, 8339 8340#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8341#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8342#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8343#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8344#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8345#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8346 8347static const struct builtin_description bdesc_3arg[] = 8348{ 8349#include "rs6000-builtin.def" 8350}; 8351 8352/* DST operations: void foo (void *, const int, const char). */ 8353 8354#undef RS6000_BUILTIN_0 8355#undef RS6000_BUILTIN_1 8356#undef RS6000_BUILTIN_2 8357#undef RS6000_BUILTIN_3 8358#undef RS6000_BUILTIN_A 8359#undef RS6000_BUILTIN_D 8360#undef RS6000_BUILTIN_H 8361#undef RS6000_BUILTIN_M 8362#undef RS6000_BUILTIN_P 8363#undef RS6000_BUILTIN_X 8364 8365#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8366#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8367#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8368#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8369#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8370#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ 8371 { MASK, ICODE, NAME, ENUM }, 8372 8373#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8374#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8375#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8376#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8377 8378static const struct builtin_description bdesc_dst[] = 8379{ 8380#include "rs6000-builtin.def" 8381}; 8382 8383/* Simple binary operations: VECc = foo (VECa, VECb). */ 8384 8385#undef RS6000_BUILTIN_0 8386#undef RS6000_BUILTIN_1 8387#undef RS6000_BUILTIN_2 8388#undef RS6000_BUILTIN_3 8389#undef RS6000_BUILTIN_A 8390#undef RS6000_BUILTIN_D 8391#undef RS6000_BUILTIN_H 8392#undef RS6000_BUILTIN_M 8393#undef RS6000_BUILTIN_P 8394#undef RS6000_BUILTIN_X 8395 8396#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8397#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8398#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \ 8399 { MASK, ICODE, NAME, ENUM }, 8400 8401#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8402#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8403#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8404#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8405#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8406#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8407#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8408 8409static const struct builtin_description bdesc_2arg[] = 8410{ 8411#include "rs6000-builtin.def" 8412}; 8413 8414#undef RS6000_BUILTIN_0 8415#undef RS6000_BUILTIN_1 8416#undef RS6000_BUILTIN_2 8417#undef RS6000_BUILTIN_3 8418#undef RS6000_BUILTIN_A 8419#undef RS6000_BUILTIN_D 8420#undef RS6000_BUILTIN_H 8421#undef RS6000_BUILTIN_M 8422#undef RS6000_BUILTIN_P 8423#undef RS6000_BUILTIN_X 8424 8425#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8426#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8427#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8428#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8429#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8430#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8431#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8432#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8433#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ 8434 { MASK, ICODE, NAME, ENUM }, 8435 8436#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8437 8438/* AltiVec predicates. */ 8439 8440static const struct builtin_description bdesc_altivec_preds[] = 8441{ 8442#include "rs6000-builtin.def" 8443}; 8444 8445/* ABS* operations. */ 8446 8447#undef RS6000_BUILTIN_0 8448#undef RS6000_BUILTIN_1 8449#undef RS6000_BUILTIN_2 8450#undef RS6000_BUILTIN_3 8451#undef RS6000_BUILTIN_A 8452#undef RS6000_BUILTIN_D 8453#undef RS6000_BUILTIN_H 8454#undef RS6000_BUILTIN_M 8455#undef RS6000_BUILTIN_P 8456#undef RS6000_BUILTIN_X 8457 8458#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8459#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8460#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8461#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8462#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \ 8463 { MASK, ICODE, NAME, ENUM }, 8464 8465#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8466#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8467#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8468#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8469#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8470 8471static const struct builtin_description bdesc_abs[] = 8472{ 8473#include "rs6000-builtin.def" 8474}; 8475 8476/* Simple unary operations: VECb = foo (unsigned literal) or VECb = 8477 foo (VECa). */ 8478 8479#undef RS6000_BUILTIN_0 8480#undef RS6000_BUILTIN_1 8481#undef RS6000_BUILTIN_2 8482#undef RS6000_BUILTIN_3 8483#undef RS6000_BUILTIN_A 8484#undef RS6000_BUILTIN_D 8485#undef RS6000_BUILTIN_H 8486#undef RS6000_BUILTIN_M 8487#undef RS6000_BUILTIN_P 8488#undef RS6000_BUILTIN_X 8489 8490#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8491#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ 8492 { MASK, ICODE, NAME, ENUM }, 8493 8494#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8495#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8496#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8497#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8498#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8499#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8500#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8501#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8502 8503static const struct builtin_description bdesc_1arg[] = 8504{ 8505#include "rs6000-builtin.def" 8506}; 8507 8508/* Simple no-argument operations: result = __builtin_darn_32 () */ 8509 8510#undef RS6000_BUILTIN_0 8511#undef RS6000_BUILTIN_1 8512#undef RS6000_BUILTIN_2 8513#undef RS6000_BUILTIN_3 8514#undef RS6000_BUILTIN_A 8515#undef RS6000_BUILTIN_D 8516#undef RS6000_BUILTIN_H 8517#undef RS6000_BUILTIN_M 8518#undef RS6000_BUILTIN_P 8519#undef RS6000_BUILTIN_X 8520 8521#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ 8522 { MASK, ICODE, NAME, ENUM }, 8523 8524#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8525#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8526#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8527#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8528#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8529#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8530#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8531#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8532#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8533 8534static const struct builtin_description bdesc_0arg[] = 8535{ 8536#include "rs6000-builtin.def" 8537}; 8538 8539/* HTM builtins. */ 8540#undef RS6000_BUILTIN_0 8541#undef RS6000_BUILTIN_1 8542#undef RS6000_BUILTIN_2 8543#undef RS6000_BUILTIN_3 8544#undef RS6000_BUILTIN_A 8545#undef RS6000_BUILTIN_D 8546#undef RS6000_BUILTIN_H 8547#undef RS6000_BUILTIN_M 8548#undef RS6000_BUILTIN_P 8549#undef RS6000_BUILTIN_X 8550 8551#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8552#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8553#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8554#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8555#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8556#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8557#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ 8558 { MASK, ICODE, NAME, ENUM }, 8559 8560#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) 8561#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8562#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8563 8564static const struct builtin_description bdesc_htm[] = 8565{ 8566#include "rs6000-builtin.def" 8567}; 8568 8569/* MMA builtins. */ 8570#undef RS6000_BUILTIN_0 8571#undef RS6000_BUILTIN_1 8572#undef RS6000_BUILTIN_2 8573#undef RS6000_BUILTIN_3 8574#undef RS6000_BUILTIN_A 8575#undef RS6000_BUILTIN_D 8576#undef RS6000_BUILTIN_H 8577#undef RS6000_BUILTIN_M 8578#undef RS6000_BUILTIN_P 8579#undef RS6000_BUILTIN_X 8580 8581#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) 8582#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) 8583#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) 8584#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) 8585#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) 8586#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) 8587#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) 8588#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) 8589#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \ 8590 { MASK, ICODE, NAME, ENUM }, 8591 8592#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) 8593#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) 8594 8595static const struct builtin_description bdesc_mma[] = 8596{ 8597#include "rs6000-builtin.def" 8598}; 8599 8600#undef RS6000_BUILTIN_0 8601#undef RS6000_BUILTIN_1 8602#undef RS6000_BUILTIN_2 8603#undef RS6000_BUILTIN_3 8604#undef RS6000_BUILTIN_4 8605#undef RS6000_BUILTIN_A 8606#undef RS6000_BUILTIN_D 8607#undef RS6000_BUILTIN_H 8608#undef RS6000_BUILTIN_M 8609#undef RS6000_BUILTIN_P 8610#undef RS6000_BUILTIN_X 8611 8612/* Return true if a builtin function is overloaded. */ 8613bool 8614rs6000_overloaded_builtin_p (enum rs6000_builtins fncode) 8615{ 8616 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0; 8617} 8618 8619const char * 8620rs6000_overloaded_builtin_name (enum rs6000_builtins fncode) 8621{ 8622 return rs6000_builtin_info[(int)fncode].name; 8623} 8624 8625/* Expand an expression EXP that calls a builtin without arguments. */ 8626static rtx 8627rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target) 8628{ 8629 rtx pat; 8630 machine_mode tmode = insn_data[icode].operand[0].mode; 8631 8632 if (icode == CODE_FOR_nothing) 8633 /* Builtin not supported on this processor. */ 8634 return 0; 8635 8636 if (icode == CODE_FOR_rs6000_mffsl 8637 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) 8638 { 8639 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>"); 8640 return const0_rtx; 8641 } 8642 8643 if (target == 0 8644 || GET_MODE (target) != tmode 8645 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 8646 target = gen_reg_rtx (tmode); 8647 8648 pat = GEN_FCN (icode) (target); 8649 if (! pat) 8650 return 0; 8651 emit_insn (pat); 8652 8653 return target; 8654} 8655 8656 8657static rtx 8658rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp) 8659{ 8660 rtx pat; 8661 tree arg0 = CALL_EXPR_ARG (exp, 0); 8662 tree arg1 = CALL_EXPR_ARG (exp, 1); 8663 rtx op0 = expand_normal (arg0); 8664 rtx op1 = expand_normal (arg1); 8665 machine_mode mode0 = insn_data[icode].operand[0].mode; 8666 machine_mode mode1 = insn_data[icode].operand[1].mode; 8667 8668 if (icode == CODE_FOR_nothing) 8669 /* Builtin not supported on this processor. */ 8670 return 0; 8671 8672 /* If we got invalid arguments bail out before generating bad rtl. */ 8673 if (arg0 == error_mark_node || arg1 == error_mark_node) 8674 return const0_rtx; 8675 8676 if (!CONST_INT_P (op0) 8677 || INTVAL (op0) > 255 8678 || INTVAL (op0) < 0) 8679 { 8680 error ("argument 1 must be an 8-bit field value"); 8681 return const0_rtx; 8682 } 8683 8684 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 8685 op0 = copy_to_mode_reg (mode0, op0); 8686 8687 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) 8688 op1 = copy_to_mode_reg (mode1, op1); 8689 8690 pat = GEN_FCN (icode) (op0, op1); 8691 if (!pat) 8692 return const0_rtx; 8693 emit_insn (pat); 8694 8695 return NULL_RTX; 8696} 8697 8698static rtx 8699rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp) 8700{ 8701 rtx pat; 8702 tree arg0 = CALL_EXPR_ARG (exp, 0); 8703 rtx op0 = expand_normal (arg0); 8704 8705 if (icode == CODE_FOR_nothing) 8706 /* Builtin not supported on this processor. */ 8707 return 0; 8708 8709 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) 8710 { 8711 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with " 8712 "%<-msoft-float%>"); 8713 return const0_rtx; 8714 } 8715 8716 /* If we got invalid arguments bail out before generating bad rtl. */ 8717 if (arg0 == error_mark_node) 8718 return const0_rtx; 8719 8720 /* Only allow bit numbers 0 to 31. */ 8721 if (!u5bit_cint_operand (op0, VOIDmode)) 8722 { 8723 error ("Argument must be a constant between 0 and 31."); 8724 return const0_rtx; 8725 } 8726 8727 pat = GEN_FCN (icode) (op0); 8728 if (!pat) 8729 return const0_rtx; 8730 emit_insn (pat); 8731 8732 return NULL_RTX; 8733} 8734 8735static rtx 8736rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp) 8737{ 8738 rtx pat; 8739 tree arg0 = CALL_EXPR_ARG (exp, 0); 8740 rtx op0 = expand_normal (arg0); 8741 machine_mode mode0 = insn_data[icode].operand[0].mode; 8742 8743 if (icode == CODE_FOR_nothing) 8744 /* Builtin not supported on this processor. */ 8745 return 0; 8746 8747 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) 8748 { 8749 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>"); 8750 return const0_rtx; 8751 } 8752 8753 /* If we got invalid arguments bail out before generating bad rtl. */ 8754 if (arg0 == error_mark_node) 8755 return const0_rtx; 8756 8757 /* If the argument is a constant, check the range. Argument can only be a 8758 2-bit value. Unfortunately, can't check the range of the value at 8759 compile time if the argument is a variable. The least significant two 8760 bits of the argument, regardless of type, are used to set the rounding 8761 mode. All other bits are ignored. */ 8762 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode)) 8763 { 8764 error ("Argument must be a value between 0 and 3."); 8765 return const0_rtx; 8766 } 8767 8768 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 8769 op0 = copy_to_mode_reg (mode0, op0); 8770 8771 pat = GEN_FCN (icode) (op0); 8772 if (!pat) 8773 return const0_rtx; 8774 emit_insn (pat); 8775 8776 return NULL_RTX; 8777} 8778static rtx 8779rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp) 8780{ 8781 rtx pat; 8782 tree arg0 = CALL_EXPR_ARG (exp, 0); 8783 rtx op0 = expand_normal (arg0); 8784 machine_mode mode0 = insn_data[icode].operand[0].mode; 8785 8786 if (TARGET_32BIT) 8787 /* Builtin not supported in 32-bit mode. */ 8788 fatal_error (input_location, 8789 "%<__builtin_set_fpscr_drn%> is not supported " 8790 "in 32-bit mode"); 8791 8792 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) 8793 { 8794 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>"); 8795 return const0_rtx; 8796 } 8797 8798 if (icode == CODE_FOR_nothing) 8799 /* Builtin not supported on this processor. */ 8800 return 0; 8801 8802 /* If we got invalid arguments bail out before generating bad rtl. */ 8803 if (arg0 == error_mark_node) 8804 return const0_rtx; 8805 8806 /* If the argument is a constant, check the range. Agrument can only be a 8807 3-bit value. Unfortunately, can't check the range of the value at 8808 compile time if the argument is a variable. The least significant two 8809 bits of the argument, regardless of type, are used to set the rounding 8810 mode. All other bits are ignored. */ 8811 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode)) 8812 { 8813 error ("Argument must be a value between 0 and 7."); 8814 return const0_rtx; 8815 } 8816 8817 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 8818 op0 = copy_to_mode_reg (mode0, op0); 8819 8820 pat = GEN_FCN (icode) (op0); 8821 if (! pat) 8822 return const0_rtx; 8823 emit_insn (pat); 8824 8825 return NULL_RTX; 8826} 8827 8828static rtx 8829rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) 8830{ 8831 rtx pat; 8832 tree arg0 = CALL_EXPR_ARG (exp, 0); 8833 rtx op0 = expand_normal (arg0); 8834 machine_mode tmode = insn_data[icode].operand[0].mode; 8835 machine_mode mode0 = insn_data[icode].operand[1].mode; 8836 8837 if (icode == CODE_FOR_nothing) 8838 /* Builtin not supported on this processor. */ 8839 return 0; 8840 8841 /* If we got invalid arguments bail out before generating bad rtl. */ 8842 if (arg0 == error_mark_node) 8843 return const0_rtx; 8844 8845 if (icode == CODE_FOR_altivec_vspltisb 8846 || icode == CODE_FOR_altivec_vspltish 8847 || icode == CODE_FOR_altivec_vspltisw) 8848 { 8849 /* Only allow 5-bit *signed* literals. */ 8850 if (!CONST_INT_P (op0) 8851 || INTVAL (op0) > 15 8852 || INTVAL (op0) < -16) 8853 { 8854 error ("argument 1 must be a 5-bit signed literal"); 8855 return CONST0_RTX (tmode); 8856 } 8857 } 8858 8859 if (target == 0 8860 || GET_MODE (target) != tmode 8861 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 8862 target = gen_reg_rtx (tmode); 8863 8864 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 8865 op0 = copy_to_mode_reg (mode0, op0); 8866 8867 pat = GEN_FCN (icode) (target, op0); 8868 if (! pat) 8869 return 0; 8870 emit_insn (pat); 8871 8872 return target; 8873} 8874 8875static rtx 8876altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target) 8877{ 8878 rtx pat, scratch1, scratch2; 8879 tree arg0 = CALL_EXPR_ARG (exp, 0); 8880 rtx op0 = expand_normal (arg0); 8881 machine_mode tmode = insn_data[icode].operand[0].mode; 8882 machine_mode mode0 = insn_data[icode].operand[1].mode; 8883 8884 /* If we have invalid arguments, bail out before generating bad rtl. */ 8885 if (arg0 == error_mark_node) 8886 return const0_rtx; 8887 8888 if (target == 0 8889 || GET_MODE (target) != tmode 8890 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 8891 target = gen_reg_rtx (tmode); 8892 8893 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 8894 op0 = copy_to_mode_reg (mode0, op0); 8895 8896 scratch1 = gen_reg_rtx (mode0); 8897 scratch2 = gen_reg_rtx (mode0); 8898 8899 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); 8900 if (! pat) 8901 return 0; 8902 emit_insn (pat); 8903 8904 return target; 8905} 8906 8907static rtx 8908rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) 8909{ 8910 rtx pat; 8911 tree arg0 = CALL_EXPR_ARG (exp, 0); 8912 tree arg1 = CALL_EXPR_ARG (exp, 1); 8913 rtx op0 = expand_normal (arg0); 8914 rtx op1 = expand_normal (arg1); 8915 machine_mode tmode = insn_data[icode].operand[0].mode; 8916 machine_mode mode0 = insn_data[icode].operand[1].mode; 8917 machine_mode mode1 = insn_data[icode].operand[2].mode; 8918 8919 if (icode == CODE_FOR_nothing) 8920 /* Builtin not supported on this processor. */ 8921 return 0; 8922 8923 /* If we got invalid arguments bail out before generating bad rtl. */ 8924 if (arg0 == error_mark_node || arg1 == error_mark_node) 8925 return const0_rtx; 8926 8927 if (icode == CODE_FOR_unpackv1ti 8928 || icode == CODE_FOR_unpackkf 8929 || icode == CODE_FOR_unpacktf 8930 || icode == CODE_FOR_unpackif 8931 || icode == CODE_FOR_unpacktd) 8932 { 8933 /* Only allow 1-bit unsigned literals. */ 8934 STRIP_NOPS (arg1); 8935 if (TREE_CODE (arg1) != INTEGER_CST 8936 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1)) 8937 { 8938 error ("argument 2 must be a 1-bit unsigned literal"); 8939 return CONST0_RTX (tmode); 8940 } 8941 } 8942 else if (icode == CODE_FOR_altivec_vspltw) 8943 { 8944 /* Only allow 2-bit unsigned literals. */ 8945 STRIP_NOPS (arg1); 8946 if (TREE_CODE (arg1) != INTEGER_CST 8947 || TREE_INT_CST_LOW (arg1) & ~3) 8948 { 8949 error ("argument 2 must be a 2-bit unsigned literal"); 8950 return CONST0_RTX (tmode); 8951 } 8952 } 8953 else if (icode == CODE_FOR_altivec_vsplth) 8954 { 8955 /* Only allow 3-bit unsigned literals. */ 8956 STRIP_NOPS (arg1); 8957 if (TREE_CODE (arg1) != INTEGER_CST 8958 || TREE_INT_CST_LOW (arg1) & ~7) 8959 { 8960 error ("argument 2 must be a 3-bit unsigned literal"); 8961 return CONST0_RTX (tmode); 8962 } 8963 } 8964 else if (icode == CODE_FOR_altivec_vspltb) 8965 { 8966 /* Only allow 4-bit unsigned literals. */ 8967 STRIP_NOPS (arg1); 8968 if (TREE_CODE (arg1) != INTEGER_CST 8969 || TREE_INT_CST_LOW (arg1) & ~15) 8970 { 8971 error ("argument 2 must be a 4-bit unsigned literal"); 8972 return CONST0_RTX (tmode); 8973 } 8974 } 8975 else if (icode == CODE_FOR_altivec_vcfux 8976 || icode == CODE_FOR_altivec_vcfsx 8977 || icode == CODE_FOR_altivec_vctsxs 8978 || icode == CODE_FOR_altivec_vctuxs) 8979 { 8980 /* Only allow 5-bit unsigned literals. */ 8981 STRIP_NOPS (arg1); 8982 if (TREE_CODE (arg1) != INTEGER_CST 8983 || TREE_INT_CST_LOW (arg1) & ~0x1f) 8984 { 8985 error ("argument 2 must be a 5-bit unsigned literal"); 8986 return CONST0_RTX (tmode); 8987 } 8988 } 8989 else if (icode == CODE_FOR_dfptstsfi_eq_dd 8990 || icode == CODE_FOR_dfptstsfi_lt_dd 8991 || icode == CODE_FOR_dfptstsfi_gt_dd 8992 || icode == CODE_FOR_dfptstsfi_unordered_dd 8993 || icode == CODE_FOR_dfptstsfi_eq_td 8994 || icode == CODE_FOR_dfptstsfi_lt_td 8995 || icode == CODE_FOR_dfptstsfi_gt_td 8996 || icode == CODE_FOR_dfptstsfi_unordered_td) 8997 { 8998 /* Only allow 6-bit unsigned literals. */ 8999 STRIP_NOPS (arg0); 9000 if (TREE_CODE (arg0) != INTEGER_CST 9001 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63)) 9002 { 9003 error ("argument 1 must be a 6-bit unsigned literal"); 9004 return CONST0_RTX (tmode); 9005 } 9006 } 9007 else if (icode == CODE_FOR_xststdcqp_kf 9008 || icode == CODE_FOR_xststdcqp_tf 9009 || icode == CODE_FOR_xststdcdp 9010 || icode == CODE_FOR_xststdcsp 9011 || icode == CODE_FOR_xvtstdcdp 9012 || icode == CODE_FOR_xvtstdcsp) 9013 { 9014 /* Only allow 7-bit unsigned literals. */ 9015 STRIP_NOPS (arg1); 9016 if (TREE_CODE (arg1) != INTEGER_CST 9017 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127)) 9018 { 9019 error ("argument 2 must be a 7-bit unsigned literal"); 9020 return CONST0_RTX (tmode); 9021 } 9022 } 9023 9024 if (target == 0 9025 || GET_MODE (target) != tmode 9026 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 9027 target = gen_reg_rtx (tmode); 9028 9029 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 9030 op0 = copy_to_mode_reg (mode0, op0); 9031 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 9032 op1 = copy_to_mode_reg (mode1, op1); 9033 9034 pat = GEN_FCN (icode) (target, op0, op1); 9035 if (! pat) 9036 return 0; 9037 emit_insn (pat); 9038 9039 return target; 9040} 9041 9042static rtx 9043altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) 9044{ 9045 rtx pat, scratch; 9046 tree cr6_form = CALL_EXPR_ARG (exp, 0); 9047 tree arg0 = CALL_EXPR_ARG (exp, 1); 9048 tree arg1 = CALL_EXPR_ARG (exp, 2); 9049 rtx op0 = expand_normal (arg0); 9050 rtx op1 = expand_normal (arg1); 9051 machine_mode tmode = SImode; 9052 machine_mode mode0 = insn_data[icode].operand[1].mode; 9053 machine_mode mode1 = insn_data[icode].operand[2].mode; 9054 int cr6_form_int; 9055 9056 if (TREE_CODE (cr6_form) != INTEGER_CST) 9057 { 9058 error ("argument 1 of %qs must be a constant", 9059 "__builtin_altivec_predicate"); 9060 return const0_rtx; 9061 } 9062 else 9063 cr6_form_int = TREE_INT_CST_LOW (cr6_form); 9064 9065 gcc_assert (mode0 == mode1); 9066 9067 /* If we have invalid arguments, bail out before generating bad rtl. */ 9068 if (arg0 == error_mark_node || arg1 == error_mark_node) 9069 return const0_rtx; 9070 9071 if (target == 0 9072 || GET_MODE (target) != tmode 9073 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 9074 target = gen_reg_rtx (tmode); 9075 9076 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 9077 op0 = copy_to_mode_reg (mode0, op0); 9078 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 9079 op1 = copy_to_mode_reg (mode1, op1); 9080 9081 /* Note that for many of the relevant operations (e.g. cmpne or 9082 cmpeq) with float or double operands, it makes more sense for the 9083 mode of the allocated scratch register to select a vector of 9084 integer. But the choice to copy the mode of operand 0 was made 9085 long ago and there are no plans to change it. */ 9086 scratch = gen_reg_rtx (mode0); 9087 9088 pat = GEN_FCN (icode) (scratch, op0, op1); 9089 if (! pat) 9090 return 0; 9091 emit_insn (pat); 9092 9093 /* The vec_any* and vec_all* predicates use the same opcodes for two 9094 different operations, but the bits in CR6 will be different 9095 depending on what information we want. So we have to play tricks 9096 with CR6 to get the right bits out. 9097 9098 If you think this is disgusting, look at the specs for the 9099 AltiVec predicates. */ 9100 9101 switch (cr6_form_int) 9102 { 9103 case 0: 9104 emit_insn (gen_cr6_test_for_zero (target)); 9105 break; 9106 case 1: 9107 emit_insn (gen_cr6_test_for_zero_reverse (target)); 9108 break; 9109 case 2: 9110 emit_insn (gen_cr6_test_for_lt (target)); 9111 break; 9112 case 3: 9113 emit_insn (gen_cr6_test_for_lt_reverse (target)); 9114 break; 9115 default: 9116 error ("argument 1 of %qs is out of range", 9117 "__builtin_altivec_predicate"); 9118 break; 9119 } 9120 9121 return target; 9122} 9123 9124rtx 9125swap_endian_selector_for_mode (machine_mode mode) 9126{ 9127 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}; 9128 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8}; 9129 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12}; 9130 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14}; 9131 9132 unsigned int *swaparray, i; 9133 rtx perm[16]; 9134 9135 switch (mode) 9136 { 9137 case E_V1TImode: 9138 swaparray = swap1; 9139 break; 9140 case E_V2DFmode: 9141 case E_V2DImode: 9142 swaparray = swap2; 9143 break; 9144 case E_V4SFmode: 9145 case E_V4SImode: 9146 swaparray = swap4; 9147 break; 9148 case E_V8HImode: 9149 swaparray = swap8; 9150 break; 9151 default: 9152 gcc_unreachable (); 9153 } 9154 9155 for (i = 0; i < 16; ++i) 9156 perm[i] = GEN_INT (swaparray[i]); 9157 9158 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, 9159 gen_rtvec_v (16, perm))); 9160} 9161 9162static rtx 9163altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) 9164{ 9165 rtx pat, addr; 9166 tree arg0 = CALL_EXPR_ARG (exp, 0); 9167 tree arg1 = CALL_EXPR_ARG (exp, 1); 9168 machine_mode tmode = insn_data[icode].operand[0].mode; 9169 machine_mode mode0 = Pmode; 9170 machine_mode mode1 = Pmode; 9171 rtx op0 = expand_normal (arg0); 9172 rtx op1 = expand_normal (arg1); 9173 9174 if (icode == CODE_FOR_nothing) 9175 /* Builtin not supported on this processor. */ 9176 return 0; 9177 9178 /* If we got invalid arguments bail out before generating bad rtl. */ 9179 if (arg0 == error_mark_node || arg1 == error_mark_node) 9180 return const0_rtx; 9181 9182 if (target == 0 9183 || GET_MODE (target) != tmode 9184 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 9185 target = gen_reg_rtx (tmode); 9186 9187 op1 = copy_to_mode_reg (mode1, op1); 9188 9189 /* For LVX, express the RTL accurately by ANDing the address with -16. 9190 LVXL and LVE*X expand to use UNSPECs to hide their special behavior, 9191 so the raw address is fine. */ 9192 if (icode == CODE_FOR_altivec_lvx_v1ti 9193 || icode == CODE_FOR_altivec_lvx_v2df 9194 || icode == CODE_FOR_altivec_lvx_v2di 9195 || icode == CODE_FOR_altivec_lvx_v4sf 9196 || icode == CODE_FOR_altivec_lvx_v4si 9197 || icode == CODE_FOR_altivec_lvx_v8hi 9198 || icode == CODE_FOR_altivec_lvx_v16qi) 9199 { 9200 rtx rawaddr; 9201 if (op0 == const0_rtx) 9202 rawaddr = op1; 9203 else 9204 { 9205 op0 = copy_to_mode_reg (mode0, op0); 9206 rawaddr = gen_rtx_PLUS (Pmode, op1, op0); 9207 } 9208 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); 9209 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr); 9210 9211 emit_insn (gen_rtx_SET (target, addr)); 9212 } 9213 else 9214 { 9215 if (op0 == const0_rtx) 9216 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1); 9217 else 9218 { 9219 op0 = copy_to_mode_reg (mode0, op0); 9220 addr = gen_rtx_MEM (blk ? BLKmode : tmode, 9221 gen_rtx_PLUS (Pmode, op1, op0)); 9222 } 9223 9224 pat = GEN_FCN (icode) (target, addr); 9225 if (! pat) 9226 return 0; 9227 emit_insn (pat); 9228 } 9229 9230 return target; 9231} 9232 9233static rtx 9234altivec_expand_stxvl_builtin (enum insn_code icode, tree exp) 9235{ 9236 rtx pat; 9237 tree arg0 = CALL_EXPR_ARG (exp, 0); 9238 tree arg1 = CALL_EXPR_ARG (exp, 1); 9239 tree arg2 = CALL_EXPR_ARG (exp, 2); 9240 rtx op0 = expand_normal (arg0); 9241 rtx op1 = expand_normal (arg1); 9242 rtx op2 = expand_normal (arg2); 9243 machine_mode mode0 = insn_data[icode].operand[0].mode; 9244 machine_mode mode1 = insn_data[icode].operand[1].mode; 9245 machine_mode mode2 = insn_data[icode].operand[2].mode; 9246 9247 if (icode == CODE_FOR_nothing) 9248 /* Builtin not supported on this processor. */ 9249 return NULL_RTX; 9250 9251 /* If we got invalid arguments bail out before generating bad rtl. */ 9252 if (arg0 == error_mark_node 9253 || arg1 == error_mark_node 9254 || arg2 == error_mark_node) 9255 return NULL_RTX; 9256 9257 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 9258 op0 = copy_to_mode_reg (mode0, op0); 9259 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 9260 op1 = copy_to_mode_reg (mode1, op1); 9261 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) 9262 op2 = copy_to_mode_reg (mode2, op2); 9263 9264 pat = GEN_FCN (icode) (op0, op1, op2); 9265 if (pat) 9266 emit_insn (pat); 9267 9268 return NULL_RTX; 9269} 9270 9271static rtx 9272altivec_expand_stv_builtin (enum insn_code icode, tree exp) 9273{ 9274 tree arg0 = CALL_EXPR_ARG (exp, 0); 9275 tree arg1 = CALL_EXPR_ARG (exp, 1); 9276 tree arg2 = CALL_EXPR_ARG (exp, 2); 9277 rtx op0 = expand_normal (arg0); 9278 rtx op1 = expand_normal (arg1); 9279 rtx op2 = expand_normal (arg2); 9280 rtx pat, addr, rawaddr; 9281 machine_mode tmode = insn_data[icode].operand[0].mode; 9282 machine_mode smode = insn_data[icode].operand[1].mode; 9283 machine_mode mode1 = Pmode; 9284 machine_mode mode2 = Pmode; 9285 9286 /* Invalid arguments. Bail before doing anything stoopid! */ 9287 if (arg0 == error_mark_node 9288 || arg1 == error_mark_node 9289 || arg2 == error_mark_node) 9290 return const0_rtx; 9291 9292 op2 = copy_to_mode_reg (mode2, op2); 9293 9294 /* For STVX, express the RTL accurately by ANDing the address with -16. 9295 STVXL and STVE*X expand to use UNSPECs to hide their special behavior, 9296 so the raw address is fine. */ 9297 if (icode == CODE_FOR_altivec_stvx_v2df 9298 || icode == CODE_FOR_altivec_stvx_v2di 9299 || icode == CODE_FOR_altivec_stvx_v4sf 9300 || icode == CODE_FOR_altivec_stvx_v4si 9301 || icode == CODE_FOR_altivec_stvx_v8hi 9302 || icode == CODE_FOR_altivec_stvx_v16qi) 9303 { 9304 if (op1 == const0_rtx) 9305 rawaddr = op2; 9306 else 9307 { 9308 op1 = copy_to_mode_reg (mode1, op1); 9309 rawaddr = gen_rtx_PLUS (Pmode, op2, op1); 9310 } 9311 9312 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); 9313 addr = gen_rtx_MEM (tmode, addr); 9314 9315 op0 = copy_to_mode_reg (tmode, op0); 9316 9317 emit_insn (gen_rtx_SET (addr, op0)); 9318 } 9319 else 9320 { 9321 if (! (*insn_data[icode].operand[1].predicate) (op0, smode)) 9322 op0 = copy_to_mode_reg (smode, op0); 9323 9324 if (op1 == const0_rtx) 9325 addr = gen_rtx_MEM (tmode, op2); 9326 else 9327 { 9328 op1 = copy_to_mode_reg (mode1, op1); 9329 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1)); 9330 } 9331 9332 pat = GEN_FCN (icode) (addr, op0); 9333 if (pat) 9334 emit_insn (pat); 9335 } 9336 9337 return NULL_RTX; 9338} 9339 9340/* Expand the MMA built-in in EXP. 9341 Store true in *EXPANDEDP if we found a built-in to expand. */ 9342 9343static rtx 9344mma_expand_builtin (tree exp, rtx target, bool *expandedp) 9345{ 9346 unsigned i; 9347 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 9348 enum rs6000_builtins fcode 9349 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 9350 const struct builtin_description *d = bdesc_mma; 9351 9352 /* Expand the MMA built-in. */ 9353 for (i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++) 9354 if (d->code == fcode) 9355 break; 9356 9357 if (i >= ARRAY_SIZE (bdesc_mma)) 9358 { 9359 *expandedp = false; 9360 return NULL_RTX; 9361 } 9362 9363 *expandedp = true; 9364 9365 tree arg; 9366 call_expr_arg_iterator iter; 9367 enum insn_code icode = d->icode; 9368 const struct insn_operand_data *insn_op; 9369 rtx op[MAX_MMA_OPERANDS]; 9370 unsigned nopnds = 0; 9371 unsigned attr = rs6000_builtin_info[fcode].attr; 9372 bool void_func = (attr & RS6000_BTC_VOID); 9373 machine_mode tmode = VOIDmode; 9374 9375 if (TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node) 9376 { 9377 tmode = insn_data[icode].operand[0].mode; 9378 if (!target 9379 || GET_MODE (target) != tmode 9380 || !(*insn_data[icode].operand[0].predicate) (target, tmode)) 9381 target = gen_reg_rtx (tmode); 9382 op[nopnds++] = target; 9383 } 9384 else 9385 target = const0_rtx; 9386 9387 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) 9388 { 9389 if (arg == error_mark_node) 9390 return const0_rtx; 9391 9392 rtx opnd; 9393 insn_op = &insn_data[icode].operand[nopnds]; 9394 if (TREE_CODE (arg) == ADDR_EXPR 9395 && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0)))) 9396 opnd = DECL_RTL (TREE_OPERAND (arg, 0)); 9397 else 9398 opnd = expand_normal (arg); 9399 9400 if (!(*insn_op->predicate) (opnd, insn_op->mode)) 9401 { 9402 if (!strcmp (insn_op->constraint, "n")) 9403 { 9404 if (!CONST_INT_P (opnd)) 9405 error ("argument %d must be an unsigned literal", nopnds); 9406 else 9407 error ("argument %d is an unsigned literal that is " 9408 "out of range", nopnds); 9409 return const0_rtx; 9410 } 9411 opnd = copy_to_mode_reg (insn_op->mode, opnd); 9412 } 9413 9414 /* Some MMA instructions have INOUT accumulator operands, so force 9415 their target register to be the same as their input register. */ 9416 if (!void_func 9417 && nopnds == 1 9418 && !strcmp (insn_op->constraint, "0") 9419 && insn_op->mode == tmode 9420 && REG_P (opnd) 9421 && (*insn_data[icode].operand[0].predicate) (opnd, tmode)) 9422 target = op[0] = opnd; 9423 9424 op[nopnds++] = opnd; 9425 } 9426 9427 unsigned attr_args = attr & RS6000_BTC_OPND_MASK; 9428 if (attr & RS6000_BTC_QUAD) 9429 attr_args++; 9430 9431 gcc_assert (nopnds == attr_args); 9432 9433 rtx pat; 9434 switch (nopnds) 9435 { 9436 case 1: 9437 pat = GEN_FCN (icode) (op[0]); 9438 break; 9439 case 2: 9440 pat = GEN_FCN (icode) (op[0], op[1]); 9441 break; 9442 case 3: 9443 /* The ASSEMBLE builtin source operands are reversed in little-endian 9444 mode, so reorder them. */ 9445 if (fcode == VSX_BUILTIN_ASSEMBLE_PAIR_INTERNAL && !WORDS_BIG_ENDIAN) 9446 std::swap (op[1], op[2]); 9447 pat = GEN_FCN (icode) (op[0], op[1], op[2]); 9448 break; 9449 case 4: 9450 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); 9451 break; 9452 case 5: 9453 /* The ASSEMBLE builtin source operands are reversed in little-endian 9454 mode, so reorder them. */ 9455 if (fcode == MMA_BUILTIN_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN) 9456 { 9457 std::swap (op[1], op[4]); 9458 std::swap (op[2], op[3]); 9459 } 9460 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); 9461 break; 9462 case 6: 9463 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); 9464 break; 9465 case 7: 9466 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]); 9467 break; 9468 default: 9469 gcc_unreachable (); 9470 } 9471 if (!pat) 9472 return NULL_RTX; 9473 emit_insn (pat); 9474 9475 return target; 9476} 9477 9478/* Return the appropriate SPR number associated with the given builtin. */ 9479static inline HOST_WIDE_INT 9480htm_spr_num (enum rs6000_builtins code) 9481{ 9482 if (code == HTM_BUILTIN_GET_TFHAR 9483 || code == HTM_BUILTIN_SET_TFHAR) 9484 return TFHAR_SPR; 9485 else if (code == HTM_BUILTIN_GET_TFIAR 9486 || code == HTM_BUILTIN_SET_TFIAR) 9487 return TFIAR_SPR; 9488 else if (code == HTM_BUILTIN_GET_TEXASR 9489 || code == HTM_BUILTIN_SET_TEXASR) 9490 return TEXASR_SPR; 9491 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU 9492 || code == HTM_BUILTIN_SET_TEXASRU); 9493 return TEXASRU_SPR; 9494} 9495 9496/* Return the correct ICODE value depending on whether we are 9497 setting or reading the HTM SPRs. */ 9498static inline enum insn_code 9499rs6000_htm_spr_icode (bool nonvoid) 9500{ 9501 if (nonvoid) 9502 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si; 9503 else 9504 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si; 9505} 9506 9507/* Expand the HTM builtin in EXP and store the result in TARGET. 9508 Store true in *EXPANDEDP if we found a builtin to expand. */ 9509static rtx 9510htm_expand_builtin (tree exp, rtx target, bool * expandedp) 9511{ 9512 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 9513 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; 9514 enum rs6000_builtins fcode 9515 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 9516 const struct builtin_description *d; 9517 size_t i; 9518 9519 *expandedp = true; 9520 9521 if (!TARGET_POWERPC64 9522 && (fcode == HTM_BUILTIN_TABORTDC 9523 || fcode == HTM_BUILTIN_TABORTDCI)) 9524 { 9525 size_t uns_fcode = (size_t)fcode; 9526 const char *name = rs6000_builtin_info[uns_fcode].name; 9527 error ("builtin %qs is only valid in 64-bit mode", name); 9528 return const0_rtx; 9529 } 9530 9531 /* Expand the HTM builtins. */ 9532 d = bdesc_htm; 9533 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++) 9534 if (d->code == fcode) 9535 { 9536 rtx op[MAX_HTM_OPERANDS], pat; 9537 int nopnds = 0; 9538 tree arg; 9539 call_expr_arg_iterator iter; 9540 unsigned attr = rs6000_builtin_info[fcode].attr; 9541 enum insn_code icode = d->icode; 9542 const struct insn_operand_data *insn_op; 9543 bool uses_spr = (attr & RS6000_BTC_SPR); 9544 rtx cr = NULL_RTX; 9545 9546 if (uses_spr) 9547 icode = rs6000_htm_spr_icode (nonvoid); 9548 insn_op = &insn_data[icode].operand[0]; 9549 9550 if (nonvoid) 9551 { 9552 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode; 9553 if (!target 9554 || GET_MODE (target) != tmode 9555 || (uses_spr && !(*insn_op->predicate) (target, tmode))) 9556 target = gen_reg_rtx (tmode); 9557 if (uses_spr) 9558 op[nopnds++] = target; 9559 } 9560 9561 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) 9562 { 9563 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS) 9564 return const0_rtx; 9565 9566 insn_op = &insn_data[icode].operand[nopnds]; 9567 9568 op[nopnds] = expand_normal (arg); 9569 9570 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode)) 9571 { 9572 if (!strcmp (insn_op->constraint, "n")) 9573 { 9574 int arg_num = (nonvoid) ? nopnds : nopnds + 1; 9575 if (!CONST_INT_P (op[nopnds])) 9576 error ("argument %d must be an unsigned literal", arg_num); 9577 else 9578 error ("argument %d is an unsigned literal that is " 9579 "out of range", arg_num); 9580 return const0_rtx; 9581 } 9582 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]); 9583 } 9584 9585 nopnds++; 9586 } 9587 9588 /* Handle the builtins for extended mnemonics. These accept 9589 no arguments, but map to builtins that take arguments. */ 9590 switch (fcode) 9591 { 9592 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */ 9593 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */ 9594 op[nopnds++] = GEN_INT (1); 9595 if (flag_checking) 9596 attr |= RS6000_BTC_UNARY; 9597 break; 9598 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */ 9599 op[nopnds++] = GEN_INT (0); 9600 if (flag_checking) 9601 attr |= RS6000_BTC_UNARY; 9602 break; 9603 default: 9604 break; 9605 } 9606 9607 /* If this builtin accesses SPRs, then pass in the appropriate 9608 SPR number and SPR regno as the last two operands. */ 9609 if (uses_spr) 9610 { 9611 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode; 9612 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode)); 9613 } 9614 /* If this builtin accesses a CR, then pass in a scratch 9615 CR as the last operand. */ 9616 else if (attr & RS6000_BTC_CR) 9617 { cr = gen_reg_rtx (CCmode); 9618 op[nopnds++] = cr; 9619 } 9620 9621 if (flag_checking) 9622 { 9623 int expected_nopnds = 0; 9624 if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_UNARY) 9625 expected_nopnds = 1; 9626 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_BINARY) 9627 expected_nopnds = 2; 9628 else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_TERNARY) 9629 expected_nopnds = 3; 9630 if (!(attr & RS6000_BTC_VOID)) 9631 expected_nopnds += 1; 9632 if (uses_spr) 9633 expected_nopnds += 1; 9634 9635 gcc_assert (nopnds == expected_nopnds 9636 && nopnds <= MAX_HTM_OPERANDS); 9637 } 9638 9639 switch (nopnds) 9640 { 9641 case 1: 9642 pat = GEN_FCN (icode) (op[0]); 9643 break; 9644 case 2: 9645 pat = GEN_FCN (icode) (op[0], op[1]); 9646 break; 9647 case 3: 9648 pat = GEN_FCN (icode) (op[0], op[1], op[2]); 9649 break; 9650 case 4: 9651 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); 9652 break; 9653 default: 9654 gcc_unreachable (); 9655 } 9656 if (!pat) 9657 return NULL_RTX; 9658 emit_insn (pat); 9659 9660 if (attr & RS6000_BTC_CR) 9661 { 9662 if (fcode == HTM_BUILTIN_TBEGIN) 9663 { 9664 /* Emit code to set TARGET to true or false depending on 9665 whether the tbegin. instruction successfully or failed 9666 to start a transaction. We do this by placing the 1's 9667 complement of CR's EQ bit into TARGET. */ 9668 rtx scratch = gen_reg_rtx (SImode); 9669 emit_insn (gen_rtx_SET (scratch, 9670 gen_rtx_EQ (SImode, cr, 9671 const0_rtx))); 9672 emit_insn (gen_rtx_SET (target, 9673 gen_rtx_XOR (SImode, scratch, 9674 GEN_INT (1)))); 9675 } 9676 else 9677 { 9678 /* Emit code to copy the 4-bit condition register field 9679 CR into the least significant end of register TARGET. */ 9680 rtx scratch1 = gen_reg_rtx (SImode); 9681 rtx scratch2 = gen_reg_rtx (SImode); 9682 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0); 9683 emit_insn (gen_movcc (subreg, cr)); 9684 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28))); 9685 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf))); 9686 } 9687 } 9688 9689 if (nonvoid) 9690 return target; 9691 return const0_rtx; 9692 } 9693 9694 *expandedp = false; 9695 return NULL_RTX; 9696} 9697 9698/* Expand the CPU builtin in FCODE and store the result in TARGET. */ 9699 9700static rtx 9701cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED, 9702 rtx target) 9703{ 9704 /* __builtin_cpu_init () is a nop, so expand to nothing. */ 9705 if (fcode == RS6000_BUILTIN_CPU_INIT) 9706 return const0_rtx; 9707 9708 if (target == 0 || GET_MODE (target) != SImode) 9709 target = gen_reg_rtx (SImode); 9710 9711#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB 9712 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0); 9713 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back 9714 to a STRING_CST. */ 9715 if (TREE_CODE (arg) == ARRAY_REF 9716 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST 9717 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST 9718 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0) 9719 arg = TREE_OPERAND (arg, 0); 9720 9721 if (TREE_CODE (arg) != STRING_CST) 9722 { 9723 error ("builtin %qs only accepts a string argument", 9724 rs6000_builtin_info[(size_t) fcode].name); 9725 return const0_rtx; 9726 } 9727 9728 if (fcode == RS6000_BUILTIN_CPU_IS) 9729 { 9730 const char *cpu = TREE_STRING_POINTER (arg); 9731 rtx cpuid = NULL_RTX; 9732 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++) 9733 if (strcmp (cpu, cpu_is_info[i].cpu) == 0) 9734 { 9735 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */ 9736 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM); 9737 break; 9738 } 9739 if (cpuid == NULL_RTX) 9740 { 9741 /* Invalid CPU argument. */ 9742 error ("cpu %qs is an invalid argument to builtin %qs", 9743 cpu, rs6000_builtin_info[(size_t) fcode].name); 9744 return const0_rtx; 9745 } 9746 9747 rtx platform = gen_reg_rtx (SImode); 9748 rtx tcbmem = gen_const_mem (SImode, 9749 gen_rtx_PLUS (Pmode, 9750 gen_rtx_REG (Pmode, TLS_REGNUM), 9751 GEN_INT (TCB_PLATFORM_OFFSET))); 9752 emit_move_insn (platform, tcbmem); 9753 emit_insn (gen_eqsi3 (target, platform, cpuid)); 9754 } 9755 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS) 9756 { 9757 const char *hwcap = TREE_STRING_POINTER (arg); 9758 rtx mask = NULL_RTX; 9759 int hwcap_offset; 9760 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++) 9761 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0) 9762 { 9763 mask = GEN_INT (cpu_supports_info[i].mask); 9764 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id); 9765 break; 9766 } 9767 if (mask == NULL_RTX) 9768 { 9769 /* Invalid HWCAP argument. */ 9770 error ("%s %qs is an invalid argument to builtin %qs", 9771 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name); 9772 return const0_rtx; 9773 } 9774 9775 rtx tcb_hwcap = gen_reg_rtx (SImode); 9776 rtx tcbmem = gen_const_mem (SImode, 9777 gen_rtx_PLUS (Pmode, 9778 gen_rtx_REG (Pmode, TLS_REGNUM), 9779 GEN_INT (hwcap_offset))); 9780 emit_move_insn (tcb_hwcap, tcbmem); 9781 rtx scratch1 = gen_reg_rtx (SImode); 9782 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask))); 9783 rtx scratch2 = gen_reg_rtx (SImode); 9784 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx)); 9785 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx))); 9786 } 9787 else 9788 gcc_unreachable (); 9789 9790 /* Record that we have expanded a CPU builtin, so that we can later 9791 emit a reference to the special symbol exported by LIBC to ensure we 9792 do not link against an old LIBC that doesn't support this feature. */ 9793 cpu_builtin_p = true; 9794 9795#else 9796 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " 9797 "capability bits", rs6000_builtin_info[(size_t) fcode].name); 9798 9799 /* For old LIBCs, always return FALSE. */ 9800 emit_move_insn (target, GEN_INT (0)); 9801#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */ 9802 9803 return target; 9804} 9805 9806static rtx 9807rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) 9808{ 9809 rtx pat; 9810 tree arg0 = CALL_EXPR_ARG (exp, 0); 9811 tree arg1 = CALL_EXPR_ARG (exp, 1); 9812 tree arg2 = CALL_EXPR_ARG (exp, 2); 9813 rtx op0 = expand_normal (arg0); 9814 rtx op1 = expand_normal (arg1); 9815 rtx op2 = expand_normal (arg2); 9816 machine_mode tmode = insn_data[icode].operand[0].mode; 9817 machine_mode mode0 = insn_data[icode].operand[1].mode; 9818 machine_mode mode1 = insn_data[icode].operand[2].mode; 9819 machine_mode mode2 = insn_data[icode].operand[3].mode; 9820 9821 if (icode == CODE_FOR_nothing) 9822 /* Builtin not supported on this processor. */ 9823 return 0; 9824 9825 /* If we got invalid arguments bail out before generating bad rtl. */ 9826 if (arg0 == error_mark_node 9827 || arg1 == error_mark_node 9828 || arg2 == error_mark_node) 9829 return const0_rtx; 9830 9831 /* Check and prepare argument depending on the instruction code. 9832 9833 Note that a switch statement instead of the sequence of tests 9834 would be incorrect as many of the CODE_FOR values could be 9835 CODE_FOR_nothing and that would yield multiple alternatives 9836 with identical values. We'd never reach here at runtime in 9837 this case. */ 9838 if (icode == CODE_FOR_altivec_vsldoi_v4sf 9839 || icode == CODE_FOR_altivec_vsldoi_v2df 9840 || icode == CODE_FOR_altivec_vsldoi_v4si 9841 || icode == CODE_FOR_altivec_vsldoi_v8hi 9842 || icode == CODE_FOR_altivec_vsldoi_v16qi) 9843 { 9844 /* Only allow 4-bit unsigned literals. */ 9845 STRIP_NOPS (arg2); 9846 if (TREE_CODE (arg2) != INTEGER_CST 9847 || TREE_INT_CST_LOW (arg2) & ~0xf) 9848 { 9849 error ("argument 3 must be a 4-bit unsigned literal"); 9850 return CONST0_RTX (tmode); 9851 } 9852 } 9853 else if (icode == CODE_FOR_vsx_xxpermdi_v2df 9854 || icode == CODE_FOR_vsx_xxpermdi_v2di 9855 || icode == CODE_FOR_vsx_xxpermdi_v2df_be 9856 || icode == CODE_FOR_vsx_xxpermdi_v2di_be 9857 || icode == CODE_FOR_vsx_xxpermdi_v1ti 9858 || icode == CODE_FOR_vsx_xxpermdi_v4sf 9859 || icode == CODE_FOR_vsx_xxpermdi_v4si 9860 || icode == CODE_FOR_vsx_xxpermdi_v8hi 9861 || icode == CODE_FOR_vsx_xxpermdi_v16qi 9862 || icode == CODE_FOR_vsx_xxsldwi_v16qi 9863 || icode == CODE_FOR_vsx_xxsldwi_v8hi 9864 || icode == CODE_FOR_vsx_xxsldwi_v4si 9865 || icode == CODE_FOR_vsx_xxsldwi_v4sf 9866 || icode == CODE_FOR_vsx_xxsldwi_v2di 9867 || icode == CODE_FOR_vsx_xxsldwi_v2df) 9868 { 9869 /* Only allow 2-bit unsigned literals. */ 9870 STRIP_NOPS (arg2); 9871 if (TREE_CODE (arg2) != INTEGER_CST 9872 || TREE_INT_CST_LOW (arg2) & ~0x3) 9873 { 9874 error ("argument 3 must be a 2-bit unsigned literal"); 9875 return CONST0_RTX (tmode); 9876 } 9877 } 9878 else if (icode == CODE_FOR_vsx_set_v2df 9879 || icode == CODE_FOR_vsx_set_v2di 9880 || icode == CODE_FOR_bcdadd 9881 || icode == CODE_FOR_bcdadd_lt 9882 || icode == CODE_FOR_bcdadd_eq 9883 || icode == CODE_FOR_bcdadd_gt 9884 || icode == CODE_FOR_bcdsub 9885 || icode == CODE_FOR_bcdsub_lt 9886 || icode == CODE_FOR_bcdsub_eq 9887 || icode == CODE_FOR_bcdsub_gt) 9888 { 9889 /* Only allow 1-bit unsigned literals. */ 9890 STRIP_NOPS (arg2); 9891 if (TREE_CODE (arg2) != INTEGER_CST 9892 || TREE_INT_CST_LOW (arg2) & ~0x1) 9893 { 9894 error ("argument 3 must be a 1-bit unsigned literal"); 9895 return CONST0_RTX (tmode); 9896 } 9897 } 9898 else if (icode == CODE_FOR_dfp_ddedpd_dd 9899 || icode == CODE_FOR_dfp_ddedpd_td) 9900 { 9901 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */ 9902 STRIP_NOPS (arg0); 9903 if (TREE_CODE (arg0) != INTEGER_CST 9904 || TREE_INT_CST_LOW (arg2) & ~0x3) 9905 { 9906 error ("argument 1 must be 0 or 2"); 9907 return CONST0_RTX (tmode); 9908 } 9909 } 9910 else if (icode == CODE_FOR_dfp_denbcd_dd 9911 || icode == CODE_FOR_dfp_denbcd_td) 9912 { 9913 /* Only allow 1-bit unsigned literals. */ 9914 STRIP_NOPS (arg0); 9915 if (TREE_CODE (arg0) != INTEGER_CST 9916 || TREE_INT_CST_LOW (arg0) & ~0x1) 9917 { 9918 error ("argument 1 must be a 1-bit unsigned literal"); 9919 return CONST0_RTX (tmode); 9920 } 9921 } 9922 else if (icode == CODE_FOR_dfp_dscli_dd 9923 || icode == CODE_FOR_dfp_dscli_td 9924 || icode == CODE_FOR_dfp_dscri_dd 9925 || icode == CODE_FOR_dfp_dscri_td) 9926 { 9927 /* Only allow 6-bit unsigned literals. */ 9928 STRIP_NOPS (arg1); 9929 if (TREE_CODE (arg1) != INTEGER_CST 9930 || TREE_INT_CST_LOW (arg1) & ~0x3f) 9931 { 9932 error ("argument 2 must be a 6-bit unsigned literal"); 9933 return CONST0_RTX (tmode); 9934 } 9935 } 9936 else if (icode == CODE_FOR_crypto_vshasigmaw 9937 || icode == CODE_FOR_crypto_vshasigmad) 9938 { 9939 /* Check whether the 2nd and 3rd arguments are integer constants and in 9940 range and prepare arguments. */ 9941 STRIP_NOPS (arg1); 9942 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2)) 9943 { 9944 error ("argument 2 must be 0 or 1"); 9945 return CONST0_RTX (tmode); 9946 } 9947 9948 STRIP_NOPS (arg2); 9949 if (TREE_CODE (arg2) != INTEGER_CST 9950 || wi::geu_p (wi::to_wide (arg2), 16)) 9951 { 9952 error ("argument 3 must be in the range [0, 15]"); 9953 return CONST0_RTX (tmode); 9954 } 9955 } 9956 9957 if (target == 0 9958 || GET_MODE (target) != tmode 9959 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 9960 target = gen_reg_rtx (tmode); 9961 9962 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 9963 op0 = copy_to_mode_reg (mode0, op0); 9964 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 9965 op1 = copy_to_mode_reg (mode1, op1); 9966 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) 9967 op2 = copy_to_mode_reg (mode2, op2); 9968 9969 pat = GEN_FCN (icode) (target, op0, op1, op2); 9970 if (! pat) 9971 return 0; 9972 emit_insn (pat); 9973 9974 return target; 9975} 9976 9977 9978/* Expand the dst builtins. */ 9979static rtx 9980altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, 9981 bool *expandedp) 9982{ 9983 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 9984 enum rs6000_builtins fcode 9985 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 9986 tree arg0, arg1, arg2; 9987 machine_mode mode0, mode1; 9988 rtx pat, op0, op1, op2; 9989 const struct builtin_description *d; 9990 size_t i; 9991 9992 *expandedp = false; 9993 9994 /* Handle DST variants. */ 9995 d = bdesc_dst; 9996 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) 9997 if (d->code == fcode) 9998 { 9999 arg0 = CALL_EXPR_ARG (exp, 0); 10000 arg1 = CALL_EXPR_ARG (exp, 1); 10001 arg2 = CALL_EXPR_ARG (exp, 2); 10002 op0 = expand_normal (arg0); 10003 op1 = expand_normal (arg1); 10004 op2 = expand_normal (arg2); 10005 mode0 = insn_data[d->icode].operand[0].mode; 10006 mode1 = insn_data[d->icode].operand[1].mode; 10007 10008 /* Invalid arguments, bail out before generating bad rtl. */ 10009 if (arg0 == error_mark_node 10010 || arg1 == error_mark_node 10011 || arg2 == error_mark_node) 10012 return const0_rtx; 10013 10014 *expandedp = true; 10015 STRIP_NOPS (arg2); 10016 if (TREE_CODE (arg2) != INTEGER_CST 10017 || TREE_INT_CST_LOW (arg2) & ~0x3) 10018 { 10019 error ("argument to %qs must be a 2-bit unsigned literal", d->name); 10020 return const0_rtx; 10021 } 10022 10023 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) 10024 op0 = copy_to_mode_reg (Pmode, op0); 10025 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) 10026 op1 = copy_to_mode_reg (mode1, op1); 10027 10028 pat = GEN_FCN (d->icode) (op0, op1, op2); 10029 if (pat != 0) 10030 emit_insn (pat); 10031 10032 return NULL_RTX; 10033 } 10034 10035 return NULL_RTX; 10036} 10037 10038/* Expand vec_init builtin. */ 10039static rtx 10040altivec_expand_vec_init_builtin (tree type, tree exp, rtx target) 10041{ 10042 machine_mode tmode = TYPE_MODE (type); 10043 machine_mode inner_mode = GET_MODE_INNER (tmode); 10044 int i, n_elt = GET_MODE_NUNITS (tmode); 10045 10046 gcc_assert (VECTOR_MODE_P (tmode)); 10047 gcc_assert (n_elt == call_expr_nargs (exp)); 10048 10049 if (!target || !register_operand (target, tmode)) 10050 target = gen_reg_rtx (tmode); 10051 10052 /* If we have a vector compromised of a single element, such as V1TImode, do 10053 the initialization directly. */ 10054 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode)) 10055 { 10056 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0)); 10057 emit_move_insn (target, gen_lowpart (tmode, x)); 10058 } 10059 else 10060 { 10061 rtvec v = rtvec_alloc (n_elt); 10062 10063 for (i = 0; i < n_elt; ++i) 10064 { 10065 rtx x = expand_normal (CALL_EXPR_ARG (exp, i)); 10066 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); 10067 } 10068 10069 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); 10070 } 10071 10072 return target; 10073} 10074 10075/* Return the integer constant in ARG. Constrain it to be in the range 10076 of the subparts of VEC_TYPE; issue an error if not. */ 10077 10078static int 10079get_element_number (tree vec_type, tree arg) 10080{ 10081 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; 10082 10083 if (!tree_fits_uhwi_p (arg) 10084 || (elt = tree_to_uhwi (arg), elt > max)) 10085 { 10086 error ("selector must be an integer constant in the range [0, %wi]", max); 10087 return 0; 10088 } 10089 10090 return elt; 10091} 10092 10093/* Expand vec_set builtin. */ 10094static rtx 10095altivec_expand_vec_set_builtin (tree exp) 10096{ 10097 machine_mode tmode, mode1; 10098 tree arg0, arg1, arg2; 10099 int elt; 10100 rtx op0, op1; 10101 10102 arg0 = CALL_EXPR_ARG (exp, 0); 10103 arg1 = CALL_EXPR_ARG (exp, 1); 10104 arg2 = CALL_EXPR_ARG (exp, 2); 10105 10106 tmode = TYPE_MODE (TREE_TYPE (arg0)); 10107 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); 10108 gcc_assert (VECTOR_MODE_P (tmode)); 10109 10110 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL); 10111 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL); 10112 elt = get_element_number (TREE_TYPE (arg0), arg2); 10113 10114 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) 10115 op1 = convert_modes (mode1, GET_MODE (op1), op1, true); 10116 10117 op0 = force_reg (tmode, op0); 10118 op1 = force_reg (mode1, op1); 10119 10120 rs6000_expand_vector_set (op0, op1, elt); 10121 10122 return op0; 10123} 10124 10125/* Expand vec_ext builtin. */ 10126static rtx 10127altivec_expand_vec_ext_builtin (tree exp, rtx target) 10128{ 10129 machine_mode tmode, mode0; 10130 tree arg0, arg1; 10131 rtx op0; 10132 rtx op1; 10133 10134 arg0 = CALL_EXPR_ARG (exp, 0); 10135 arg1 = CALL_EXPR_ARG (exp, 1); 10136 10137 op0 = expand_normal (arg0); 10138 op1 = expand_normal (arg1); 10139 10140 if (TREE_CODE (arg1) == INTEGER_CST) 10141 { 10142 unsigned HOST_WIDE_INT elt; 10143 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)); 10144 unsigned int truncated_selector; 10145 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0) 10146 returns low-order bits of INTEGER_CST for modulo indexing. */ 10147 elt = TREE_INT_CST_LOW (arg1); 10148 truncated_selector = elt % size; 10149 op1 = GEN_INT (truncated_selector); 10150 } 10151 10152 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); 10153 mode0 = TYPE_MODE (TREE_TYPE (arg0)); 10154 gcc_assert (VECTOR_MODE_P (mode0)); 10155 10156 op0 = force_reg (mode0, op0); 10157 10158 if (optimize || !target || !register_operand (target, tmode)) 10159 target = gen_reg_rtx (tmode); 10160 10161 rs6000_expand_vector_extract (target, op0, op1); 10162 10163 return target; 10164} 10165 10166/* Expand the builtin in EXP and store the result in TARGET. Store 10167 true in *EXPANDEDP if we found a builtin to expand. */ 10168static rtx 10169altivec_expand_builtin (tree exp, rtx target, bool *expandedp) 10170{ 10171 const struct builtin_description *d; 10172 size_t i; 10173 enum insn_code icode; 10174 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 10175 tree arg0, arg1, arg2; 10176 rtx op0, pat; 10177 machine_mode tmode, mode0; 10178 enum rs6000_builtins fcode 10179 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 10180 10181 if (rs6000_overloaded_builtin_p (fcode)) 10182 { 10183 *expandedp = true; 10184 error ("unresolved overload for Altivec builtin %qF", fndecl); 10185 10186 /* Given it is invalid, just generate a normal call. */ 10187 return expand_call (exp, target, false); 10188 } 10189 10190 target = altivec_expand_dst_builtin (exp, target, expandedp); 10191 if (*expandedp) 10192 return target; 10193 10194 *expandedp = true; 10195 10196 switch (fcode) 10197 { 10198 case ALTIVEC_BUILTIN_STVX_V2DF: 10199 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp); 10200 case ALTIVEC_BUILTIN_STVX_V2DI: 10201 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp); 10202 case ALTIVEC_BUILTIN_STVX_V4SF: 10203 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp); 10204 case ALTIVEC_BUILTIN_STVX: 10205 case ALTIVEC_BUILTIN_STVX_V4SI: 10206 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp); 10207 case ALTIVEC_BUILTIN_STVX_V8HI: 10208 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp); 10209 case ALTIVEC_BUILTIN_STVX_V16QI: 10210 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp); 10211 case ALTIVEC_BUILTIN_STVEBX: 10212 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp); 10213 case ALTIVEC_BUILTIN_STVEHX: 10214 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); 10215 case ALTIVEC_BUILTIN_STVEWX: 10216 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); 10217 case ALTIVEC_BUILTIN_STVXL_V2DF: 10218 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp); 10219 case ALTIVEC_BUILTIN_STVXL_V2DI: 10220 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp); 10221 case ALTIVEC_BUILTIN_STVXL_V4SF: 10222 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp); 10223 case ALTIVEC_BUILTIN_STVXL: 10224 case ALTIVEC_BUILTIN_STVXL_V4SI: 10225 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp); 10226 case ALTIVEC_BUILTIN_STVXL_V8HI: 10227 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp); 10228 case ALTIVEC_BUILTIN_STVXL_V16QI: 10229 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp); 10230 10231 case ALTIVEC_BUILTIN_STVLX: 10232 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp); 10233 case ALTIVEC_BUILTIN_STVLXL: 10234 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp); 10235 case ALTIVEC_BUILTIN_STVRX: 10236 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp); 10237 case ALTIVEC_BUILTIN_STVRXL: 10238 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); 10239 10240 case P9V_BUILTIN_STXVL: 10241 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp); 10242 10243 case P9V_BUILTIN_XST_LEN_R: 10244 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp); 10245 10246 case VSX_BUILTIN_STXVD2X_V1TI: 10247 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp); 10248 case VSX_BUILTIN_STXVD2X_V2DF: 10249 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); 10250 case VSX_BUILTIN_STXVD2X_V2DI: 10251 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp); 10252 case VSX_BUILTIN_STXVW4X_V4SF: 10253 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp); 10254 case VSX_BUILTIN_STXVW4X_V4SI: 10255 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp); 10256 case VSX_BUILTIN_STXVW4X_V8HI: 10257 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp); 10258 case VSX_BUILTIN_STXVW4X_V16QI: 10259 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp); 10260 10261 /* For the following on big endian, it's ok to use any appropriate 10262 unaligned-supporting store, so use a generic expander. For 10263 little-endian, the exact element-reversing instruction must 10264 be used. */ 10265 case VSX_BUILTIN_ST_ELEMREV_V1TI: 10266 { 10267 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti 10268 : CODE_FOR_vsx_st_elemrev_v1ti); 10269 return altivec_expand_stv_builtin (code, exp); 10270 } 10271 case VSX_BUILTIN_ST_ELEMREV_V2DF: 10272 { 10273 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df 10274 : CODE_FOR_vsx_st_elemrev_v2df); 10275 return altivec_expand_stv_builtin (code, exp); 10276 } 10277 case VSX_BUILTIN_ST_ELEMREV_V2DI: 10278 { 10279 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di 10280 : CODE_FOR_vsx_st_elemrev_v2di); 10281 return altivec_expand_stv_builtin (code, exp); 10282 } 10283 case VSX_BUILTIN_ST_ELEMREV_V4SF: 10284 { 10285 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf 10286 : CODE_FOR_vsx_st_elemrev_v4sf); 10287 return altivec_expand_stv_builtin (code, exp); 10288 } 10289 case VSX_BUILTIN_ST_ELEMREV_V4SI: 10290 { 10291 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si 10292 : CODE_FOR_vsx_st_elemrev_v4si); 10293 return altivec_expand_stv_builtin (code, exp); 10294 } 10295 case VSX_BUILTIN_ST_ELEMREV_V8HI: 10296 { 10297 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi 10298 : CODE_FOR_vsx_st_elemrev_v8hi); 10299 return altivec_expand_stv_builtin (code, exp); 10300 } 10301 case VSX_BUILTIN_ST_ELEMREV_V16QI: 10302 { 10303 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi 10304 : CODE_FOR_vsx_st_elemrev_v16qi); 10305 return altivec_expand_stv_builtin (code, exp); 10306 } 10307 10308 case ALTIVEC_BUILTIN_MFVSCR: 10309 icode = CODE_FOR_altivec_mfvscr; 10310 tmode = insn_data[icode].operand[0].mode; 10311 10312 if (target == 0 10313 || GET_MODE (target) != tmode 10314 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 10315 target = gen_reg_rtx (tmode); 10316 10317 pat = GEN_FCN (icode) (target); 10318 if (! pat) 10319 return 0; 10320 emit_insn (pat); 10321 return target; 10322 10323 case ALTIVEC_BUILTIN_MTVSCR: 10324 icode = CODE_FOR_altivec_mtvscr; 10325 arg0 = CALL_EXPR_ARG (exp, 0); 10326 op0 = expand_normal (arg0); 10327 mode0 = insn_data[icode].operand[0].mode; 10328 10329 /* If we got invalid arguments bail out before generating bad rtl. */ 10330 if (arg0 == error_mark_node) 10331 return const0_rtx; 10332 10333 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 10334 op0 = copy_to_mode_reg (mode0, op0); 10335 10336 pat = GEN_FCN (icode) (op0); 10337 if (pat) 10338 emit_insn (pat); 10339 return NULL_RTX; 10340 10341 case ALTIVEC_BUILTIN_DSSALL: 10342 emit_insn (gen_altivec_dssall ()); 10343 return NULL_RTX; 10344 10345 case ALTIVEC_BUILTIN_DSS: 10346 icode = CODE_FOR_altivec_dss; 10347 arg0 = CALL_EXPR_ARG (exp, 0); 10348 STRIP_NOPS (arg0); 10349 op0 = expand_normal (arg0); 10350 mode0 = insn_data[icode].operand[0].mode; 10351 10352 /* If we got invalid arguments bail out before generating bad rtl. */ 10353 if (arg0 == error_mark_node) 10354 return const0_rtx; 10355 10356 if (TREE_CODE (arg0) != INTEGER_CST 10357 || TREE_INT_CST_LOW (arg0) & ~0x3) 10358 { 10359 error ("argument to %qs must be a 2-bit unsigned literal", "dss"); 10360 return const0_rtx; 10361 } 10362 10363 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) 10364 op0 = copy_to_mode_reg (mode0, op0); 10365 10366 emit_insn (gen_altivec_dss (op0)); 10367 return NULL_RTX; 10368 10369 case ALTIVEC_BUILTIN_VEC_INIT_V4SI: 10370 case ALTIVEC_BUILTIN_VEC_INIT_V8HI: 10371 case ALTIVEC_BUILTIN_VEC_INIT_V16QI: 10372 case ALTIVEC_BUILTIN_VEC_INIT_V4SF: 10373 case VSX_BUILTIN_VEC_INIT_V2DF: 10374 case VSX_BUILTIN_VEC_INIT_V2DI: 10375 case VSX_BUILTIN_VEC_INIT_V1TI: 10376 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); 10377 10378 case ALTIVEC_BUILTIN_VEC_SET_V4SI: 10379 case ALTIVEC_BUILTIN_VEC_SET_V8HI: 10380 case ALTIVEC_BUILTIN_VEC_SET_V16QI: 10381 case ALTIVEC_BUILTIN_VEC_SET_V4SF: 10382 case VSX_BUILTIN_VEC_SET_V2DF: 10383 case VSX_BUILTIN_VEC_SET_V2DI: 10384 case VSX_BUILTIN_VEC_SET_V1TI: 10385 return altivec_expand_vec_set_builtin (exp); 10386 10387 case ALTIVEC_BUILTIN_VEC_EXT_V4SI: 10388 case ALTIVEC_BUILTIN_VEC_EXT_V8HI: 10389 case ALTIVEC_BUILTIN_VEC_EXT_V16QI: 10390 case ALTIVEC_BUILTIN_VEC_EXT_V4SF: 10391 case VSX_BUILTIN_VEC_EXT_V2DF: 10392 case VSX_BUILTIN_VEC_EXT_V2DI: 10393 case VSX_BUILTIN_VEC_EXT_V1TI: 10394 return altivec_expand_vec_ext_builtin (exp, target); 10395 10396 case P9V_BUILTIN_VEC_EXTRACT4B: 10397 arg1 = CALL_EXPR_ARG (exp, 1); 10398 STRIP_NOPS (arg1); 10399 10400 /* Generate a normal call if it is invalid. */ 10401 if (arg1 == error_mark_node) 10402 return expand_call (exp, target, false); 10403 10404 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12) 10405 { 10406 error ("second argument to %qs must be [0, 12]", "vec_vextract4b"); 10407 return expand_call (exp, target, false); 10408 } 10409 break; 10410 10411 case P9V_BUILTIN_VEC_INSERT4B: 10412 arg2 = CALL_EXPR_ARG (exp, 2); 10413 STRIP_NOPS (arg2); 10414 10415 /* Generate a normal call if it is invalid. */ 10416 if (arg2 == error_mark_node) 10417 return expand_call (exp, target, false); 10418 10419 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12) 10420 { 10421 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b"); 10422 return expand_call (exp, target, false); 10423 } 10424 break; 10425 10426 default: 10427 break; 10428 /* Fall through. */ 10429 } 10430 10431 /* Expand abs* operations. */ 10432 d = bdesc_abs; 10433 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) 10434 if (d->code == fcode) 10435 return altivec_expand_abs_builtin (d->icode, exp, target); 10436 10437 /* Expand the AltiVec predicates. */ 10438 d = bdesc_altivec_preds; 10439 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++) 10440 if (d->code == fcode) 10441 return altivec_expand_predicate_builtin (d->icode, exp, target); 10442 10443 /* LV* are funky. We initialized them differently. */ 10444 switch (fcode) 10445 { 10446 case ALTIVEC_BUILTIN_LVSL: 10447 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, 10448 exp, target, false); 10449 case ALTIVEC_BUILTIN_LVSR: 10450 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, 10451 exp, target, false); 10452 case ALTIVEC_BUILTIN_LVEBX: 10453 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, 10454 exp, target, false); 10455 case ALTIVEC_BUILTIN_LVEHX: 10456 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, 10457 exp, target, false); 10458 case ALTIVEC_BUILTIN_LVEWX: 10459 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, 10460 exp, target, false); 10461 case ALTIVEC_BUILTIN_LVXL_V2DF: 10462 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df, 10463 exp, target, false); 10464 case ALTIVEC_BUILTIN_LVXL_V2DI: 10465 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di, 10466 exp, target, false); 10467 case ALTIVEC_BUILTIN_LVXL_V4SF: 10468 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf, 10469 exp, target, false); 10470 case ALTIVEC_BUILTIN_LVXL: 10471 case ALTIVEC_BUILTIN_LVXL_V4SI: 10472 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si, 10473 exp, target, false); 10474 case ALTIVEC_BUILTIN_LVXL_V8HI: 10475 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi, 10476 exp, target, false); 10477 case ALTIVEC_BUILTIN_LVXL_V16QI: 10478 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi, 10479 exp, target, false); 10480 case ALTIVEC_BUILTIN_LVX_V1TI: 10481 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti, 10482 exp, target, false); 10483 case ALTIVEC_BUILTIN_LVX_V2DF: 10484 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df, 10485 exp, target, false); 10486 case ALTIVEC_BUILTIN_LVX_V2DI: 10487 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di, 10488 exp, target, false); 10489 case ALTIVEC_BUILTIN_LVX_V4SF: 10490 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf, 10491 exp, target, false); 10492 case ALTIVEC_BUILTIN_LVX: 10493 case ALTIVEC_BUILTIN_LVX_V4SI: 10494 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si, 10495 exp, target, false); 10496 case ALTIVEC_BUILTIN_LVX_V8HI: 10497 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi, 10498 exp, target, false); 10499 case ALTIVEC_BUILTIN_LVX_V16QI: 10500 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi, 10501 exp, target, false); 10502 case ALTIVEC_BUILTIN_LVLX: 10503 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx, 10504 exp, target, true); 10505 case ALTIVEC_BUILTIN_LVLXL: 10506 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl, 10507 exp, target, true); 10508 case ALTIVEC_BUILTIN_LVRX: 10509 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx, 10510 exp, target, true); 10511 case ALTIVEC_BUILTIN_LVRXL: 10512 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, 10513 exp, target, true); 10514 case VSX_BUILTIN_LXVD2X_V1TI: 10515 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti, 10516 exp, target, false); 10517 case VSX_BUILTIN_LXVD2X_V2DF: 10518 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, 10519 exp, target, false); 10520 case VSX_BUILTIN_LXVD2X_V2DI: 10521 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di, 10522 exp, target, false); 10523 case VSX_BUILTIN_LXVW4X_V4SF: 10524 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf, 10525 exp, target, false); 10526 case VSX_BUILTIN_LXVW4X_V4SI: 10527 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si, 10528 exp, target, false); 10529 case VSX_BUILTIN_LXVW4X_V8HI: 10530 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi, 10531 exp, target, false); 10532 case VSX_BUILTIN_LXVW4X_V16QI: 10533 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi, 10534 exp, target, false); 10535 /* For the following on big endian, it's ok to use any appropriate 10536 unaligned-supporting load, so use a generic expander. For 10537 little-endian, the exact element-reversing instruction must 10538 be used. */ 10539 case VSX_BUILTIN_LD_ELEMREV_V2DF: 10540 { 10541 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df 10542 : CODE_FOR_vsx_ld_elemrev_v2df); 10543 return altivec_expand_lv_builtin (code, exp, target, false); 10544 } 10545 case VSX_BUILTIN_LD_ELEMREV_V1TI: 10546 { 10547 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti 10548 : CODE_FOR_vsx_ld_elemrev_v1ti); 10549 return altivec_expand_lv_builtin (code, exp, target, false); 10550 } 10551 case VSX_BUILTIN_LD_ELEMREV_V2DI: 10552 { 10553 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di 10554 : CODE_FOR_vsx_ld_elemrev_v2di); 10555 return altivec_expand_lv_builtin (code, exp, target, false); 10556 } 10557 case VSX_BUILTIN_LD_ELEMREV_V4SF: 10558 { 10559 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf 10560 : CODE_FOR_vsx_ld_elemrev_v4sf); 10561 return altivec_expand_lv_builtin (code, exp, target, false); 10562 } 10563 case VSX_BUILTIN_LD_ELEMREV_V4SI: 10564 { 10565 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si 10566 : CODE_FOR_vsx_ld_elemrev_v4si); 10567 return altivec_expand_lv_builtin (code, exp, target, false); 10568 } 10569 case VSX_BUILTIN_LD_ELEMREV_V8HI: 10570 { 10571 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi 10572 : CODE_FOR_vsx_ld_elemrev_v8hi); 10573 return altivec_expand_lv_builtin (code, exp, target, false); 10574 } 10575 case VSX_BUILTIN_LD_ELEMREV_V16QI: 10576 { 10577 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi 10578 : CODE_FOR_vsx_ld_elemrev_v16qi); 10579 return altivec_expand_lv_builtin (code, exp, target, false); 10580 } 10581 break; 10582 default: 10583 break; 10584 /* Fall through. */ 10585 } 10586 10587 *expandedp = false; 10588 return NULL_RTX; 10589} 10590 10591/* Check whether a builtin function is supported in this target 10592 configuration. */ 10593bool 10594rs6000_builtin_is_supported_p (enum rs6000_builtins fncode) 10595{ 10596 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask; 10597 if ((fnmask & rs6000_builtin_mask) != fnmask) 10598 return false; 10599 else 10600 return true; 10601} 10602 10603/* Raise an error message for a builtin function that is called without the 10604 appropriate target options being set. */ 10605 10606static void 10607rs6000_invalid_builtin (enum rs6000_builtins fncode) 10608{ 10609 size_t uns_fncode = (size_t) fncode; 10610 const char *name = rs6000_builtin_info[uns_fncode].name; 10611 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; 10612 10613 gcc_assert (name != NULL); 10614 if ((fnmask & RS6000_BTM_CELL) != 0) 10615 error ("%qs is only valid for the cell processor", name); 10616 else if ((fnmask & RS6000_BTM_VSX) != 0) 10617 error ("%qs requires the %qs option", name, "-mvsx"); 10618 else if ((fnmask & RS6000_BTM_HTM) != 0) 10619 error ("%qs requires the %qs option", name, "-mhtm"); 10620 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) 10621 error ("%qs requires the %qs option", name, "-maltivec"); 10622 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) 10623 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) 10624 error ("%qs requires the %qs and %qs options", name, "-mhard-dfp", 10625 "-mpower8-vector"); 10626 else if ((fnmask & RS6000_BTM_DFP) != 0) 10627 error ("%qs requires the %qs option", name, "-mhard-dfp"); 10628 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0) 10629 error ("%qs requires the %qs option", name, "-mpower8-vector"); 10630 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT)) 10631 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT)) 10632 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", 10633 "-m64"); 10634 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0) 10635 error ("%qs requires the %qs option", name, "-mcpu=power9"); 10636 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) 10637 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) 10638 error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", 10639 "-m64"); 10640 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC) 10641 error ("%qs requires the %qs option", name, "-mcpu=power9"); 10642 else if ((fnmask & RS6000_BTM_P10) != 0) 10643 error ("%qs requires the %qs option", name, "-mcpu=power10"); 10644 else if ((fnmask & RS6000_BTM_MMA) != 0) 10645 error ("%qs requires the %qs option", name, "-mmma"); 10646 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128) 10647 { 10648 if (!TARGET_HARD_FLOAT) 10649 error ("%qs requires the %qs option", name, "-mhard-float"); 10650 else 10651 error ("%qs requires the %qs option", name, 10652 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128"); 10653 } 10654 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0) 10655 error ("%qs requires the %qs option", name, "-mhard-float"); 10656 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0) 10657 error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name); 10658 else if ((fnmask & RS6000_BTM_FLOAT128) != 0) 10659 error ("%qs requires the %qs option", name, "%<-mfloat128%>"); 10660 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) 10661 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) 10662 error ("%qs requires the %qs (or newer), and %qs or %qs options", 10663 name, "-mcpu=power7", "-m64", "-mpowerpc64"); 10664 else 10665 error ("%qs is not supported with the current options", name); 10666} 10667 10668/* Target hook for early folding of built-ins, shamelessly stolen 10669 from ia64.c. */ 10670 10671tree 10672rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED, 10673 int n_args ATTRIBUTE_UNUSED, 10674 tree *args ATTRIBUTE_UNUSED, 10675 bool ignore ATTRIBUTE_UNUSED) 10676{ 10677#ifdef SUBTARGET_FOLD_BUILTIN 10678 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore); 10679#else 10680 return NULL_TREE; 10681#endif 10682} 10683 10684/* Helper function to sort out which built-ins may be valid without having 10685 a LHS. */ 10686static bool 10687rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code) 10688{ 10689 /* Check for built-ins explicitly marked as a void function. */ 10690 if (rs6000_builtin_info[fn_code].attr & RS6000_BTC_VOID) 10691 return true; 10692 10693 switch (fn_code) 10694 { 10695 case ALTIVEC_BUILTIN_STVX_V16QI: 10696 case ALTIVEC_BUILTIN_STVX_V8HI: 10697 case ALTIVEC_BUILTIN_STVX_V4SI: 10698 case ALTIVEC_BUILTIN_STVX_V4SF: 10699 case ALTIVEC_BUILTIN_STVX_V2DI: 10700 case ALTIVEC_BUILTIN_STVX_V2DF: 10701 case VSX_BUILTIN_STXVW4X_V16QI: 10702 case VSX_BUILTIN_STXVW4X_V8HI: 10703 case VSX_BUILTIN_STXVW4X_V4SF: 10704 case VSX_BUILTIN_STXVW4X_V4SI: 10705 case VSX_BUILTIN_STXVD2X_V2DF: 10706 case VSX_BUILTIN_STXVD2X_V2DI: 10707 return true; 10708 default: 10709 return false; 10710 } 10711} 10712 10713/* Helper function to handle the gimple folding of a vector compare 10714 operation. This sets up true/false vectors, and uses the 10715 VEC_COND_EXPR operation. 10716 CODE indicates which comparison is to be made. (EQ, GT, ...). 10717 TYPE indicates the type of the result. */ 10718static tree 10719fold_build_vec_cmp (tree_code code, tree type, 10720 tree arg0, tree arg1) 10721{ 10722 tree cmp_type = truth_type_for (type); 10723 tree zero_vec = build_zero_cst (type); 10724 tree minus_one_vec = build_minus_one_cst (type); 10725 tree cmp = fold_build2 (code, cmp_type, arg0, arg1); 10726 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec); 10727} 10728 10729/* Helper function to handle the in-between steps for the 10730 vector compare built-ins. */ 10731static void 10732fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt) 10733{ 10734 tree arg0 = gimple_call_arg (stmt, 0); 10735 tree arg1 = gimple_call_arg (stmt, 1); 10736 tree lhs = gimple_call_lhs (stmt); 10737 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1); 10738 gimple *g = gimple_build_assign (lhs, cmp); 10739 gimple_set_location (g, gimple_location (stmt)); 10740 gsi_replace (gsi, g, true); 10741} 10742 10743/* Helper function to map V2DF and V4SF types to their 10744 integral equivalents (V2DI and V4SI). */ 10745tree map_to_integral_tree_type (tree input_tree_type) 10746{ 10747 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type))) 10748 return input_tree_type; 10749 else 10750 { 10751 if (types_compatible_p (TREE_TYPE (input_tree_type), 10752 TREE_TYPE (V2DF_type_node))) 10753 return V2DI_type_node; 10754 else if (types_compatible_p (TREE_TYPE (input_tree_type), 10755 TREE_TYPE (V4SF_type_node))) 10756 return V4SI_type_node; 10757 else 10758 gcc_unreachable (); 10759 } 10760} 10761 10762/* Helper function to handle the vector merge[hl] built-ins. The 10763 implementation difference between h and l versions for this code are in 10764 the values used when building of the permute vector for high word versus 10765 low word merge. The variance is keyed off the use_high parameter. */ 10766static void 10767fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high) 10768{ 10769 tree arg0 = gimple_call_arg (stmt, 0); 10770 tree arg1 = gimple_call_arg (stmt, 1); 10771 tree lhs = gimple_call_lhs (stmt); 10772 tree lhs_type = TREE_TYPE (lhs); 10773 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); 10774 int midpoint = n_elts / 2; 10775 int offset = 0; 10776 10777 if (use_high == 1) 10778 offset = midpoint; 10779 10780 /* The permute_type will match the lhs for integral types. For double and 10781 float types, the permute type needs to map to the V2 or V4 type that 10782 matches size. */ 10783 tree permute_type; 10784 permute_type = map_to_integral_tree_type (lhs_type); 10785 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); 10786 10787 for (int i = 0; i < midpoint; i++) 10788 { 10789 elts.safe_push (build_int_cst (TREE_TYPE (permute_type), 10790 offset + i)); 10791 elts.safe_push (build_int_cst (TREE_TYPE (permute_type), 10792 offset + n_elts + i)); 10793 } 10794 10795 tree permute = elts.build (); 10796 10797 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); 10798 gimple_set_location (g, gimple_location (stmt)); 10799 gsi_replace (gsi, g, true); 10800} 10801 10802/* Helper function to handle the vector merge[eo] built-ins. */ 10803static void 10804fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd) 10805{ 10806 tree arg0 = gimple_call_arg (stmt, 0); 10807 tree arg1 = gimple_call_arg (stmt, 1); 10808 tree lhs = gimple_call_lhs (stmt); 10809 tree lhs_type = TREE_TYPE (lhs); 10810 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); 10811 10812 /* The permute_type will match the lhs for integral types. For double and 10813 float types, the permute type needs to map to the V2 or V4 type that 10814 matches size. */ 10815 tree permute_type; 10816 permute_type = map_to_integral_tree_type (lhs_type); 10817 10818 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); 10819 10820 /* Build the permute vector. */ 10821 for (int i = 0; i < n_elts / 2; i++) 10822 { 10823 elts.safe_push (build_int_cst (TREE_TYPE (permute_type), 10824 2*i + use_odd)); 10825 elts.safe_push (build_int_cst (TREE_TYPE (permute_type), 10826 2*i + use_odd + n_elts)); 10827 } 10828 10829 tree permute = elts.build (); 10830 10831 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); 10832 gimple_set_location (g, gimple_location (stmt)); 10833 gsi_replace (gsi, g, true); 10834} 10835 10836/* Expand the MMA built-ins early, so that we can convert the pass-by-reference 10837 __vector_quad arguments into pass-by-value arguments, leading to more 10838 efficient code generation. */ 10839 10840bool 10841rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi) 10842{ 10843 gimple *stmt = gsi_stmt (*gsi); 10844 tree fndecl = gimple_call_fndecl (stmt); 10845 enum rs6000_builtins fncode 10846 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 10847 unsigned attr = rs6000_builtin_info[fncode].attr; 10848 10849 if ((attr & RS6000_BTC_GIMPLE) == 0) 10850 return false; 10851 10852 unsigned nopnds = (attr & RS6000_BTC_OPND_MASK); 10853 gimple_seq new_seq = NULL; 10854 gimple *new_call; 10855 tree new_decl; 10856 10857 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC 10858 || fncode == VSX_BUILTIN_DISASSEMBLE_PAIR) 10859 { 10860 /* This is an MMA disassemble built-in function. */ 10861 push_gimplify_context (true); 10862 tree dst_ptr = gimple_call_arg (stmt, 0); 10863 tree src_ptr = gimple_call_arg (stmt, 1); 10864 tree src_type = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) 10865 ? build_pointer_type (vector_quad_type_node) 10866 : build_pointer_type (vector_pair_type_node); 10867 if (TREE_TYPE (src_ptr) != src_type) 10868 src_ptr = build1 (NOP_EXPR, src_type, src_ptr); 10869 10870 tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); 10871 gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); 10872 10873 /* If we are disassembling an accumulator/pair and our destination is 10874 another accumulator/pair, then just copy the entire thing as is. */ 10875 if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC 10876 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) 10877 || (fncode == VSX_BUILTIN_DISASSEMBLE_PAIR 10878 && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) 10879 { 10880 tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, 10881 src_type, dst_ptr)); 10882 gimplify_assign (dst, src, &new_seq); 10883 pop_gimplify_context (NULL); 10884 gsi_replace_with_seq (gsi, new_seq, true); 10885 return true; 10886 } 10887 10888 /* We're disassembling an accumulator into a different type, so we need 10889 to emit a xxmfacc instruction now, since we cannot do it later. */ 10890 if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) 10891 { 10892 new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL]; 10893 new_call = gimple_build_call (new_decl, 1, src); 10894 src = create_tmp_reg_or_ssa_name (vector_quad_type_node); 10895 gimple_call_set_lhs (new_call, src); 10896 gimple_seq_add_stmt (&new_seq, new_call); 10897 } 10898 10899 /* Copy the accumulator/pair vector by vector. */ 10900 unsigned nvecs = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2; 10901 tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, 10902 ptr_mode, true); 10903 tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); 10904 tree array_type = build_array_type_nelts (unsigned_V16QI_type_node, nvecs); 10905 tree src_array = build1 (VIEW_CONVERT_EXPR, array_type, src); 10906 for (unsigned i = 0; i < nvecs; i++) 10907 { 10908 unsigned index = WORDS_BIG_ENDIAN ? i : nvecs - 1 - i; 10909 tree ref = build4 (ARRAY_REF, unsigned_V16QI_type_node, src_array, 10910 build_int_cst (size_type_node, i), 10911 NULL_TREE, NULL_TREE); 10912 tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, 10913 build_int_cst (dst_type, index * 16)); 10914 gimplify_assign (dst, ref, &new_seq); 10915 } 10916 pop_gimplify_context (NULL); 10917 gsi_replace_with_seq (gsi, new_seq, true); 10918 return true; 10919 } 10920 else if (fncode == VSX_BUILTIN_LXVP) 10921 { 10922 push_gimplify_context (true); 10923 tree offset = gimple_call_arg (stmt, 0); 10924 tree ptr = gimple_call_arg (stmt, 1); 10925 tree lhs = gimple_call_lhs (stmt); 10926 if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) 10927 ptr = build1 (VIEW_CONVERT_EXPR, 10928 build_pointer_type (vector_pair_type_node), ptr); 10929 tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, 10930 TREE_TYPE (ptr), ptr, offset)); 10931 gimplify_assign (lhs, mem, &new_seq); 10932 pop_gimplify_context (NULL); 10933 gsi_replace_with_seq (gsi, new_seq, true); 10934 return true; 10935 } 10936 else if (fncode == VSX_BUILTIN_STXVP) 10937 { 10938 push_gimplify_context (true); 10939 tree src = gimple_call_arg (stmt, 0); 10940 tree offset = gimple_call_arg (stmt, 1); 10941 tree ptr = gimple_call_arg (stmt, 2); 10942 if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) 10943 ptr = build1 (VIEW_CONVERT_EXPR, 10944 build_pointer_type (vector_pair_type_node), ptr); 10945 tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, 10946 TREE_TYPE (ptr), ptr, offset)); 10947 gimplify_assign (mem, src, &new_seq); 10948 pop_gimplify_context (NULL); 10949 gsi_replace_with_seq (gsi, new_seq, true); 10950 return true; 10951 } 10952 10953 /* Convert this built-in into an internal version that uses pass-by-value 10954 arguments. The internal built-in follows immediately after this one. */ 10955 new_decl = rs6000_builtin_decls[fncode + 1]; 10956 tree lhs, op[MAX_MMA_OPERANDS]; 10957 tree acc = gimple_call_arg (stmt, 0); 10958 push_gimplify_context (true); 10959 10960 if ((attr & RS6000_BTC_QUAD) != 0) 10961 { 10962 /* This built-in has a pass-by-reference accumulator input, so load it 10963 into a temporary accumulator for use as a pass-by-value input. */ 10964 op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); 10965 for (unsigned i = 1; i < nopnds; i++) 10966 op[i] = gimple_call_arg (stmt, i); 10967 gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); 10968 } 10969 else 10970 { 10971 /* This built-in does not use its pass-by-reference accumulator argument 10972 as an input argument, so remove it from the input list. */ 10973 nopnds--; 10974 for (unsigned i = 0; i < nopnds; i++) 10975 op[i] = gimple_call_arg (stmt, i + 1); 10976 } 10977 10978 switch (nopnds) 10979 { 10980 case 0: 10981 new_call = gimple_build_call (new_decl, 0); 10982 break; 10983 case 1: 10984 new_call = gimple_build_call (new_decl, 1, op[0]); 10985 break; 10986 case 2: 10987 new_call = gimple_build_call (new_decl, 2, op[0], op[1]); 10988 break; 10989 case 3: 10990 new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); 10991 break; 10992 case 4: 10993 new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); 10994 break; 10995 case 5: 10996 new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], 10997 op[4]); 10998 break; 10999 case 6: 11000 new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], 11001 op[4], op[5]); 11002 break; 11003 case 7: 11004 new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], 11005 op[4], op[5], op[6]); 11006 break; 11007 default: 11008 gcc_unreachable (); 11009 } 11010 11011 if (fncode == VSX_BUILTIN_BUILD_PAIR || fncode == VSX_BUILTIN_ASSEMBLE_PAIR) 11012 lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); 11013 else 11014 lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); 11015 gimple_call_set_lhs (new_call, lhs); 11016 gimple_seq_add_stmt (&new_seq, new_call); 11017 gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); 11018 pop_gimplify_context (NULL); 11019 gsi_replace_with_seq (gsi, new_seq, true); 11020 11021 return true; 11022} 11023 11024/* Fold a machine-dependent built-in in GIMPLE. (For folding into 11025 a constant, use rs6000_fold_builtin.) */ 11026 11027bool 11028rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) 11029{ 11030 gimple *stmt = gsi_stmt (*gsi); 11031 tree fndecl = gimple_call_fndecl (stmt); 11032 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD); 11033 enum rs6000_builtins fn_code 11034 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 11035 tree arg0, arg1, lhs, temp; 11036 enum tree_code bcode; 11037 gimple *g; 11038 11039 size_t uns_fncode = (size_t) fn_code; 11040 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode; 11041 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name; 11042 const char *fn_name2 = (icode != CODE_FOR_nothing) 11043 ? get_insn_name ((int) icode) 11044 : "nothing"; 11045 11046 if (TARGET_DEBUG_BUILTIN) 11047 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n", 11048 fn_code, fn_name1, fn_name2); 11049 11050 if (!rs6000_fold_gimple) 11051 return false; 11052 11053 /* Prevent gimple folding for code that does not have a LHS, unless it is 11054 allowed per the rs6000_builtin_valid_without_lhs helper function. */ 11055 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code)) 11056 return false; 11057 11058 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */ 11059 if (!rs6000_builtin_is_supported_p (fn_code)) 11060 return false; 11061 11062 if (rs6000_gimple_fold_mma_builtin (gsi)) 11063 return true; 11064 11065 switch (fn_code) 11066 { 11067 /* Flavors of vec_add. We deliberately don't expand 11068 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to 11069 TImode, resulting in much poorer code generation. */ 11070 case ALTIVEC_BUILTIN_VADDUBM: 11071 case ALTIVEC_BUILTIN_VADDUHM: 11072 case ALTIVEC_BUILTIN_VADDUWM: 11073 case P8V_BUILTIN_VADDUDM: 11074 case ALTIVEC_BUILTIN_VADDFP: 11075 case VSX_BUILTIN_XVADDDP: 11076 bcode = PLUS_EXPR; 11077 do_binary: 11078 arg0 = gimple_call_arg (stmt, 0); 11079 arg1 = gimple_call_arg (stmt, 1); 11080 lhs = gimple_call_lhs (stmt); 11081 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs))) 11082 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs)))) 11083 { 11084 /* Ensure the binary operation is performed in a type 11085 that wraps if it is integral type. */ 11086 gimple_seq stmts = NULL; 11087 tree type = unsigned_type_for (TREE_TYPE (lhs)); 11088 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11089 type, arg0); 11090 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11091 type, arg1); 11092 tree res = gimple_build (&stmts, gimple_location (stmt), bcode, 11093 type, uarg0, uarg1); 11094 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11095 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, 11096 build1 (VIEW_CONVERT_EXPR, 11097 TREE_TYPE (lhs), res)); 11098 gsi_replace (gsi, g, true); 11099 return true; 11100 } 11101 g = gimple_build_assign (lhs, bcode, arg0, arg1); 11102 gimple_set_location (g, gimple_location (stmt)); 11103 gsi_replace (gsi, g, true); 11104 return true; 11105 /* Flavors of vec_sub. We deliberately don't expand 11106 P8V_BUILTIN_VSUBUQM. */ 11107 case ALTIVEC_BUILTIN_VSUBUBM: 11108 case ALTIVEC_BUILTIN_VSUBUHM: 11109 case ALTIVEC_BUILTIN_VSUBUWM: 11110 case P8V_BUILTIN_VSUBUDM: 11111 case ALTIVEC_BUILTIN_VSUBFP: 11112 case VSX_BUILTIN_XVSUBDP: 11113 bcode = MINUS_EXPR; 11114 goto do_binary; 11115 case VSX_BUILTIN_XVMULSP: 11116 case VSX_BUILTIN_XVMULDP: 11117 arg0 = gimple_call_arg (stmt, 0); 11118 arg1 = gimple_call_arg (stmt, 1); 11119 lhs = gimple_call_lhs (stmt); 11120 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1); 11121 gimple_set_location (g, gimple_location (stmt)); 11122 gsi_replace (gsi, g, true); 11123 return true; 11124 /* Even element flavors of vec_mul (signed). */ 11125 case ALTIVEC_BUILTIN_VMULESB: 11126 case ALTIVEC_BUILTIN_VMULESH: 11127 case P8V_BUILTIN_VMULESW: 11128 /* Even element flavors of vec_mul (unsigned). */ 11129 case ALTIVEC_BUILTIN_VMULEUB: 11130 case ALTIVEC_BUILTIN_VMULEUH: 11131 case P8V_BUILTIN_VMULEUW: 11132 arg0 = gimple_call_arg (stmt, 0); 11133 arg1 = gimple_call_arg (stmt, 1); 11134 lhs = gimple_call_lhs (stmt); 11135 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1); 11136 gimple_set_location (g, gimple_location (stmt)); 11137 gsi_replace (gsi, g, true); 11138 return true; 11139 /* Odd element flavors of vec_mul (signed). */ 11140 case ALTIVEC_BUILTIN_VMULOSB: 11141 case ALTIVEC_BUILTIN_VMULOSH: 11142 case P8V_BUILTIN_VMULOSW: 11143 /* Odd element flavors of vec_mul (unsigned). */ 11144 case ALTIVEC_BUILTIN_VMULOUB: 11145 case ALTIVEC_BUILTIN_VMULOUH: 11146 case P8V_BUILTIN_VMULOUW: 11147 arg0 = gimple_call_arg (stmt, 0); 11148 arg1 = gimple_call_arg (stmt, 1); 11149 lhs = gimple_call_lhs (stmt); 11150 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1); 11151 gimple_set_location (g, gimple_location (stmt)); 11152 gsi_replace (gsi, g, true); 11153 return true; 11154 /* Flavors of vec_div (Integer). */ 11155 case VSX_BUILTIN_DIV_V2DI: 11156 case VSX_BUILTIN_UDIV_V2DI: 11157 arg0 = gimple_call_arg (stmt, 0); 11158 arg1 = gimple_call_arg (stmt, 1); 11159 lhs = gimple_call_lhs (stmt); 11160 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1); 11161 gimple_set_location (g, gimple_location (stmt)); 11162 gsi_replace (gsi, g, true); 11163 return true; 11164 /* Flavors of vec_div (Float). */ 11165 case VSX_BUILTIN_XVDIVSP: 11166 case VSX_BUILTIN_XVDIVDP: 11167 arg0 = gimple_call_arg (stmt, 0); 11168 arg1 = gimple_call_arg (stmt, 1); 11169 lhs = gimple_call_lhs (stmt); 11170 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1); 11171 gimple_set_location (g, gimple_location (stmt)); 11172 gsi_replace (gsi, g, true); 11173 return true; 11174 /* Flavors of vec_and. */ 11175 case ALTIVEC_BUILTIN_VAND_V16QI_UNS: 11176 case ALTIVEC_BUILTIN_VAND_V16QI: 11177 case ALTIVEC_BUILTIN_VAND_V8HI_UNS: 11178 case ALTIVEC_BUILTIN_VAND_V8HI: 11179 case ALTIVEC_BUILTIN_VAND_V4SI_UNS: 11180 case ALTIVEC_BUILTIN_VAND_V4SI: 11181 case ALTIVEC_BUILTIN_VAND_V2DI_UNS: 11182 case ALTIVEC_BUILTIN_VAND_V2DI: 11183 case ALTIVEC_BUILTIN_VAND_V4SF: 11184 case ALTIVEC_BUILTIN_VAND_V2DF: 11185 arg0 = gimple_call_arg (stmt, 0); 11186 arg1 = gimple_call_arg (stmt, 1); 11187 lhs = gimple_call_lhs (stmt); 11188 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1); 11189 gimple_set_location (g, gimple_location (stmt)); 11190 gsi_replace (gsi, g, true); 11191 return true; 11192 /* Flavors of vec_andc. */ 11193 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: 11194 case ALTIVEC_BUILTIN_VANDC_V16QI: 11195 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: 11196 case ALTIVEC_BUILTIN_VANDC_V8HI: 11197 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: 11198 case ALTIVEC_BUILTIN_VANDC_V4SI: 11199 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: 11200 case ALTIVEC_BUILTIN_VANDC_V2DI: 11201 case ALTIVEC_BUILTIN_VANDC_V4SF: 11202 case ALTIVEC_BUILTIN_VANDC_V2DF: 11203 arg0 = gimple_call_arg (stmt, 0); 11204 arg1 = gimple_call_arg (stmt, 1); 11205 lhs = gimple_call_lhs (stmt); 11206 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); 11207 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); 11208 gimple_set_location (g, gimple_location (stmt)); 11209 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11210 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp); 11211 gimple_set_location (g, gimple_location (stmt)); 11212 gsi_replace (gsi, g, true); 11213 return true; 11214 /* Flavors of vec_nand. */ 11215 case P8V_BUILTIN_VEC_NAND: 11216 case P8V_BUILTIN_NAND_V16QI_UNS: 11217 case P8V_BUILTIN_NAND_V16QI: 11218 case P8V_BUILTIN_NAND_V8HI_UNS: 11219 case P8V_BUILTIN_NAND_V8HI: 11220 case P8V_BUILTIN_NAND_V4SI_UNS: 11221 case P8V_BUILTIN_NAND_V4SI: 11222 case P8V_BUILTIN_NAND_V2DI_UNS: 11223 case P8V_BUILTIN_NAND_V2DI: 11224 case P8V_BUILTIN_NAND_V4SF: 11225 case P8V_BUILTIN_NAND_V2DF: 11226 arg0 = gimple_call_arg (stmt, 0); 11227 arg1 = gimple_call_arg (stmt, 1); 11228 lhs = gimple_call_lhs (stmt); 11229 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); 11230 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1); 11231 gimple_set_location (g, gimple_location (stmt)); 11232 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11233 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); 11234 gimple_set_location (g, gimple_location (stmt)); 11235 gsi_replace (gsi, g, true); 11236 return true; 11237 /* Flavors of vec_or. */ 11238 case ALTIVEC_BUILTIN_VOR_V16QI_UNS: 11239 case ALTIVEC_BUILTIN_VOR_V16QI: 11240 case ALTIVEC_BUILTIN_VOR_V8HI_UNS: 11241 case ALTIVEC_BUILTIN_VOR_V8HI: 11242 case ALTIVEC_BUILTIN_VOR_V4SI_UNS: 11243 case ALTIVEC_BUILTIN_VOR_V4SI: 11244 case ALTIVEC_BUILTIN_VOR_V2DI_UNS: 11245 case ALTIVEC_BUILTIN_VOR_V2DI: 11246 case ALTIVEC_BUILTIN_VOR_V4SF: 11247 case ALTIVEC_BUILTIN_VOR_V2DF: 11248 arg0 = gimple_call_arg (stmt, 0); 11249 arg1 = gimple_call_arg (stmt, 1); 11250 lhs = gimple_call_lhs (stmt); 11251 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1); 11252 gimple_set_location (g, gimple_location (stmt)); 11253 gsi_replace (gsi, g, true); 11254 return true; 11255 /* flavors of vec_orc. */ 11256 case P8V_BUILTIN_ORC_V16QI_UNS: 11257 case P8V_BUILTIN_ORC_V16QI: 11258 case P8V_BUILTIN_ORC_V8HI_UNS: 11259 case P8V_BUILTIN_ORC_V8HI: 11260 case P8V_BUILTIN_ORC_V4SI_UNS: 11261 case P8V_BUILTIN_ORC_V4SI: 11262 case P8V_BUILTIN_ORC_V2DI_UNS: 11263 case P8V_BUILTIN_ORC_V2DI: 11264 case P8V_BUILTIN_ORC_V4SF: 11265 case P8V_BUILTIN_ORC_V2DF: 11266 arg0 = gimple_call_arg (stmt, 0); 11267 arg1 = gimple_call_arg (stmt, 1); 11268 lhs = gimple_call_lhs (stmt); 11269 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); 11270 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); 11271 gimple_set_location (g, gimple_location (stmt)); 11272 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11273 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp); 11274 gimple_set_location (g, gimple_location (stmt)); 11275 gsi_replace (gsi, g, true); 11276 return true; 11277 /* Flavors of vec_xor. */ 11278 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: 11279 case ALTIVEC_BUILTIN_VXOR_V16QI: 11280 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: 11281 case ALTIVEC_BUILTIN_VXOR_V8HI: 11282 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: 11283 case ALTIVEC_BUILTIN_VXOR_V4SI: 11284 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: 11285 case ALTIVEC_BUILTIN_VXOR_V2DI: 11286 case ALTIVEC_BUILTIN_VXOR_V4SF: 11287 case ALTIVEC_BUILTIN_VXOR_V2DF: 11288 arg0 = gimple_call_arg (stmt, 0); 11289 arg1 = gimple_call_arg (stmt, 1); 11290 lhs = gimple_call_lhs (stmt); 11291 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1); 11292 gimple_set_location (g, gimple_location (stmt)); 11293 gsi_replace (gsi, g, true); 11294 return true; 11295 /* Flavors of vec_nor. */ 11296 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: 11297 case ALTIVEC_BUILTIN_VNOR_V16QI: 11298 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: 11299 case ALTIVEC_BUILTIN_VNOR_V8HI: 11300 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: 11301 case ALTIVEC_BUILTIN_VNOR_V4SI: 11302 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: 11303 case ALTIVEC_BUILTIN_VNOR_V2DI: 11304 case ALTIVEC_BUILTIN_VNOR_V4SF: 11305 case ALTIVEC_BUILTIN_VNOR_V2DF: 11306 arg0 = gimple_call_arg (stmt, 0); 11307 arg1 = gimple_call_arg (stmt, 1); 11308 lhs = gimple_call_lhs (stmt); 11309 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); 11310 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1); 11311 gimple_set_location (g, gimple_location (stmt)); 11312 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11313 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); 11314 gimple_set_location (g, gimple_location (stmt)); 11315 gsi_replace (gsi, g, true); 11316 return true; 11317 /* flavors of vec_abs. */ 11318 case ALTIVEC_BUILTIN_ABS_V16QI: 11319 case ALTIVEC_BUILTIN_ABS_V8HI: 11320 case ALTIVEC_BUILTIN_ABS_V4SI: 11321 case ALTIVEC_BUILTIN_ABS_V4SF: 11322 case P8V_BUILTIN_ABS_V2DI: 11323 case VSX_BUILTIN_XVABSDP: 11324 arg0 = gimple_call_arg (stmt, 0); 11325 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0))) 11326 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0)))) 11327 return false; 11328 lhs = gimple_call_lhs (stmt); 11329 g = gimple_build_assign (lhs, ABS_EXPR, arg0); 11330 gimple_set_location (g, gimple_location (stmt)); 11331 gsi_replace (gsi, g, true); 11332 return true; 11333 /* flavors of vec_min. */ 11334 case VSX_BUILTIN_XVMINDP: 11335 case P8V_BUILTIN_VMINSD: 11336 case P8V_BUILTIN_VMINUD: 11337 case ALTIVEC_BUILTIN_VMINSB: 11338 case ALTIVEC_BUILTIN_VMINSH: 11339 case ALTIVEC_BUILTIN_VMINSW: 11340 case ALTIVEC_BUILTIN_VMINUB: 11341 case ALTIVEC_BUILTIN_VMINUH: 11342 case ALTIVEC_BUILTIN_VMINUW: 11343 case ALTIVEC_BUILTIN_VMINFP: 11344 arg0 = gimple_call_arg (stmt, 0); 11345 arg1 = gimple_call_arg (stmt, 1); 11346 lhs = gimple_call_lhs (stmt); 11347 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1); 11348 gimple_set_location (g, gimple_location (stmt)); 11349 gsi_replace (gsi, g, true); 11350 return true; 11351 /* flavors of vec_max. */ 11352 case VSX_BUILTIN_XVMAXDP: 11353 case P8V_BUILTIN_VMAXSD: 11354 case P8V_BUILTIN_VMAXUD: 11355 case ALTIVEC_BUILTIN_VMAXSB: 11356 case ALTIVEC_BUILTIN_VMAXSH: 11357 case ALTIVEC_BUILTIN_VMAXSW: 11358 case ALTIVEC_BUILTIN_VMAXUB: 11359 case ALTIVEC_BUILTIN_VMAXUH: 11360 case ALTIVEC_BUILTIN_VMAXUW: 11361 case ALTIVEC_BUILTIN_VMAXFP: 11362 arg0 = gimple_call_arg (stmt, 0); 11363 arg1 = gimple_call_arg (stmt, 1); 11364 lhs = gimple_call_lhs (stmt); 11365 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1); 11366 gimple_set_location (g, gimple_location (stmt)); 11367 gsi_replace (gsi, g, true); 11368 return true; 11369 /* Flavors of vec_eqv. */ 11370 case P8V_BUILTIN_EQV_V16QI: 11371 case P8V_BUILTIN_EQV_V8HI: 11372 case P8V_BUILTIN_EQV_V4SI: 11373 case P8V_BUILTIN_EQV_V4SF: 11374 case P8V_BUILTIN_EQV_V2DF: 11375 case P8V_BUILTIN_EQV_V2DI: 11376 arg0 = gimple_call_arg (stmt, 0); 11377 arg1 = gimple_call_arg (stmt, 1); 11378 lhs = gimple_call_lhs (stmt); 11379 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); 11380 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1); 11381 gimple_set_location (g, gimple_location (stmt)); 11382 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11383 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); 11384 gimple_set_location (g, gimple_location (stmt)); 11385 gsi_replace (gsi, g, true); 11386 return true; 11387 /* Flavors of vec_rotate_left. */ 11388 case ALTIVEC_BUILTIN_VRLB: 11389 case ALTIVEC_BUILTIN_VRLH: 11390 case ALTIVEC_BUILTIN_VRLW: 11391 case P8V_BUILTIN_VRLD: 11392 arg0 = gimple_call_arg (stmt, 0); 11393 arg1 = gimple_call_arg (stmt, 1); 11394 lhs = gimple_call_lhs (stmt); 11395 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); 11396 gimple_set_location (g, gimple_location (stmt)); 11397 gsi_replace (gsi, g, true); 11398 return true; 11399 /* Flavors of vector shift right algebraic. 11400 vec_sra{b,h,w} -> vsra{b,h,w}. */ 11401 case ALTIVEC_BUILTIN_VSRAB: 11402 case ALTIVEC_BUILTIN_VSRAH: 11403 case ALTIVEC_BUILTIN_VSRAW: 11404 case P8V_BUILTIN_VSRAD: 11405 { 11406 arg0 = gimple_call_arg (stmt, 0); 11407 arg1 = gimple_call_arg (stmt, 1); 11408 lhs = gimple_call_lhs (stmt); 11409 tree arg1_type = TREE_TYPE (arg1); 11410 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); 11411 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); 11412 location_t loc = gimple_location (stmt); 11413 /* Force arg1 into the range valid matching the arg0 type. */ 11414 /* Build a vector consisting of the max valid bit-size values. */ 11415 int n_elts = VECTOR_CST_NELTS (arg1); 11416 tree element_size = build_int_cst (unsigned_element_type, 11417 128 / n_elts); 11418 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); 11419 for (int i = 0; i < n_elts; i++) 11420 elts.safe_push (element_size); 11421 tree modulo_tree = elts.build (); 11422 /* Modulo the provided shift value against that vector. */ 11423 gimple_seq stmts = NULL; 11424 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11425 unsigned_arg1_type, arg1); 11426 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, 11427 unsigned_arg1_type, unsigned_arg1, 11428 modulo_tree); 11429 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11430 /* And finally, do the shift. */ 11431 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1); 11432 gimple_set_location (g, loc); 11433 gsi_replace (gsi, g, true); 11434 return true; 11435 } 11436 /* Flavors of vector shift left. 11437 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ 11438 case ALTIVEC_BUILTIN_VSLB: 11439 case ALTIVEC_BUILTIN_VSLH: 11440 case ALTIVEC_BUILTIN_VSLW: 11441 case P8V_BUILTIN_VSLD: 11442 { 11443 location_t loc; 11444 gimple_seq stmts = NULL; 11445 arg0 = gimple_call_arg (stmt, 0); 11446 tree arg0_type = TREE_TYPE (arg0); 11447 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type)) 11448 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type))) 11449 return false; 11450 arg1 = gimple_call_arg (stmt, 1); 11451 tree arg1_type = TREE_TYPE (arg1); 11452 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); 11453 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); 11454 loc = gimple_location (stmt); 11455 lhs = gimple_call_lhs (stmt); 11456 /* Force arg1 into the range valid matching the arg0 type. */ 11457 /* Build a vector consisting of the max valid bit-size values. */ 11458 int n_elts = VECTOR_CST_NELTS (arg1); 11459 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type)) 11460 * BITS_PER_UNIT; 11461 tree element_size = build_int_cst (unsigned_element_type, 11462 tree_size_in_bits / n_elts); 11463 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1); 11464 for (int i = 0; i < n_elts; i++) 11465 elts.safe_push (element_size); 11466 tree modulo_tree = elts.build (); 11467 /* Modulo the provided shift value against that vector. */ 11468 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11469 unsigned_arg1_type, arg1); 11470 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, 11471 unsigned_arg1_type, unsigned_arg1, 11472 modulo_tree); 11473 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11474 /* And finally, do the shift. */ 11475 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1); 11476 gimple_set_location (g, gimple_location (stmt)); 11477 gsi_replace (gsi, g, true); 11478 return true; 11479 } 11480 /* Flavors of vector shift right. */ 11481 case ALTIVEC_BUILTIN_VSRB: 11482 case ALTIVEC_BUILTIN_VSRH: 11483 case ALTIVEC_BUILTIN_VSRW: 11484 case P8V_BUILTIN_VSRD: 11485 { 11486 arg0 = gimple_call_arg (stmt, 0); 11487 arg1 = gimple_call_arg (stmt, 1); 11488 lhs = gimple_call_lhs (stmt); 11489 tree arg1_type = TREE_TYPE (arg1); 11490 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); 11491 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); 11492 location_t loc = gimple_location (stmt); 11493 gimple_seq stmts = NULL; 11494 /* Convert arg0 to unsigned. */ 11495 tree arg0_unsigned 11496 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11497 unsigned_type_for (TREE_TYPE (arg0)), arg0); 11498 /* Force arg1 into the range valid matching the arg0 type. */ 11499 /* Build a vector consisting of the max valid bit-size values. */ 11500 int n_elts = VECTOR_CST_NELTS (arg1); 11501 tree element_size = build_int_cst (unsigned_element_type, 11502 128 / n_elts); 11503 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); 11504 for (int i = 0; i < n_elts; i++) 11505 elts.safe_push (element_size); 11506 tree modulo_tree = elts.build (); 11507 /* Modulo the provided shift value against that vector. */ 11508 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, 11509 unsigned_arg1_type, arg1); 11510 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, 11511 unsigned_arg1_type, unsigned_arg1, 11512 modulo_tree); 11513 /* Do the shift. */ 11514 tree res 11515 = gimple_build (&stmts, RSHIFT_EXPR, 11516 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1); 11517 /* Convert result back to the lhs type. */ 11518 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res); 11519 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11520 update_call_from_tree (gsi, res); 11521 return true; 11522 } 11523 /* Vector loads. */ 11524 case ALTIVEC_BUILTIN_LVX_V16QI: 11525 case ALTIVEC_BUILTIN_LVX_V8HI: 11526 case ALTIVEC_BUILTIN_LVX_V4SI: 11527 case ALTIVEC_BUILTIN_LVX_V4SF: 11528 case ALTIVEC_BUILTIN_LVX_V2DI: 11529 case ALTIVEC_BUILTIN_LVX_V2DF: 11530 case ALTIVEC_BUILTIN_LVX_V1TI: 11531 { 11532 arg0 = gimple_call_arg (stmt, 0); // offset 11533 arg1 = gimple_call_arg (stmt, 1); // address 11534 lhs = gimple_call_lhs (stmt); 11535 location_t loc = gimple_location (stmt); 11536 /* Since arg1 may be cast to a different type, just use ptr_type_node 11537 here instead of trying to enforce TBAA on pointer types. */ 11538 tree arg1_type = ptr_type_node; 11539 tree lhs_type = TREE_TYPE (lhs); 11540 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create 11541 the tree using the value from arg0. The resulting type will match 11542 the type of arg1. */ 11543 gimple_seq stmts = NULL; 11544 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); 11545 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, 11546 arg1_type, arg1, temp_offset); 11547 /* Mask off any lower bits from the address. */ 11548 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, 11549 arg1_type, temp_addr, 11550 build_int_cst (arg1_type, -16)); 11551 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11552 if (!is_gimple_mem_ref_addr (aligned_addr)) 11553 { 11554 tree t = make_ssa_name (TREE_TYPE (aligned_addr)); 11555 gimple *g = gimple_build_assign (t, aligned_addr); 11556 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11557 aligned_addr = t; 11558 } 11559 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also 11560 take an offset, but since we've already incorporated the offset 11561 above, here we just pass in a zero. */ 11562 gimple *g 11563 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr, 11564 build_int_cst (arg1_type, 0))); 11565 gimple_set_location (g, loc); 11566 gsi_replace (gsi, g, true); 11567 return true; 11568 } 11569 /* Vector stores. */ 11570 case ALTIVEC_BUILTIN_STVX_V16QI: 11571 case ALTIVEC_BUILTIN_STVX_V8HI: 11572 case ALTIVEC_BUILTIN_STVX_V4SI: 11573 case ALTIVEC_BUILTIN_STVX_V4SF: 11574 case ALTIVEC_BUILTIN_STVX_V2DI: 11575 case ALTIVEC_BUILTIN_STVX_V2DF: 11576 { 11577 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ 11578 arg1 = gimple_call_arg (stmt, 1); /* Offset. */ 11579 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ 11580 location_t loc = gimple_location (stmt); 11581 tree arg0_type = TREE_TYPE (arg0); 11582 /* Use ptr_type_node (no TBAA) for the arg2_type. 11583 FIXME: (Richard) "A proper fix would be to transition this type as 11584 seen from the frontend to GIMPLE, for example in a similar way we 11585 do for MEM_REFs by piggy-backing that on an extra argument, a 11586 constant zero pointer of the alias pointer type to use (which would 11587 also serve as a type indicator of the store itself). I'd use a 11588 target specific internal function for this (not sure if we can have 11589 those target specific, but I guess if it's folded away then that's 11590 fine) and get away with the overload set." */ 11591 tree arg2_type = ptr_type_node; 11592 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create 11593 the tree using the value from arg0. The resulting type will match 11594 the type of arg2. */ 11595 gimple_seq stmts = NULL; 11596 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); 11597 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, 11598 arg2_type, arg2, temp_offset); 11599 /* Mask off any lower bits from the address. */ 11600 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, 11601 arg2_type, temp_addr, 11602 build_int_cst (arg2_type, -16)); 11603 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11604 if (!is_gimple_mem_ref_addr (aligned_addr)) 11605 { 11606 tree t = make_ssa_name (TREE_TYPE (aligned_addr)); 11607 gimple *g = gimple_build_assign (t, aligned_addr); 11608 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11609 aligned_addr = t; 11610 } 11611 /* The desired gimple result should be similar to: 11612 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */ 11613 gimple *g 11614 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr, 11615 build_int_cst (arg2_type, 0)), arg0); 11616 gimple_set_location (g, loc); 11617 gsi_replace (gsi, g, true); 11618 return true; 11619 } 11620 11621 /* unaligned Vector loads. */ 11622 case VSX_BUILTIN_LXVW4X_V16QI: 11623 case VSX_BUILTIN_LXVW4X_V8HI: 11624 case VSX_BUILTIN_LXVW4X_V4SF: 11625 case VSX_BUILTIN_LXVW4X_V4SI: 11626 case VSX_BUILTIN_LXVD2X_V2DF: 11627 case VSX_BUILTIN_LXVD2X_V2DI: 11628 { 11629 arg0 = gimple_call_arg (stmt, 0); // offset 11630 arg1 = gimple_call_arg (stmt, 1); // address 11631 lhs = gimple_call_lhs (stmt); 11632 location_t loc = gimple_location (stmt); 11633 /* Since arg1 may be cast to a different type, just use ptr_type_node 11634 here instead of trying to enforce TBAA on pointer types. */ 11635 tree arg1_type = ptr_type_node; 11636 tree lhs_type = TREE_TYPE (lhs); 11637 /* In GIMPLE the type of the MEM_REF specifies the alignment. The 11638 required alignment (power) is 4 bytes regardless of data type. */ 11639 tree align_ltype = build_aligned_type (lhs_type, 4); 11640 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create 11641 the tree using the value from arg0. The resulting type will match 11642 the type of arg1. */ 11643 gimple_seq stmts = NULL; 11644 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); 11645 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, 11646 arg1_type, arg1, temp_offset); 11647 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11648 if (!is_gimple_mem_ref_addr (temp_addr)) 11649 { 11650 tree t = make_ssa_name (TREE_TYPE (temp_addr)); 11651 gimple *g = gimple_build_assign (t, temp_addr); 11652 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11653 temp_addr = t; 11654 } 11655 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also 11656 take an offset, but since we've already incorporated the offset 11657 above, here we just pass in a zero. */ 11658 gimple *g; 11659 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr, 11660 build_int_cst (arg1_type, 0))); 11661 gimple_set_location (g, loc); 11662 gsi_replace (gsi, g, true); 11663 return true; 11664 } 11665 11666 /* unaligned Vector stores. */ 11667 case VSX_BUILTIN_STXVW4X_V16QI: 11668 case VSX_BUILTIN_STXVW4X_V8HI: 11669 case VSX_BUILTIN_STXVW4X_V4SF: 11670 case VSX_BUILTIN_STXVW4X_V4SI: 11671 case VSX_BUILTIN_STXVD2X_V2DF: 11672 case VSX_BUILTIN_STXVD2X_V2DI: 11673 { 11674 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ 11675 arg1 = gimple_call_arg (stmt, 1); /* Offset. */ 11676 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ 11677 location_t loc = gimple_location (stmt); 11678 tree arg0_type = TREE_TYPE (arg0); 11679 /* Use ptr_type_node (no TBAA) for the arg2_type. */ 11680 tree arg2_type = ptr_type_node; 11681 /* In GIMPLE the type of the MEM_REF specifies the alignment. The 11682 required alignment (power) is 4 bytes regardless of data type. */ 11683 tree align_stype = build_aligned_type (arg0_type, 4); 11684 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create 11685 the tree using the value from arg1. */ 11686 gimple_seq stmts = NULL; 11687 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); 11688 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, 11689 arg2_type, arg2, temp_offset); 11690 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11691 if (!is_gimple_mem_ref_addr (temp_addr)) 11692 { 11693 tree t = make_ssa_name (TREE_TYPE (temp_addr)); 11694 gimple *g = gimple_build_assign (t, temp_addr); 11695 gsi_insert_before (gsi, g, GSI_SAME_STMT); 11696 temp_addr = t; 11697 } 11698 gimple *g; 11699 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr, 11700 build_int_cst (arg2_type, 0)), arg0); 11701 gimple_set_location (g, loc); 11702 gsi_replace (gsi, g, true); 11703 return true; 11704 } 11705 11706 /* Vector Fused multiply-add (fma). */ 11707 case ALTIVEC_BUILTIN_VMADDFP: 11708 case VSX_BUILTIN_XVMADDDP: 11709 case ALTIVEC_BUILTIN_VMLADDUHM: 11710 { 11711 arg0 = gimple_call_arg (stmt, 0); 11712 arg1 = gimple_call_arg (stmt, 1); 11713 tree arg2 = gimple_call_arg (stmt, 2); 11714 lhs = gimple_call_lhs (stmt); 11715 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2); 11716 gimple_call_set_lhs (g, lhs); 11717 gimple_call_set_nothrow (g, true); 11718 gimple_set_location (g, gimple_location (stmt)); 11719 gsi_replace (gsi, g, true); 11720 return true; 11721 } 11722 11723 /* Vector compares; EQ, NE, GE, GT, LE. */ 11724 case ALTIVEC_BUILTIN_VCMPEQUB: 11725 case ALTIVEC_BUILTIN_VCMPEQUH: 11726 case ALTIVEC_BUILTIN_VCMPEQUW: 11727 case P8V_BUILTIN_VCMPEQUD: 11728 fold_compare_helper (gsi, EQ_EXPR, stmt); 11729 return true; 11730 11731 case P9V_BUILTIN_CMPNEB: 11732 case P9V_BUILTIN_CMPNEH: 11733 case P9V_BUILTIN_CMPNEW: 11734 fold_compare_helper (gsi, NE_EXPR, stmt); 11735 return true; 11736 11737 case VSX_BUILTIN_CMPGE_16QI: 11738 case VSX_BUILTIN_CMPGE_U16QI: 11739 case VSX_BUILTIN_CMPGE_8HI: 11740 case VSX_BUILTIN_CMPGE_U8HI: 11741 case VSX_BUILTIN_CMPGE_4SI: 11742 case VSX_BUILTIN_CMPGE_U4SI: 11743 case VSX_BUILTIN_CMPGE_2DI: 11744 case VSX_BUILTIN_CMPGE_U2DI: 11745 fold_compare_helper (gsi, GE_EXPR, stmt); 11746 return true; 11747 11748 case ALTIVEC_BUILTIN_VCMPGTSB: 11749 case ALTIVEC_BUILTIN_VCMPGTUB: 11750 case ALTIVEC_BUILTIN_VCMPGTSH: 11751 case ALTIVEC_BUILTIN_VCMPGTUH: 11752 case ALTIVEC_BUILTIN_VCMPGTSW: 11753 case ALTIVEC_BUILTIN_VCMPGTUW: 11754 case P8V_BUILTIN_VCMPGTUD: 11755 case P8V_BUILTIN_VCMPGTSD: 11756 fold_compare_helper (gsi, GT_EXPR, stmt); 11757 return true; 11758 11759 case VSX_BUILTIN_CMPLE_16QI: 11760 case VSX_BUILTIN_CMPLE_U16QI: 11761 case VSX_BUILTIN_CMPLE_8HI: 11762 case VSX_BUILTIN_CMPLE_U8HI: 11763 case VSX_BUILTIN_CMPLE_4SI: 11764 case VSX_BUILTIN_CMPLE_U4SI: 11765 case VSX_BUILTIN_CMPLE_2DI: 11766 case VSX_BUILTIN_CMPLE_U2DI: 11767 fold_compare_helper (gsi, LE_EXPR, stmt); 11768 return true; 11769 11770 /* flavors of vec_splat_[us]{8,16,32}. */ 11771 case ALTIVEC_BUILTIN_VSPLTISB: 11772 case ALTIVEC_BUILTIN_VSPLTISH: 11773 case ALTIVEC_BUILTIN_VSPLTISW: 11774 { 11775 arg0 = gimple_call_arg (stmt, 0); 11776 lhs = gimple_call_lhs (stmt); 11777 11778 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a 11779 5-bit signed constant in range -16 to +15. */ 11780 if (TREE_CODE (arg0) != INTEGER_CST 11781 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15)) 11782 return false; 11783 gimple_seq stmts = NULL; 11784 location_t loc = gimple_location (stmt); 11785 tree splat_value = gimple_convert (&stmts, loc, 11786 TREE_TYPE (TREE_TYPE (lhs)), arg0); 11787 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11788 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value); 11789 g = gimple_build_assign (lhs, splat_tree); 11790 gimple_set_location (g, gimple_location (stmt)); 11791 gsi_replace (gsi, g, true); 11792 return true; 11793 } 11794 11795 /* Flavors of vec_splat. */ 11796 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */ 11797 case ALTIVEC_BUILTIN_VSPLTB: 11798 case ALTIVEC_BUILTIN_VSPLTH: 11799 case ALTIVEC_BUILTIN_VSPLTW: 11800 case VSX_BUILTIN_XXSPLTD_V2DI: 11801 case VSX_BUILTIN_XXSPLTD_V2DF: 11802 { 11803 arg0 = gimple_call_arg (stmt, 0); /* input vector. */ 11804 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */ 11805 /* Only fold the vec_splat_*() if arg1 is both a constant value and 11806 is a valid index into the arg0 vector. */ 11807 unsigned int n_elts = VECTOR_CST_NELTS (arg0); 11808 if (TREE_CODE (arg1) != INTEGER_CST 11809 || TREE_INT_CST_LOW (arg1) > (n_elts -1)) 11810 return false; 11811 lhs = gimple_call_lhs (stmt); 11812 tree lhs_type = TREE_TYPE (lhs); 11813 tree arg0_type = TREE_TYPE (arg0); 11814 tree splat; 11815 if (TREE_CODE (arg0) == VECTOR_CST) 11816 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1)); 11817 else 11818 { 11819 /* Determine (in bits) the length and start location of the 11820 splat value for a call to the tree_vec_extract helper. */ 11821 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type)) 11822 * BITS_PER_UNIT / n_elts; 11823 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size; 11824 tree len = build_int_cst (bitsizetype, splat_elem_size); 11825 tree start = build_int_cst (bitsizetype, splat_start_bit); 11826 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0, 11827 len, start); 11828 } 11829 /* And finally, build the new vector. */ 11830 tree splat_tree = build_vector_from_val (lhs_type, splat); 11831 g = gimple_build_assign (lhs, splat_tree); 11832 gimple_set_location (g, gimple_location (stmt)); 11833 gsi_replace (gsi, g, true); 11834 return true; 11835 } 11836 11837 /* vec_mergel (integrals). */ 11838 case ALTIVEC_BUILTIN_VMRGLH: 11839 case ALTIVEC_BUILTIN_VMRGLW: 11840 case VSX_BUILTIN_XXMRGLW_4SI: 11841 case ALTIVEC_BUILTIN_VMRGLB: 11842 case VSX_BUILTIN_VEC_MERGEL_V2DI: 11843 case VSX_BUILTIN_XXMRGLW_4SF: 11844 case VSX_BUILTIN_VEC_MERGEL_V2DF: 11845 fold_mergehl_helper (gsi, stmt, 1); 11846 return true; 11847 /* vec_mergeh (integrals). */ 11848 case ALTIVEC_BUILTIN_VMRGHH: 11849 case ALTIVEC_BUILTIN_VMRGHW: 11850 case VSX_BUILTIN_XXMRGHW_4SI: 11851 case ALTIVEC_BUILTIN_VMRGHB: 11852 case VSX_BUILTIN_VEC_MERGEH_V2DI: 11853 case VSX_BUILTIN_XXMRGHW_4SF: 11854 case VSX_BUILTIN_VEC_MERGEH_V2DF: 11855 fold_mergehl_helper (gsi, stmt, 0); 11856 return true; 11857 11858 /* Flavors of vec_mergee. */ 11859 case P8V_BUILTIN_VMRGEW_V4SI: 11860 case P8V_BUILTIN_VMRGEW_V2DI: 11861 case P8V_BUILTIN_VMRGEW_V4SF: 11862 case P8V_BUILTIN_VMRGEW_V2DF: 11863 fold_mergeeo_helper (gsi, stmt, 0); 11864 return true; 11865 /* Flavors of vec_mergeo. */ 11866 case P8V_BUILTIN_VMRGOW_V4SI: 11867 case P8V_BUILTIN_VMRGOW_V2DI: 11868 case P8V_BUILTIN_VMRGOW_V4SF: 11869 case P8V_BUILTIN_VMRGOW_V2DF: 11870 fold_mergeeo_helper (gsi, stmt, 1); 11871 return true; 11872 11873 /* d = vec_pack (a, b) */ 11874 case P8V_BUILTIN_VPKUDUM: 11875 case ALTIVEC_BUILTIN_VPKUHUM: 11876 case ALTIVEC_BUILTIN_VPKUWUM: 11877 { 11878 arg0 = gimple_call_arg (stmt, 0); 11879 arg1 = gimple_call_arg (stmt, 1); 11880 lhs = gimple_call_lhs (stmt); 11881 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1); 11882 gimple_set_location (g, gimple_location (stmt)); 11883 gsi_replace (gsi, g, true); 11884 return true; 11885 } 11886 11887 /* d = vec_unpackh (a) */ 11888 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call 11889 in this code is sensitive to endian-ness, and needs to be inverted to 11890 handle both LE and BE targets. */ 11891 case ALTIVEC_BUILTIN_VUPKHSB: 11892 case ALTIVEC_BUILTIN_VUPKHSH: 11893 case P8V_BUILTIN_VUPKHSW: 11894 { 11895 arg0 = gimple_call_arg (stmt, 0); 11896 lhs = gimple_call_lhs (stmt); 11897 if (BYTES_BIG_ENDIAN) 11898 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); 11899 else 11900 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); 11901 gimple_set_location (g, gimple_location (stmt)); 11902 gsi_replace (gsi, g, true); 11903 return true; 11904 } 11905 /* d = vec_unpackl (a) */ 11906 case ALTIVEC_BUILTIN_VUPKLSB: 11907 case ALTIVEC_BUILTIN_VUPKLSH: 11908 case P8V_BUILTIN_VUPKLSW: 11909 { 11910 arg0 = gimple_call_arg (stmt, 0); 11911 lhs = gimple_call_lhs (stmt); 11912 if (BYTES_BIG_ENDIAN) 11913 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); 11914 else 11915 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); 11916 gimple_set_location (g, gimple_location (stmt)); 11917 gsi_replace (gsi, g, true); 11918 return true; 11919 } 11920 /* There is no gimple type corresponding with pixel, so just return. */ 11921 case ALTIVEC_BUILTIN_VUPKHPX: 11922 case ALTIVEC_BUILTIN_VUPKLPX: 11923 return false; 11924 11925 /* vec_perm. */ 11926 case ALTIVEC_BUILTIN_VPERM_16QI: 11927 case ALTIVEC_BUILTIN_VPERM_8HI: 11928 case ALTIVEC_BUILTIN_VPERM_4SI: 11929 case ALTIVEC_BUILTIN_VPERM_2DI: 11930 case ALTIVEC_BUILTIN_VPERM_4SF: 11931 case ALTIVEC_BUILTIN_VPERM_2DF: 11932 { 11933 arg0 = gimple_call_arg (stmt, 0); 11934 arg1 = gimple_call_arg (stmt, 1); 11935 tree permute = gimple_call_arg (stmt, 2); 11936 lhs = gimple_call_lhs (stmt); 11937 location_t loc = gimple_location (stmt); 11938 gimple_seq stmts = NULL; 11939 // convert arg0 and arg1 to match the type of the permute 11940 // for the VEC_PERM_EXPR operation. 11941 tree permute_type = (TREE_TYPE (permute)); 11942 tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, 11943 permute_type, arg0); 11944 tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, 11945 permute_type, arg1); 11946 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR, 11947 permute_type, arg0_ptype, arg1_ptype, 11948 permute); 11949 // Convert the result back to the desired lhs type upon completion. 11950 tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, 11951 TREE_TYPE (lhs), lhs_ptype); 11952 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); 11953 g = gimple_build_assign (lhs, temp); 11954 gimple_set_location (g, loc); 11955 gsi_replace (gsi, g, true); 11956 return true; 11957 } 11958 11959 default: 11960 if (TARGET_DEBUG_BUILTIN) 11961 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n", 11962 fn_code, fn_name1, fn_name2); 11963 break; 11964 } 11965 11966 return false; 11967} 11968 11969/* Expand an expression EXP that calls a built-in function, 11970 with result going to TARGET if that's convenient 11971 (and in mode MODE if that's convenient). 11972 SUBTARGET may be used as the target for computing one of EXP's operands. 11973 IGNORE is nonzero if the value is to be ignored. */ 11974 11975rtx 11976rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 11977 machine_mode mode ATTRIBUTE_UNUSED, 11978 int ignore ATTRIBUTE_UNUSED) 11979{ 11980 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 11981 enum rs6000_builtins fcode 11982 = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); 11983 size_t uns_fcode = (size_t)fcode; 11984 const struct builtin_description *d; 11985 size_t i; 11986 rtx ret; 11987 bool success; 11988 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; 11989 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); 11990 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; 11991 11992 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit 11993 floating point type, depending on whether long double is the IBM extended 11994 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if 11995 we only define one variant of the built-in function, and switch the code 11996 when defining it, rather than defining two built-ins and using the 11997 overload table in rs6000-c.c to switch between the two. If we don't have 11998 the proper assembler, don't do this switch because CODE_FOR_*kf* and 11999 CODE_FOR_*tf* will be CODE_FOR_nothing. */ 12000 if (FLOAT128_IEEE_P (TFmode)) 12001 switch (icode) 12002 { 12003 default: 12004 break; 12005 12006 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break; 12007 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break; 12008 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break; 12009 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break; 12010 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break; 12011 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break; 12012 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break; 12013 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break; 12014 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break; 12015 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break; 12016 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break; 12017 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break; 12018 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break; 12019 } 12020 12021 if (TARGET_DEBUG_BUILTIN) 12022 { 12023 const char *name1 = rs6000_builtin_info[uns_fcode].name; 12024 const char *name2 = (icode != CODE_FOR_nothing) 12025 ? get_insn_name ((int) icode) 12026 : "nothing"; 12027 const char *name3; 12028 12029 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK) 12030 { 12031 default: name3 = "unknown"; break; 12032 case RS6000_BTC_SPECIAL: name3 = "special"; break; 12033 case RS6000_BTC_UNARY: name3 = "unary"; break; 12034 case RS6000_BTC_BINARY: name3 = "binary"; break; 12035 case RS6000_BTC_TERNARY: name3 = "ternary"; break; 12036 case RS6000_BTC_PREDICATE: name3 = "predicate"; break; 12037 case RS6000_BTC_ABS: name3 = "abs"; break; 12038 case RS6000_BTC_DST: name3 = "dst"; break; 12039 } 12040 12041 12042 fprintf (stderr, 12043 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n", 12044 (name1) ? name1 : "---", fcode, 12045 (name2) ? name2 : "---", (int) icode, 12046 name3, 12047 func_valid_p ? "" : ", not valid"); 12048 } 12049 12050 if (!func_valid_p) 12051 { 12052 rs6000_invalid_builtin (fcode); 12053 12054 /* Given it is invalid, just generate a normal call. */ 12055 return expand_call (exp, target, ignore); 12056 } 12057 12058 switch (fcode) 12059 { 12060 case RS6000_BUILTIN_RECIP: 12061 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target); 12062 12063 case RS6000_BUILTIN_RECIPF: 12064 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target); 12065 12066 case RS6000_BUILTIN_RSQRTF: 12067 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target); 12068 12069 case RS6000_BUILTIN_RSQRT: 12070 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target); 12071 12072 case POWER7_BUILTIN_BPERMD: 12073 return rs6000_expand_binop_builtin (((TARGET_64BIT) 12074 ? CODE_FOR_bpermd_di 12075 : CODE_FOR_bpermd_si), exp, target); 12076 12077 case RS6000_BUILTIN_GET_TB: 12078 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase, 12079 target); 12080 12081 case RS6000_BUILTIN_MFTB: 12082 return rs6000_expand_zeroop_builtin (((TARGET_64BIT) 12083 ? CODE_FOR_rs6000_mftb_di 12084 : CODE_FOR_rs6000_mftb_si), 12085 target); 12086 12087 case RS6000_BUILTIN_MFFS: 12088 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target); 12089 12090 case RS6000_BUILTIN_MTFSB0: 12091 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp); 12092 12093 case RS6000_BUILTIN_MTFSB1: 12094 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp); 12095 12096 case RS6000_BUILTIN_SET_FPSCR_RN: 12097 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn, 12098 exp); 12099 12100 case RS6000_BUILTIN_SET_FPSCR_DRN: 12101 return 12102 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn, 12103 exp); 12104 12105 case RS6000_BUILTIN_MFFSL: 12106 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target); 12107 12108 case RS6000_BUILTIN_MTFSF: 12109 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp); 12110 12111 case RS6000_BUILTIN_CPU_INIT: 12112 case RS6000_BUILTIN_CPU_IS: 12113 case RS6000_BUILTIN_CPU_SUPPORTS: 12114 return cpu_expand_builtin (fcode, exp, target); 12115 12116 case MISC_BUILTIN_SPEC_BARRIER: 12117 { 12118 emit_insn (gen_speculation_barrier ()); 12119 return NULL_RTX; 12120 } 12121 12122 case ALTIVEC_BUILTIN_MASK_FOR_LOAD: 12123 case ALTIVEC_BUILTIN_MASK_FOR_STORE: 12124 { 12125 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct 12126 : (int) CODE_FOR_altivec_lvsl_direct); 12127 machine_mode tmode = insn_data[icode2].operand[0].mode; 12128 machine_mode mode = insn_data[icode2].operand[1].mode; 12129 tree arg; 12130 rtx op, addr, pat; 12131 12132 gcc_assert (TARGET_ALTIVEC); 12133 12134 arg = CALL_EXPR_ARG (exp, 0); 12135 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg))); 12136 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); 12137 addr = memory_address (mode, op); 12138 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE) 12139 op = addr; 12140 else 12141 { 12142 /* For the load case need to negate the address. */ 12143 op = gen_reg_rtx (GET_MODE (addr)); 12144 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr))); 12145 } 12146 op = gen_rtx_MEM (mode, op); 12147 12148 if (target == 0 12149 || GET_MODE (target) != tmode 12150 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode)) 12151 target = gen_reg_rtx (tmode); 12152 12153 pat = GEN_FCN (icode2) (target, op); 12154 if (!pat) 12155 return 0; 12156 emit_insn (pat); 12157 12158 return target; 12159 } 12160 12161 case ALTIVEC_BUILTIN_VCFUX: 12162 case ALTIVEC_BUILTIN_VCFSX: 12163 case ALTIVEC_BUILTIN_VCTUXS: 12164 case ALTIVEC_BUILTIN_VCTSXS: 12165 /* FIXME: There's got to be a nicer way to handle this case than 12166 constructing a new CALL_EXPR. */ 12167 if (call_expr_nargs (exp) == 1) 12168 { 12169 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp), 12170 2, CALL_EXPR_ARG (exp, 0), integer_zero_node); 12171 } 12172 break; 12173 12174 /* For the pack and unpack int128 routines, fix up the builtin so it 12175 uses the correct IBM128 type. */ 12176 case MISC_BUILTIN_PACK_IF: 12177 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) 12178 { 12179 icode = CODE_FOR_packtf; 12180 fcode = MISC_BUILTIN_PACK_TF; 12181 uns_fcode = (size_t)fcode; 12182 } 12183 break; 12184 12185 case MISC_BUILTIN_UNPACK_IF: 12186 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) 12187 { 12188 icode = CODE_FOR_unpacktf; 12189 fcode = MISC_BUILTIN_UNPACK_TF; 12190 uns_fcode = (size_t)fcode; 12191 } 12192 break; 12193 12194 default: 12195 break; 12196 } 12197 12198 if (TARGET_MMA) 12199 { 12200 ret = mma_expand_builtin (exp, target, &success); 12201 12202 if (success) 12203 return ret; 12204 } 12205 if (TARGET_ALTIVEC) 12206 { 12207 ret = altivec_expand_builtin (exp, target, &success); 12208 12209 if (success) 12210 return ret; 12211 } 12212 if (TARGET_HTM) 12213 { 12214 ret = htm_expand_builtin (exp, target, &success); 12215 12216 if (success) 12217 return ret; 12218 } 12219 12220 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_OPND_MASK; 12221 /* RS6000_BTC_SPECIAL represents no-operand operators. */ 12222 gcc_assert (attr == RS6000_BTC_UNARY 12223 || attr == RS6000_BTC_BINARY 12224 || attr == RS6000_BTC_TERNARY 12225 || attr == RS6000_BTC_SPECIAL); 12226 12227 /* Handle simple unary operations. */ 12228 d = bdesc_1arg; 12229 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 12230 if (d->code == fcode) 12231 return rs6000_expand_unop_builtin (icode, exp, target); 12232 12233 /* Handle simple binary operations. */ 12234 d = bdesc_2arg; 12235 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 12236 if (d->code == fcode) 12237 return rs6000_expand_binop_builtin (icode, exp, target); 12238 12239 /* Handle simple ternary operations. */ 12240 d = bdesc_3arg; 12241 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) 12242 if (d->code == fcode) 12243 return rs6000_expand_ternop_builtin (icode, exp, target); 12244 12245 /* Handle simple no-argument operations. */ 12246 d = bdesc_0arg; 12247 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) 12248 if (d->code == fcode) 12249 return rs6000_expand_zeroop_builtin (icode, target); 12250 12251 gcc_unreachable (); 12252} 12253 12254/* Create a builtin vector type with a name. Taking care not to give 12255 the canonical type a name. */ 12256 12257static tree 12258rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts) 12259{ 12260 tree result = build_vector_type (elt_type, num_elts); 12261 12262 /* Copy so we don't give the canonical type a name. */ 12263 result = build_variant_type_copy (result); 12264 12265 add_builtin_type (name, result); 12266 12267 return result; 12268} 12269 12270void 12271rs6000_init_builtins (void) 12272{ 12273 tree tdecl; 12274 tree ftype; 12275 machine_mode mode; 12276 12277 if (TARGET_DEBUG_BUILTIN) 12278 fprintf (stderr, "rs6000_init_builtins%s%s\n", 12279 (TARGET_ALTIVEC) ? ", altivec" : "", 12280 (TARGET_VSX) ? ", vsx" : ""); 12281 12282 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long" 12283 : "__vector long long", 12284 long_long_integer_type_node, 2); 12285 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2); 12286 V4SI_type_node = rs6000_vector_type ("__vector signed int", 12287 intSI_type_node, 4); 12288 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4); 12289 V8HI_type_node = rs6000_vector_type ("__vector signed short", 12290 intHI_type_node, 8); 12291 V16QI_type_node = rs6000_vector_type ("__vector signed char", 12292 intQI_type_node, 16); 12293 12294 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char", 12295 unsigned_intQI_type_node, 16); 12296 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short", 12297 unsigned_intHI_type_node, 8); 12298 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int", 12299 unsigned_intSI_type_node, 4); 12300 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 12301 ? "__vector unsigned long" 12302 : "__vector unsigned long long", 12303 long_long_unsigned_type_node, 2); 12304 12305 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); 12306 12307 const_str_type_node 12308 = build_pointer_type (build_qualified_type (char_type_node, 12309 TYPE_QUAL_CONST)); 12310 12311 /* We use V1TI mode as a special container to hold __int128_t items that 12312 must live in VSX registers. */ 12313 if (intTI_type_node) 12314 { 12315 V1TI_type_node = rs6000_vector_type ("__vector __int128", 12316 intTI_type_node, 1); 12317 unsigned_V1TI_type_node 12318 = rs6000_vector_type ("__vector unsigned __int128", 12319 unsigned_intTI_type_node, 1); 12320 } 12321 12322 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' 12323 types, especially in C++ land. Similarly, 'vector pixel' is distinct from 12324 'vector unsigned short'. */ 12325 12326 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); 12327 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); 12328 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); 12329 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node); 12330 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); 12331 12332 long_integer_type_internal_node = long_integer_type_node; 12333 long_unsigned_type_internal_node = long_unsigned_type_node; 12334 long_long_integer_type_internal_node = long_long_integer_type_node; 12335 long_long_unsigned_type_internal_node = long_long_unsigned_type_node; 12336 intQI_type_internal_node = intQI_type_node; 12337 uintQI_type_internal_node = unsigned_intQI_type_node; 12338 intHI_type_internal_node = intHI_type_node; 12339 uintHI_type_internal_node = unsigned_intHI_type_node; 12340 intSI_type_internal_node = intSI_type_node; 12341 uintSI_type_internal_node = unsigned_intSI_type_node; 12342 intDI_type_internal_node = intDI_type_node; 12343 uintDI_type_internal_node = unsigned_intDI_type_node; 12344 intTI_type_internal_node = intTI_type_node; 12345 uintTI_type_internal_node = unsigned_intTI_type_node; 12346 float_type_internal_node = float_type_node; 12347 double_type_internal_node = double_type_node; 12348 long_double_type_internal_node = long_double_type_node; 12349 dfloat64_type_internal_node = dfloat64_type_node; 12350 dfloat128_type_internal_node = dfloat128_type_node; 12351 void_type_internal_node = void_type_node; 12352 12353 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point. 12354 IFmode is the IBM extended 128-bit format that is a pair of doubles. 12355 TFmode will be either IEEE 128-bit floating point or the IBM double-double 12356 format that uses a pair of doubles, depending on the switches and 12357 defaults. 12358 12359 If we don't support for either 128-bit IBM double double or IEEE 128-bit 12360 floating point, we need make sure the type is non-zero or else self-test 12361 fails during bootstrap. 12362 12363 Always create __ibm128 as a separate type, even if the current long double 12364 format is IBM extended double. 12365 12366 For IEEE 128-bit floating point, always create the type __ieee128. If the 12367 user used -mfloat128, rs6000-c.c will create a define from __float128 to 12368 __ieee128. */ 12369 if (TARGET_FLOAT128_TYPE) 12370 { 12371 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) 12372 ibm128_float_type_node = long_double_type_node; 12373 else 12374 { 12375 ibm128_float_type_node = make_node (REAL_TYPE); 12376 TYPE_PRECISION (ibm128_float_type_node) = 128; 12377 SET_TYPE_MODE (ibm128_float_type_node, IFmode); 12378 layout_type (ibm128_float_type_node); 12379 } 12380 12381 lang_hooks.types.register_builtin_type (ibm128_float_type_node, 12382 "__ibm128"); 12383 12384 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) 12385 ieee128_float_type_node = long_double_type_node; 12386 else 12387 ieee128_float_type_node = float128_type_node; 12388 12389 lang_hooks.types.register_builtin_type (ieee128_float_type_node, 12390 "__ieee128"); 12391 } 12392 12393 else 12394 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node; 12395 12396 /* Vector pair and vector quad support. */ 12397 if (TARGET_EXTRA_BUILTINS) 12398 { 12399 vector_pair_type_node = make_unsigned_type (256); 12400 SET_TYPE_ALIGN (vector_pair_type_node, 256); 12401 SET_TYPE_MODE (vector_pair_type_node, POImode); 12402 layout_type (vector_pair_type_node); 12403 lang_hooks.types.register_builtin_type (vector_pair_type_node, 12404 "__vector_pair"); 12405 12406 vector_quad_type_node = make_unsigned_type (512); 12407 SET_TYPE_ALIGN (vector_quad_type_node, 512); 12408 SET_TYPE_MODE (vector_quad_type_node, PXImode); 12409 layout_type (vector_quad_type_node); 12410 lang_hooks.types.register_builtin_type (vector_quad_type_node, 12411 "__vector_quad"); 12412 } 12413 12414 /* Initialize the modes for builtin_function_type, mapping a machine mode to 12415 tree type node. */ 12416 builtin_mode_to_type[QImode][0] = integer_type_node; 12417 builtin_mode_to_type[HImode][0] = integer_type_node; 12418 builtin_mode_to_type[SImode][0] = intSI_type_node; 12419 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node; 12420 builtin_mode_to_type[DImode][0] = intDI_type_node; 12421 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node; 12422 builtin_mode_to_type[TImode][0] = intTI_type_node; 12423 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node; 12424 builtin_mode_to_type[SFmode][0] = float_type_node; 12425 builtin_mode_to_type[DFmode][0] = double_type_node; 12426 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node; 12427 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node; 12428 builtin_mode_to_type[TFmode][0] = long_double_type_node; 12429 builtin_mode_to_type[DDmode][0] = dfloat64_type_node; 12430 builtin_mode_to_type[TDmode][0] = dfloat128_type_node; 12431 builtin_mode_to_type[V1TImode][0] = V1TI_type_node; 12432 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node; 12433 builtin_mode_to_type[V2DImode][0] = V2DI_type_node; 12434 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node; 12435 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node; 12436 builtin_mode_to_type[V4SImode][0] = V4SI_type_node; 12437 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node; 12438 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node; 12439 builtin_mode_to_type[V8HImode][0] = V8HI_type_node; 12440 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node; 12441 builtin_mode_to_type[V16QImode][0] = V16QI_type_node; 12442 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node; 12443 builtin_mode_to_type[POImode][1] = vector_pair_type_node; 12444 builtin_mode_to_type[PXImode][1] = vector_quad_type_node; 12445 12446 tdecl = add_builtin_type ("__bool char", bool_char_type_node); 12447 TYPE_NAME (bool_char_type_node) = tdecl; 12448 12449 tdecl = add_builtin_type ("__bool short", bool_short_type_node); 12450 TYPE_NAME (bool_short_type_node) = tdecl; 12451 12452 tdecl = add_builtin_type ("__bool int", bool_int_type_node); 12453 TYPE_NAME (bool_int_type_node) = tdecl; 12454 12455 tdecl = add_builtin_type ("__pixel", pixel_type_node); 12456 TYPE_NAME (pixel_type_node) = tdecl; 12457 12458 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char", 12459 bool_char_type_node, 16); 12460 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short", 12461 bool_short_type_node, 8); 12462 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int", 12463 bool_int_type_node, 4); 12464 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 12465 ? "__vector __bool long" 12466 : "__vector __bool long long", 12467 bool_long_long_type_node, 2); 12468 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel", 12469 pixel_type_node, 8); 12470 12471 /* Create Altivec, VSX and MMA builtins on machines with at least the 12472 general purpose extensions (970 and newer) to allow the use of 12473 the target attribute. */ 12474 if (TARGET_EXTRA_BUILTINS) 12475 { 12476 altivec_init_builtins (); 12477 mma_init_builtins (); 12478 } 12479 if (TARGET_HTM) 12480 htm_init_builtins (); 12481 12482 if (TARGET_EXTRA_BUILTINS) 12483 rs6000_common_init_builtins (); 12484 12485 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode, 12486 RS6000_BUILTIN_RECIP, "__builtin_recipdiv"); 12487 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP); 12488 12489 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode, 12490 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf"); 12491 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF); 12492 12493 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode, 12494 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt"); 12495 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT); 12496 12497 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode, 12498 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf"); 12499 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF); 12500 12501 mode = (TARGET_64BIT) ? DImode : SImode; 12502 ftype = builtin_function_type (mode, mode, mode, VOIDmode, 12503 POWER7_BUILTIN_BPERMD, "__builtin_bpermd"); 12504 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD); 12505 12506 ftype = build_function_type_list (unsigned_intDI_type_node, 12507 NULL_TREE); 12508 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB); 12509 12510 if (TARGET_64BIT) 12511 ftype = build_function_type_list (unsigned_intDI_type_node, 12512 NULL_TREE); 12513 else 12514 ftype = build_function_type_list (unsigned_intSI_type_node, 12515 NULL_TREE); 12516 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB); 12517 12518 ftype = build_function_type_list (double_type_node, NULL_TREE); 12519 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS); 12520 12521 ftype = build_function_type_list (double_type_node, NULL_TREE); 12522 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL); 12523 12524 ftype = build_function_type_list (void_type_node, 12525 intSI_type_node, 12526 NULL_TREE); 12527 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0); 12528 12529 ftype = build_function_type_list (void_type_node, 12530 intSI_type_node, 12531 NULL_TREE); 12532 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1); 12533 12534 ftype = build_function_type_list (void_type_node, 12535 intDI_type_node, 12536 NULL_TREE); 12537 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN); 12538 12539 ftype = build_function_type_list (void_type_node, 12540 intDI_type_node, 12541 NULL_TREE); 12542 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN); 12543 12544 ftype = build_function_type_list (void_type_node, 12545 intSI_type_node, double_type_node, 12546 NULL_TREE); 12547 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF); 12548 12549 ftype = build_function_type_list (void_type_node, NULL_TREE); 12550 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT); 12551 def_builtin ("__builtin_ppc_speculation_barrier", ftype, 12552 MISC_BUILTIN_SPEC_BARRIER); 12553 12554 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node, 12555 NULL_TREE); 12556 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS); 12557 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS); 12558 12559 if (TARGET_XCOFF) 12560 { 12561 /* AIX libm provides clog as __clog. */ 12562 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE) 12563 set_user_assembler_name (tdecl, "__clog"); 12564 12565 /* When long double is 64 bit, some long double builtins of libc 12566 functions (like __builtin_frexpl) must call the double version 12567 (frexp) not the long double version (frexpl) that expects a 128 bit 12568 argument. */ 12569 if (! TARGET_LONG_DOUBLE_128) 12570 { 12571 if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE) 12572 set_user_assembler_name (tdecl, "fmod"); 12573 if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE) 12574 set_user_assembler_name (tdecl, "frexp"); 12575 if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE) 12576 set_user_assembler_name (tdecl, "ldexp"); 12577 if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE) 12578 set_user_assembler_name (tdecl, "modf"); 12579 } 12580 } 12581 12582#ifdef SUBTARGET_INIT_BUILTINS 12583 SUBTARGET_INIT_BUILTINS; 12584#endif 12585 12586 /* Register the compatibility builtins after all of the normal 12587 builtins have been defined. */ 12588 const struct builtin_compatibility *d = bdesc_compat; 12589 unsigned i; 12590 for (i = 0; i < ARRAY_SIZE (bdesc_compat); i++, d++) 12591 { 12592 tree decl = rs6000_builtin_decls[(int)d->code]; 12593 if (decl != NULL) 12594 add_builtin_function (d->name, TREE_TYPE (decl), (int)d->code, 12595 BUILT_IN_MD, NULL, NULL_TREE); 12596 } 12597} 12598 12599/* Returns the rs6000 builtin decl for CODE. Note that we don't check 12600 the builtin mask here since there could be some #pragma/attribute 12601 target functions and the rs6000_builtin_mask could be wrong when 12602 this checking happens, though it will be updated properly later. */ 12603 12604tree 12605rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) 12606{ 12607 if (code >= RS6000_BUILTIN_COUNT) 12608 return error_mark_node; 12609 12610 return rs6000_builtin_decls[code]; 12611} 12612 12613static void 12614altivec_init_builtins (void) 12615{ 12616 const struct builtin_description *d; 12617 size_t i; 12618 tree ftype; 12619 tree decl; 12620 12621 tree pvoid_type_node = build_pointer_type (void_type_node); 12622 12623 tree pcvoid_type_node 12624 = build_pointer_type (build_qualified_type (void_type_node, 12625 TYPE_QUAL_CONST)); 12626 12627 tree int_ftype_opaque 12628 = build_function_type_list (integer_type_node, 12629 opaque_V4SI_type_node, NULL_TREE); 12630 tree opaque_ftype_opaque 12631 = build_function_type_list (integer_type_node, NULL_TREE); 12632 tree opaque_ftype_opaque_int 12633 = build_function_type_list (opaque_V4SI_type_node, 12634 opaque_V4SI_type_node, integer_type_node, NULL_TREE); 12635 tree opaque_ftype_opaque_opaque_int 12636 = build_function_type_list (opaque_V4SI_type_node, 12637 opaque_V4SI_type_node, opaque_V4SI_type_node, 12638 integer_type_node, NULL_TREE); 12639 tree opaque_ftype_opaque_opaque_opaque 12640 = build_function_type_list (opaque_V4SI_type_node, 12641 opaque_V4SI_type_node, opaque_V4SI_type_node, 12642 opaque_V4SI_type_node, NULL_TREE); 12643 tree opaque_ftype_opaque_opaque 12644 = build_function_type_list (opaque_V4SI_type_node, 12645 opaque_V4SI_type_node, opaque_V4SI_type_node, 12646 NULL_TREE); 12647 tree int_ftype_int_opaque_opaque 12648 = build_function_type_list (integer_type_node, 12649 integer_type_node, opaque_V4SI_type_node, 12650 opaque_V4SI_type_node, NULL_TREE); 12651 tree int_ftype_int_v4si_v4si 12652 = build_function_type_list (integer_type_node, 12653 integer_type_node, V4SI_type_node, 12654 V4SI_type_node, NULL_TREE); 12655 tree int_ftype_int_v2di_v2di 12656 = build_function_type_list (integer_type_node, 12657 integer_type_node, V2DI_type_node, 12658 V2DI_type_node, NULL_TREE); 12659 tree void_ftype_v4si 12660 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); 12661 tree v8hi_ftype_void 12662 = build_function_type_list (V8HI_type_node, NULL_TREE); 12663 tree void_ftype_void 12664 = build_function_type_list (void_type_node, NULL_TREE); 12665 tree void_ftype_int 12666 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); 12667 12668 tree opaque_ftype_long_pcvoid 12669 = build_function_type_list (opaque_V4SI_type_node, 12670 long_integer_type_node, pcvoid_type_node, 12671 NULL_TREE); 12672 tree v16qi_ftype_pcvoid 12673 = build_function_type_list (V16QI_type_node, 12674 pcvoid_type_node, 12675 NULL_TREE); 12676 tree v16qi_ftype_long_pcvoid 12677 = build_function_type_list (V16QI_type_node, 12678 long_integer_type_node, pcvoid_type_node, 12679 NULL_TREE); 12680 tree v8hi_ftype_long_pcvoid 12681 = build_function_type_list (V8HI_type_node, 12682 long_integer_type_node, pcvoid_type_node, 12683 NULL_TREE); 12684 tree v4si_ftype_long_pcvoid 12685 = build_function_type_list (V4SI_type_node, 12686 long_integer_type_node, pcvoid_type_node, 12687 NULL_TREE); 12688 tree v4sf_ftype_long_pcvoid 12689 = build_function_type_list (V4SF_type_node, 12690 long_integer_type_node, pcvoid_type_node, 12691 NULL_TREE); 12692 tree v2df_ftype_long_pcvoid 12693 = build_function_type_list (V2DF_type_node, 12694 long_integer_type_node, pcvoid_type_node, 12695 NULL_TREE); 12696 tree v2di_ftype_long_pcvoid 12697 = build_function_type_list (V2DI_type_node, 12698 long_integer_type_node, pcvoid_type_node, 12699 NULL_TREE); 12700 tree v1ti_ftype_long_pcvoid 12701 = build_function_type_list (V1TI_type_node, 12702 long_integer_type_node, pcvoid_type_node, 12703 NULL_TREE); 12704 12705 tree void_ftype_opaque_long_pvoid 12706 = build_function_type_list (void_type_node, 12707 opaque_V4SI_type_node, long_integer_type_node, 12708 pvoid_type_node, NULL_TREE); 12709 tree void_ftype_v4si_long_pvoid 12710 = build_function_type_list (void_type_node, 12711 V4SI_type_node, long_integer_type_node, 12712 pvoid_type_node, NULL_TREE); 12713 tree void_ftype_v16qi_long_pvoid 12714 = build_function_type_list (void_type_node, 12715 V16QI_type_node, long_integer_type_node, 12716 pvoid_type_node, NULL_TREE); 12717 12718 tree void_ftype_v16qi_pvoid_long 12719 = build_function_type_list (void_type_node, 12720 V16QI_type_node, pvoid_type_node, 12721 long_integer_type_node, NULL_TREE); 12722 12723 tree void_ftype_v8hi_long_pvoid 12724 = build_function_type_list (void_type_node, 12725 V8HI_type_node, long_integer_type_node, 12726 pvoid_type_node, NULL_TREE); 12727 tree void_ftype_v4sf_long_pvoid 12728 = build_function_type_list (void_type_node, 12729 V4SF_type_node, long_integer_type_node, 12730 pvoid_type_node, NULL_TREE); 12731 tree void_ftype_v2df_long_pvoid 12732 = build_function_type_list (void_type_node, 12733 V2DF_type_node, long_integer_type_node, 12734 pvoid_type_node, NULL_TREE); 12735 tree void_ftype_v1ti_long_pvoid 12736 = build_function_type_list (void_type_node, 12737 V1TI_type_node, long_integer_type_node, 12738 pvoid_type_node, NULL_TREE); 12739 tree void_ftype_v2di_long_pvoid 12740 = build_function_type_list (void_type_node, 12741 V2DI_type_node, long_integer_type_node, 12742 pvoid_type_node, NULL_TREE); 12743 tree int_ftype_int_v8hi_v8hi 12744 = build_function_type_list (integer_type_node, 12745 integer_type_node, V8HI_type_node, 12746 V8HI_type_node, NULL_TREE); 12747 tree int_ftype_int_v16qi_v16qi 12748 = build_function_type_list (integer_type_node, 12749 integer_type_node, V16QI_type_node, 12750 V16QI_type_node, NULL_TREE); 12751 tree int_ftype_int_v4sf_v4sf 12752 = build_function_type_list (integer_type_node, 12753 integer_type_node, V4SF_type_node, 12754 V4SF_type_node, NULL_TREE); 12755 tree int_ftype_int_v2df_v2df 12756 = build_function_type_list (integer_type_node, 12757 integer_type_node, V2DF_type_node, 12758 V2DF_type_node, NULL_TREE); 12759 tree v2di_ftype_v2di 12760 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE); 12761 tree v4si_ftype_v4si 12762 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); 12763 tree v8hi_ftype_v8hi 12764 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); 12765 tree v16qi_ftype_v16qi 12766 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); 12767 tree v4sf_ftype_v4sf 12768 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); 12769 tree v2df_ftype_v2df 12770 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE); 12771 tree void_ftype_pcvoid_int_int 12772 = build_function_type_list (void_type_node, 12773 pcvoid_type_node, integer_type_node, 12774 integer_type_node, NULL_TREE); 12775 12776 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); 12777 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); 12778 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); 12779 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); 12780 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); 12781 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); 12782 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); 12783 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); 12784 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); 12785 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); 12786 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid, 12787 ALTIVEC_BUILTIN_LVXL_V2DF); 12788 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid, 12789 ALTIVEC_BUILTIN_LVXL_V2DI); 12790 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid, 12791 ALTIVEC_BUILTIN_LVXL_V4SF); 12792 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid, 12793 ALTIVEC_BUILTIN_LVXL_V4SI); 12794 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid, 12795 ALTIVEC_BUILTIN_LVXL_V8HI); 12796 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid, 12797 ALTIVEC_BUILTIN_LVXL_V16QI); 12798 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); 12799 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid, 12800 ALTIVEC_BUILTIN_LVX_V1TI); 12801 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid, 12802 ALTIVEC_BUILTIN_LVX_V2DF); 12803 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid, 12804 ALTIVEC_BUILTIN_LVX_V2DI); 12805 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid, 12806 ALTIVEC_BUILTIN_LVX_V4SF); 12807 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid, 12808 ALTIVEC_BUILTIN_LVX_V4SI); 12809 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid, 12810 ALTIVEC_BUILTIN_LVX_V8HI); 12811 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid, 12812 ALTIVEC_BUILTIN_LVX_V16QI); 12813 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); 12814 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid, 12815 ALTIVEC_BUILTIN_STVX_V2DF); 12816 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid, 12817 ALTIVEC_BUILTIN_STVX_V2DI); 12818 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid, 12819 ALTIVEC_BUILTIN_STVX_V4SF); 12820 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid, 12821 ALTIVEC_BUILTIN_STVX_V4SI); 12822 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid, 12823 ALTIVEC_BUILTIN_STVX_V8HI); 12824 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid, 12825 ALTIVEC_BUILTIN_STVX_V16QI); 12826 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); 12827 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); 12828 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid, 12829 ALTIVEC_BUILTIN_STVXL_V2DF); 12830 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid, 12831 ALTIVEC_BUILTIN_STVXL_V2DI); 12832 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid, 12833 ALTIVEC_BUILTIN_STVXL_V4SF); 12834 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid, 12835 ALTIVEC_BUILTIN_STVXL_V4SI); 12836 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid, 12837 ALTIVEC_BUILTIN_STVXL_V8HI); 12838 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid, 12839 ALTIVEC_BUILTIN_STVXL_V16QI); 12840 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); 12841 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); 12842 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); 12843 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); 12844 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); 12845 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); 12846 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); 12847 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); 12848 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); 12849 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); 12850 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); 12851 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); 12852 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); 12853 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); 12854 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); 12855 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); 12856 12857 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid, 12858 VSX_BUILTIN_LXVD2X_V2DF); 12859 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid, 12860 VSX_BUILTIN_LXVD2X_V2DI); 12861 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid, 12862 VSX_BUILTIN_LXVW4X_V4SF); 12863 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid, 12864 VSX_BUILTIN_LXVW4X_V4SI); 12865 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid, 12866 VSX_BUILTIN_LXVW4X_V8HI); 12867 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid, 12868 VSX_BUILTIN_LXVW4X_V16QI); 12869 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid, 12870 VSX_BUILTIN_STXVD2X_V2DF); 12871 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid, 12872 VSX_BUILTIN_STXVD2X_V2DI); 12873 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid, 12874 VSX_BUILTIN_STXVW4X_V4SF); 12875 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid, 12876 VSX_BUILTIN_STXVW4X_V4SI); 12877 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid, 12878 VSX_BUILTIN_STXVW4X_V8HI); 12879 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid, 12880 VSX_BUILTIN_STXVW4X_V16QI); 12881 12882 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid, 12883 VSX_BUILTIN_LD_ELEMREV_V2DF); 12884 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid, 12885 VSX_BUILTIN_LD_ELEMREV_V2DI); 12886 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid, 12887 VSX_BUILTIN_LD_ELEMREV_V4SF); 12888 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid, 12889 VSX_BUILTIN_LD_ELEMREV_V4SI); 12890 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid, 12891 VSX_BUILTIN_LD_ELEMREV_V8HI); 12892 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid, 12893 VSX_BUILTIN_LD_ELEMREV_V16QI); 12894 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid, 12895 VSX_BUILTIN_ST_ELEMREV_V2DF); 12896 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid, 12897 VSX_BUILTIN_ST_ELEMREV_V1TI); 12898 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid, 12899 VSX_BUILTIN_ST_ELEMREV_V2DI); 12900 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid, 12901 VSX_BUILTIN_ST_ELEMREV_V4SF); 12902 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid, 12903 VSX_BUILTIN_ST_ELEMREV_V4SI); 12904 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid, 12905 VSX_BUILTIN_ST_ELEMREV_V8HI); 12906 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid, 12907 VSX_BUILTIN_ST_ELEMREV_V16QI); 12908 12909 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid, 12910 VSX_BUILTIN_VEC_LD); 12911 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid, 12912 VSX_BUILTIN_VEC_ST); 12913 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid, 12914 VSX_BUILTIN_VEC_XL); 12915 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid, 12916 VSX_BUILTIN_VEC_XL_BE); 12917 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid, 12918 VSX_BUILTIN_VEC_XST); 12919 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid, 12920 VSX_BUILTIN_VEC_XST_BE); 12921 12922 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); 12923 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS); 12924 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE); 12925 12926 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); 12927 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); 12928 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT); 12929 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT); 12930 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); 12931 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); 12932 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); 12933 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); 12934 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); 12935 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); 12936 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); 12937 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); 12938 12939 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque, 12940 ALTIVEC_BUILTIN_VEC_ADDE); 12941 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque, 12942 ALTIVEC_BUILTIN_VEC_ADDEC); 12943 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque, 12944 ALTIVEC_BUILTIN_VEC_CMPNE); 12945 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque, 12946 ALTIVEC_BUILTIN_VEC_MUL); 12947 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque, 12948 ALTIVEC_BUILTIN_VEC_SUBE); 12949 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque, 12950 ALTIVEC_BUILTIN_VEC_SUBEC); 12951 12952 /* Cell builtins. */ 12953 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX); 12954 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL); 12955 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX); 12956 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL); 12957 12958 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX); 12959 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL); 12960 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX); 12961 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL); 12962 12963 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX); 12964 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL); 12965 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX); 12966 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL); 12967 12968 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX); 12969 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL); 12970 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); 12971 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); 12972 12973 if (TARGET_P9_VECTOR) 12974 { 12975 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long, 12976 P9V_BUILTIN_STXVL); 12977 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long, 12978 P9V_BUILTIN_XST_LEN_R); 12979 } 12980 12981 /* Add the DST variants. */ 12982 d = bdesc_dst; 12983 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) 12984 { 12985 /* It is expected that these dst built-in functions may have 12986 d->icode equal to CODE_FOR_nothing. */ 12987 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code); 12988 } 12989 12990 /* Initialize the predicates. */ 12991 d = bdesc_altivec_preds; 12992 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++) 12993 { 12994 machine_mode mode1; 12995 tree type; 12996 12997 if (rs6000_overloaded_builtin_p (d->code)) 12998 mode1 = VOIDmode; 12999 else 13000 { 13001 /* Cannot define builtin if the instruction is disabled. */ 13002 gcc_assert (d->icode != CODE_FOR_nothing); 13003 mode1 = insn_data[d->icode].operand[1].mode; 13004 } 13005 13006 switch (mode1) 13007 { 13008 case E_VOIDmode: 13009 type = int_ftype_int_opaque_opaque; 13010 break; 13011 case E_V2DImode: 13012 type = int_ftype_int_v2di_v2di; 13013 break; 13014 case E_V4SImode: 13015 type = int_ftype_int_v4si_v4si; 13016 break; 13017 case E_V8HImode: 13018 type = int_ftype_int_v8hi_v8hi; 13019 break; 13020 case E_V16QImode: 13021 type = int_ftype_int_v16qi_v16qi; 13022 break; 13023 case E_V4SFmode: 13024 type = int_ftype_int_v4sf_v4sf; 13025 break; 13026 case E_V2DFmode: 13027 type = int_ftype_int_v2df_v2df; 13028 break; 13029 default: 13030 gcc_unreachable (); 13031 } 13032 13033 def_builtin (d->name, type, d->code); 13034 } 13035 13036 /* Initialize the abs* operators. */ 13037 d = bdesc_abs; 13038 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) 13039 { 13040 machine_mode mode0; 13041 tree type; 13042 13043 /* Cannot define builtin if the instruction is disabled. */ 13044 gcc_assert (d->icode != CODE_FOR_nothing); 13045 mode0 = insn_data[d->icode].operand[0].mode; 13046 13047 switch (mode0) 13048 { 13049 case E_V2DImode: 13050 type = v2di_ftype_v2di; 13051 break; 13052 case E_V4SImode: 13053 type = v4si_ftype_v4si; 13054 break; 13055 case E_V8HImode: 13056 type = v8hi_ftype_v8hi; 13057 break; 13058 case E_V16QImode: 13059 type = v16qi_ftype_v16qi; 13060 break; 13061 case E_V4SFmode: 13062 type = v4sf_ftype_v4sf; 13063 break; 13064 case E_V2DFmode: 13065 type = v2df_ftype_v2df; 13066 break; 13067 default: 13068 gcc_unreachable (); 13069 } 13070 13071 def_builtin (d->name, type, d->code); 13072 } 13073 13074 /* Initialize target builtin that implements 13075 targetm.vectorize.builtin_mask_for_load. */ 13076 13077 decl = add_builtin_function ("__builtin_altivec_mask_for_load", 13078 v16qi_ftype_pcvoid, 13079 ALTIVEC_BUILTIN_MASK_FOR_LOAD, 13080 BUILT_IN_MD, NULL, NULL_TREE); 13081 TREE_READONLY (decl) = 1; 13082 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ 13083 altivec_builtin_mask_for_load = decl; 13084 13085 /* Access to the vec_init patterns. */ 13086 ftype = build_function_type_list (V4SI_type_node, integer_type_node, 13087 integer_type_node, integer_type_node, 13088 integer_type_node, NULL_TREE); 13089 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI); 13090 13091 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node, 13092 short_integer_type_node, 13093 short_integer_type_node, 13094 short_integer_type_node, 13095 short_integer_type_node, 13096 short_integer_type_node, 13097 short_integer_type_node, 13098 short_integer_type_node, NULL_TREE); 13099 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI); 13100 13101 ftype = build_function_type_list (V16QI_type_node, char_type_node, 13102 char_type_node, char_type_node, 13103 char_type_node, char_type_node, 13104 char_type_node, char_type_node, 13105 char_type_node, char_type_node, 13106 char_type_node, char_type_node, 13107 char_type_node, char_type_node, 13108 char_type_node, char_type_node, 13109 char_type_node, NULL_TREE); 13110 def_builtin ("__builtin_vec_init_v16qi", ftype, 13111 ALTIVEC_BUILTIN_VEC_INIT_V16QI); 13112 13113 ftype = build_function_type_list (V4SF_type_node, float_type_node, 13114 float_type_node, float_type_node, 13115 float_type_node, NULL_TREE); 13116 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF); 13117 13118 /* VSX builtins. */ 13119 ftype = build_function_type_list (V2DF_type_node, double_type_node, 13120 double_type_node, NULL_TREE); 13121 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF); 13122 13123 ftype = build_function_type_list (V2DI_type_node, intDI_type_node, 13124 intDI_type_node, NULL_TREE); 13125 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI); 13126 13127 /* Access to the vec_set patterns. */ 13128 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node, 13129 intSI_type_node, 13130 integer_type_node, NULL_TREE); 13131 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI); 13132 13133 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, 13134 intHI_type_node, 13135 integer_type_node, NULL_TREE); 13136 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI); 13137 13138 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node, 13139 intQI_type_node, 13140 integer_type_node, NULL_TREE); 13141 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI); 13142 13143 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node, 13144 float_type_node, 13145 integer_type_node, NULL_TREE); 13146 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF); 13147 13148 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node, 13149 double_type_node, 13150 integer_type_node, NULL_TREE); 13151 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF); 13152 13153 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node, 13154 intDI_type_node, 13155 integer_type_node, NULL_TREE); 13156 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI); 13157 13158 /* Access to the vec_extract patterns. */ 13159 ftype = build_function_type_list (intSI_type_node, V4SI_type_node, 13160 integer_type_node, NULL_TREE); 13161 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI); 13162 13163 ftype = build_function_type_list (intHI_type_node, V8HI_type_node, 13164 integer_type_node, NULL_TREE); 13165 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI); 13166 13167 ftype = build_function_type_list (intQI_type_node, V16QI_type_node, 13168 integer_type_node, NULL_TREE); 13169 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI); 13170 13171 ftype = build_function_type_list (float_type_node, V4SF_type_node, 13172 integer_type_node, NULL_TREE); 13173 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF); 13174 13175 ftype = build_function_type_list (double_type_node, V2DF_type_node, 13176 integer_type_node, NULL_TREE); 13177 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF); 13178 13179 ftype = build_function_type_list (intDI_type_node, V2DI_type_node, 13180 integer_type_node, NULL_TREE); 13181 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI); 13182 13183 13184 if (V1TI_type_node) 13185 { 13186 tree v1ti_ftype_long_pcvoid 13187 = build_function_type_list (V1TI_type_node, 13188 long_integer_type_node, pcvoid_type_node, 13189 NULL_TREE); 13190 tree void_ftype_v1ti_long_pvoid 13191 = build_function_type_list (void_type_node, 13192 V1TI_type_node, long_integer_type_node, 13193 pvoid_type_node, NULL_TREE); 13194 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid, 13195 VSX_BUILTIN_LD_ELEMREV_V1TI); 13196 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid, 13197 VSX_BUILTIN_LXVD2X_V1TI); 13198 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid, 13199 VSX_BUILTIN_STXVD2X_V1TI); 13200 ftype = build_function_type_list (V1TI_type_node, intTI_type_node, 13201 NULL_TREE, NULL_TREE); 13202 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI); 13203 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node, 13204 intTI_type_node, 13205 integer_type_node, NULL_TREE); 13206 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI); 13207 ftype = build_function_type_list (intTI_type_node, V1TI_type_node, 13208 integer_type_node, NULL_TREE); 13209 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI); 13210 } 13211 13212} 13213 13214static void 13215mma_init_builtins (void) 13216{ 13217 const struct builtin_description *d = bdesc_mma; 13218 13219 for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++) 13220 { 13221 tree op[MAX_MMA_OPERANDS], type; 13222 unsigned icode = (unsigned) d->icode; 13223 unsigned attr = rs6000_builtin_info[d->code].attr; 13224 int attr_args = (attr & RS6000_BTC_OPND_MASK); 13225 bool gimple_func = (attr & RS6000_BTC_GIMPLE); 13226 unsigned nopnds = 0; 13227 13228 if (d->name == 0) 13229 { 13230 if (TARGET_DEBUG_BUILTIN) 13231 fprintf (stderr, "mma_builtin, bdesc_mma[%ld] no name\n", 13232 (long unsigned) i); 13233 continue; 13234 } 13235 13236 if (gimple_func) 13237 { 13238 gcc_assert (icode == CODE_FOR_nothing); 13239 /* Some MMA built-ins that are expanded into gimple are converted 13240 into internal MMA built-ins that are expanded into rtl. 13241 The internal built-in follows immediately after this built-in. */ 13242 if (d->code != VSX_BUILTIN_LXVP 13243 && d->code != VSX_BUILTIN_STXVP) 13244 { 13245 op[nopnds++] = void_type_node; 13246 icode = d[1].icode; 13247 } 13248 } 13249 else 13250 { 13251 if ((attr & RS6000_BTC_QUAD) == 0) 13252 attr_args--; 13253 13254 /* Ensure we have the correct number and type of operands. */ 13255 gcc_assert (attr_args == insn_data[icode].n_operands - 1); 13256 } 13257 13258 if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC 13259 || d->code == VSX_BUILTIN_DISASSEMBLE_PAIR) 13260 { 13261 /* This is a disassemble MMA built-in function. */ 13262 gcc_assert (attr_args == RS6000_BTC_BINARY); 13263 op[nopnds++] = build_pointer_type (void_type_node); 13264 if (attr & RS6000_BTC_QUAD) 13265 op[nopnds++] = build_pointer_type (vector_quad_type_node); 13266 else 13267 op[nopnds++] = build_pointer_type (vector_pair_type_node); 13268 } 13269 else if (d->code == VSX_BUILTIN_LXVP) 13270 { 13271 op[nopnds++] = vector_pair_type_node; 13272 op[nopnds++] = sizetype; 13273 op[nopnds++] = build_pointer_type (vector_pair_type_node); 13274 } 13275 else if (d->code == VSX_BUILTIN_STXVP) 13276 { 13277 op[nopnds++] = void_type_node; 13278 op[nopnds++] = vector_pair_type_node; 13279 op[nopnds++] = sizetype; 13280 op[nopnds++] = build_pointer_type (vector_pair_type_node); 13281 } 13282 else 13283 { 13284 /* This is a normal MMA built-in function. */ 13285 unsigned j = (attr & RS6000_BTC_QUAD) ? 1 : 0; 13286 for (; j < insn_data[icode].n_operands; j++) 13287 { 13288 machine_mode mode = insn_data[icode].operand[j].mode; 13289 if (gimple_func && mode == PXImode) 13290 op[nopnds++] = build_pointer_type (vector_quad_type_node); 13291 else if (gimple_func 13292 && mode == POImode 13293 && (d->code == VSX_BUILTIN_BUILD_PAIR 13294 || d->code == VSX_BUILTIN_ASSEMBLE_PAIR)) 13295 op[nopnds++] = build_pointer_type (vector_pair_type_node); 13296 else 13297 /* MMA uses unsigned types. */ 13298 op[nopnds++] = builtin_mode_to_type[mode][1]; 13299 } 13300 } 13301 13302 switch (nopnds) 13303 { 13304 case 1: 13305 type = build_function_type_list (op[0], NULL_TREE); 13306 break; 13307 case 2: 13308 type = build_function_type_list (op[0], op[1], NULL_TREE); 13309 break; 13310 case 3: 13311 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE); 13312 break; 13313 case 4: 13314 type = build_function_type_list (op[0], op[1], op[2], op[3], 13315 NULL_TREE); 13316 break; 13317 case 5: 13318 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], 13319 NULL_TREE); 13320 break; 13321 case 6: 13322 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], 13323 op[5], NULL_TREE); 13324 break; 13325 case 7: 13326 type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], 13327 op[5], op[6], NULL_TREE); 13328 break; 13329 default: 13330 gcc_unreachable (); 13331 } 13332 13333 def_builtin (d->name, type, d->code); 13334 } 13335} 13336 13337static void 13338htm_init_builtins (void) 13339{ 13340 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; 13341 const struct builtin_description *d; 13342 size_t i; 13343 13344 d = bdesc_htm; 13345 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++) 13346 { 13347 tree op[MAX_HTM_OPERANDS], type; 13348 HOST_WIDE_INT mask = d->mask; 13349 unsigned attr = rs6000_builtin_info[d->code].attr; 13350 bool void_func = (attr & RS6000_BTC_VOID); 13351 int attr_args = (attr & RS6000_BTC_OPND_MASK); 13352 int nopnds = 0; 13353 tree gpr_type_node; 13354 tree rettype; 13355 tree argtype; 13356 13357 /* It is expected that these htm built-in functions may have 13358 d->icode equal to CODE_FOR_nothing. */ 13359 13360 if (TARGET_32BIT && TARGET_POWERPC64) 13361 gpr_type_node = long_long_unsigned_type_node; 13362 else 13363 gpr_type_node = long_unsigned_type_node; 13364 13365 if (attr & RS6000_BTC_SPR) 13366 { 13367 rettype = gpr_type_node; 13368 argtype = gpr_type_node; 13369 } 13370 else if (d->code == HTM_BUILTIN_TABORTDC 13371 || d->code == HTM_BUILTIN_TABORTDCI) 13372 { 13373 rettype = unsigned_type_node; 13374 argtype = gpr_type_node; 13375 } 13376 else 13377 { 13378 rettype = unsigned_type_node; 13379 argtype = unsigned_type_node; 13380 } 13381 13382 if ((mask & builtin_mask) != mask) 13383 { 13384 if (TARGET_DEBUG_BUILTIN) 13385 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name); 13386 continue; 13387 } 13388 13389 if (d->name == 0) 13390 { 13391 if (TARGET_DEBUG_BUILTIN) 13392 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n", 13393 (long unsigned) i); 13394 continue; 13395 } 13396 13397 op[nopnds++] = (void_func) ? void_type_node : rettype; 13398 13399 if (attr_args == RS6000_BTC_UNARY) 13400 op[nopnds++] = argtype; 13401 else if (attr_args == RS6000_BTC_BINARY) 13402 { 13403 op[nopnds++] = argtype; 13404 op[nopnds++] = argtype; 13405 } 13406 else if (attr_args == RS6000_BTC_TERNARY) 13407 { 13408 op[nopnds++] = argtype; 13409 op[nopnds++] = argtype; 13410 op[nopnds++] = argtype; 13411 } 13412 13413 switch (nopnds) 13414 { 13415 case 1: 13416 type = build_function_type_list (op[0], NULL_TREE); 13417 break; 13418 case 2: 13419 type = build_function_type_list (op[0], op[1], NULL_TREE); 13420 break; 13421 case 3: 13422 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE); 13423 break; 13424 case 4: 13425 type = build_function_type_list (op[0], op[1], op[2], op[3], 13426 NULL_TREE); 13427 break; 13428 default: 13429 gcc_unreachable (); 13430 } 13431 13432 def_builtin (d->name, type, d->code); 13433 } 13434} 13435 13436/* Map types for builtin functions with an explicit return type and up to 3 13437 arguments. Functions with fewer than 3 arguments use VOIDmode as the type 13438 of the argument. */ 13439static tree 13440builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, 13441 machine_mode mode_arg1, machine_mode mode_arg2, 13442 enum rs6000_builtins builtin, const char *name) 13443{ 13444 struct builtin_hash_struct h; 13445 struct builtin_hash_struct *h2; 13446 int num_args = 3; 13447 int i; 13448 tree ret_type = NULL_TREE; 13449 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE }; 13450 13451 /* Create builtin_hash_table. */ 13452 if (builtin_hash_table == NULL) 13453 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500); 13454 13455 h.type = NULL_TREE; 13456 h.mode[0] = mode_ret; 13457 h.mode[1] = mode_arg0; 13458 h.mode[2] = mode_arg1; 13459 h.mode[3] = mode_arg2; 13460 h.uns_p[0] = 0; 13461 h.uns_p[1] = 0; 13462 h.uns_p[2] = 0; 13463 h.uns_p[3] = 0; 13464 13465 /* If the builtin is a type that produces unsigned results or takes unsigned 13466 arguments, and it is returned as a decl for the vectorizer (such as 13467 widening multiplies, permute), make sure the arguments and return value 13468 are type correct. */ 13469 switch (builtin) 13470 { 13471 /* unsigned 1 argument functions. */ 13472 case CRYPTO_BUILTIN_VSBOX: 13473 case CRYPTO_BUILTIN_VSBOX_BE: 13474 case P8V_BUILTIN_VGBBD: 13475 case MISC_BUILTIN_CDTBCD: 13476 case MISC_BUILTIN_CBCDTD: 13477 case P10V_BUILTIN_XVCVSPBF16: 13478 case P10V_BUILTIN_XVCVBF16SPN: 13479 h.uns_p[0] = 1; 13480 h.uns_p[1] = 1; 13481 break; 13482 13483 /* unsigned 2 argument functions. */ 13484 case ALTIVEC_BUILTIN_VMULEUB: 13485 case ALTIVEC_BUILTIN_VMULEUH: 13486 case P8V_BUILTIN_VMULEUW: 13487 case ALTIVEC_BUILTIN_VMULOUB: 13488 case ALTIVEC_BUILTIN_VMULOUH: 13489 case P8V_BUILTIN_VMULOUW: 13490 case CRYPTO_BUILTIN_VCIPHER: 13491 case CRYPTO_BUILTIN_VCIPHER_BE: 13492 case CRYPTO_BUILTIN_VCIPHERLAST: 13493 case CRYPTO_BUILTIN_VCIPHERLAST_BE: 13494 case CRYPTO_BUILTIN_VNCIPHER: 13495 case CRYPTO_BUILTIN_VNCIPHER_BE: 13496 case CRYPTO_BUILTIN_VNCIPHERLAST: 13497 case CRYPTO_BUILTIN_VNCIPHERLAST_BE: 13498 case CRYPTO_BUILTIN_VPMSUMB: 13499 case CRYPTO_BUILTIN_VPMSUMH: 13500 case CRYPTO_BUILTIN_VPMSUMW: 13501 case CRYPTO_BUILTIN_VPMSUMD: 13502 case CRYPTO_BUILTIN_VPMSUM: 13503 case MISC_BUILTIN_ADDG6S: 13504 case MISC_BUILTIN_DIVWEU: 13505 case MISC_BUILTIN_DIVDEU: 13506 case VSX_BUILTIN_UDIV_V2DI: 13507 case ALTIVEC_BUILTIN_VMAXUB: 13508 case ALTIVEC_BUILTIN_VMINUB: 13509 case ALTIVEC_BUILTIN_VMAXUH: 13510 case ALTIVEC_BUILTIN_VMINUH: 13511 case ALTIVEC_BUILTIN_VMAXUW: 13512 case ALTIVEC_BUILTIN_VMINUW: 13513 case P8V_BUILTIN_VMAXUD: 13514 case P8V_BUILTIN_VMINUD: 13515 case ALTIVEC_BUILTIN_VAND_V16QI_UNS: 13516 case ALTIVEC_BUILTIN_VAND_V8HI_UNS: 13517 case ALTIVEC_BUILTIN_VAND_V4SI_UNS: 13518 case ALTIVEC_BUILTIN_VAND_V2DI_UNS: 13519 case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: 13520 case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: 13521 case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: 13522 case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: 13523 case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: 13524 case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: 13525 case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: 13526 case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: 13527 case ALTIVEC_BUILTIN_VOR_V16QI_UNS: 13528 case ALTIVEC_BUILTIN_VOR_V8HI_UNS: 13529 case ALTIVEC_BUILTIN_VOR_V4SI_UNS: 13530 case ALTIVEC_BUILTIN_VOR_V2DI_UNS: 13531 case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: 13532 case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: 13533 case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: 13534 case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: 13535 case P8V_BUILTIN_EQV_V16QI_UNS: 13536 case P8V_BUILTIN_EQV_V8HI_UNS: 13537 case P8V_BUILTIN_EQV_V4SI_UNS: 13538 case P8V_BUILTIN_EQV_V2DI_UNS: 13539 case P8V_BUILTIN_EQV_V1TI_UNS: 13540 case P8V_BUILTIN_NAND_V16QI_UNS: 13541 case P8V_BUILTIN_NAND_V8HI_UNS: 13542 case P8V_BUILTIN_NAND_V4SI_UNS: 13543 case P8V_BUILTIN_NAND_V2DI_UNS: 13544 case P8V_BUILTIN_NAND_V1TI_UNS: 13545 case P8V_BUILTIN_ORC_V16QI_UNS: 13546 case P8V_BUILTIN_ORC_V8HI_UNS: 13547 case P8V_BUILTIN_ORC_V4SI_UNS: 13548 case P8V_BUILTIN_ORC_V2DI_UNS: 13549 case P8V_BUILTIN_ORC_V1TI_UNS: 13550 h.uns_p[0] = 1; 13551 h.uns_p[1] = 1; 13552 h.uns_p[2] = 1; 13553 break; 13554 13555 /* unsigned 3 argument functions. */ 13556 case ALTIVEC_BUILTIN_VPERM_16QI_UNS: 13557 case ALTIVEC_BUILTIN_VPERM_8HI_UNS: 13558 case ALTIVEC_BUILTIN_VPERM_4SI_UNS: 13559 case ALTIVEC_BUILTIN_VPERM_2DI_UNS: 13560 case ALTIVEC_BUILTIN_VSEL_16QI_UNS: 13561 case ALTIVEC_BUILTIN_VSEL_8HI_UNS: 13562 case ALTIVEC_BUILTIN_VSEL_4SI_UNS: 13563 case ALTIVEC_BUILTIN_VSEL_2DI_UNS: 13564 case VSX_BUILTIN_VPERM_16QI_UNS: 13565 case VSX_BUILTIN_VPERM_8HI_UNS: 13566 case VSX_BUILTIN_VPERM_4SI_UNS: 13567 case VSX_BUILTIN_VPERM_2DI_UNS: 13568 case VSX_BUILTIN_XXSEL_16QI_UNS: 13569 case VSX_BUILTIN_XXSEL_8HI_UNS: 13570 case VSX_BUILTIN_XXSEL_4SI_UNS: 13571 case VSX_BUILTIN_XXSEL_2DI_UNS: 13572 case CRYPTO_BUILTIN_VPERMXOR: 13573 case CRYPTO_BUILTIN_VPERMXOR_V2DI: 13574 case CRYPTO_BUILTIN_VPERMXOR_V4SI: 13575 case CRYPTO_BUILTIN_VPERMXOR_V8HI: 13576 case CRYPTO_BUILTIN_VPERMXOR_V16QI: 13577 case CRYPTO_BUILTIN_VSHASIGMAW: 13578 case CRYPTO_BUILTIN_VSHASIGMAD: 13579 case CRYPTO_BUILTIN_VSHASIGMA: 13580 h.uns_p[0] = 1; 13581 h.uns_p[1] = 1; 13582 h.uns_p[2] = 1; 13583 h.uns_p[3] = 1; 13584 break; 13585 13586 /* signed permute functions with unsigned char mask. */ 13587 case ALTIVEC_BUILTIN_VPERM_16QI: 13588 case ALTIVEC_BUILTIN_VPERM_8HI: 13589 case ALTIVEC_BUILTIN_VPERM_4SI: 13590 case ALTIVEC_BUILTIN_VPERM_4SF: 13591 case ALTIVEC_BUILTIN_VPERM_2DI: 13592 case ALTIVEC_BUILTIN_VPERM_2DF: 13593 case VSX_BUILTIN_VPERM_16QI: 13594 case VSX_BUILTIN_VPERM_8HI: 13595 case VSX_BUILTIN_VPERM_4SI: 13596 case VSX_BUILTIN_VPERM_4SF: 13597 case VSX_BUILTIN_VPERM_2DI: 13598 case VSX_BUILTIN_VPERM_2DF: 13599 h.uns_p[3] = 1; 13600 break; 13601 13602 /* unsigned args, signed return. */ 13603 case VSX_BUILTIN_XVCVUXDSP: 13604 case VSX_BUILTIN_XVCVUXDDP_UNS: 13605 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF: 13606 h.uns_p[1] = 1; 13607 break; 13608 13609 /* signed args, unsigned return. */ 13610 case VSX_BUILTIN_XVCVDPUXDS_UNS: 13611 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI: 13612 case MISC_BUILTIN_UNPACK_TD: 13613 case MISC_BUILTIN_UNPACK_V1TI: 13614 h.uns_p[0] = 1; 13615 break; 13616 13617 /* unsigned arguments, bool return (compares). */ 13618 case ALTIVEC_BUILTIN_VCMPEQUB: 13619 case ALTIVEC_BUILTIN_VCMPEQUH: 13620 case ALTIVEC_BUILTIN_VCMPEQUW: 13621 case P8V_BUILTIN_VCMPEQUD: 13622 case VSX_BUILTIN_CMPGE_U16QI: 13623 case VSX_BUILTIN_CMPGE_U8HI: 13624 case VSX_BUILTIN_CMPGE_U4SI: 13625 case VSX_BUILTIN_CMPGE_U2DI: 13626 case ALTIVEC_BUILTIN_VCMPGTUB: 13627 case ALTIVEC_BUILTIN_VCMPGTUH: 13628 case ALTIVEC_BUILTIN_VCMPGTUW: 13629 case P8V_BUILTIN_VCMPGTUD: 13630 h.uns_p[1] = 1; 13631 h.uns_p[2] = 1; 13632 break; 13633 13634 /* unsigned arguments for 128-bit pack instructions. */ 13635 case MISC_BUILTIN_PACK_TD: 13636 case MISC_BUILTIN_PACK_V1TI: 13637 h.uns_p[1] = 1; 13638 h.uns_p[2] = 1; 13639 break; 13640 13641 /* unsigned second arguments (vector shift right). */ 13642 case ALTIVEC_BUILTIN_VSRB: 13643 case ALTIVEC_BUILTIN_VSRH: 13644 case ALTIVEC_BUILTIN_VSRW: 13645 case P8V_BUILTIN_VSRD: 13646 h.uns_p[2] = 1; 13647 break; 13648 13649 case VSX_BUILTIN_LXVP: 13650 h.uns_p[0] = 1; 13651 h.uns_p[2] = 1; 13652 break; 13653 13654 case VSX_BUILTIN_STXVP: 13655 h.uns_p[1] = 1; 13656 h.uns_p[3] = 1; 13657 break; 13658 13659 default: 13660 break; 13661 } 13662 13663 /* Figure out how many args are present. */ 13664 while (num_args > 0 && h.mode[num_args] == VOIDmode) 13665 num_args--; 13666 13667 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]]; 13668 if (!ret_type && h.uns_p[0]) 13669 ret_type = builtin_mode_to_type[h.mode[0]][0]; 13670 13671 /* If the required decimal float type has been disabled, 13672 then return NULL_TREE. */ 13673 if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0])) 13674 return NULL_TREE; 13675 13676 if (!ret_type) 13677 fatal_error (input_location, 13678 "internal error: builtin function %qs had an unexpected " 13679 "return type %qs", name, GET_MODE_NAME (h.mode[0])); 13680 13681 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++) 13682 arg_type[i] = NULL_TREE; 13683 13684 for (i = 0; i < num_args; i++) 13685 { 13686 int m = (int) h.mode[i+1]; 13687 int uns_p = h.uns_p[i+1]; 13688 13689 arg_type[i] = builtin_mode_to_type[m][uns_p]; 13690 if (!arg_type[i] && uns_p) 13691 arg_type[i] = builtin_mode_to_type[m][0]; 13692 13693 /* If the required decimal float type has been disabled, 13694 then return NULL_TREE. */ 13695 if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m)) 13696 return NULL_TREE; 13697 13698 if (!arg_type[i]) 13699 fatal_error (input_location, 13700 "internal error: builtin function %qs, argument %d " 13701 "had unexpected argument type %qs", name, i, 13702 GET_MODE_NAME (m)); 13703 } 13704 13705 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT); 13706 if (*found == NULL) 13707 { 13708 h2 = ggc_alloc<builtin_hash_struct> (); 13709 *h2 = h; 13710 *found = h2; 13711 13712 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1], 13713 arg_type[2], NULL_TREE); 13714 } 13715 13716 return (*found)->type; 13717} 13718 13719static void 13720rs6000_common_init_builtins (void) 13721{ 13722 const struct builtin_description *d; 13723 size_t i; 13724 13725 tree opaque_ftype_opaque = NULL_TREE; 13726 tree opaque_ftype_opaque_opaque = NULL_TREE; 13727 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE; 13728 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; 13729 13730 /* Create Altivec and VSX builtins on machines with at least the 13731 general purpose extensions (970 and newer) to allow the use of 13732 the target attribute. */ 13733 13734 if (TARGET_EXTRA_BUILTINS) 13735 builtin_mask |= RS6000_BTM_COMMON; 13736 13737 /* Add the ternary operators. */ 13738 d = bdesc_3arg; 13739 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) 13740 { 13741 tree type; 13742 HOST_WIDE_INT mask = d->mask; 13743 13744 if ((mask & builtin_mask) != mask) 13745 { 13746 if (TARGET_DEBUG_BUILTIN) 13747 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name); 13748 continue; 13749 } 13750 13751 if (rs6000_overloaded_builtin_p (d->code)) 13752 { 13753 if (! (type = opaque_ftype_opaque_opaque_opaque)) 13754 type = opaque_ftype_opaque_opaque_opaque 13755 = build_function_type_list (opaque_V4SI_type_node, 13756 opaque_V4SI_type_node, 13757 opaque_V4SI_type_node, 13758 opaque_V4SI_type_node, 13759 NULL_TREE); 13760 } 13761 else 13762 { 13763 enum insn_code icode = d->icode; 13764 if (d->name == 0) 13765 { 13766 if (TARGET_DEBUG_BUILTIN) 13767 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n", 13768 (long unsigned)i); 13769 13770 continue; 13771 } 13772 13773 if (icode == CODE_FOR_nothing) 13774 { 13775 if (TARGET_DEBUG_BUILTIN) 13776 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n", 13777 d->name); 13778 13779 continue; 13780 } 13781 13782 type = builtin_function_type (insn_data[icode].operand[0].mode, 13783 insn_data[icode].operand[1].mode, 13784 insn_data[icode].operand[2].mode, 13785 insn_data[icode].operand[3].mode, 13786 d->code, d->name); 13787 } 13788 13789 def_builtin (d->name, type, d->code); 13790 } 13791 13792 /* Add the binary operators. */ 13793 d = bdesc_2arg; 13794 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 13795 { 13796 machine_mode mode0, mode1, mode2; 13797 tree type; 13798 HOST_WIDE_INT mask = d->mask; 13799 13800 if ((mask & builtin_mask) != mask) 13801 { 13802 if (TARGET_DEBUG_BUILTIN) 13803 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name); 13804 continue; 13805 } 13806 13807 if (rs6000_overloaded_builtin_p (d->code)) 13808 { 13809 const struct altivec_builtin_types *desc; 13810 13811 /* Verify the builtin we are overloading has already been defined. */ 13812 type = NULL_TREE; 13813 for (desc = altivec_overloaded_builtins; 13814 desc->code != RS6000_BUILTIN_NONE; desc++) 13815 if (desc->code == d->code 13816 && rs6000_builtin_decls[(int)desc->overloaded_code]) 13817 { 13818 if (! (type = opaque_ftype_opaque_opaque)) 13819 type = opaque_ftype_opaque_opaque 13820 = build_function_type_list (opaque_V4SI_type_node, 13821 opaque_V4SI_type_node, 13822 opaque_V4SI_type_node, 13823 NULL_TREE); 13824 break; 13825 } 13826 } 13827 else 13828 { 13829 enum insn_code icode = d->icode; 13830 if (d->name == 0) 13831 { 13832 if (TARGET_DEBUG_BUILTIN) 13833 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n", 13834 (long unsigned)i); 13835 13836 continue; 13837 } 13838 13839 if (icode == CODE_FOR_nothing) 13840 { 13841 if (TARGET_DEBUG_BUILTIN) 13842 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n", 13843 d->name); 13844 13845 continue; 13846 } 13847 13848 mode0 = insn_data[icode].operand[0].mode; 13849 mode1 = insn_data[icode].operand[1].mode; 13850 mode2 = insn_data[icode].operand[2].mode; 13851 13852 type = builtin_function_type (mode0, mode1, mode2, VOIDmode, 13853 d->code, d->name); 13854 } 13855 13856 def_builtin (d->name, type, d->code); 13857 } 13858 13859 /* Add the simple unary operators. */ 13860 d = bdesc_1arg; 13861 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 13862 { 13863 machine_mode mode0, mode1; 13864 tree type; 13865 HOST_WIDE_INT mask = d->mask; 13866 13867 if ((mask & builtin_mask) != mask) 13868 { 13869 if (TARGET_DEBUG_BUILTIN) 13870 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name); 13871 continue; 13872 } 13873 13874 if (rs6000_overloaded_builtin_p (d->code)) 13875 { 13876 if (! (type = opaque_ftype_opaque)) 13877 type = opaque_ftype_opaque 13878 = build_function_type_list (opaque_V4SI_type_node, 13879 opaque_V4SI_type_node, 13880 NULL_TREE); 13881 } 13882 else 13883 { 13884 enum insn_code icode = d->icode; 13885 if (d->name == 0) 13886 { 13887 if (TARGET_DEBUG_BUILTIN) 13888 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n", 13889 (long unsigned)i); 13890 13891 continue; 13892 } 13893 13894 if (icode == CODE_FOR_nothing) 13895 { 13896 if (TARGET_DEBUG_BUILTIN) 13897 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n", 13898 d->name); 13899 13900 continue; 13901 } 13902 13903 mode0 = insn_data[icode].operand[0].mode; 13904 mode1 = insn_data[icode].operand[1].mode; 13905 13906 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode, 13907 d->code, d->name); 13908 } 13909 13910 def_builtin (d->name, type, d->code); 13911 } 13912 13913 /* Add the simple no-argument operators. */ 13914 d = bdesc_0arg; 13915 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) 13916 { 13917 machine_mode mode0; 13918 tree type; 13919 HOST_WIDE_INT mask = d->mask; 13920 13921 if ((mask & builtin_mask) != mask) 13922 { 13923 if (TARGET_DEBUG_BUILTIN) 13924 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name); 13925 continue; 13926 } 13927 if (rs6000_overloaded_builtin_p (d->code)) 13928 { 13929 if (!opaque_ftype_opaque) 13930 opaque_ftype_opaque 13931 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE); 13932 type = opaque_ftype_opaque; 13933 } 13934 else 13935 { 13936 enum insn_code icode = d->icode; 13937 if (d->name == 0) 13938 { 13939 if (TARGET_DEBUG_BUILTIN) 13940 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n", 13941 (long unsigned) i); 13942 continue; 13943 } 13944 if (icode == CODE_FOR_nothing) 13945 { 13946 if (TARGET_DEBUG_BUILTIN) 13947 fprintf (stderr, 13948 "rs6000_builtin, skip no-argument %s (no code)\n", 13949 d->name); 13950 continue; 13951 } 13952 mode0 = insn_data[icode].operand[0].mode; 13953 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode, 13954 d->code, d->name); 13955 } 13956 def_builtin (d->name, type, d->code); 13957 } 13958} 13959 13960/* Return the internal arg pointer used for function incoming 13961 arguments. When -fsplit-stack, the arg pointer is r12 so we need 13962 to copy it to a pseudo in order for it to be preserved over calls 13963 and suchlike. We'd really like to use a pseudo here for the 13964 internal arg pointer but data-flow analysis is not prepared to 13965 accept pseudos as live at the beginning of a function. */ 13966 13967rtx 13968rs6000_internal_arg_pointer (void) 13969{ 13970 if (flag_split_stack 13971 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl)) 13972 == NULL)) 13973 13974 { 13975 if (cfun->machine->split_stack_arg_pointer == NULL_RTX) 13976 { 13977 rtx pat; 13978 13979 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode); 13980 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1; 13981 13982 /* Put the pseudo initialization right after the note at the 13983 beginning of the function. */ 13984 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer, 13985 gen_rtx_REG (Pmode, 12)); 13986 push_topmost_sequence (); 13987 emit_insn_after (pat, get_insns ()); 13988 pop_topmost_sequence (); 13989 } 13990 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer, 13991 FIRST_PARM_OFFSET (current_function_decl)); 13992 return copy_to_reg (ret); 13993 } 13994 return virtual_incoming_args_rtx; 13995} 13996 13997 13998/* A C compound statement that outputs the assembler code for a thunk 13999 function, used to implement C++ virtual function calls with 14000 multiple inheritance. The thunk acts as a wrapper around a virtual 14001 function, adjusting the implicit object parameter before handing 14002 control off to the real function. 14003 14004 First, emit code to add the integer DELTA to the location that 14005 contains the incoming first argument. Assume that this argument 14006 contains a pointer, and is the one used to pass the `this' pointer 14007 in C++. This is the incoming argument *before* the function 14008 prologue, e.g. `%o0' on a sparc. The addition must preserve the 14009 values of all other incoming arguments. 14010 14011 After the addition, emit code to jump to FUNCTION, which is a 14012 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does 14013 not touch the return address. Hence returning from FUNCTION will 14014 return to whoever called the current `thunk'. 14015 14016 The effect must be as if FUNCTION had been called directly with the 14017 adjusted first argument. This macro is responsible for emitting 14018 all of the code for a thunk function; output_function_prologue() 14019 and output_function_epilogue() are not invoked. 14020 14021 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already 14022 been extracted from it.) It might possibly be useful on some 14023 targets, but probably not. 14024 14025 If you do not define this macro, the target-independent code in the 14026 C++ frontend will generate a less efficient heavyweight thunk that 14027 calls FUNCTION instead of jumping to it. The generic approach does 14028 not support varargs. */ 14029 14030void 14031rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 14032 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 14033 tree function) 14034{ 14035 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl)); 14036 rtx this_rtx, funexp; 14037 rtx_insn *insn; 14038 14039 reload_completed = 1; 14040 epilogue_completed = 1; 14041 14042 /* Mark the end of the (empty) prologue. */ 14043 emit_note (NOTE_INSN_PROLOGUE_END); 14044 14045 /* Find the "this" pointer. If the function returns a structure, 14046 the structure return pointer is in r3. */ 14047 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 14048 this_rtx = gen_rtx_REG (Pmode, 4); 14049 else 14050 this_rtx = gen_rtx_REG (Pmode, 3); 14051 14052 /* Apply the constant offset, if required. */ 14053 if (delta) 14054 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta))); 14055 14056 /* Apply the offset from the vtable, if required. */ 14057 if (vcall_offset) 14058 { 14059 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 14060 rtx tmp = gen_rtx_REG (Pmode, 12); 14061 14062 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); 14063 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000) 14064 { 14065 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx)); 14066 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); 14067 } 14068 else 14069 { 14070 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx); 14071 14072 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc)); 14073 } 14074 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp)); 14075 } 14076 14077 /* Generate a tail call to the target function. */ 14078 if (!TREE_USED (function)) 14079 { 14080 assemble_external (function); 14081 TREE_USED (function) = 1; 14082 } 14083 funexp = XEXP (DECL_RTL (function), 0); 14084 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 14085 14086 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx, const0_rtx)); 14087 SIBLING_CALL_P (insn) = 1; 14088 emit_barrier (); 14089 14090 /* Run just enough of rest_of_compilation to get the insns emitted. 14091 There's not really enough bulk here to make other passes such as 14092 instruction scheduling worth while. */ 14093 insn = get_insns (); 14094 shorten_branches (insn); 14095 assemble_start_function (thunk_fndecl, fnname); 14096 final_start_function (insn, file, 1); 14097 final (insn, file, 1); 14098 final_end_function (); 14099 assemble_end_function (thunk_fndecl, fnname); 14100 14101 reload_completed = 0; 14102 epilogue_completed = 0; 14103} 14104 14105#include "gt-rs6000-call.h" 14106