1;; Predicate definitions for POWER and PowerPC. 2;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return 1 for anything except PARALLEL. 21(define_predicate "any_operand" 22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem")) 23 24;; Return 1 for any PARALLEL. 25(define_predicate "any_parallel_operand" 26 (match_code "parallel")) 27 28;; Return 1 if op is COUNT register. 29(define_predicate "count_register_operand" 30 (and (match_code "reg") 31 (match_test "REGNO (op) == CTR_REGNO 32 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 33 34;; Return 1 if op is a SUBREG that is used to look at a SFmode value as 35;; and integer or vice versa. 36;; 37;; In the normal case where SFmode is in a floating point/vector register, it 38;; is stored as a DFmode and has a different format. If we don't transform the 39;; value, things that use logical operations on the values will get the wrong 40;; value. 41;; 42;; If we don't have 64-bit and direct move, this conversion will be done by 43;; store and load, instead of by fiddling with the bits within the register. 44(define_predicate "sf_subreg_operand" 45 (match_code "subreg") 46{ 47 rtx inner_reg = SUBREG_REG (op); 48 machine_mode inner_mode = GET_MODE (inner_reg); 49 50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg)) 51 return 0; 52 53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT) 54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode)) 55 { 56 if (INT_REGNO_P (REGNO (inner_reg))) 57 return 0; 58 59 return 1; 60 } 61 return 0; 62}) 63 64;; Return 1 if op is an Altivec register. 65(define_predicate "altivec_register_operand" 66 (match_operand 0 "register_operand") 67{ 68 if (SUBREG_P (op)) 69 { 70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 71 return 0; 72 73 op = SUBREG_REG (op); 74 } 75 76 if (!REG_P (op)) 77 return 0; 78 79 if (!HARD_REGISTER_P (op)) 80 return 1; 81 82 return ALTIVEC_REGNO_P (REGNO (op)); 83}) 84 85;; Return 1 if op is a VSX register. 86(define_predicate "vsx_register_operand" 87 (match_operand 0 "register_operand") 88{ 89 if (SUBREG_P (op)) 90 { 91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 92 return 0; 93 94 op = SUBREG_REG (op); 95 } 96 97 if (!REG_P (op)) 98 return 0; 99 100 if (!HARD_REGISTER_P (op)) 101 return 1; 102 103 return VSX_REGNO_P (REGNO (op)); 104}) 105 106;; Like vsx_register_operand, but allow SF SUBREGS 107(define_predicate "vsx_reg_sfsubreg_ok" 108 (match_operand 0 "register_operand") 109{ 110 if (SUBREG_P (op)) 111 op = SUBREG_REG (op); 112 113 if (!REG_P (op)) 114 return 0; 115 116 if (!HARD_REGISTER_P (op)) 117 return 1; 118 119 return VSX_REGNO_P (REGNO (op)); 120}) 121 122;; Return 1 if op is a vector register that operates on floating point vectors 123;; (either altivec or VSX). 124(define_predicate "vfloat_operand" 125 (match_operand 0 "register_operand") 126{ 127 if (SUBREG_P (op)) 128 { 129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 130 return 0; 131 132 op = SUBREG_REG (op); 133 } 134 135 if (!REG_P (op)) 136 return 0; 137 138 if (!HARD_REGISTER_P (op)) 139 return 1; 140 141 return VFLOAT_REGNO_P (REGNO (op)); 142}) 143 144;; Return 1 if op is a vector register that operates on integer vectors 145;; (only altivec, VSX doesn't support integer vectors) 146(define_predicate "vint_operand" 147 (match_operand 0 "register_operand") 148{ 149 if (SUBREG_P (op)) 150 { 151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 152 return 0; 153 154 op = SUBREG_REG (op); 155 } 156 157 if (!REG_P (op)) 158 return 0; 159 160 if (!HARD_REGISTER_P (op)) 161 return 1; 162 163 return VINT_REGNO_P (REGNO (op)); 164}) 165 166;; Return 1 if op is a vector register to do logical operations on (and, or, 167;; xor, etc.) 168(define_predicate "vlogical_operand" 169 (match_operand 0 "register_operand") 170{ 171 if (SUBREG_P (op)) 172 { 173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 174 return 0; 175 176 op = SUBREG_REG (op); 177 } 178 179 180 if (!REG_P (op)) 181 return 0; 182 183 if (!HARD_REGISTER_P (op)) 184 return 1; 185 186 return VLOGICAL_REGNO_P (REGNO (op)); 187}) 188 189;; Return 1 if op is the carry register. 190(define_predicate "ca_operand" 191 (match_operand 0 "register_operand") 192{ 193 if (SUBREG_P (op)) 194 op = SUBREG_REG (op); 195 196 if (!REG_P (op)) 197 return 0; 198 199 return CA_REGNO_P (REGNO (op)); 200}) 201 202;; Return 1 if operand is constant zero (scalars and vectors). 203(define_predicate "zero_constant" 204 (and (match_code "const_int,const_double,const_wide_int,const_vector") 205 (match_test "op == CONST0_RTX (mode)"))) 206 207;; Return 1 if operand is constant -1 (scalars and vectors). 208(define_predicate "all_ones_constant" 209 (and (match_code "const_int,const_double,const_wide_int,const_vector") 210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)"))) 211 212;; Return 1 if op is a signed 5-bit constant integer. 213(define_predicate "s5bit_cint_operand" 214 (and (match_code "const_int") 215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) 216 217;; Return 1 if op is a unsigned 3-bit constant integer. 218(define_predicate "u3bit_cint_operand" 219 (and (match_code "const_int") 220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7"))) 221 222;; Return 1 if op is a unsigned 5-bit constant integer. 223(define_predicate "u5bit_cint_operand" 224 (and (match_code "const_int") 225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) 226 227;; Return 1 if op is a unsigned 6-bit constant integer. 228(define_predicate "u6bit_cint_operand" 229 (and (match_code "const_int") 230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63"))) 231 232;; Return 1 if op is an unsigned 7-bit constant integer. 233(define_predicate "u7bit_cint_operand" 234 (and (match_code "const_int") 235 (match_test "IN_RANGE (INTVAL (op), 0, 127)"))) 236 237;; Return 1 if op is an unsigned 8-bit constant integer. 238(define_predicate "u8bit_cint_operand" 239 (and (match_code "const_int") 240 (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) 241 242;; Return 1 if op is a signed 8-bit constant integer. 243;; Integer multiplication complete more quickly 244(define_predicate "s8bit_cint_operand" 245 (and (match_code "const_int") 246 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) 247 248;; Return 1 if op is a unsigned 10-bit constant integer. 249(define_predicate "u10bit_cint_operand" 250 (and (match_code "const_int") 251 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023"))) 252 253;; Return 1 if op is a constant integer that can fit in a D field. 254(define_predicate "short_cint_operand" 255 (and (match_code "const_int") 256 (match_test "satisfies_constraint_I (op)"))) 257 258;; Return 1 if op is a constant integer that can fit in an unsigned D field. 259(define_predicate "u_short_cint_operand" 260 (and (match_code "const_int") 261 (match_test "satisfies_constraint_K (op)"))) 262 263;; Return 1 if op is a constant integer that is a signed 16-bit constant 264;; shifted left 16 bits 265(define_predicate "upper16_cint_operand" 266 (and (match_code "const_int") 267 (match_test "satisfies_constraint_L (op)"))) 268 269;; Return 1 if op is a constant integer that cannot fit in a signed D field. 270(define_predicate "non_short_cint_operand" 271 (and (match_code "const_int") 272 (match_test "(unsigned HOST_WIDE_INT) 273 (INTVAL (op) + 0x8000) >= 0x10000"))) 274 275;; Return 1 if op is a positive constant integer that is an exact power of 2. 276(define_predicate "exact_log2_cint_operand" 277 (and (match_code "const_int") 278 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) 279 280;; Match op = 0 or op = 1. 281(define_predicate "const_0_to_1_operand" 282 (and (match_code "const_int") 283 (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) 284 285;; Match op = 0..3. 286(define_predicate "const_0_to_3_operand" 287 (and (match_code "const_int") 288 (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) 289 290;; Match op = 2 or op = 3. 291(define_predicate "const_2_to_3_operand" 292 (and (match_code "const_int") 293 (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) 294 295;; Match op = 0..7. 296(define_predicate "const_0_to_7_operand" 297 (and (match_code "const_int") 298 (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) 299 300;; Match op = 0..11 301(define_predicate "const_0_to_12_operand" 302 (and (match_code "const_int") 303 (match_test "IN_RANGE (INTVAL (op), 0, 12)"))) 304 305;; Match op = 0..15 306(define_predicate "const_0_to_15_operand" 307 (and (match_code "const_int") 308 (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) 309 310;; Return 1 if op is a 34-bit constant integer. 311(define_predicate "cint34_operand" 312 (match_code "const_int") 313{ 314 if (!TARGET_PREFIXED) 315 return 0; 316 317 return SIGNED_INTEGER_34BIT_P (INTVAL (op)); 318}) 319 320;; Return 1 if op is a register that is not special. 321;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where 322;; you need to be careful in moving a SFmode to SImode and vice versa due to 323;; the fact that SFmode is represented as DFmode in the VSX registers. 324(define_predicate "gpc_reg_operand" 325 (match_operand 0 "register_operand") 326{ 327 if (SUBREG_P (op)) 328 { 329 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 330 return 0; 331 332 op = SUBREG_REG (op); 333 } 334 335 if (!REG_P (op)) 336 return 0; 337 338 if (!HARD_REGISTER_P (op)) 339 return 1; 340 341 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op))) 342 return 1; 343 344 if (TARGET_VSX && VSX_REGNO_P (REGNO (op))) 345 return 1; 346 347 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op)); 348}) 349 350;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't 351;; allow floating point or vector registers. Since vector registers are not 352;; allowed, we don't have to reject SFmode/SImode subregs. 353(define_predicate "int_reg_operand" 354 (match_operand 0 "register_operand") 355{ 356 if (SUBREG_P (op)) 357 { 358 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode)) 359 return 0; 360 361 op = SUBREG_REG (op); 362 } 363 364 if (!REG_P (op)) 365 return 0; 366 367 if (!HARD_REGISTER_P (op)) 368 return 1; 369 370 return INT_REGNO_P (REGNO (op)); 371}) 372 373;; Like int_reg_operand, but don't return true for pseudo registers 374;; We don't have to check for SF SUBREGS because pseudo registers 375;; are not allowed, and SF SUBREGs are ok within GPR registers. 376(define_predicate "int_reg_operand_not_pseudo" 377 (match_operand 0 "register_operand") 378{ 379 if (SUBREG_P (op)) 380 op = SUBREG_REG (op); 381 382 if (!REG_P (op)) 383 return 0; 384 385 if (!HARD_REGISTER_P (op)) 386 return 0; 387 388 return INT_REGNO_P (REGNO (op)); 389}) 390 391;; Like int_reg_operand, but only return true for base registers 392(define_predicate "base_reg_operand" 393 (match_operand 0 "int_reg_operand") 394{ 395 if (SUBREG_P (op)) 396 op = SUBREG_REG (op); 397 398 if (!REG_P (op)) 399 return 0; 400 401 return (REGNO (op) != FIRST_GPR_REGNO); 402}) 403 404 405;; Return true if this is a traditional floating point register 406(define_predicate "fpr_reg_operand" 407 (match_code "reg,subreg") 408{ 409 HOST_WIDE_INT r; 410 411 if (SUBREG_P (op)) 412 op = SUBREG_REG (op); 413 414 if (!REG_P (op)) 415 return 0; 416 417 r = REGNO (op); 418 if (!HARD_REGISTER_NUM_P (r)) 419 return 1; 420 421 return FP_REGNO_P (r); 422}) 423 424;; Return 1 if op is a general purpose register that is an even register 425;; which suitable for a load/store quad operation 426;; Subregs are not allowed here because when they are combine can 427;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to 428;; think the innermost reg needs reloading, in TImode instead of 429;; PTImode. So reload will choose a reg in TImode which has no 430;; requirement that the reg be even. 431(define_predicate "quad_int_reg_operand" 432 (match_code "reg") 433{ 434 HOST_WIDE_INT r; 435 436 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC) 437 return 0; 438 439 r = REGNO (op); 440 if (!HARD_REGISTER_NUM_P (r)) 441 return 1; 442 443 return (INT_REGNO_P (r) && ((r & 1) == 0)); 444}) 445 446;; Return 1 if op is a register that is a condition register field. 447(define_predicate "cc_reg_operand" 448 (match_operand 0 "register_operand") 449{ 450 if (SUBREG_P (op)) 451 op = SUBREG_REG (op); 452 453 if (!REG_P (op)) 454 return 0; 455 456 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 457 return 1; 458 459 return CR_REGNO_P (REGNO (op)); 460}) 461 462;; Return 1 if op is a register that is a condition register field not cr0. 463(define_predicate "cc_reg_not_cr0_operand" 464 (match_operand 0 "register_operand") 465{ 466 if (SUBREG_P (op)) 467 op = SUBREG_REG (op); 468 469 if (!REG_P (op)) 470 return 0; 471 472 if (REGNO (op) > LAST_VIRTUAL_REGISTER) 473 return 1; 474 475 return CR_REGNO_NOT_CR0_P (REGNO (op)); 476}) 477 478;; Return 1 if op is a constant integer valid for D field 479;; or non-special register register. 480(define_predicate "reg_or_short_operand" 481 (if_then_else (match_code "const_int") 482 (match_operand 0 "short_cint_operand") 483 (match_operand 0 "gpc_reg_operand"))) 484 485;; Return 1 if op is a constant integer valid for DS field 486;; or non-special register. 487(define_predicate "reg_or_aligned_short_operand" 488 (if_then_else (match_code "const_int") 489 (and (match_operand 0 "short_cint_operand") 490 (match_test "!(INTVAL (op) & 3)")) 491 (match_operand 0 "gpc_reg_operand"))) 492 493;; Return 1 if op is a constant integer whose high-order 16 bits are zero 494;; or non-special register. 495(define_predicate "reg_or_u_short_operand" 496 (if_then_else (match_code "const_int") 497 (match_operand 0 "u_short_cint_operand") 498 (match_operand 0 "gpc_reg_operand"))) 499 500;; Return 1 if op is any constant integer or a non-special register. 501(define_predicate "reg_or_cint_operand" 502 (ior (match_code "const_int") 503 (match_operand 0 "gpc_reg_operand"))) 504 505;; Return 1 if op is constant zero or a non-special register. 506(define_predicate "reg_or_zero_operand" 507 (ior (match_operand 0 "zero_constant") 508 (match_operand 0 "gpc_reg_operand"))) 509 510;; Return 1 if op is a constant integer valid for addition with addis, addi. 511(define_predicate "add_cint_operand" 512 (and (match_code "const_int") 513 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) 514 + (mode == SImode ? 0x80000000 : 0x80008000)) 515 < (unsigned HOST_WIDE_INT) 0x100000000ll"))) 516 517;; Return 1 if op is a constant integer valid for addition 518;; or non-special register. 519(define_predicate "reg_or_add_cint_operand" 520 (if_then_else (match_code "const_int") 521 (match_operand 0 "add_cint_operand") 522 (match_operand 0 "gpc_reg_operand"))) 523 524;; Return 1 if op is a constant integer valid for subtraction 525;; or non-special register. 526(define_predicate "reg_or_sub_cint_operand" 527 (if_then_else (match_code "const_int") 528 (match_test "(unsigned HOST_WIDE_INT) 529 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) 530 < (unsigned HOST_WIDE_INT) 0x100000000ll") 531 (match_operand 0 "gpc_reg_operand"))) 532 533;; Return 1 if op is any 32-bit unsigned constant integer 534;; or non-special register. 535(define_predicate "reg_or_logical_cint_operand" 536 (if_then_else (match_code "const_int") 537 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 538 && INTVAL (op) >= 0) 539 || ((INTVAL (op) & GET_MODE_MASK (mode) 540 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") 541 (match_operand 0 "gpc_reg_operand"))) 542 543;; Like reg_or_logical_cint_operand, but allow vsx registers 544(define_predicate "vsx_reg_or_cint_operand" 545 (ior (match_operand 0 "vsx_register_operand") 546 (match_operand 0 "reg_or_logical_cint_operand"))) 547 548;; Return 1 if operand is a CONST_DOUBLE that can be set in a register 549;; with no more than one instruction per word. 550(define_predicate "easy_fp_constant" 551 (match_code "const_double") 552{ 553 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode)); 554 555 /* Consider all constants with -msoft-float to be easy when regs are 556 32-bit and thus can be loaded with a maximum of 2 insns. For 557 64-bit avoid long dependent insn sequences. */ 558 if (TARGET_SOFT_FLOAT) 559 { 560 if (!TARGET_POWERPC64) 561 return 1; 562 563 int size = GET_MODE_SIZE (mode); 564 if (size < 8) 565 return 1; 566 567 int load_from_mem_insns = 2; 568 if (size > 8) 569 load_from_mem_insns++; 570 if (TARGET_CMODEL != CMODEL_SMALL) 571 load_from_mem_insns++; 572 if (num_insns_constant (op, mode) <= load_from_mem_insns) 573 return 1; 574 } 575 576 /* 0.0D is not all zero bits. */ 577 if (DECIMAL_FLOAT_MODE_P (mode)) 578 return 0; 579 580 /* The constant 0.0 is easy under VSX. */ 581 if (TARGET_VSX && op == CONST0_RTX (mode)) 582 return 1; 583 584 /* Otherwise consider floating point constants hard, so that the 585 constant gets pushed to memory during the early RTL phases. This 586 has the advantage that double precision constants that can be 587 represented in single precision without a loss of precision will 588 use single precision loads. */ 589 return 0; 590}) 591 592;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB 593;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. 594 595(define_predicate "xxspltib_constant_split" 596 (match_code "const_vector,vec_duplicate,const_int") 597{ 598 int value = 256; 599 int num_insns = -1; 600 601 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 602 return false; 603 604 return num_insns > 1; 605}) 606 607 608;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB 609;; instruction. 610 611(define_predicate "xxspltib_constant_nosplit" 612 (match_code "const_vector,vec_duplicate,const_int") 613{ 614 int value = 256; 615 int num_insns = -1; 616 617 if (!xxspltib_constant_p (op, mode, &num_insns, &value)) 618 return false; 619 620 return num_insns == 1; 621}) 622 623;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 624;; vector register without using memory. 625(define_predicate "easy_vector_constant" 626 (match_code "const_vector") 627{ 628 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) 629 { 630 int value = 256; 631 int num_insns = -1; 632 633 if (zero_constant (op, mode) || all_ones_constant (op, mode)) 634 return true; 635 636 if (TARGET_P9_VECTOR 637 && xxspltib_constant_p (op, mode, &num_insns, &value)) 638 return true; 639 640 return easy_altivec_constant (op, mode); 641 } 642 643 return false; 644}) 645 646;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. 647(define_predicate "easy_vector_constant_add_self" 648 (and (match_code "const_vector") 649 (and (match_test "TARGET_ALTIVEC") 650 (match_test "easy_altivec_constant (op, mode)"))) 651{ 652 HOST_WIDE_INT val; 653 int elt; 654 if (mode == V2DImode || mode == V2DFmode) 655 return 0; 656 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 657 val = const_vector_elt_as_int (op, elt); 658 val = ((val & 0xff) ^ 0x80) - 0x80; 659 return EASY_VECTOR_15_ADD_SELF (val); 660}) 661 662;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. 663(define_predicate "easy_vector_constant_msb" 664 (and (match_code "const_vector") 665 (and (match_test "TARGET_ALTIVEC") 666 (match_test "easy_altivec_constant (op, mode)"))) 667{ 668 HOST_WIDE_INT val; 669 int elt; 670 if (mode == V2DImode || mode == V2DFmode) 671 return 0; 672 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0; 673 val = const_vector_elt_as_int (op, elt); 674 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); 675}) 676 677;; Return true if this is an easy altivec constant that we form 678;; by using VSLDOI. 679(define_predicate "easy_vector_constant_vsldoi" 680 (and (match_code "const_vector") 681 (and (match_test "TARGET_ALTIVEC") 682 (and (match_test "easy_altivec_constant (op, mode)") 683 (match_test "vspltis_shifted (op) != 0"))))) 684 685;; Return 1 if operand is a vector int register or is either a vector constant 686;; of all 0 bits of a vector constant of all 1 bits. 687(define_predicate "vector_int_reg_or_same_bit" 688 (match_code "reg,subreg,const_vector") 689{ 690 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 691 return 0; 692 693 else if (REG_P (op) || SUBREG_P (op)) 694 return vint_operand (op, mode); 695 696 else 697 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode); 698}) 699 700;; Return 1 if operand is 0.0. 701(define_predicate "zero_fp_constant" 702 (and (match_code "const_double") 703 (match_test "SCALAR_FLOAT_MODE_P (mode) 704 && op == CONST0_RTX (mode)"))) 705 706;; Return 1 if the operand is in volatile memory. Note that during the 707;; RTL generation phase, memory_operand does not return TRUE for volatile 708;; memory references. So this function allows us to recognize volatile 709;; references where it's safe. 710(define_predicate "volatile_mem_operand" 711 (and (match_code "mem") 712 (match_test "MEM_VOLATILE_P (op)") 713 (if_then_else (match_test "reload_completed") 714 (match_operand 0 "memory_operand") 715 (match_test "memory_address_p (mode, XEXP (op, 0))")))) 716 717;; Return 1 if the operand is a volatile or non-volatile memory operand. 718(define_predicate "any_memory_operand" 719 (ior (match_operand 0 "memory_operand") 720 (match_operand 0 "volatile_mem_operand"))) 721 722;; Return 1 if the operand is an offsettable memory operand. 723(define_predicate "offsettable_mem_operand" 724 (and (match_operand 0 "any_memory_operand") 725 (match_test "offsettable_nonstrict_memref_p (op)"))) 726 727;; Return 1 if the operand is a simple offsettable memory operand 728;; that does not include pre-increment, post-increment, etc. 729(define_predicate "simple_offsettable_mem_operand" 730 (match_operand 0 "offsettable_mem_operand") 731{ 732 rtx addr = XEXP (op, 0); 733 734 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 735 return 0; 736 737 if (!CONSTANT_P (XEXP (addr, 1))) 738 return 0; 739 740 return base_reg_operand (XEXP (addr, 0), Pmode); 741}) 742 743;; Return 1 if the operand is suitable for load/store quad memory. 744;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). 745(define_predicate "quad_memory_operand" 746 (match_code "mem") 747{ 748 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) 749 return false; 750 751 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128) 752 return false; 753 754 return quad_address_p (XEXP (op, 0), mode, false); 755}) 756 757;; Return 1 if the operand is suitable for load/store to vector registers with 758;; d-form addressing (register+offset), which was added in ISA 3.0. 759;; Unlike quad_memory_operand, we do not have to check for alignment. 760(define_predicate "vsx_quad_dform_memory_operand" 761 (match_code "mem") 762{ 763 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16) 764 return false; 765 766 return quad_address_p (XEXP (op, 0), mode, false); 767}) 768 769;; Return 1 if the operand is an indexed or indirect memory operand. 770(define_predicate "indexed_or_indirect_operand" 771 (match_code "mem") 772{ 773 op = XEXP (op, 0); 774 if (VECTOR_MEM_ALTIVEC_P (mode) 775 && GET_CODE (op) == AND 776 && CONST_INT_P (XEXP (op, 1)) 777 && INTVAL (XEXP (op, 1)) == -16) 778 op = XEXP (op, 0); 779 780 return indexed_or_indirect_address (op, mode); 781}) 782 783;; Like indexed_or_indirect_operand, but also allow a GPR register if direct 784;; moves are supported. 785(define_predicate "reg_or_indexed_operand" 786 (match_code "mem,reg,subreg") 787{ 788 if (MEM_P (op)) 789 return indexed_or_indirect_operand (op, mode); 790 else if (TARGET_DIRECT_MOVE) 791 return register_operand (op, mode); 792 return 793 0; 794}) 795 796;; Return 1 if the operand is an indexed or indirect memory operand with an 797;; AND -16 in it, used to recognize when we need to switch to Altivec loads 798;; to realign loops instead of VSX (altivec silently ignores the bottom bits, 799;; while VSX uses the full address and traps) 800(define_predicate "altivec_indexed_or_indirect_operand" 801 (match_code "mem") 802{ 803 op = XEXP (op, 0); 804 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) 805 && GET_CODE (op) == AND 806 && CONST_INT_P (XEXP (op, 1)) 807 && INTVAL (XEXP (op, 1)) == -16) 808 return indexed_or_indirect_address (XEXP (op, 0), mode); 809 810 return 0; 811}) 812 813;; Return 1 if the operand is an indexed or indirect address. 814(define_special_predicate "indexed_or_indirect_address" 815 (and (match_test "REG_P (op) 816 || (GET_CODE (op) == PLUS 817 /* Omit testing REG_P (XEXP (op, 0)). */ 818 && REG_P (XEXP (op, 1)))") 819 (match_operand 0 "address_operand"))) 820 821;; Return 1 if the operand is an index-form address. 822(define_special_predicate "indexed_address" 823 (match_test "(GET_CODE (op) == PLUS 824 && REG_P (XEXP (op, 0)) 825 && REG_P (XEXP (op, 1)))")) 826 827;; Return 1 if the operand is a MEM with an update-form address. This may 828;; also include update-indexed form. 829(define_special_predicate "update_address_mem" 830 (match_test "(MEM_P (op) 831 && (GET_CODE (XEXP (op, 0)) == PRE_INC 832 || GET_CODE (XEXP (op, 0)) == PRE_DEC 833 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))")) 834 835;; Return 1 if the operand is a MEM with an indexed-form address. 836(define_special_predicate "indexed_address_mem" 837 (match_test "(MEM_P (op) 838 && (indexed_address (XEXP (op, 0), mode) 839 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY 840 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))")) 841 842;; Return 1 if the operand is either a non-special register or can be used 843;; as the operand of a `mode' add insn. 844(define_predicate "add_operand" 845 (if_then_else (match_code "const_int") 846 (match_test "satisfies_constraint_I (op) 847 || satisfies_constraint_L (op) 848 || satisfies_constraint_eI (op)") 849 (match_operand 0 "gpc_reg_operand"))) 850 851;; Return 1 if the operand is either a non-special register, or 0, or -1. 852(define_predicate "adde_operand" 853 (if_then_else (match_code "const_int") 854 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1") 855 (match_operand 0 "gpc_reg_operand"))) 856 857;; Return 1 if OP is a constant but not a valid add_operand. 858(define_predicate "non_add_cint_operand" 859 (and (match_code "const_int") 860 (not (match_operand 0 "add_operand")))) 861 862;; Return 1 if the operand is a constant that can be used as the operand 863;; of an AND, OR or XOR. 864(define_predicate "logical_const_operand" 865 (match_code "const_int") 866{ 867 HOST_WIDE_INT opl; 868 869 opl = INTVAL (op) & GET_MODE_MASK (mode); 870 871 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 872 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); 873}) 874 875;; Return 1 if the operand is a non-special register or a constant that 876;; can be used as the operand of an AND, OR or XOR. 877(define_predicate "logical_operand" 878 (ior (match_operand 0 "gpc_reg_operand") 879 (match_operand 0 "logical_const_operand"))) 880 881;; Return 1 if op is a constant that is not a logical operand, but could 882;; be split into one. 883(define_predicate "non_logical_cint_operand" 884 (and (match_code "const_int,const_wide_int") 885 (and (not (match_operand 0 "logical_operand")) 886 (match_operand 0 "reg_or_logical_cint_operand")))) 887 888;; Return 1 if the operand is either a non-special register or a 889;; constant that can be used as the operand of a logical AND. 890(define_predicate "and_operand" 891 (ior (and (match_code "const_int") 892 (match_test "rs6000_is_valid_and_mask (op, mode)")) 893 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 894 (match_operand 0 "gpc_reg_operand") 895 (match_operand 0 "logical_operand")))) 896 897;; Return 1 if the operand is either a logical operand or a short cint operand. 898(define_predicate "scc_eq_operand" 899 (ior (match_operand 0 "logical_operand") 900 (match_operand 0 "short_cint_operand"))) 901 902;; Return 1 if the operand is a general non-special register or memory operand. 903(define_predicate "reg_or_mem_operand" 904 (ior (match_operand 0 "gpc_reg_operand") 905 (match_operand 0 "any_memory_operand") 906 (and (match_code "mem") 907 (match_test "macho_lo_sum_memory_operand (op, mode)")))) 908 909;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. 910(define_predicate "zero_reg_mem_operand" 911 (ior (and (match_test "TARGET_VSX") 912 (match_operand 0 "zero_fp_constant")) 913 (match_operand 0 "reg_or_mem_operand"))) 914 915;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit 916;; data types inside of a vector that scalar instructions operate on 917(define_predicate "vsx_scalar_64bit" 918 (match_code "const_int") 919{ 920 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT); 921}) 922 923;; Return 1 if the operand is a general register or memory operand without 924;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC 925;; lwa instruction. 926(define_predicate "lwa_operand" 927 (match_code "reg,subreg,mem") 928{ 929 rtx inner, addr, offset; 930 931 inner = op; 932 if (reload_completed && SUBREG_P (inner)) 933 inner = SUBREG_REG (inner); 934 935 if (gpc_reg_operand (inner, mode)) 936 return true; 937 if (!any_memory_operand (inner, mode)) 938 return false; 939 940 addr = XEXP (inner, 0); 941 942 /* The LWA instruction uses the DS-form instruction format which requires 943 that the bottom two bits of the offset must be 0. The prefixed PLWA does 944 not have this restriction. While the actual load from memory is 32-bits, 945 we pass in DImode here to test for using a DS instruction. */ 946 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS)) 947 return true; 948 949 if (GET_CODE (addr) == PRE_INC 950 || GET_CODE (addr) == PRE_DEC 951 || (GET_CODE (addr) == PRE_MODIFY 952 && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) 953 return false; 954 if (GET_CODE (addr) == LO_SUM 955 && REG_P (XEXP (addr, 0)) 956 && GET_CODE (XEXP (addr, 1)) == CONST) 957 addr = XEXP (XEXP (addr, 1), 0); 958 if (GET_CODE (addr) != PLUS) 959 return true; 960 offset = XEXP (addr, 1); 961 if (!CONST_INT_P (offset)) 962 return true; 963 return INTVAL (offset) % 4 == 0; 964}) 965 966;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. 967(define_predicate "symbol_ref_operand" 968 (and (match_code "symbol_ref") 969 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) 970 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) 971 972;; Return 1 if op is an operand that can be loaded via the GOT. 973;; or non-special register register field no cr0 974(define_predicate "got_operand" 975 (match_code "symbol_ref,const,label_ref")) 976 977;; Return 1 if op is a simple reference that can be loaded via the GOT, 978;; excluding labels involving addition. 979(define_predicate "got_no_const_operand" 980 (match_code "symbol_ref,label_ref")) 981 982;; Return 1 if op is a SYMBOL_REF for a TLS symbol. 983(define_predicate "rs6000_tls_symbol_ref" 984 (and (match_code "symbol_ref") 985 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) 986 987;; Return 1 for the CONST_INT or UNSPEC second CALL operand. 988;; Prevents unwanted substitution of the unspec got_reg arg. 989(define_predicate "unspec_tls" 990 (match_code "const_int,unspec") 991{ 992 if (CONST_INT_P (op)) 993 return 1; 994 if (XINT (op, 1) == UNSPEC_TLSGD) 995 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx; 996 if (XINT (op, 1) == UNSPEC_TLSLD) 997 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx; 998 return 0; 999}) 1000 1001;; Return 1 if the operand, used inside a MEM, is a valid first argument 1002;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. 1003(define_predicate "call_operand" 1004 (if_then_else (match_code "reg") 1005 (match_test "REGNO (op) == LR_REGNO 1006 || REGNO (op) == CTR_REGNO 1007 || !HARD_REGISTER_P (op)") 1008 (match_code "symbol_ref"))) 1009 1010;; Return 1 if the operand, used inside a MEM, is a valid first argument 1011;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR. 1012(define_predicate "indirect_call_operand" 1013 (match_code "reg,unspec") 1014{ 1015 if (REG_P (op)) 1016 return (REGNO (op) == LR_REGNO 1017 || REGNO (op) == CTR_REGNO); 1018 if (GET_CODE (op) == UNSPEC) 1019 { 1020 if (XINT (op, 1) != UNSPEC_PLTSEQ) 1021 return false; 1022 op = XVECEXP (op, 0, 0); 1023 return REG_P (op) && REGNO (op) == CTR_REGNO; 1024 } 1025 return false; 1026}) 1027 1028;; Return 1 if the operand is a SYMBOL_REF for a function known to be in 1029;; this file. 1030(define_predicate "current_file_function_operand" 1031 (and (match_code "symbol_ref") 1032 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) 1033 && (SYMBOL_REF_LOCAL_P (op) 1034 || (op == XEXP (DECL_RTL (current_function_decl), 0) 1035 && !decl_replaceable_p (current_function_decl))) 1036 && !((DEFAULT_ABI == ABI_AIX 1037 || DEFAULT_ABI == ABI_ELFv2) 1038 && (SYMBOL_REF_EXTERNAL_P (op) 1039 || SYMBOL_REF_WEAK (op))) 1040 && !(DEFAULT_ABI == ABI_ELFv2 1041 && SYMBOL_REF_DECL (op) != NULL 1042 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL 1043 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op)) 1044 != rs6000_pcrel_p (cfun)))"))) 1045 1046;; Return 1 if this operand is a valid input for a move insn. 1047(define_predicate "input_operand" 1048 (match_code "symbol_ref,const,reg,subreg,mem, 1049 const_double,const_wide_int,const_vector,const_int") 1050{ 1051 /* Memory is always valid. */ 1052 if (any_memory_operand (op, mode)) 1053 return 1; 1054 1055 /* For floating-point, easy constants are valid. */ 1056 if (SCALAR_FLOAT_MODE_P (mode) 1057 && easy_fp_constant (op, mode)) 1058 return 1; 1059 1060 /* Allow any integer constant. */ 1061 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op)) 1062 return 1; 1063 1064 /* Allow easy vector constants. */ 1065 if (GET_CODE (op) == CONST_VECTOR 1066 && easy_vector_constant (op, mode)) 1067 return 1; 1068 1069 /* For floating-point or multi-word mode, the only remaining valid type 1070 is a register. */ 1071 if (SCALAR_FLOAT_MODE_P (mode) 1072 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1073 return register_operand (op, mode); 1074 1075 /* We don't allow moving the carry bit around. */ 1076 if (ca_operand (op, mode)) 1077 return 0; 1078 1079 /* The only cases left are integral modes one word or smaller (we 1080 do not get called for MODE_CC values). These can be in any 1081 register. */ 1082 if (register_operand (op, mode)) 1083 return 1; 1084 1085 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region 1086 to be valid. */ 1087 if (DEFAULT_ABI == ABI_V4 1088 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST) 1089 && small_data_operand (op, Pmode)) 1090 return 1; 1091 1092 return 0; 1093}) 1094 1095;; Return 1 if this operand is a valid input for a vsx_splat insn. 1096(define_predicate "splat_input_operand" 1097 (match_code "reg,subreg,mem") 1098{ 1099 machine_mode vmode; 1100 1101 if (mode == DFmode) 1102 vmode = V2DFmode; 1103 else if (mode == DImode) 1104 vmode = V2DImode; 1105 else if (mode == SImode && TARGET_P9_VECTOR) 1106 vmode = V4SImode; 1107 else if (mode == SFmode && TARGET_P9_VECTOR) 1108 vmode = V4SFmode; 1109 else 1110 return false; 1111 1112 if (MEM_P (op)) 1113 { 1114 rtx addr = XEXP (op, 0); 1115 1116 if (! volatile_ok && MEM_VOLATILE_P (op)) 1117 return 0; 1118 1119 if (lra_in_progress || reload_completed) 1120 return indexed_or_indirect_address (addr, vmode); 1121 else 1122 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op)); 1123 } 1124 return gpc_reg_operand (op, mode); 1125}) 1126 1127;; Return 1 if this operand is valid for a MMA assemble accumulator insn. 1128(define_special_predicate "mma_assemble_input_operand" 1129 (match_test "(mode == V16QImode 1130 && (vsx_register_operand (op, mode) 1131 || (MEM_P (op) 1132 && (indexed_or_indirect_address (XEXP (op, 0), mode) 1133 || quad_address_p (XEXP (op, 0), mode, false)))))")) 1134 1135;; Return true if operand is an operator used in rotate-and-mask instructions. 1136(define_predicate "rotate_mask_operator" 1137 (match_code "rotate,ashift,lshiftrt")) 1138 1139;; Return true if operand is boolean operator. 1140(define_predicate "boolean_operator" 1141 (match_code "and,ior,xor")) 1142 1143;; Return true if operand is OR-form of boolean operator. 1144(define_predicate "boolean_or_operator" 1145 (match_code "ior,xor")) 1146 1147;; Return true if operand is an equality operator. 1148(define_special_predicate "equality_operator" 1149 (match_code "eq,ne")) 1150 1151;; Return 1 if OP is a comparison operation that is valid for a branch 1152;; instruction. We check the opcode against the mode of the CC value. 1153;; validate_condition_mode is an assertion. 1154(define_predicate "branch_comparison_operator" 1155 (and (match_operand 0 "comparison_operator") 1156 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") 1157 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode 1158 && !flag_finite_math_only") 1159 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered") 1160 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne")) 1161 (match_test "validate_condition_mode (GET_CODE (op), 1162 GET_MODE (XEXP (op, 0))), 1163 1"))) 1164 1165;; Return 1 if OP is a comparison that needs an extra instruction to do (a 1166;; crlogical or an extra branch). 1167(define_predicate "extra_insn_branch_comparison_operator" 1168 (and (match_operand 0 "comparison_operator") 1169 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode") 1170 (match_code "ltgt,le,ge,unlt,ungt,uneq") 1171 (match_test "validate_condition_mode (GET_CODE (op), 1172 GET_MODE (XEXP (op, 0))), 1173 1"))) 1174 1175;; Return 1 if OP is an unsigned comparison operator. 1176(define_predicate "unsigned_comparison_operator" 1177 (match_code "ltu,gtu,leu,geu")) 1178 1179;; Return 1 if OP is a signed comparison operator. 1180(define_predicate "signed_comparison_operator" 1181 (match_code "lt,gt,le,ge")) 1182 1183;; Return 1 if OP is a signed comparison or an equality operator. 1184(define_predicate "signed_or_equality_comparison_operator" 1185 (ior (match_operand 0 "equality_operator") 1186 (match_operand 0 "signed_comparison_operator"))) 1187 1188;; Return 1 if OP is an unsigned comparison or an equality operator. 1189(define_predicate "unsigned_or_equality_comparison_operator" 1190 (ior (match_operand 0 "equality_operator") 1191 (match_operand 0 "unsigned_comparison_operator"))) 1192 1193;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- 1194;; it must be a positive comparison. 1195(define_predicate "scc_comparison_operator" 1196 (and (match_operand 0 "branch_comparison_operator") 1197 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1198 1199;; Return 1 if OP is a comparison operation whose inverse would be valid for 1200;; an SCC insn. 1201(define_predicate "scc_rev_comparison_operator" 1202 (and (match_operand 0 "branch_comparison_operator") 1203 (match_code "ne,le,ge,leu,geu,ordered"))) 1204 1205;; Return 1 if OP is a comparison operator suitable for floating point 1206;; vector/scalar comparisons that generate a -1/0 mask. 1207(define_predicate "fpmask_comparison_operator" 1208 (match_code "eq,gt,ge")) 1209 1210;; Return 1 if OP is a comparison operator suitable for vector/scalar 1211;; comparisons that generate a 0/-1 mask (i.e. the inverse of 1212;; fpmask_comparison_operator). 1213(define_predicate "invert_fpmask_comparison_operator" 1214 (match_code "ne,unlt,unle")) 1215 1216;; Return 1 if OP is a comparison operation suitable for integer vector/scalar 1217;; comparisons that generate a -1/0 mask. 1218(define_predicate "vecint_comparison_operator" 1219 (match_code "eq,gt,gtu")) 1220 1221;; Return 1 if OP is a comparison operation that is valid for a branch 1222;; insn, which is true if the corresponding bit in the CC register is set. 1223(define_predicate "branch_positive_comparison_operator" 1224 (and (match_operand 0 "branch_comparison_operator") 1225 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 1226 1227;; Return 1 if OP is valid for a save_world call in prologue, known to be 1228;; a PARLLEL. 1229(define_predicate "save_world_operation" 1230 (match_code "parallel") 1231{ 1232 int index; 1233 int i; 1234 rtx elt; 1235 int count = XVECLEN (op, 0); 1236 1237 if (count != 54) 1238 return 0; 1239 1240 index = 0; 1241 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1242 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1243 return 0; 1244 1245 for (i=1; i <= 18; i++) 1246 { 1247 elt = XVECEXP (op, 0, index++); 1248 if (GET_CODE (elt) != SET 1249 || !MEM_P (SET_DEST (elt)) 1250 || !memory_operand (SET_DEST (elt), DFmode) 1251 || !REG_P (SET_SRC (elt)) 1252 || GET_MODE (SET_SRC (elt)) != DFmode) 1253 return 0; 1254 } 1255 1256 for (i=1; i <= 12; i++) 1257 { 1258 elt = XVECEXP (op, 0, index++); 1259 if (GET_CODE (elt) != SET 1260 || !MEM_P (SET_DEST (elt)) 1261 || !REG_P (SET_SRC (elt)) 1262 || GET_MODE (SET_SRC (elt)) != V4SImode) 1263 return 0; 1264 } 1265 1266 for (i=1; i <= 19; i++) 1267 { 1268 elt = XVECEXP (op, 0, index++); 1269 if (GET_CODE (elt) != SET 1270 || !MEM_P (SET_DEST (elt)) 1271 || !memory_operand (SET_DEST (elt), Pmode) 1272 || !REG_P (SET_SRC (elt)) 1273 || GET_MODE (SET_SRC (elt)) != Pmode) 1274 return 0; 1275 } 1276 1277 elt = XVECEXP (op, 0, index++); 1278 if (GET_CODE (elt) != SET 1279 || !MEM_P (SET_DEST (elt)) 1280 || !memory_operand (SET_DEST (elt), Pmode) 1281 || !REG_P (SET_SRC (elt)) 1282 || REGNO (SET_SRC (elt)) != CR2_REGNO 1283 || GET_MODE (SET_SRC (elt)) != Pmode) 1284 return 0; 1285 1286 if (GET_CODE (XVECEXP (op, 0, index++)) != SET 1287 || GET_CODE (XVECEXP (op, 0, index++)) != SET) 1288 return 0; 1289 return 1; 1290}) 1291 1292;; Return 1 if OP is valid for a restore_world call in epilogue, known to be 1293;; a PARLLEL. 1294(define_predicate "restore_world_operation" 1295 (match_code "parallel") 1296{ 1297 int index; 1298 int i; 1299 rtx elt; 1300 int count = XVECLEN (op, 0); 1301 1302 if (count != 58) 1303 return 0; 1304 1305 index = 0; 1306 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 1307 || GET_CODE (XVECEXP (op, 0, index++)) != USE 1308 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 1309 return 0; 1310 1311 elt = XVECEXP (op, 0, index++); 1312 if (GET_CODE (elt) != SET 1313 || !MEM_P (SET_SRC (elt)) 1314 || !memory_operand (SET_SRC (elt), Pmode) 1315 || !REG_P (SET_DEST (elt)) 1316 || REGNO (SET_DEST (elt)) != CR2_REGNO 1317 || GET_MODE (SET_DEST (elt)) != Pmode) 1318 return 0; 1319 1320 for (i=1; i <= 19; i++) 1321 { 1322 elt = XVECEXP (op, 0, index++); 1323 if (GET_CODE (elt) != SET 1324 || !MEM_P (SET_SRC (elt)) 1325 || !memory_operand (SET_SRC (elt), Pmode) 1326 || !REG_P (SET_DEST (elt)) 1327 || GET_MODE (SET_DEST (elt)) != Pmode) 1328 return 0; 1329 } 1330 1331 for (i=1; i <= 12; i++) 1332 { 1333 elt = XVECEXP (op, 0, index++); 1334 if (GET_CODE (elt) != SET 1335 || !MEM_P (SET_SRC (elt)) 1336 || !REG_P (SET_DEST (elt)) 1337 || GET_MODE (SET_DEST (elt)) != V4SImode) 1338 return 0; 1339 } 1340 1341 for (i=1; i <= 18; i++) 1342 { 1343 elt = XVECEXP (op, 0, index++); 1344 if (GET_CODE (elt) != SET 1345 || !MEM_P (SET_SRC (elt)) 1346 || !memory_operand (SET_SRC (elt), DFmode) 1347 || !REG_P (SET_DEST (elt)) 1348 || GET_MODE (SET_DEST (elt)) != DFmode) 1349 return 0; 1350 } 1351 1352 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1353 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1354 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1355 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1356 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1357 return 0; 1358 return 1; 1359}) 1360 1361;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. 1362(define_predicate "vrsave_operation" 1363 (match_code "parallel") 1364{ 1365 int count = XVECLEN (op, 0); 1366 unsigned int dest_regno, src_regno; 1367 int i; 1368 1369 if (count <= 1 1370 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1371 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) 1372 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE 1373 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) 1374 return 0; 1375 1376 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1377 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); 1378 1379 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) 1380 return 0; 1381 1382 for (i = 1; i < count; i++) 1383 { 1384 rtx elt = XVECEXP (op, 0, i); 1385 1386 if (GET_CODE (elt) != CLOBBER 1387 && GET_CODE (elt) != SET) 1388 return 0; 1389 } 1390 1391 return 1; 1392}) 1393 1394;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. 1395(define_predicate "mfcr_operation" 1396 (match_code "parallel") 1397{ 1398 int count = XVECLEN (op, 0); 1399 int i; 1400 1401 /* Perform a quick check so we don't blow up below. */ 1402 if (count < 1 1403 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1404 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1405 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1406 return 0; 1407 1408 for (i = 0; i < count; i++) 1409 { 1410 rtx exp = XVECEXP (op, 0, i); 1411 rtx unspec; 1412 int maskval; 1413 rtx src_reg; 1414 1415 src_reg = XVECEXP (SET_SRC (exp), 0, 0); 1416 1417 if (!REG_P (src_reg) 1418 || GET_MODE (src_reg) != CCmode 1419 || ! CR_REGNO_P (REGNO (src_reg))) 1420 return 0; 1421 1422 if (GET_CODE (exp) != SET 1423 || !REG_P (SET_DEST (exp)) 1424 || GET_MODE (SET_DEST (exp)) != SImode 1425 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) 1426 return 0; 1427 unspec = SET_SRC (exp); 1428 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); 1429 1430 if (GET_CODE (unspec) != UNSPEC 1431 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR 1432 || XVECLEN (unspec, 0) != 2 1433 || XVECEXP (unspec, 0, 0) != src_reg 1434 || !CONST_INT_P (XVECEXP (unspec, 0, 1)) 1435 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1436 return 0; 1437 } 1438 return 1; 1439}) 1440 1441;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. 1442(define_predicate "mtcrf_operation" 1443 (match_code "parallel") 1444{ 1445 int count = XVECLEN (op, 0); 1446 int i; 1447 rtx src_reg; 1448 1449 /* Perform a quick check so we don't blow up below. */ 1450 if (count < 1 1451 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1452 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1453 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1454 return 0; 1455 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); 1456 1457 if (!REG_P (src_reg) 1458 || GET_MODE (src_reg) != SImode 1459 || ! INT_REGNO_P (REGNO (src_reg))) 1460 return 0; 1461 1462 for (i = 0; i < count; i++) 1463 { 1464 rtx exp = XVECEXP (op, 0, i); 1465 rtx unspec; 1466 int maskval; 1467 1468 if (GET_CODE (exp) != SET 1469 || !REG_P (SET_DEST (exp)) 1470 || GET_MODE (SET_DEST (exp)) != CCmode 1471 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) 1472 return 0; 1473 unspec = SET_SRC (exp); 1474 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); 1475 1476 if (GET_CODE (unspec) != UNSPEC 1477 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR 1478 || XVECLEN (unspec, 0) != 2 1479 || XVECEXP (unspec, 0, 0) != src_reg 1480 || !CONST_INT_P (XVECEXP (unspec, 0, 1)) 1481 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1482 return 0; 1483 } 1484 return 1; 1485}) 1486 1487;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL. 1488(define_predicate "crsave_operation" 1489 (match_code "parallel") 1490{ 1491 int count = XVECLEN (op, 0); 1492 int i; 1493 1494 for (i = 1; i < count; i++) 1495 { 1496 rtx exp = XVECEXP (op, 0, i); 1497 1498 if (GET_CODE (exp) != USE 1499 || !REG_P (XEXP (exp, 0)) 1500 || GET_MODE (XEXP (exp, 0)) != CCmode 1501 || ! CR_REGNO_P (REGNO (XEXP (exp, 0)))) 1502 return 0; 1503 } 1504 return 1; 1505}) 1506 1507;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. 1508(define_predicate "lmw_operation" 1509 (match_code "parallel") 1510{ 1511 int count = XVECLEN (op, 0); 1512 unsigned int dest_regno; 1513 rtx src_addr; 1514 unsigned int base_regno; 1515 HOST_WIDE_INT offset; 1516 int i; 1517 1518 /* Perform a quick check so we don't blow up below. */ 1519 if (count <= 1 1520 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1521 || !REG_P (SET_DEST (XVECEXP (op, 0, 0))) 1522 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))) 1523 return 0; 1524 1525 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1526 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1527 1528 if (dest_regno > 31 1529 || count != 32 - (int) dest_regno) 1530 return 0; 1531 1532 if (legitimate_indirect_address_p (src_addr, 0)) 1533 { 1534 offset = 0; 1535 base_regno = REGNO (src_addr); 1536 if (base_regno == 0) 1537 return 0; 1538 } 1539 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false)) 1540 { 1541 offset = INTVAL (XEXP (src_addr, 1)); 1542 base_regno = REGNO (XEXP (src_addr, 0)); 1543 } 1544 else 1545 return 0; 1546 1547 for (i = 0; i < count; i++) 1548 { 1549 rtx elt = XVECEXP (op, 0, i); 1550 rtx newaddr; 1551 rtx addr_reg; 1552 HOST_WIDE_INT newoffset; 1553 1554 if (GET_CODE (elt) != SET 1555 || !REG_P (SET_DEST (elt)) 1556 || GET_MODE (SET_DEST (elt)) != SImode 1557 || REGNO (SET_DEST (elt)) != dest_regno + i 1558 || !MEM_P (SET_SRC (elt)) 1559 || GET_MODE (SET_SRC (elt)) != SImode) 1560 return 0; 1561 newaddr = XEXP (SET_SRC (elt), 0); 1562 if (legitimate_indirect_address_p (newaddr, 0)) 1563 { 1564 newoffset = 0; 1565 addr_reg = newaddr; 1566 } 1567 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1568 { 1569 addr_reg = XEXP (newaddr, 0); 1570 newoffset = INTVAL (XEXP (newaddr, 1)); 1571 } 1572 else 1573 return 0; 1574 if (REGNO (addr_reg) != base_regno 1575 || newoffset != offset + 4 * i) 1576 return 0; 1577 } 1578 1579 return 1; 1580}) 1581 1582;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. 1583(define_predicate "stmw_operation" 1584 (match_code "parallel") 1585{ 1586 int count = XVECLEN (op, 0); 1587 unsigned int src_regno; 1588 rtx dest_addr; 1589 unsigned int base_regno; 1590 HOST_WIDE_INT offset; 1591 int i; 1592 1593 /* Perform a quick check so we don't blow up below. */ 1594 if (count <= 1 1595 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1596 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0))) 1597 || !REG_P (SET_SRC (XVECEXP (op, 0, 0)))) 1598 return 0; 1599 1600 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1601 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1602 1603 if (src_regno > 31 1604 || count != 32 - (int) src_regno) 1605 return 0; 1606 1607 if (legitimate_indirect_address_p (dest_addr, 0)) 1608 { 1609 offset = 0; 1610 base_regno = REGNO (dest_addr); 1611 if (base_regno == 0) 1612 return 0; 1613 } 1614 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false)) 1615 { 1616 offset = INTVAL (XEXP (dest_addr, 1)); 1617 base_regno = REGNO (XEXP (dest_addr, 0)); 1618 } 1619 else 1620 return 0; 1621 1622 for (i = 0; i < count; i++) 1623 { 1624 rtx elt = XVECEXP (op, 0, i); 1625 rtx newaddr; 1626 rtx addr_reg; 1627 HOST_WIDE_INT newoffset; 1628 1629 if (GET_CODE (elt) != SET 1630 || !REG_P (SET_SRC (elt)) 1631 || GET_MODE (SET_SRC (elt)) != SImode 1632 || REGNO (SET_SRC (elt)) != src_regno + i 1633 || !MEM_P (SET_DEST (elt)) 1634 || GET_MODE (SET_DEST (elt)) != SImode) 1635 return 0; 1636 newaddr = XEXP (SET_DEST (elt), 0); 1637 if (legitimate_indirect_address_p (newaddr, 0)) 1638 { 1639 newoffset = 0; 1640 addr_reg = newaddr; 1641 } 1642 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false)) 1643 { 1644 addr_reg = XEXP (newaddr, 0); 1645 newoffset = INTVAL (XEXP (newaddr, 1)); 1646 } 1647 else 1648 return 0; 1649 if (REGNO (addr_reg) != base_regno 1650 || newoffset != offset + 4 * i) 1651 return 0; 1652 } 1653 1654 return 1; 1655}) 1656 1657;; Return 1 if OP is a stack tie operand. 1658(define_predicate "tie_operand" 1659 (match_code "parallel") 1660{ 1661 return (GET_CODE (XVECEXP (op, 0, 0)) == SET 1662 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0)) 1663 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode 1664 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx); 1665}) 1666 1667;; Match a small code model toc reference (or medium and large 1668;; model toc references before reload). 1669(define_predicate "small_toc_ref" 1670 (match_code "unspec,plus") 1671{ 1672 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode)) 1673 op = XEXP (op, 0); 1674 1675 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; 1676}) 1677 1678 1679;; Match the first insn (addis) in fusing the combination of addis and loads to 1680;; GPR registers on power8. 1681(define_predicate "fusion_gpr_addis" 1682 (match_code "const_int,high,plus") 1683{ 1684 HOST_WIDE_INT value; 1685 rtx int_const; 1686 1687 if (GET_CODE (op) == HIGH) 1688 return 1; 1689 1690 if (CONST_INT_P (op)) 1691 int_const = op; 1692 1693 else if (GET_CODE (op) == PLUS 1694 && base_reg_operand (XEXP (op, 0), Pmode) 1695 && CONST_INT_P (XEXP (op, 1))) 1696 int_const = XEXP (op, 1); 1697 1698 else 1699 return 0; 1700 1701 value = INTVAL (int_const); 1702 if ((value & (HOST_WIDE_INT)0xffff) != 0) 1703 return 0; 1704 1705 if ((value & (HOST_WIDE_INT)0xffff0000) == 0) 1706 return 0; 1707 1708 /* Power8 only does the fusion if the top 12 bits of the addis value are all 1709 1's or 0's. */ 1710 return (IN_RANGE (value >> 16, -16, 15)); 1711}) 1712 1713;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis 1714;; and loads to GPR registers on power8. 1715(define_predicate "fusion_gpr_mem_load" 1716 (match_code "mem,sign_extend,zero_extend") 1717{ 1718 rtx addr, base, offset; 1719 1720 /* Handle sign/zero extend. */ 1721 if (GET_CODE (op) == ZERO_EXTEND 1722 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND)) 1723 { 1724 op = XEXP (op, 0); 1725 mode = GET_MODE (op); 1726 } 1727 1728 if (!MEM_P (op)) 1729 return 0; 1730 1731 switch (mode) 1732 { 1733 case E_QImode: 1734 case E_HImode: 1735 case E_SImode: 1736 break; 1737 1738 case E_DImode: 1739 if (!TARGET_POWERPC64) 1740 return 0; 1741 break; 1742 1743 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they 1744 are not common. */ 1745 default: 1746 return 0; 1747 } 1748 1749 addr = XEXP (op, 0); 1750 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1751 return 0; 1752 1753 base = XEXP (addr, 0); 1754 if (!base_reg_operand (base, GET_MODE (base))) 1755 return 0; 1756 1757 offset = XEXP (addr, 1); 1758 1759 if (GET_CODE (addr) == PLUS) 1760 return satisfies_constraint_I (offset); 1761 1762 else if (GET_CODE (addr) == LO_SUM) 1763 { 1764 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1765 return small_toc_ref (offset, GET_MODE (offset)); 1766 1767 else if (TARGET_ELF && !TARGET_POWERPC64) 1768 return CONSTANT_P (offset); 1769 } 1770 1771 return 0; 1772}) 1773 1774;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the 1775;; memory field with both the addis and the memory offset. Sign extension 1776;; is not handled here, since lha and lwa are not fused. 1777(define_predicate "fusion_addis_mem_combo_load" 1778 (match_code "mem,zero_extend") 1779{ 1780 rtx addr, base, offset; 1781 1782 /* Handle zero extend. */ 1783 if (GET_CODE (op) == ZERO_EXTEND) 1784 { 1785 op = XEXP (op, 0); 1786 mode = GET_MODE (op); 1787 } 1788 1789 if (!MEM_P (op)) 1790 return 0; 1791 1792 switch (mode) 1793 { 1794 case E_QImode: 1795 case E_HImode: 1796 case E_SImode: 1797 break; 1798 1799 /* Do not fuse 64-bit DImode in 32-bit since it splits into two 1800 separate instructions. */ 1801 case E_DImode: 1802 if (!TARGET_POWERPC64) 1803 return 0; 1804 break; 1805 1806 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they 1807 are not common. */ 1808 default: 1809 return 0; 1810 } 1811 1812 addr = XEXP (op, 0); 1813 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) 1814 return 0; 1815 1816 base = XEXP (addr, 0); 1817 if (!fusion_gpr_addis (base, GET_MODE (base))) 1818 return 0; 1819 1820 offset = XEXP (addr, 1); 1821 if (GET_CODE (addr) == PLUS) 1822 return satisfies_constraint_I (offset); 1823 1824 else if (GET_CODE (addr) == LO_SUM) 1825 { 1826 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64)) 1827 return small_toc_ref (offset, GET_MODE (offset)); 1828 1829 else if (TARGET_ELF && !TARGET_POWERPC64) 1830 return CONSTANT_P (offset); 1831 } 1832 1833 return 0; 1834}) 1835 1836 1837;; Return true if the operand is a PC-relative address of a local symbol or a 1838;; label that can be used directly in a memory operation. 1839(define_predicate "pcrel_local_address" 1840 (match_code "label_ref,symbol_ref,const") 1841{ 1842 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); 1843 return iform == INSN_FORM_PCREL_LOCAL; 1844}) 1845 1846;; Return true if the operand is a PC-relative external symbol whose address 1847;; can be loaded into a register. 1848(define_predicate "pcrel_external_address" 1849 (match_code "symbol_ref,const") 1850{ 1851 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT); 1852 return iform == INSN_FORM_PCREL_EXTERNAL; 1853}) 1854 1855;; Return true if the address is PC-relative and the symbol is either local or 1856;; external. 1857(define_predicate "pcrel_local_or_external_address" 1858 (ior (match_operand 0 "pcrel_local_address") 1859 (match_operand 0 "pcrel_external_address"))) 1860 1861;; Return true if the operand is a memory address that uses a prefixed address. 1862(define_predicate "prefixed_memory" 1863 (match_code "mem") 1864{ 1865 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT); 1866}) 1867 1868;; Return true if the operand is a valid Mach-O pic address. 1869;; 1870(define_predicate "macho_pic_address" 1871 (match_code "const,unspec") 1872{ 1873 if (GET_CODE (op) == CONST) 1874 op = XEXP (op, 0); 1875 1876 if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_MACHOPIC_OFFSET) 1877 return CONSTANT_P (XVECEXP (op, 0, 0)); 1878 else 1879 return false; 1880}) 1881