1;; Scheduling description for IBM POWER8 processor. 2;; Copyright (C) 2013-2020 Free Software Foundation, Inc. 3;; 4;; Contributed by Pat Haugen (pthaugen@us.ibm.com). 5 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22(define_automaton "power8fxu,power8lsu,power8vsu,power8misc") 23 24(define_cpu_unit "fxu0_power8,fxu1_power8" "power8fxu") 25(define_cpu_unit "lu0_power8,lu1_power8" "power8lsu") 26(define_cpu_unit "lsu0_power8,lsu1_power8" "power8lsu") 27(define_cpu_unit "vsu0_power8,vsu1_power8" "power8vsu") 28(define_cpu_unit "bpu_power8,cru_power8" "power8misc") 29(define_cpu_unit "du0_power8,du1_power8,du2_power8,du3_power8,du4_power8,\ 30 du5_power8,du6_power8" "power8misc") 31 32 33; Dispatch group reservations 34(define_reservation "DU_any_power8" 35 "du0_power8|du1_power8|du2_power8|du3_power8|du4_power8|\ 36 du5_power8") 37 38; 2-way Cracked instructions go in slots 0-1 39; (can also have a second in slots 3-4 if insns are adjacent) 40(define_reservation "DU_cracked_power8" 41 "du0_power8+du1_power8") 42 43; Insns that are first in group 44(define_reservation "DU_first_power8" 45 "du0_power8") 46 47; Insns that are first and last in group 48(define_reservation "DU_both_power8" 49 "du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+\ 50 du5_power8+du6_power8") 51 52; Dispatch slots are allocated in order conforming to program order. 53(absence_set "du0_power8" "du1_power8,du2_power8,du3_power8,du4_power8,\ 54 du5_power8,du6_power8") 55(absence_set "du1_power8" "du2_power8,du3_power8,du4_power8,du5_power8,\ 56 du6_power8") 57(absence_set "du2_power8" "du3_power8,du4_power8,du5_power8,du6_power8") 58(absence_set "du3_power8" "du4_power8,du5_power8,du6_power8") 59(absence_set "du4_power8" "du5_power8,du6_power8") 60(absence_set "du5_power8" "du6_power8") 61 62 63; Execution unit reservations 64(define_reservation "FXU_power8" 65 "fxu0_power8|fxu1_power8") 66 67(define_reservation "LU_power8" 68 "lu0_power8|lu1_power8") 69 70(define_reservation "LSU_power8" 71 "lsu0_power8|lsu1_power8") 72 73(define_reservation "LU_or_LSU_power8" 74 "lu0_power8|lu1_power8|lsu0_power8|lsu1_power8") 75 76(define_reservation "VSU_power8" 77 "vsu0_power8|vsu1_power8") 78 79 80; LS Unit 81(define_insn_reservation "power8-load" 3 82 (and (eq_attr "type" "load") 83 (eq_attr "sign_extend" "no") 84 (eq_attr "update" "no") 85 (eq_attr "cpu" "power8")) 86 "DU_any_power8,LU_or_LSU_power8") 87 88(define_insn_reservation "power8-load-update" 3 89 (and (eq_attr "type" "load") 90 (eq_attr "sign_extend" "no") 91 (eq_attr "update" "yes") 92 (eq_attr "cpu" "power8")) 93 "DU_cracked_power8,LU_or_LSU_power8+FXU_power8") 94 95(define_insn_reservation "power8-load-ext" 3 96 (and (eq_attr "type" "load") 97 (eq_attr "sign_extend" "yes") 98 (eq_attr "update" "no") 99 (eq_attr "cpu" "power8")) 100 "DU_cracked_power8,LU_or_LSU_power8,FXU_power8") 101 102(define_insn_reservation "power8-load-ext-update" 3 103 (and (eq_attr "type" "load") 104 (eq_attr "sign_extend" "yes") 105 (eq_attr "update" "yes") 106 (eq_attr "cpu" "power8")) 107 "DU_both_power8,LU_or_LSU_power8+FXU_power8,FXU_power8") 108 109(define_insn_reservation "power8-fpload" 5 110 (and (ior (eq_attr "type" "vecload") 111 (and (eq_attr "type" "fpload") 112 (eq_attr "update" "no"))) 113 (eq_attr "cpu" "power8")) 114 "DU_any_power8,LU_power8") 115 116(define_insn_reservation "power8-fpload-update" 5 117 (and (eq_attr "type" "fpload") 118 (eq_attr "update" "yes") 119 (eq_attr "cpu" "power8")) 120 "DU_cracked_power8,LU_power8+FXU_power8") 121 122(define_insn_reservation "power8-store" 5 ; store-forwarding latency 123 (and (eq_attr "type" "store") 124 (not (and (eq_attr "update" "yes") 125 (eq_attr "indexed" "yes"))) 126 (eq_attr "cpu" "power8")) 127 "DU_any_power8,LSU_power8+LU_power8") 128 129(define_insn_reservation "power8-store-update-indexed" 5 130 (and (eq_attr "type" "store") 131 (eq_attr "update" "yes") 132 (eq_attr "indexed" "yes") 133 (eq_attr "cpu" "power8")) 134 "DU_cracked_power8,LSU_power8+LU_power8") 135 136(define_insn_reservation "power8-fpstore" 5 137 (and (eq_attr "type" "fpstore") 138 (eq_attr "update" "no") 139 (eq_attr "cpu" "power8")) 140 "DU_any_power8,LSU_power8+VSU_power8") 141 142(define_insn_reservation "power8-fpstore-update" 5 143 (and (eq_attr "type" "fpstore") 144 (eq_attr "update" "yes") 145 (eq_attr "cpu" "power8")) 146 "DU_any_power8,LSU_power8+VSU_power8") 147 148(define_insn_reservation "power8-vecstore" 5 149 (and (eq_attr "type" "vecstore") 150 (eq_attr "cpu" "power8")) 151 "DU_cracked_power8,LSU_power8+VSU_power8") 152 153(define_insn_reservation "power8-larx" 3 154 (and (eq_attr "type" "load_l") 155 (eq_attr "cpu" "power8")) 156 "DU_both_power8,LU_or_LSU_power8") 157 158(define_insn_reservation "power8-stcx" 10 159 (and (eq_attr "type" "store_c") 160 (eq_attr "cpu" "power8")) 161 "DU_both_power8,LSU_power8+LU_power8") 162 163(define_insn_reservation "power8-sync" 1 164 (and (eq_attr "type" "sync,isync") 165 (eq_attr "cpu" "power8")) 166 "DU_both_power8,LSU_power8") 167 168 169; FX Unit 170(define_insn_reservation "power8-1cyc" 1 171 (and (ior (eq_attr "type" "integer,insert,trap,isel") 172 (and (eq_attr "type" "add,logical,shift,exts") 173 (eq_attr "dot" "no"))) 174 (eq_attr "cpu" "power8")) 175 "DU_any_power8,FXU_power8") 176 177; Extra cycle to LU/LSU 178(define_bypass 2 "power8-1cyc" 179 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 180 power8-vecstore,power8-larx,power8-stcx") 181; "power8-load,power8-load-update,power8-load-ext,\ 182; power8-load-ext-update,power8-fpload,power8-fpload-update,\ 183; power8-store,power8-store-update,power8-store-update-indexed,\ 184; power8-fpstore,power8-fpstore-update,power8-vecstore,\ 185; power8-larx,power8-stcx") 186 187(define_insn_reservation "power8-2cyc" 2 188 (and (eq_attr "type" "cntlz,popcnt") 189 (eq_attr "cpu" "power8")) 190 "DU_any_power8,FXU_power8") 191 192(define_insn_reservation "power8-two" 2 193 (and (eq_attr "type" "two") 194 (eq_attr "cpu" "power8")) 195 "DU_any_power8+DU_any_power8,FXU_power8,FXU_power8") 196 197(define_insn_reservation "power8-three" 3 198 (and (eq_attr "type" "three") 199 (eq_attr "cpu" "power8")) 200 "DU_any_power8+DU_any_power8+DU_any_power8,FXU_power8,FXU_power8,FXU_power8") 201 202; cmp - Normal compare insns 203(define_insn_reservation "power8-cmp" 2 204 (and (eq_attr "type" "cmp") 205 (eq_attr "cpu" "power8")) 206 "DU_any_power8,FXU_power8") 207 208; add/logical with dot : add./and./nor./etc 209(define_insn_reservation "power8-fast-compare" 2 210 (and (eq_attr "type" "add,logical") 211 (eq_attr "dot" "yes") 212 (eq_attr "cpu" "power8")) 213 "DU_any_power8,FXU_power8") 214 215; exts/shift with dot : rldicl./exts./rlwinm./slwi./rlwnm./slw./etc 216(define_insn_reservation "power8-compare" 2 217 (and (eq_attr "type" "shift,exts") 218 (eq_attr "dot" "yes") 219 (eq_attr "cpu" "power8")) 220 "DU_cracked_power8,FXU_power8,FXU_power8") 221 222; Extra cycle to LU/LSU 223(define_bypass 3 "power8-fast-compare,power8-compare" 224 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 225 power8-vecstore,power8-larx,power8-stcx") 226 227; 5 cycle CR latency 228(define_bypass 5 "power8-fast-compare,power8-compare" 229 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") 230 231(define_insn_reservation "power8-mul" 4 232 (and (eq_attr "type" "mul") 233 (eq_attr "dot" "no") 234 (eq_attr "cpu" "power8")) 235 "DU_any_power8,FXU_power8") 236 237(define_insn_reservation "power8-mul-compare" 4 238 (and (eq_attr "type" "mul") 239 (eq_attr "dot" "yes") 240 (eq_attr "cpu" "power8")) 241 "DU_cracked_power8,FXU_power8") 242 243; Extra cycle to LU/LSU 244(define_bypass 5 "power8-mul,power8-mul-compare" 245 "power8-load*,power8-fpload*,power8-store*,power8-fpstore*,\ 246 power8-vecstore,power8-larx,power8-stcx") 247 248; 7 cycle CR latency 249(define_bypass 7 "power8-mul,power8-mul-compare" 250 "power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch") 251 252; FXU divides are not pipelined 253(define_insn_reservation "power8-idiv" 37 254 (and (eq_attr "type" "div") 255 (eq_attr "size" "32") 256 (eq_attr "cpu" "power8")) 257 "DU_any_power8,fxu0_power8*37|fxu1_power8*37") 258 259(define_insn_reservation "power8-ldiv" 68 260 (and (eq_attr "type" "div") 261 (eq_attr "size" "64") 262 (eq_attr "cpu" "power8")) 263 "DU_any_power8,fxu0_power8*68|fxu1_power8*68") 264 265(define_insn_reservation "power8-mtjmpr" 5 266 (and (eq_attr "type" "mtjmpr") 267 (eq_attr "cpu" "power8")) 268 "DU_first_power8,FXU_power8") 269 270; Should differentiate between 1 cr field and > 1 since mtocrf is not microcode 271(define_insn_reservation "power8-mtcr" 3 272 (and (eq_attr "type" "mtcr") 273 (eq_attr "cpu" "power8")) 274 "DU_both_power8,FXU_power8") 275 276 277; CR Unit 278(define_insn_reservation "power8-mfjmpr" 5 279 (and (eq_attr "type" "mfjmpr") 280 (eq_attr "cpu" "power8")) 281 "DU_first_power8,cru_power8+FXU_power8") 282 283(define_insn_reservation "power8-crlogical" 3 284 (and (eq_attr "type" "cr_logical") 285 (eq_attr "cpu" "power8")) 286 "DU_first_power8,cru_power8") 287 288(define_insn_reservation "power8-mfcr" 5 289 (and (eq_attr "type" "mfcr") 290 (eq_attr "cpu" "power8")) 291 "DU_both_power8,cru_power8") 292 293(define_insn_reservation "power8-mfcrf" 3 294 (and (eq_attr "type" "mfcrf") 295 (eq_attr "cpu" "power8")) 296 "DU_first_power8,cru_power8") 297 298 299; BR Unit 300; Branches take dispatch slot 7, but reserve any remaining prior slots to 301; prevent other insns from grabbing them once this is assigned. 302(define_insn_reservation "power8-branch" 3 303 (and (eq_attr "type" "jmpreg,branch") 304 (eq_attr "cpu" "power8")) 305 "(du6_power8\ 306 |du5_power8+du6_power8\ 307 |du4_power8+du5_power8+du6_power8\ 308 |du3_power8+du4_power8+du5_power8+du6_power8\ 309 |du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ 310 |du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+du6_power8\ 311 |du0_power8+du1_power8+du2_power8+du3_power8+du4_power8+du5_power8+\ 312 du6_power8),bpu_power8") 313 314; Branch updating LR/CTR feeding mf[lr|ctr] 315(define_bypass 4 "power8-branch" "power8-mfjmpr") 316 317 318; VS Unit (includes FP/VSX/VMX/DFP/Crypto) 319(define_insn_reservation "power8-fp" 6 320 (and (eq_attr "type" "fp,fpsimple,dmul,dfp") 321 (eq_attr "cpu" "power8")) 322 "DU_any_power8,VSU_power8") 323 324; Additional 3 cycles for any CR result 325(define_bypass 9 "power8-fp" "power8-crlogical,power8-mfcr*,power8-branch") 326 327(define_insn_reservation "power8-fpcompare" 8 328 (and (eq_attr "type" "fpcompare") 329 (eq_attr "cpu" "power8")) 330 "DU_any_power8,VSU_power8") 331 332(define_insn_reservation "power8-sdiv" 27 333 (and (eq_attr "type" "sdiv") 334 (eq_attr "cpu" "power8")) 335 "DU_any_power8,VSU_power8") 336 337(define_insn_reservation "power8-ddiv" 33 338 (and (eq_attr "type" "ddiv") 339 (eq_attr "cpu" "power8")) 340 "DU_any_power8,VSU_power8") 341 342(define_insn_reservation "power8-sqrt" 32 343 (and (eq_attr "type" "ssqrt") 344 (eq_attr "cpu" "power8")) 345 "DU_any_power8,VSU_power8") 346 347(define_insn_reservation "power8-dsqrt" 44 348 (and (eq_attr "type" "dsqrt") 349 (eq_attr "cpu" "power8")) 350 "DU_any_power8,VSU_power8") 351 352(define_insn_reservation "power8-vecsimple" 2 353 (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp, 354 veccmpfx") 355 (eq_attr "cpu" "power8")) 356 "DU_any_power8,VSU_power8") 357 358(define_insn_reservation "power8-vecnormal" 6 359 (and (eq_attr "type" "vecfloat,vecdouble") 360 (eq_attr "cpu" "power8")) 361 "DU_any_power8,VSU_power8") 362 363(define_bypass 7 "power8-vecnormal" 364 "power8-vecsimple,power8-veccomplex,power8-fpstore*,\ 365 power8-vecstore") 366 367(define_insn_reservation "power8-veccomplex" 7 368 (and (eq_attr "type" "veccomplex") 369 (eq_attr "cpu" "power8")) 370 "DU_any_power8,VSU_power8") 371 372(define_insn_reservation "power8-vecfdiv" 25 373 (and (eq_attr "type" "vecfdiv") 374 (eq_attr "cpu" "power8")) 375 "DU_any_power8,VSU_power8") 376 377(define_insn_reservation "power8-vecdiv" 31 378 (and (eq_attr "type" "vecdiv") 379 (eq_attr "cpu" "power8")) 380 "DU_any_power8,VSU_power8") 381 382(define_insn_reservation "power8-mffgpr" 5 383 (and (eq_attr "type" "mffgpr") 384 (eq_attr "cpu" "power8")) 385 "DU_any_power8,VSU_power8") 386 387(define_insn_reservation "power8-mftgpr" 6 388 (and (eq_attr "type" "mftgpr") 389 (eq_attr "cpu" "power8")) 390 "DU_any_power8,VSU_power8") 391 392(define_insn_reservation "power8-crypto" 7 393 (and (eq_attr "type" "crypto") 394 (eq_attr "cpu" "power8")) 395 "DU_any_power8,VSU_power8") 396 397