1;; Scheduling description for IBM POWER6 processor.
2;;   Copyright (C) 2006-2020 Free Software Foundation, Inc.
3;;   Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; Sources:
22
23;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine 
24;; (2 engines per chip).  The chip can issue up to 5 internal ops 
25;; per cycle.
26
27(define_automaton "power6iu,power6lsu,power6fpu,power6bu")
28
29(define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
30(define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
31(define_cpu_unit "bpu_power6" "power6bu")
32(define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
33
34(define_reservation "LS2_power6"
35                    "lsu1_power6+lsu2_power6")
36
37(define_reservation "FPU_power6"
38                    "fpu1_power6|fpu2_power6")
39
40(define_reservation "BRU_power6"
41                    "bpu_power6")
42
43(define_reservation "LSU_power6"
44                    "lsu1_power6|lsu2_power6")
45
46(define_reservation "LSF_power6"
47                    "(lsu1_power6+fpu1_power6)\
48                    |(lsu1_power6+fpu2_power6)\
49                    |(lsu2_power6+fpu1_power6)\
50                    |(lsu2_power6+fpu2_power6)")
51
52(define_reservation "LX2_power6"
53                    "(iu1_power6+iu2_power6+lsu1_power6)\
54                    |(iu1_power6+iu2_power6+lsu2_power6)")
55
56(define_reservation "FX2_power6"
57                    "iu1_power6+iu2_power6")
58
59(define_reservation "X2F_power6"
60                    "(iu1_power6+iu2_power6+fpu1_power6)\
61                    |(iu1_power6+iu2_power6+fpu2_power6)")
62
63(define_reservation "BX2_power6"
64                    "iu1_power6+iu2_power6+bpu_power6")
65
66(define_reservation "LSX_power6"
67                    "(iu1_power6+lsu1_power6)\
68                    |(iu1_power6+lsu2_power6)\
69                    |(iu2_power6+lsu1_power6)\
70                    |(iu2_power6+lsu2_power6)")
71
72(define_reservation "FXU_power6"
73                    "iu1_power6|iu2_power6")
74
75(define_reservation "XLF_power6"
76                    "(iu1_power6+lsu1_power6+fpu1_power6)\
77                    |(iu1_power6+lsu1_power6+fpu2_power6)\
78                    |(iu1_power6+lsu2_power6+fpu1_power6)\
79                    |(iu1_power6+lsu2_power6+fpu2_power6)\
80                    |(iu2_power6+lsu1_power6+fpu1_power6)\
81                    |(iu2_power6+lsu1_power6+fpu2_power6)\
82                    |(iu2_power6+lsu2_power6+fpu1_power6)\
83                    |(iu2_power6+lsu2_power6+fpu2_power6)")
84
85(define_reservation "BRX_power6"
86                    "(bpu_power6+iu1_power6)\
87                    |(bpu_power6+iu2_power6)")
88
89; Load/store
90
91; The default for a value written by a fixed point load
92; that is read/written by a subsequent fixed point op.
93(define_insn_reservation "power6-load" 2 ; fx
94  (and (eq_attr "type" "load")
95       (eq_attr "sign_extend" "no")
96       (eq_attr "update" "no")
97       (eq_attr "cpu" "power6"))
98  "LSU_power6")
99
100; define the bypass for the case where the value written
101; by a fixed point load is used as the source value on
102; a store.
103(define_bypass 1 "power6-load,\
104                  power6-load-update,\
105                  power6-load-update-indexed"
106                 "power6-store,\
107                  power6-store-update,\
108                  power6-store-update-indexed,\
109                  power6-fpstore,\
110                  power6-fpstore-update"
111  "rs6000_store_data_bypass_p")
112
113(define_insn_reservation "power6-load-ext" 4 ; fx
114  (and (eq_attr "type" "load")
115       (eq_attr "sign_extend" "yes")
116       (eq_attr "update" "no")
117       (eq_attr "cpu" "power6"))
118  "LSU_power6")
119
120; define the bypass for the case where the value written
121; by a fixed point load ext is used as the source value on
122; a store.
123(define_bypass 1 "power6-load-ext,\
124                  power6-load-ext-update,\
125	          power6-load-ext-update-indexed"
126                 "power6-store,\
127                  power6-store-update,\
128                  power6-store-update-indexed,\
129                  power6-fpstore,\
130                  power6-fpstore-update"
131  "rs6000_store_data_bypass_p")
132
133(define_insn_reservation "power6-load-update" 2 ; fx
134  (and (eq_attr "type" "load")
135       (eq_attr "sign_extend" "no")
136       (eq_attr "update" "yes")
137       (eq_attr "indexed" "no")
138       (eq_attr "cpu" "power6"))
139  "LSX_power6")
140
141(define_insn_reservation "power6-load-update-indexed" 2 ; fx
142  (and (eq_attr "type" "load")
143       (eq_attr "sign_extend" "no")
144       (eq_attr "update" "yes")
145       (eq_attr "indexed" "yes")
146       (eq_attr "cpu" "power6"))
147  "LSX_power6")
148
149(define_insn_reservation "power6-load-ext-update" 4 ; fx
150  (and (eq_attr "type" "load")
151       (eq_attr "sign_extend" "yes")
152       (eq_attr "update" "yes")
153       (eq_attr "indexed" "no")
154       (eq_attr "cpu" "power6"))
155  "LSX_power6")
156
157(define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
158  (and (eq_attr "type" "load")
159       (eq_attr "sign_extend" "yes")
160       (eq_attr "update" "yes")
161       (eq_attr "indexed" "yes")
162       (eq_attr "cpu" "power6"))
163  "LSX_power6")
164
165(define_insn_reservation "power6-fpload" 1
166  (and (eq_attr "type" "fpload")
167       (eq_attr "update" "no")
168       (eq_attr "cpu" "power6"))
169  "LSU_power6")
170
171(define_insn_reservation "power6-fpload-update" 1
172  (and (eq_attr "type" "fpload")
173       (eq_attr "update" "yes")
174       (eq_attr "cpu" "power6"))
175  "LSX_power6")
176
177(define_insn_reservation "power6-store" 14
178  (and (eq_attr "type" "store")
179       (eq_attr "update" "no")
180       (eq_attr "cpu" "power6"))
181  "LSU_power6")
182
183(define_insn_reservation "power6-store-update" 14
184  (and (eq_attr "type" "store")
185       (eq_attr "update" "yes")
186       (eq_attr "indexed" "no")
187       (eq_attr "cpu" "power6"))
188  "LSX_power6")
189
190(define_insn_reservation "power6-store-update-indexed" 14
191  (and (eq_attr "type" "store")
192       (eq_attr "update" "yes")
193       (eq_attr "indexed" "yes")
194       (eq_attr "cpu" "power6"))
195  "LX2_power6")
196
197(define_insn_reservation "power6-fpstore" 14
198  (and (eq_attr "type" "fpstore")
199       (eq_attr "update" "no")
200       (eq_attr "cpu" "power6"))
201  "LSF_power6")
202
203(define_insn_reservation "power6-fpstore-update" 14
204  (and (eq_attr "type" "fpstore")
205       (eq_attr "update" "yes")
206       (eq_attr "cpu" "power6"))
207  "XLF_power6")
208
209(define_insn_reservation "power6-larx" 3
210  (and (eq_attr "type" "load_l")
211       (eq_attr "cpu" "power6"))
212  "LS2_power6")
213
214(define_insn_reservation "power6-stcx" 10 ; best case
215  (and (eq_attr "type" "store_c")
216       (eq_attr "cpu" "power6"))
217  "LSX_power6")
218
219(define_insn_reservation "power6-sync" 11 ; N/A
220  (and (eq_attr "type" "sync")
221       (eq_attr "cpu" "power6"))
222  "LSU_power6")
223
224(define_insn_reservation "power6-integer" 1
225  (and (ior (eq_attr "type" "integer")
226	    (and (eq_attr "type" "add,logical")
227		 (eq_attr "dot" "no")))
228       (eq_attr "cpu" "power6"))
229  "FXU_power6")
230
231(define_insn_reservation "power6-isel" 1
232  (and (eq_attr "type" "isel")
233       (eq_attr "cpu" "power6"))
234  "FXU_power6")
235
236(define_insn_reservation "power6-exts" 1
237  (and (eq_attr "type" "exts")
238       (eq_attr "dot" "no")
239       (eq_attr "cpu" "power6"))
240  "FXU_power6")
241
242(define_insn_reservation "power6-shift" 1
243  (and (eq_attr "type" "shift")
244       (eq_attr "var_shift" "no")
245       (eq_attr "dot" "no")
246       (eq_attr "cpu" "power6"))
247  "FXU_power6")
248
249(define_insn_reservation "power6-popcnt" 1
250  (and (eq_attr "type" "popcnt")
251       (eq_attr "cpu" "power6"))
252  "FXU_power6")
253
254(define_insn_reservation "power6-insert" 1
255  (and (eq_attr "type" "insert")
256       (eq_attr "size" "32")
257       (eq_attr "cpu" "power6"))
258  "FX2_power6")
259
260(define_insn_reservation "power6-insert-dword" 1
261  (and (eq_attr "type" "insert")
262       (eq_attr "size" "64")
263       (eq_attr "cpu" "power6"))
264  "FX2_power6")
265
266; define the bypass for the case where the value written
267; by a fixed point op is used as the source value on a
268; store.
269(define_bypass 1 "power6-integer,\
270                  power6-exts,\
271                  power6-shift,\
272                  power6-insert,\
273                  power6-insert-dword"
274                 "power6-store,\
275                  power6-store-update,\
276                  power6-store-update-indexed,\
277                  power6-fpstore,\
278                  power6-fpstore-update"
279  "rs6000_store_data_bypass_p")
280
281(define_insn_reservation "power6-cntlz" 2
282  (and (eq_attr "type" "cntlz")
283       (eq_attr "cpu" "power6"))
284  "FXU_power6")
285
286(define_bypass 1 "power6-cntlz"
287                 "power6-store,\
288                  power6-store-update,\
289                  power6-store-update-indexed,\
290                  power6-fpstore,\
291                  power6-fpstore-update"
292  "rs6000_store_data_bypass_p")
293
294(define_insn_reservation "power6-var-rotate" 4
295  (and (eq_attr "type" "shift")
296       (eq_attr "var_shift" "yes")
297       (eq_attr "dot" "no")
298       (eq_attr "cpu" "power6"))
299  "FXU_power6")
300
301(define_insn_reservation "power6-trap" 1 ; N/A
302  (and (eq_attr "type" "trap")
303       (eq_attr "cpu" "power6"))
304  "BRX_power6")
305
306(define_insn_reservation "power6-two" 1
307  (and (eq_attr "type" "two")
308       (eq_attr "cpu" "power6"))
309  "(iu1_power6,iu1_power6)\
310  |(iu1_power6+iu2_power6,nothing)\
311  |(iu1_power6,iu2_power6)\
312  |(iu2_power6,iu1_power6)\
313  |(iu2_power6,iu2_power6)")
314
315(define_insn_reservation "power6-three" 1
316  (and (eq_attr "type" "three")
317       (eq_attr "cpu" "power6"))
318  "(iu1_power6,iu1_power6,iu1_power6)\
319  |(iu1_power6,iu1_power6,iu2_power6)\
320  |(iu1_power6,iu2_power6,iu1_power6)\
321  |(iu1_power6,iu2_power6,iu2_power6)\
322  |(iu2_power6,iu1_power6,iu1_power6)\
323  |(iu2_power6,iu1_power6,iu2_power6)\
324  |(iu2_power6,iu2_power6,iu1_power6)\
325  |(iu2_power6,iu2_power6,iu2_power6)\
326  |(iu1_power6+iu2_power6,iu1_power6)\
327  |(iu1_power6+iu2_power6,iu2_power6)\
328  |(iu1_power6,iu1_power6+iu2_power6)\
329  |(iu2_power6,iu1_power6+iu2_power6)")
330
331(define_insn_reservation "power6-cmp" 1
332  (and (eq_attr "type" "cmp")
333       (eq_attr "cpu" "power6"))
334  "FXU_power6")
335
336(define_insn_reservation "power6-compare" 1
337  (and (eq_attr "type" "exts")
338       (eq_attr "dot" "yes")
339       (eq_attr "cpu" "power6"))
340  "FXU_power6")
341
342(define_insn_reservation "power6-fast-compare" 1
343  (and (eq_attr "type" "add,logical")
344       (eq_attr "dot" "yes")
345       (eq_attr "cpu" "power6"))
346  "FXU_power6")
347
348; define the bypass for the case where the value written
349; by a fixed point rec form op is used as the source value
350; on a store.
351(define_bypass 1 "power6-compare,\
352                  power6-fast-compare"
353                 "power6-store,\
354                  power6-store-update,\
355                  power6-store-update-indexed,\
356                  power6-fpstore,\
357                  power6-fpstore-update"
358  "rs6000_store_data_bypass_p")
359
360(define_insn_reservation "power6-delayed-compare" 2 ; N/A
361  (and (eq_attr "type" "shift")
362       (eq_attr "var_shift" "no")
363       (eq_attr "dot" "yes")
364       (eq_attr "cpu" "power6"))
365  "FXU_power6")
366
367(define_insn_reservation "power6-var-delayed-compare" 4
368  (and (eq_attr "type" "shift")
369       (eq_attr "var_shift" "yes")
370       (eq_attr "dot" "yes")
371       (eq_attr "cpu" "power6"))
372  "FXU_power6")
373
374(define_insn_reservation "power6-lmul-cmp" 16
375  (and (eq_attr "type" "mul")
376       (eq_attr "dot" "yes")
377       (eq_attr "size" "64")
378       (eq_attr "cpu" "power6"))
379  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
380  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
381
382(define_insn_reservation "power6-imul-cmp" 16
383  (and (eq_attr "type" "mul")
384       (eq_attr "dot" "yes")
385       (eq_attr "size" "32")
386       (eq_attr "cpu" "power6"))
387  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
388  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
389
390(define_insn_reservation "power6-lmul" 16
391  (and (eq_attr "type" "mul")
392       (eq_attr "dot" "no")
393       (eq_attr "size" "64")
394       (eq_attr "cpu" "power6"))
395  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
396  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
397
398(define_insn_reservation "power6-imul" 16
399  (and (eq_attr "type" "mul")
400       (eq_attr "dot" "no")
401       (eq_attr "size" "32")
402       (eq_attr "cpu" "power6"))
403  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
404  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
405
406(define_insn_reservation "power6-imul3" 16
407  (and (eq_attr "type" "mul")
408       (eq_attr "size" "8,16")
409       (eq_attr "cpu" "power6"))
410  "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
411  |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
412
413(define_bypass 9 "power6-imul,\
414                  power6-lmul,\
415                  power6-imul-cmp,\
416                  power6-lmul-cmp,\
417                  power6-imul3"
418                 "power6-store,\
419                  power6-store-update,\
420                  power6-store-update-indexed,\
421                  power6-fpstore,\
422                  power6-fpstore-update"
423  "rs6000_store_data_bypass_p")
424
425(define_insn_reservation "power6-idiv" 44
426  (and (eq_attr "type" "div")
427       (eq_attr "size" "32")
428       (eq_attr "cpu" "power6"))
429  "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
430  |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
431
432; The latency for this bypass is yet to be defined
433;(define_bypass ? "power6-idiv"
434;                 "power6-store,\
435;                  power6-store-update,\
436;                  power6-store-update-indexed,\
437;                  power6-fpstore,\
438;                  power6-fpstore-update"
439;  "rs6000_store_data_bypass_p")
440
441(define_insn_reservation "power6-ldiv" 56
442  (and (eq_attr "type" "div")
443       (eq_attr "size" "64")
444       (eq_attr "cpu" "power6"))
445  "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
446  |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
447
448; The latency for this bypass is yet to be defined
449;(define_bypass ? "power6-ldiv"
450;                 "power6-store,\
451;                  power6-store-update,\
452;                  power6-store-update-indexed,\
453;                  power6-fpstore,\
454;                  power6-fpstore-update"
455;  "rs6000_store_data_bypass_p")
456
457(define_insn_reservation "power6-mtjmpr" 2
458  (and (eq_attr "type" "mtjmpr,mfjmpr")
459       (eq_attr "cpu" "power6"))
460  "BX2_power6")
461
462(define_bypass 5 "power6-mtjmpr" "power6-branch")
463
464(define_insn_reservation "power6-branch" 2
465  (and (eq_attr "type" "jmpreg,branch")
466       (eq_attr "cpu" "power6"))
467  "BRU_power6")
468
469(define_bypass 5 "power6-branch" "power6-mtjmpr")
470
471(define_insn_reservation "power6-crlogical" 3
472  (and (eq_attr "type" "cr_logical")
473       (eq_attr "cpu" "power6"))
474  "BRU_power6")
475
476(define_bypass 3 "power6-crlogical" "power6-branch")
477
478(define_insn_reservation "power6-mfcr" 6 ; N/A
479  (and (eq_attr "type" "mfcr")
480       (eq_attr "cpu" "power6"))
481  "BX2_power6")
482
483; mfcrf (1 field)
484(define_insn_reservation "power6-mfcrf" 3 ; N/A
485  (and (eq_attr "type" "mfcrf")
486       (eq_attr "cpu" "power6"))
487  "BX2_power6") ;
488
489; mtcrf (1 field)
490(define_insn_reservation "power6-mtcr" 4 ; N/A
491  (and (eq_attr "type" "mtcr")
492       (eq_attr "cpu" "power6"))
493  "BX2_power6")
494
495(define_bypass 9 "power6-mtcr" "power6-branch")
496
497(define_insn_reservation "power6-fp" 6
498  (and (eq_attr "type" "fp,fpsimple,dmul,dfp")
499       (eq_attr "cpu" "power6"))
500  "FPU_power6")
501
502; Any fp instruction that updates a CR has a latency
503; of 6 to a dependent branch
504(define_bypass 6 "power6-fp" "power6-branch")
505
506(define_bypass 1 "power6-fp"
507                 "power6-fpstore,power6-fpstore-update"
508  "rs6000_store_data_bypass_p")
509
510(define_insn_reservation "power6-fpcompare" 8
511  (and (eq_attr "type" "fpcompare")
512       (eq_attr "cpu" "power6"))
513  "FPU_power6")
514
515(define_bypass 12 "power6-fpcompare"
516                  "power6-branch,power6-crlogical")
517
518(define_insn_reservation "power6-sdiv" 26
519  (and (eq_attr "type" "sdiv")
520       (eq_attr "cpu" "power6"))
521  "FPU_power6")
522
523(define_insn_reservation "power6-ddiv" 32
524  (and (eq_attr "type" "ddiv")
525       (eq_attr "cpu" "power6"))
526  "FPU_power6")
527
528(define_insn_reservation "power6-sqrt" 30
529  (and (eq_attr "type" "ssqrt")
530       (eq_attr "cpu" "power6"))
531  "FPU_power6")
532
533(define_insn_reservation "power6-dsqrt" 42
534  (and (eq_attr "type" "dsqrt")
535       (eq_attr "cpu" "power6"))
536  "FPU_power6")
537
538(define_insn_reservation "power6-isync" 2 ; N/A 
539  (and (eq_attr "type" "isync")
540       (eq_attr "cpu" "power6"))
541  "FXU_power6")
542
543(define_insn_reservation "power6-vecload" 1
544  (and (eq_attr "type" "vecload")
545       (eq_attr "cpu" "power6"))
546  "LSU_power6")
547
548(define_insn_reservation "power6-vecstore" 1
549  (and (eq_attr "type" "vecstore")
550       (eq_attr "cpu" "power6"))
551  "LSF_power6")
552
553(define_insn_reservation "power6-vecsimple" 3
554  (and (eq_attr "type" "vecsimple,veclogical,vecmove")
555       (eq_attr "cpu" "power6"))
556  "FPU_power6")
557
558(define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
559                                     power6-vecperm")
560
561(define_bypass 5 "power6-vecsimple" "power6-vecfloat")
562
563(define_bypass 4 "power6-vecsimple" "power6-vecstore" )
564
565(define_insn_reservation "power6-veccmp" 1
566  (and (eq_attr "type" "veccmp,veccmpfx")
567       (eq_attr "cpu" "power6"))
568  "FPU_power6")
569
570(define_bypass 10 "power6-veccmp" "power6-branch")
571
572(define_insn_reservation "power6-vecfloat" 7
573  (and (eq_attr "type" "vecfloat")
574       (eq_attr "cpu" "power6"))
575  "FPU_power6")
576
577(define_bypass 10 "power6-vecfloat" "power6-vecsimple")
578
579(define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
580                                     power6-vecperm")
581
582(define_bypass 9 "power6-vecfloat" "power6-vecstore" )
583
584(define_insn_reservation "power6-veccomplex" 7
585  (and (eq_attr "type" "vecsimple")
586       (eq_attr "cpu" "power6"))
587  "FPU_power6")
588
589(define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
590                                       power6-vecfloat" )
591
592(define_bypass 9 "power6-veccomplex" "power6-vecperm" )
593
594(define_bypass 8 "power6-veccomplex" "power6-vecstore" )
595
596(define_insn_reservation "power6-vecperm" 4
597  (and (eq_attr "type" "vecperm")
598       (eq_attr "cpu" "power6"))
599  "FPU_power6")
600
601(define_bypass 7 "power6-vecperm" "power6-vecsimple,\
602                                   power6-vecfloat" )
603
604(define_bypass 6 "power6-vecperm" "power6-veccomplex" )
605
606(define_bypass 5 "power6-vecperm" "power6-vecstore" )
607
608(define_insn_reservation "power6-mftgpr" 8
609  (and (eq_attr "type" "mftgpr")
610       (eq_attr "cpu" "power6"))
611  "X2F_power6")
612
613(define_insn_reservation "power6-mffgpr" 14
614  (and (eq_attr "type" "mffgpr")
615       (eq_attr "cpu" "power6"))
616  "LX2_power6")
617
618(define_bypass 4 "power6-mftgpr" "power6-imul,\
619                                  power6-lmul,\
620                                  power6-imul-cmp,\
621                                  power6-lmul-cmp,\
622                                  power6-imul3,\
623                                  power6-idiv,\
624                                  power6-ldiv" )
625