1/* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler 2 Copyright (C) 2012-2020 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21/* ------------------------------------------------------------------------ */ 22 23#define IN_TARGET_CODE 1 24 25#include "config.h" 26#include "system.h" 27#include "coretypes.h" 28#include "backend.h" 29#include "target.h" 30#include "rtl.h" 31#include "tree.h" 32#include "tree-pass.h" 33#include "stringpool.h" 34#include "attribs.h" 35#include "df.h" 36#include "memmodel.h" 37#include "tm_p.h" 38#include "optabs.h" /* For GEN_FCN. */ 39#include "regs.h" 40#include "emit-rtl.h" 41#include "recog.h" 42#include "diagnostic-core.h" 43#include "stor-layout.h" 44#include "varasm.h" 45#include "calls.h" 46#include "output.h" 47#include "explow.h" 48#include "expr.h" 49#include "tm-constrs.h" 50#include "builtins.h" 51#include "cpplib.h" 52#include "context.h" 53 54/* This file should be included last. */ 55#include "target-def.h" 56 57/* ------------------------------------------------------------------------ */ 58 59/* This file is divided into five parts: 60 61 PART 1: Auxiliary static variable definitions and 62 target hook static variable definitions. 63 64 PART 2: Auxiliary static function definitions. 65 66 PART 3: Implement target hook stuff definitions. 67 68 PART 4: Implemet extern function definitions, 69 the prototype is in nds32-protos.h. 70 71 PART 5: Initialize target hook structure and definitions. */ 72 73/* ------------------------------------------------------------------------ */ 74 75/* PART 1: Auxiliary static variable definitions and 76 target hook static variable definitions. */ 77 78/* Define intrinsic register names. 79 Please refer to nds32_intrinsic.h file, the index is corresponding to 80 'enum nds32_intrinsic_registers' data type values. 81 NOTE that the base value starting from 1024. */ 82static const char * const nds32_intrinsic_register_names[] = 83{ 84 "$CPU_VER", 85 "$ICM_CFG", 86 "$DCM_CFG", 87 "$MMU_CFG", 88 "$MSC_CFG", 89 "$MSC_CFG2", 90 "$CORE_ID", 91 "$FUCOP_EXIST", 92 93 "$PSW", 94 "$IPSW", 95 "$P_IPSW", 96 "$IVB", 97 "$EVA", 98 "$P_EVA", 99 "$ITYPE", 100 "$P_ITYPE", 101 102 "$MERR", 103 "$IPC", 104 "$P_IPC", 105 "$OIPC", 106 "$P_P0", 107 "$P_P1", 108 109 "$INT_MASK", 110 "$INT_MASK2", 111 "$INT_MASK3", 112 "$INT_PEND", 113 "$INT_PEND2", 114 "$INT_PEND3", 115 "$SP_USR", 116 "$SP_PRIV", 117 "$INT_PRI", 118 "$INT_PRI2", 119 "$INT_PRI3", 120 "$INT_PRI4", 121 "$INT_CTRL", 122 "$INT_TRIGGER", 123 "$INT_TRIGGER2", 124 "$INT_GPR_PUSH_DIS", 125 126 "$MMU_CTL", 127 "$L1_PPTB", 128 "$TLB_VPN", 129 "$TLB_DATA", 130 "$TLB_MISC", 131 "$VLPT_IDX", 132 "$ILMB", 133 "$DLMB", 134 135 "$CACHE_CTL", 136 "$HSMP_SADDR", 137 "$HSMP_EADDR", 138 "$SDZ_CTL", 139 "$N12MISC_CTL", 140 "$MISC_CTL", 141 "$ECC_MISC", 142 143 "$BPC0", 144 "$BPC1", 145 "$BPC2", 146 "$BPC3", 147 "$BPC4", 148 "$BPC5", 149 "$BPC6", 150 "$BPC7", 151 152 "$BPA0", 153 "$BPA1", 154 "$BPA2", 155 "$BPA3", 156 "$BPA4", 157 "$BPA5", 158 "$BPA6", 159 "$BPA7", 160 161 "$BPAM0", 162 "$BPAM1", 163 "$BPAM2", 164 "$BPAM3", 165 "$BPAM4", 166 "$BPAM5", 167 "$BPAM6", 168 "$BPAM7", 169 170 "$BPV0", 171 "$BPV1", 172 "$BPV2", 173 "$BPV3", 174 "$BPV4", 175 "$BPV5", 176 "$BPV6", 177 "$BPV7", 178 179 "$BPCID0", 180 "$BPCID1", 181 "$BPCID2", 182 "$BPCID3", 183 "$BPCID4", 184 "$BPCID5", 185 "$BPCID6", 186 "$BPCID7", 187 188 "$EDM_CFG", 189 "$EDMSW", 190 "$EDM_CTL", 191 "$EDM_DTR", 192 "$BPMTC", 193 "$DIMBR", 194 195 "$TECR0", 196 "$TECR1", 197 "$PFMC0", 198 "$PFMC1", 199 "$PFMC2", 200 "$PFM_CTL", 201 "$PFT_CTL", 202 "$HSP_CTL", 203 "$SP_BOUND", 204 "$SP_BOUND_PRIV", 205 "$SP_BASE", 206 "$SP_BASE_PRIV", 207 "$FUCOP_CTL", 208 "$PRUSR_ACC_CTL", 209 210 "$DMA_CFG", 211 "$DMA_GCSW", 212 "$DMA_CHNSEL", 213 "$DMA_ACT", 214 "$DMA_SETUP", 215 "$DMA_ISADDR", 216 "$DMA_ESADDR", 217 "$DMA_TCNT", 218 "$DMA_STATUS", 219 "$DMA_2DSET", 220 "$DMA_2DSCTL", 221 "$DMA_RCNT", 222 "$DMA_HSTATUS", 223 224 "$PC", 225 "$SP_USR1", 226 "$SP_USR2", 227 "$SP_USR3", 228 "$SP_PRIV1", 229 "$SP_PRIV2", 230 "$SP_PRIV3", 231 "$BG_REGION", 232 "$SFCR", 233 "$SIGN", 234 "$ISIGN", 235 "$P_ISIGN", 236 "$IFC_LP", 237 "$ITB" 238}; 239 240/* Define instrinsic cctl names. */ 241static const char * const nds32_cctl_names[] = 242{ 243 "L1D_VA_FILLCK", 244 "L1D_VA_ULCK", 245 "L1I_VA_FILLCK", 246 "L1I_VA_ULCK", 247 248 "L1D_IX_WBINVAL", 249 "L1D_IX_INVAL", 250 "L1D_IX_WB", 251 "L1I_IX_INVAL", 252 253 "L1D_VA_INVAL", 254 "L1D_VA_WB", 255 "L1D_VA_WBINVAL", 256 "L1I_VA_INVAL", 257 258 "L1D_IX_RTAG", 259 "L1D_IX_RWD", 260 "L1I_IX_RTAG", 261 "L1I_IX_RWD", 262 263 "L1D_IX_WTAG", 264 "L1D_IX_WWD", 265 "L1I_IX_WTAG", 266 "L1I_IX_WWD" 267}; 268 269static const char * const nds32_dpref_names[] = 270{ 271 "SRD", 272 "MRD", 273 "SWR", 274 "MWR", 275 "PTE", 276 "CLWR" 277}; 278 279/* Defining register allocation order for performance. 280 We want to allocate callee-saved registers after others. 281 It may be used by nds32_adjust_reg_alloc_order(). */ 282static const int nds32_reg_alloc_order_for_speed[] = 283{ 284 0, 1, 2, 3, 4, 5, 16, 17, 285 18, 19, 20, 21, 22, 23, 24, 25, 286 26, 27, 6, 7, 8, 9, 10, 11, 287 12, 13, 14, 15 288}; 289 290/* Defining target-specific uses of __attribute__. */ 291static const struct attribute_spec nds32_attribute_table[] = 292{ 293 /* Syntax: { name, min_len, max_len, decl_required, type_required, 294 function_type_required, affects_type_identity, handler, 295 exclude } */ 296 297 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ 298 { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, 299 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ 300 { "exception", 1, 8, false, false, false, false, NULL, NULL }, 301 /* Argument is user's interrupt numbers. The vector number is always 0. */ 302 { "reset", 1, 1, false, false, false, false, NULL, NULL }, 303 304 /* The attributes describing isr nested type. */ 305 { "nested", 0, 0, false, false, false, false, NULL, NULL }, 306 { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, 307 { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, 308 { "critical", 0, 0, false, false, false, false, NULL, NULL }, 309 310 /* The attributes describing isr register save scheme. */ 311 { "save_all", 0, 0, false, false, false, false, NULL, NULL }, 312 { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, 313 314 /* The attributes used by reset attribute. */ 315 { "nmi", 1, 1, false, false, false, false, NULL, NULL }, 316 { "warm", 1, 1, false, false, false, false, NULL, NULL }, 317 318 /* The attributes describing isr security level. */ 319 { "secure", 1, 1, false, false, false, false, NULL, NULL }, 320 321 /* The attribute telling no prologue/epilogue. */ 322 { "naked", 0, 0, false, false, false, false, NULL, NULL }, 323 324 /* The attribute is used to tell this function to be ROM patch. */ 325 { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, 326 327 /* FOR BACKWARD COMPATIBILITY, 328 this attribute also tells no prologue/epilogue. */ 329 { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, 330 331 /* The last attribute spec is set to be NULL. */ 332 { NULL, 0, 0, false, false, false, false, NULL, NULL } 333}; 334 335 336/* ------------------------------------------------------------------------ */ 337 338/* PART 2: Auxiliary static function definitions. */ 339 340/* Function to save and restore machine-specific function data. */ 341static struct machine_function * 342nds32_init_machine_status (void) 343{ 344 struct machine_function *machine; 345 machine = ggc_cleared_alloc<machine_function> (); 346 347 /* Initially assume this function does not use __builtin_eh_return. */ 348 machine->use_eh_return_p = 0; 349 350 /* Initially assume this function needs prologue/epilogue. */ 351 machine->naked_p = 0; 352 353 /* Initially assume this function does NOT use fp_as_gp optimization. */ 354 machine->fp_as_gp_p = 0; 355 356 /* Initially this function is not under strictly aligned situation. */ 357 machine->strict_aligned_p = 0; 358 359 /* Initially this function has no naked and no_prologue attributes. */ 360 machine->attr_naked_p = 0; 361 machine->attr_no_prologue_p = 0; 362 363 return machine; 364} 365 366/* Function to compute stack frame size and 367 store into cfun->machine structure. */ 368static void 369nds32_compute_stack_frame (void) 370{ 371 int r; 372 int block_size; 373 bool v3pushpop_p; 374 375 /* Because nds32_compute_stack_frame() will be called from different place, 376 everytime we enter this function, we have to assume this function 377 needs prologue/epilogue. */ 378 cfun->machine->naked_p = 0; 379 380 /* We need to mark whether this function has naked and no_prologue 381 attribute so that we can distinguish the difference if users applies 382 -mret-in-naked-func option. */ 383 cfun->machine->attr_naked_p 384 = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) 385 ? 1 : 0; 386 cfun->machine->attr_no_prologue_p 387 = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) 388 ? 1 : 0; 389 390 /* If __builtin_eh_return is used, we better have frame pointer needed 391 so that we can easily locate the stack slot of return address. */ 392 if (crtl->calls_eh_return) 393 { 394 frame_pointer_needed = 1; 395 396 /* We need to mark eh data registers that need to be saved 397 in the stack. */ 398 cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0); 399 for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++) 400 cfun->machine->eh_return_data_last_regno = r; 401 402 cfun->machine->eh_return_data_regs_size 403 = 4 * (cfun->machine->eh_return_data_last_regno 404 - cfun->machine->eh_return_data_first_regno 405 + 1); 406 cfun->machine->use_eh_return_p = 1; 407 } 408 else 409 { 410 /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we 411 do not need to handle __builtin_eh_return case in this function. */ 412 cfun->machine->eh_return_data_first_regno = SP_REGNUM; 413 cfun->machine->eh_return_data_last_regno = SP_REGNUM; 414 415 cfun->machine->eh_return_data_regs_size = 0; 416 cfun->machine->use_eh_return_p = 0; 417 } 418 419 /* Get variadic arguments size to prepare pretend arguments and 420 we will push them into stack at prologue by ourself. */ 421 cfun->machine->va_args_size = crtl->args.pretend_args_size; 422 if (cfun->machine->va_args_size != 0) 423 { 424 cfun->machine->va_args_first_regno 425 = NDS32_GPR_ARG_FIRST_REGNUM 426 + NDS32_MAX_GPR_REGS_FOR_ARGS 427 - (crtl->args.pretend_args_size / UNITS_PER_WORD); 428 cfun->machine->va_args_last_regno 429 = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; 430 } 431 else 432 { 433 cfun->machine->va_args_first_regno = SP_REGNUM; 434 cfun->machine->va_args_last_regno = SP_REGNUM; 435 } 436 437 /* Important: We need to make sure that varargs area is 8-byte alignment. */ 438 block_size = cfun->machine->va_args_size; 439 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 440 { 441 cfun->machine->va_args_area_padding_bytes 442 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; 443 } 444 445 /* Get local variables, incoming variables, and temporary variables size. 446 Note that we need to make sure it is 8-byte alignment because 447 there may be no padding bytes if we are using LRA. */ 448 cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); 449 450 /* Get outgoing arguments size. */ 451 cfun->machine->out_args_size = crtl->outgoing_args_size; 452 453 /* If $fp value is required to be saved on stack, it needs 4 bytes space. 454 Check whether $fp is ever live. */ 455 cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; 456 457 /* If $gp value is required to be saved on stack, it needs 4 bytes space. 458 Check whether we are using PIC code genration. */ 459 cfun->machine->gp_size = 460 (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; 461 462 /* If $lp value is required to be saved on stack, it needs 4 bytes space. 463 Check whether $lp is ever live. */ 464 cfun->machine->lp_size 465 = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; 466 467 /* Initially there is no padding bytes. */ 468 cfun->machine->callee_saved_area_gpr_padding_bytes = 0; 469 470 /* Calculate the bytes of saving callee-saved registers on stack. */ 471 cfun->machine->callee_saved_gpr_regs_size = 0; 472 cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; 473 cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; 474 cfun->machine->callee_saved_fpr_regs_size = 0; 475 cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM; 476 cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM; 477 478 /* Currently, there is no need to check $r28~$r31 479 because we will save them in another way. */ 480 for (r = 0; r < 28; r++) 481 { 482 if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) 483 { 484 /* Mark the first required callee-saved register 485 (only need to set it once). 486 If first regno == SP_REGNUM, we can tell that 487 it is the first time to be here. */ 488 if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) 489 cfun->machine->callee_saved_first_gpr_regno = r; 490 /* Mark the last required callee-saved register. */ 491 cfun->machine->callee_saved_last_gpr_regno = r; 492 } 493 } 494 495 /* Recording fpu callee-saved register. */ 496 if (TARGET_HARD_FLOAT) 497 { 498 for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++) 499 { 500 if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) 501 { 502 /* Mark the first required callee-saved register. */ 503 if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) 504 { 505 /* Make first callee-saved number is even, 506 bacause we use doubleword access, and this way 507 promise 8-byte alignemt. */ 508 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) 509 cfun->machine->callee_saved_first_fpr_regno = r - 1; 510 else 511 cfun->machine->callee_saved_first_fpr_regno = r; 512 } 513 cfun->machine->callee_saved_last_fpr_regno = r; 514 } 515 } 516 517 /* Make last callee-saved register number is odd, 518 we hope callee-saved register is even. */ 519 int last_fpr = cfun->machine->callee_saved_last_fpr_regno; 520 if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr)) 521 cfun->machine->callee_saved_last_fpr_regno++; 522 } 523 524 /* Check if this function can omit prologue/epilogue code fragment. 525 If there is 'no_prologue'/'naked'/'secure' attribute in this function, 526 we can set 'naked_p' flag to indicate that 527 we do not have to generate prologue/epilogue. 528 Or, if all the following conditions succeed, 529 we can set this function 'naked_p' as well: 530 condition 1: first_regno == last_regno == SP_REGNUM, 531 which means we do not have to save 532 any callee-saved registers. 533 condition 2: Both $lp and $fp are NOT live in this function, 534 which means we do not need to save them and there 535 is no outgoing size. 536 condition 3: There is no local_size, which means 537 we do not need to adjust $sp. */ 538 if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) 539 || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) 540 || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) 541 || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM 542 && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM 543 && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM 544 && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM 545 && !df_regs_ever_live_p (FP_REGNUM) 546 && !df_regs_ever_live_p (LP_REGNUM) 547 && cfun->machine->local_size == 0 548 && !flag_pic)) 549 { 550 /* Set this function 'naked_p' and other functions can check this flag. 551 Note that in nds32 port, the 'naked_p = 1' JUST means there is no 552 callee-saved, local size, and outgoing size. 553 The varargs space and ret instruction may still present in 554 the prologue/epilogue expanding. */ 555 cfun->machine->naked_p = 1; 556 557 /* No need to save $fp, $gp, and $lp. 558 We should set these value to be zero 559 so that nds32_initial_elimination_offset() can work properly. */ 560 cfun->machine->fp_size = 0; 561 cfun->machine->gp_size = 0; 562 cfun->machine->lp_size = 0; 563 564 /* If stack usage computation is required, 565 we need to provide the static stack size. */ 566 if (flag_stack_usage_info) 567 current_function_static_stack_size = 0; 568 569 /* No need to do following adjustment, return immediately. */ 570 return; 571 } 572 573 v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; 574 575 /* Adjustment for v3push instructions: 576 If we are using v3push (push25/pop25) instructions, 577 we need to make sure Rb is $r6 and Re is 578 located on $r6, $r8, $r10, or $r14. 579 Some results above will be discarded and recomputed. 580 Note that it is only available under V3/V3M ISA and we 581 DO NOT setup following stuff for isr or variadic function. */ 582 if (v3pushpop_p) 583 { 584 /* Recompute: 585 cfun->machine->fp_size 586 cfun->machine->gp_size 587 cfun->machine->lp_size 588 cfun->machine->callee_saved_first_gpr_regno 589 cfun->machine->callee_saved_last_gpr_regno */ 590 591 /* For v3push instructions, $fp, $gp, and $lp are always saved. */ 592 cfun->machine->fp_size = 4; 593 cfun->machine->gp_size = 4; 594 cfun->machine->lp_size = 4; 595 596 /* Remember to set Rb = $r6. */ 597 cfun->machine->callee_saved_first_gpr_regno = 6; 598 599 if (cfun->machine->callee_saved_last_gpr_regno <= 6) 600 { 601 /* Re = $r6 */ 602 cfun->machine->callee_saved_last_gpr_regno = 6; 603 } 604 else if (cfun->machine->callee_saved_last_gpr_regno <= 8) 605 { 606 /* Re = $r8 */ 607 cfun->machine->callee_saved_last_gpr_regno = 8; 608 } 609 else if (cfun->machine->callee_saved_last_gpr_regno <= 10) 610 { 611 /* Re = $r10 */ 612 cfun->machine->callee_saved_last_gpr_regno = 10; 613 } 614 else if (cfun->machine->callee_saved_last_gpr_regno <= 14) 615 { 616 /* Re = $r14 */ 617 cfun->machine->callee_saved_last_gpr_regno = 14; 618 } 619 else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) 620 { 621 /* If last_regno is SP_REGNUM, which means 622 it is never changed, so set it to Re = $r6. */ 623 cfun->machine->callee_saved_last_gpr_regno = 6; 624 } 625 else 626 { 627 /* The program flow should not go here. */ 628 gcc_unreachable (); 629 } 630 } 631 632 int sp_adjust = cfun->machine->local_size 633 + cfun->machine->out_args_size 634 + cfun->machine->callee_saved_area_gpr_padding_bytes 635 + cfun->machine->callee_saved_fpr_regs_size; 636 637 if (!v3pushpop_p 638 && sp_adjust == 0 639 && !frame_pointer_needed) 640 { 641 block_size = cfun->machine->fp_size 642 + cfun->machine->gp_size 643 + cfun->machine->lp_size; 644 645 if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) 646 block_size += (4 * (cfun->machine->callee_saved_last_gpr_regno 647 - cfun->machine->callee_saved_first_gpr_regno 648 + 1)); 649 650 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 651 { 652 /* $r14 is last callee save register. */ 653 if (cfun->machine->callee_saved_last_gpr_regno 654 < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) 655 { 656 cfun->machine->callee_saved_last_gpr_regno++; 657 } 658 else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) 659 { 660 cfun->machine->callee_saved_first_gpr_regno 661 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; 662 cfun->machine->callee_saved_last_gpr_regno 663 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; 664 } 665 } 666 } 667 668 /* We have correctly set callee_saved_first_gpr_regno 669 and callee_saved_last_gpr_regno. 670 Initially, the callee_saved_gpr_regs_size is supposed to be 0. 671 As long as callee_saved_last_gpr_regno is not SP_REGNUM, 672 we can update callee_saved_gpr_regs_size with new size. */ 673 if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) 674 { 675 /* Compute pushed size of callee-saved registers. */ 676 cfun->machine->callee_saved_gpr_regs_size 677 = 4 * (cfun->machine->callee_saved_last_gpr_regno 678 - cfun->machine->callee_saved_first_gpr_regno 679 + 1); 680 } 681 682 if (TARGET_HARD_FLOAT) 683 { 684 /* Compute size of callee svaed floating-point registers. */ 685 if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM) 686 { 687 cfun->machine->callee_saved_fpr_regs_size 688 = 4 * (cfun->machine->callee_saved_last_fpr_regno 689 - cfun->machine->callee_saved_first_fpr_regno 690 + 1); 691 } 692 } 693 694 /* Important: We need to make sure that 695 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) 696 is 8-byte alignment. 697 If it is not, calculate the padding bytes. */ 698 block_size = cfun->machine->fp_size 699 + cfun->machine->gp_size 700 + cfun->machine->lp_size 701 + cfun->machine->callee_saved_gpr_regs_size; 702 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 703 { 704 cfun->machine->callee_saved_area_gpr_padding_bytes 705 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; 706 } 707 708 /* If stack usage computation is required, 709 we need to provide the static stack size. */ 710 if (flag_stack_usage_info) 711 { 712 current_function_static_stack_size 713 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) 714 + cfun->machine->local_size 715 + cfun->machine->out_args_size; 716 } 717} 718 719/* Function to create a parallel rtx pattern 720 which presents stack push multiple behavior. 721 The overall concept are: 722 "push registers to memory", 723 "adjust stack pointer". */ 724static void 725nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, 726 bool save_fp_p, bool save_gp_p, bool save_lp_p, 727 bool vaarg_p) 728{ 729 unsigned regno; 730 int extra_count; 731 int num_use_regs; 732 int par_index; 733 int offset; 734 735 rtx reg; 736 rtx mem; 737 rtx push_rtx; 738 rtx adjust_sp_rtx; 739 rtx parallel_insn; 740 rtx dwarf; 741 742 /* We need to provide a customized rtx which contains 743 necessary information for data analysis, 744 so we create a parallel rtx like this: 745 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) 746 (reg:SI Rb)) 747 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) 748 (reg:SI Rb+1)) 749 ... 750 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) 751 (reg:SI Re)) 752 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) 753 (reg:SI FP_REGNUM)) 754 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) 755 (reg:SI GP_REGNUM)) 756 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) 757 (reg:SI LP_REGNUM)) 758 (set (reg:SI SP_REGNUM) 759 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ 760 761 /* Calculate the number of registers that will be pushed. */ 762 extra_count = 0; 763 if (save_fp_p) 764 extra_count++; 765 if (save_gp_p) 766 extra_count++; 767 if (save_lp_p) 768 extra_count++; 769 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ 770 if (Rb == SP_REGNUM && Re == SP_REGNUM) 771 num_use_regs = extra_count; 772 else 773 num_use_regs = Re - Rb + 1 + extra_count; 774 775 /* In addition to used registers, 776 we need one more space for (set sp sp-x) rtx. */ 777 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 778 rtvec_alloc (num_use_regs + 1)); 779 par_index = 0; 780 781 /* Initialize offset and start to create push behavior. */ 782 offset = -(num_use_regs * 4); 783 784 /* Create (set mem regX) from Rb, Rb+1 up to Re. */ 785 for (regno = Rb; regno <= Re; regno++) 786 { 787 /* Rb and Re may be SP_REGNUM. 788 We need to break this loop immediately. */ 789 if (regno == SP_REGNUM) 790 break; 791 792 reg = gen_rtx_REG (SImode, regno); 793 mem = gen_frame_mem (SImode, plus_constant (Pmode, 794 stack_pointer_rtx, 795 offset)); 796 push_rtx = gen_rtx_SET (mem, reg); 797 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 798 RTX_FRAME_RELATED_P (push_rtx) = 1; 799 offset = offset + 4; 800 par_index++; 801 } 802 803 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ 804 if (save_fp_p) 805 { 806 reg = gen_rtx_REG (SImode, FP_REGNUM); 807 mem = gen_frame_mem (SImode, plus_constant (Pmode, 808 stack_pointer_rtx, 809 offset)); 810 push_rtx = gen_rtx_SET (mem, reg); 811 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 812 RTX_FRAME_RELATED_P (push_rtx) = 1; 813 offset = offset + 4; 814 par_index++; 815 } 816 if (save_gp_p) 817 { 818 reg = gen_rtx_REG (SImode, GP_REGNUM); 819 mem = gen_frame_mem (SImode, plus_constant (Pmode, 820 stack_pointer_rtx, 821 offset)); 822 push_rtx = gen_rtx_SET (mem, reg); 823 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 824 RTX_FRAME_RELATED_P (push_rtx) = 1; 825 offset = offset + 4; 826 par_index++; 827 } 828 if (save_lp_p) 829 { 830 reg = gen_rtx_REG (SImode, LP_REGNUM); 831 mem = gen_frame_mem (SImode, plus_constant (Pmode, 832 stack_pointer_rtx, 833 offset)); 834 push_rtx = gen_rtx_SET (mem, reg); 835 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 836 RTX_FRAME_RELATED_P (push_rtx) = 1; 837 offset = offset + 4; 838 par_index++; 839 } 840 841 /* Create (set sp sp-x). */ 842 843 /* We need to re-calculate the offset value again for adjustment. */ 844 offset = -(num_use_regs * 4); 845 adjust_sp_rtx 846 = gen_rtx_SET (stack_pointer_rtx, 847 plus_constant (Pmode, stack_pointer_rtx, offset)); 848 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 849 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; 850 851 parallel_insn = emit_insn (parallel_insn); 852 853 /* The insn rtx 'parallel_insn' will change frame layout. 854 We need to use RTX_FRAME_RELATED_P so that GCC is able to 855 generate CFI (Call Frame Information) stuff. */ 856 RTX_FRAME_RELATED_P (parallel_insn) = 1; 857 858 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG 859 since we will not restore those register at epilogue. */ 860 if (vaarg_p) 861 { 862 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, 863 copy_rtx (adjust_sp_rtx), NULL_RTX); 864 REG_NOTES (parallel_insn) = dwarf; 865 } 866} 867 868/* Function to create a parallel rtx pattern 869 which presents stack pop multiple behavior. 870 The overall concept are: 871 "pop registers from memory", 872 "adjust stack pointer". */ 873static void 874nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, 875 bool save_fp_p, bool save_gp_p, bool save_lp_p) 876{ 877 unsigned regno; 878 int extra_count; 879 int num_use_regs; 880 int par_index; 881 int offset; 882 883 rtx reg; 884 rtx mem; 885 rtx pop_rtx; 886 rtx adjust_sp_rtx; 887 rtx parallel_insn; 888 rtx dwarf = NULL_RTX; 889 890 /* We need to provide a customized rtx which contains 891 necessary information for data analysis, 892 so we create a parallel rtx like this: 893 (parallel [(set (reg:SI Rb) 894 (mem (reg:SI SP_REGNUM))) 895 (set (reg:SI Rb+1) 896 (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) 897 ... 898 (set (reg:SI Re) 899 (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) 900 (set (reg:SI FP_REGNUM) 901 (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) 902 (set (reg:SI GP_REGNUM) 903 (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) 904 (set (reg:SI LP_REGNUM) 905 (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) 906 (set (reg:SI SP_REGNUM) 907 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ 908 909 /* Calculate the number of registers that will be poped. */ 910 extra_count = 0; 911 if (save_fp_p) 912 extra_count++; 913 if (save_gp_p) 914 extra_count++; 915 if (save_lp_p) 916 extra_count++; 917 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ 918 if (Rb == SP_REGNUM && Re == SP_REGNUM) 919 num_use_regs = extra_count; 920 else 921 num_use_regs = Re - Rb + 1 + extra_count; 922 923 /* In addition to used registers, 924 we need one more space for (set sp sp+x) rtx. */ 925 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 926 rtvec_alloc (num_use_regs + 1)); 927 par_index = 0; 928 929 /* Initialize offset and start to create pop behavior. */ 930 offset = 0; 931 932 /* Create (set regX mem) from Rb, Rb+1 up to Re. */ 933 for (regno = Rb; regno <= Re; regno++) 934 { 935 /* Rb and Re may be SP_REGNUM. 936 We need to break this loop immediately. */ 937 if (regno == SP_REGNUM) 938 break; 939 940 reg = gen_rtx_REG (SImode, regno); 941 mem = gen_frame_mem (SImode, plus_constant (Pmode, 942 stack_pointer_rtx, 943 offset)); 944 pop_rtx = gen_rtx_SET (reg, mem); 945 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 946 RTX_FRAME_RELATED_P (pop_rtx) = 1; 947 offset = offset + 4; 948 par_index++; 949 950 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 951 } 952 953 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ 954 if (save_fp_p) 955 { 956 reg = gen_rtx_REG (SImode, FP_REGNUM); 957 mem = gen_frame_mem (SImode, plus_constant (Pmode, 958 stack_pointer_rtx, 959 offset)); 960 pop_rtx = gen_rtx_SET (reg, mem); 961 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 962 RTX_FRAME_RELATED_P (pop_rtx) = 1; 963 offset = offset + 4; 964 par_index++; 965 966 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 967 } 968 if (save_gp_p) 969 { 970 reg = gen_rtx_REG (SImode, GP_REGNUM); 971 mem = gen_frame_mem (SImode, plus_constant (Pmode, 972 stack_pointer_rtx, 973 offset)); 974 pop_rtx = gen_rtx_SET (reg, mem); 975 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 976 RTX_FRAME_RELATED_P (pop_rtx) = 1; 977 offset = offset + 4; 978 par_index++; 979 980 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 981 } 982 if (save_lp_p) 983 { 984 reg = gen_rtx_REG (SImode, LP_REGNUM); 985 mem = gen_frame_mem (SImode, plus_constant (Pmode, 986 stack_pointer_rtx, 987 offset)); 988 pop_rtx = gen_rtx_SET (reg, mem); 989 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 990 RTX_FRAME_RELATED_P (pop_rtx) = 1; 991 offset = offset + 4; 992 par_index++; 993 994 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 995 } 996 997 /* Create (set sp sp+x). */ 998 999 /* The offset value is already in place. No need to re-calculate it. */ 1000 adjust_sp_rtx 1001 = gen_rtx_SET (stack_pointer_rtx, 1002 plus_constant (Pmode, stack_pointer_rtx, offset)); 1003 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1004 1005 /* Tell gcc we adjust SP in this insn. */ 1006 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); 1007 1008 parallel_insn = emit_insn (parallel_insn); 1009 1010 /* The insn rtx 'parallel_insn' will change frame layout. 1011 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1012 generate CFI (Call Frame Information) stuff. */ 1013 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1014 1015 /* Add CFI info by manual. */ 1016 REG_NOTES (parallel_insn) = dwarf; 1017} 1018 1019/* Function to create a parallel rtx pattern 1020 which presents stack v3push behavior. 1021 The overall concept are: 1022 "push registers to memory", 1023 "adjust stack pointer". */ 1024static void 1025nds32_emit_stack_v3push (unsigned Rb, 1026 unsigned Re, 1027 unsigned imm8u) 1028{ 1029 unsigned regno; 1030 int num_use_regs; 1031 int par_index; 1032 int offset; 1033 1034 rtx reg; 1035 rtx mem; 1036 rtx push_rtx; 1037 rtx adjust_sp_rtx; 1038 rtx parallel_insn; 1039 1040 /* We need to provide a customized rtx which contains 1041 necessary information for data analysis, 1042 so we create a parallel rtx like this: 1043 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) 1044 (reg:SI Rb)) 1045 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) 1046 (reg:SI Rb+1)) 1047 ... 1048 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) 1049 (reg:SI Re)) 1050 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) 1051 (reg:SI FP_REGNUM)) 1052 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) 1053 (reg:SI GP_REGNUM)) 1054 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) 1055 (reg:SI LP_REGNUM)) 1056 (set (reg:SI SP_REGNUM) 1057 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ 1058 1059 /* Calculate the number of registers that will be pushed. 1060 Since $fp, $gp, and $lp is always pushed with v3push instruction, 1061 we need to count these three registers. 1062 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1063 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1064 num_use_regs = Re - Rb + 1 + 3; 1065 1066 /* In addition to used registers, 1067 we need one more space for (set sp sp-x-imm8u) rtx. */ 1068 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 1069 rtvec_alloc (num_use_regs + 1)); 1070 par_index = 0; 1071 1072 /* Initialize offset and start to create push behavior. */ 1073 offset = -(num_use_regs * 4); 1074 1075 /* Create (set mem regX) from Rb, Rb+1 up to Re. 1076 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1077 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1078 for (regno = Rb; regno <= Re; regno++) 1079 { 1080 reg = gen_rtx_REG (SImode, regno); 1081 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1082 stack_pointer_rtx, 1083 offset)); 1084 push_rtx = gen_rtx_SET (mem, reg); 1085 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1086 RTX_FRAME_RELATED_P (push_rtx) = 1; 1087 offset = offset + 4; 1088 par_index++; 1089 } 1090 1091 /* Create (set mem fp). */ 1092 reg = gen_rtx_REG (SImode, FP_REGNUM); 1093 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1094 stack_pointer_rtx, 1095 offset)); 1096 push_rtx = gen_rtx_SET (mem, reg); 1097 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1098 RTX_FRAME_RELATED_P (push_rtx) = 1; 1099 offset = offset + 4; 1100 par_index++; 1101 /* Create (set mem gp). */ 1102 reg = gen_rtx_REG (SImode, GP_REGNUM); 1103 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1104 stack_pointer_rtx, 1105 offset)); 1106 push_rtx = gen_rtx_SET (mem, reg); 1107 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1108 RTX_FRAME_RELATED_P (push_rtx) = 1; 1109 offset = offset + 4; 1110 par_index++; 1111 /* Create (set mem lp). */ 1112 reg = gen_rtx_REG (SImode, LP_REGNUM); 1113 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1114 stack_pointer_rtx, 1115 offset)); 1116 push_rtx = gen_rtx_SET (mem, reg); 1117 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1118 RTX_FRAME_RELATED_P (push_rtx) = 1; 1119 offset = offset + 4; 1120 par_index++; 1121 1122 /* Create (set sp sp-x-imm8u). */ 1123 1124 /* We need to re-calculate the offset value again for adjustment. */ 1125 offset = -(num_use_regs * 4); 1126 adjust_sp_rtx 1127 = gen_rtx_SET (stack_pointer_rtx, 1128 plus_constant (Pmode, 1129 stack_pointer_rtx, 1130 offset - imm8u)); 1131 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1132 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; 1133 1134 parallel_insn = emit_insn (parallel_insn); 1135 1136 /* The insn rtx 'parallel_insn' will change frame layout. 1137 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1138 generate CFI (Call Frame Information) stuff. */ 1139 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1140} 1141 1142/* Function to create a parallel rtx pattern 1143 which presents stack v3pop behavior. 1144 The overall concept are: 1145 "pop registers from memory", 1146 "adjust stack pointer". */ 1147static void 1148nds32_emit_stack_v3pop (unsigned Rb, 1149 unsigned Re, 1150 unsigned imm8u) 1151{ 1152 unsigned regno; 1153 int num_use_regs; 1154 int par_index; 1155 int offset; 1156 1157 rtx reg; 1158 rtx mem; 1159 rtx pop_rtx; 1160 rtx adjust_sp_rtx; 1161 rtx parallel_insn; 1162 rtx dwarf = NULL_RTX; 1163 1164 /* We need to provide a customized rtx which contains 1165 necessary information for data analysis, 1166 so we create a parallel rtx like this: 1167 (parallel [(set (reg:SI Rb) 1168 (mem (reg:SI SP_REGNUM))) 1169 (set (reg:SI Rb+1) 1170 (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) 1171 ... 1172 (set (reg:SI Re) 1173 (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) 1174 (set (reg:SI FP_REGNUM) 1175 (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) 1176 (set (reg:SI GP_REGNUM) 1177 (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) 1178 (set (reg:SI LP_REGNUM) 1179 (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) 1180 (set (reg:SI SP_REGNUM) 1181 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ 1182 1183 /* Calculate the number of registers that will be poped. 1184 Since $fp, $gp, and $lp is always poped with v3pop instruction, 1185 we need to count these three registers. 1186 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1187 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1188 num_use_regs = Re - Rb + 1 + 3; 1189 1190 /* In addition to used registers, 1191 we need one more space for (set sp sp+x+imm8u) rtx. */ 1192 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 1193 rtvec_alloc (num_use_regs + 1)); 1194 par_index = 0; 1195 1196 /* Initialize offset and start to create pop behavior. */ 1197 offset = 0; 1198 1199 /* Create (set regX mem) from Rb, Rb+1 up to Re. 1200 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1201 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1202 for (regno = Rb; regno <= Re; regno++) 1203 { 1204 reg = gen_rtx_REG (SImode, regno); 1205 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1206 stack_pointer_rtx, 1207 offset)); 1208 pop_rtx = gen_rtx_SET (reg, mem); 1209 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1210 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1211 offset = offset + 4; 1212 par_index++; 1213 1214 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1215 } 1216 1217 /* Create (set fp mem). */ 1218 reg = gen_rtx_REG (SImode, FP_REGNUM); 1219 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1220 stack_pointer_rtx, 1221 offset)); 1222 pop_rtx = gen_rtx_SET (reg, mem); 1223 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1224 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1225 offset = offset + 4; 1226 par_index++; 1227 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1228 1229 /* Create (set gp mem). */ 1230 reg = gen_rtx_REG (SImode, GP_REGNUM); 1231 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1232 stack_pointer_rtx, 1233 offset)); 1234 pop_rtx = gen_rtx_SET (reg, mem); 1235 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1236 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1237 offset = offset + 4; 1238 par_index++; 1239 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1240 1241 /* Create (set lp mem ). */ 1242 reg = gen_rtx_REG (SImode, LP_REGNUM); 1243 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1244 stack_pointer_rtx, 1245 offset)); 1246 pop_rtx = gen_rtx_SET (reg, mem); 1247 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1248 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1249 offset = offset + 4; 1250 par_index++; 1251 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1252 1253 /* Create (set sp sp+x+imm8u). */ 1254 1255 /* The offset value is already in place. No need to re-calculate it. */ 1256 adjust_sp_rtx 1257 = gen_rtx_SET (stack_pointer_rtx, 1258 plus_constant (Pmode, 1259 stack_pointer_rtx, 1260 offset + imm8u)); 1261 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1262 1263 if (frame_pointer_needed) 1264 { 1265 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) 1266 (const_int 0)) 1267 mean reset frame pointer to $sp and reset to offset 0. */ 1268 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 1269 const0_rtx); 1270 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 1271 } 1272 else 1273 { 1274 /* Tell gcc we adjust SP in this insn. */ 1275 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, 1276 copy_rtx (adjust_sp_rtx), dwarf); 1277 } 1278 1279 parallel_insn = emit_insn (parallel_insn); 1280 1281 /* The insn rtx 'parallel_insn' will change frame layout. 1282 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1283 generate CFI (Call Frame Information) stuff. */ 1284 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1285 1286 /* Add CFI info by manual. */ 1287 REG_NOTES (parallel_insn) = dwarf; 1288} 1289 1290static void 1291nds32_emit_load_gp (void) 1292{ 1293 rtx got_symbol, pat; 1294 1295 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ 1296 emit_insn (gen_blockage ()); 1297 1298 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 1299 /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ 1300 pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); 1301 pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); 1302 emit_insn (gen_sethi (pic_offset_table_rtx,pat)); 1303 1304 /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ 1305 pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); 1306 pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); 1307 emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); 1308 1309 /* add5.pc $gp */ 1310 emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); 1311 1312 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ 1313 emit_insn (gen_blockage ()); 1314} 1315 1316/* Function that may creates more instructions 1317 for large value on adjusting stack pointer. 1318 1319 In nds32 target, 'addi' can be used for stack pointer 1320 adjustment in prologue/epilogue stage. 1321 However, sometimes there are too many local variables so that 1322 the adjustment value is not able to be fit in the 'addi' instruction. 1323 One solution is to move value into a register 1324 and then use 'add' instruction. 1325 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ 1326static void 1327nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) 1328{ 1329 rtx tmp_reg; 1330 rtx frame_adjust_insn; 1331 rtx adjust_value_rtx = GEN_INT (adjust_value); 1332 1333 if (adjust_value == 0) 1334 return; 1335 1336 if (!satisfies_constraint_Is15 (adjust_value_rtx)) 1337 { 1338 /* The value is not able to fit in single addi instruction. 1339 Create more instructions of moving value into a register 1340 and then add stack pointer with it. */ 1341 1342 /* $r15 is going to be temporary register to hold the value. */ 1343 tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); 1344 1345 /* Create one more instruction to move value 1346 into the temporary register. */ 1347 emit_move_insn (tmp_reg, adjust_value_rtx); 1348 1349 /* Create new 'add' rtx. */ 1350 frame_adjust_insn = gen_addsi3 (to_reg, 1351 from_reg, 1352 tmp_reg); 1353 /* Emit rtx into insn list and receive its transformed insn rtx. */ 1354 frame_adjust_insn = emit_insn (frame_adjust_insn); 1355 1356 /* Because (tmp_reg <- full_value) may be split into two 1357 rtl patterns, we cannot set its RTX_FRAME_RELATED_P. 1358 We need to construct another (sp <- sp + full_value) 1359 and then insert it into sp_adjust_insn's reg note to 1360 represent a frame related expression. 1361 GCC knows how to refer it and output debug information. */ 1362 1363 rtx plus_rtx; 1364 rtx set_rtx; 1365 1366 plus_rtx = plus_constant (Pmode, from_reg, adjust_value); 1367 set_rtx = gen_rtx_SET (to_reg, plus_rtx); 1368 add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); 1369 } 1370 else 1371 { 1372 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ 1373 frame_adjust_insn = gen_addsi3 (to_reg, 1374 from_reg, 1375 adjust_value_rtx); 1376 /* Emit rtx into instructions list and receive INSN rtx form. */ 1377 frame_adjust_insn = emit_insn (frame_adjust_insn); 1378 } 1379 1380 /* The insn rtx 'sp_adjust_insn' will change frame layout. 1381 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1382 generate CFI (Call Frame Information) stuff. */ 1383 RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; 1384} 1385 1386/* Return true if MODE/TYPE need double word alignment. */ 1387static bool 1388nds32_needs_double_word_align (machine_mode mode, const_tree type) 1389{ 1390 unsigned int align; 1391 1392 /* Pick up the alignment according to the mode or type. */ 1393 align = NDS32_MODE_TYPE_ALIGN (mode, type); 1394 1395 return (align > PARM_BOUNDARY); 1396} 1397 1398/* Return true if FUNC is a naked function. */ 1399bool 1400nds32_naked_function_p (tree func) 1401{ 1402 /* FOR BACKWARD COMPATIBILITY, 1403 we need to support 'no_prologue' attribute as well. */ 1404 tree t_naked; 1405 tree t_no_prologue; 1406 1407 if (TREE_CODE (func) != FUNCTION_DECL) 1408 abort (); 1409 1410 /* We have to use lookup_attribute() to check attributes. 1411 Because attr_naked_p and attr_no_prologue_p are set in 1412 nds32_compute_stack_frame() and the function has not been 1413 invoked yet. */ 1414 t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); 1415 t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); 1416 1417 return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); 1418} 1419 1420/* Function that determine whether a load postincrement is a good thing to use 1421 for a given mode. */ 1422bool 1423nds32_use_load_post_increment (machine_mode mode) 1424{ 1425 return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); 1426} 1427 1428/* Function that check if 'X' is a valid address register. 1429 The variable 'STRICT' is very important to 1430 make decision for register number. 1431 1432 STRICT : true 1433 => We are in reload pass or after reload pass. 1434 The register number should be strictly limited in general registers. 1435 1436 STRICT : false 1437 => Before reload pass, we are free to use any register number. */ 1438static bool 1439nds32_address_register_rtx_p (rtx x, bool strict) 1440{ 1441 int regno; 1442 1443 if (GET_CODE (x) != REG) 1444 return false; 1445 1446 regno = REGNO (x); 1447 1448 if (strict) 1449 return REGNO_OK_FOR_BASE_P (regno); 1450 else 1451 return true; 1452} 1453 1454/* Function that check if 'INDEX' is valid to be a index rtx for address. 1455 1456 OUTER_MODE : Machine mode of outer address rtx. 1457 INDEX : Check if this rtx is valid to be a index for address. 1458 STRICT : If it is true, we are in reload pass or after reload pass. */ 1459static bool 1460nds32_legitimate_index_p (machine_mode outer_mode, 1461 rtx index, 1462 bool strict) 1463{ 1464 int regno; 1465 rtx op0; 1466 rtx op1; 1467 1468 switch (GET_CODE (index)) 1469 { 1470 case REG: 1471 regno = REGNO (index); 1472 /* If we are in reload pass or after reload pass, 1473 we need to limit it to general register. */ 1474 if (strict) 1475 return REGNO_OK_FOR_INDEX_P (regno); 1476 else 1477 return true; 1478 1479 case CONST_INT: 1480 /* The alignment of the integer value is determined by 'outer_mode'. */ 1481 switch (GET_MODE_SIZE (outer_mode)) 1482 { 1483 case 1: 1484 /* Further check if the value is legal for the 'outer_mode'. */ 1485 if (satisfies_constraint_Is15 (index)) 1486 return true; 1487 break; 1488 1489 case 2: 1490 /* Further check if the value is legal for the 'outer_mode'. */ 1491 if (satisfies_constraint_Is16 (index)) 1492 { 1493 /* If it is not under strictly aligned situation, 1494 we can return true without checking alignment. */ 1495 if (!cfun->machine->strict_aligned_p) 1496 return true; 1497 /* Make sure address is half word alignment. */ 1498 else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) 1499 return true; 1500 } 1501 break; 1502 1503 case 4: 1504 /* Further check if the value is legal for the 'outer_mode'. */ 1505 if (satisfies_constraint_Is17 (index)) 1506 { 1507 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 1508 { 1509 if (!satisfies_constraint_Is14 (index)) 1510 return false; 1511 } 1512 1513 /* If it is not under strictly aligned situation, 1514 we can return true without checking alignment. */ 1515 if (!cfun->machine->strict_aligned_p) 1516 return true; 1517 /* Make sure address is word alignment. */ 1518 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) 1519 return true; 1520 } 1521 break; 1522 1523 case 8: 1524 if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, 1525 SImode))) 1526 { 1527 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 1528 { 1529 if (!satisfies_constraint_Is14 (index)) 1530 return false; 1531 } 1532 1533 /* If it is not under strictly aligned situation, 1534 we can return true without checking alignment. */ 1535 if (!cfun->machine->strict_aligned_p) 1536 return true; 1537 /* Make sure address is word alignment. 1538 Currently we do not have 64-bit load/store yet, 1539 so we will use two 32-bit load/store instructions to do 1540 memory access and they are single word alignment. */ 1541 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) 1542 return true; 1543 } 1544 break; 1545 1546 default: 1547 return false; 1548 } 1549 1550 return false; 1551 1552 case MULT: 1553 op0 = XEXP (index, 0); 1554 op1 = XEXP (index, 1); 1555 1556 if (REG_P (op0) && CONST_INT_P (op1)) 1557 { 1558 int multiplier; 1559 multiplier = INTVAL (op1); 1560 1561 /* We only allow (mult reg const_int_1), (mult reg const_int_2), 1562 (mult reg const_int_4) or (mult reg const_int_8). */ 1563 if (multiplier != 1 && multiplier != 2 1564 && multiplier != 4 && multiplier != 8) 1565 return false; 1566 1567 regno = REGNO (op0); 1568 /* Limit it in general registers if we are 1569 in reload pass or after reload pass. */ 1570 if(strict) 1571 return REGNO_OK_FOR_INDEX_P (regno); 1572 else 1573 return true; 1574 } 1575 1576 return false; 1577 1578 case ASHIFT: 1579 op0 = XEXP (index, 0); 1580 op1 = XEXP (index, 1); 1581 1582 if (REG_P (op0) && CONST_INT_P (op1)) 1583 { 1584 int sv; 1585 /* op1 is already the sv value for use to do left shift. */ 1586 sv = INTVAL (op1); 1587 1588 /* We only allow (ashift reg const_int_0) 1589 or (ashift reg const_int_1) or (ashift reg const_int_2) or 1590 (ashift reg const_int_3). */ 1591 if (sv != 0 && sv != 1 && sv !=2 && sv != 3) 1592 return false; 1593 1594 regno = REGNO (op0); 1595 /* Limit it in general registers if we are 1596 in reload pass or after reload pass. */ 1597 if(strict) 1598 return REGNO_OK_FOR_INDEX_P (regno); 1599 else 1600 return true; 1601 } 1602 1603 return false; 1604 1605 default: 1606 return false; 1607 } 1608} 1609 1610static void 1611nds32_register_pass ( 1612 rtl_opt_pass *(*make_pass_func) (gcc::context *), 1613 enum pass_positioning_ops pass_pos, 1614 const char *ref_pass_name) 1615{ 1616 opt_pass *new_opt_pass = make_pass_func (g); 1617 1618 struct register_pass_info insert_pass = 1619 { 1620 new_opt_pass, /* pass */ 1621 ref_pass_name, /* reference_pass_name */ 1622 1, /* ref_pass_instance_number */ 1623 pass_pos /* po_op */ 1624 }; 1625 1626 register_pass (&insert_pass); 1627} 1628 1629/* This function is called from nds32_option_override (). 1630 All new passes should be registered here. */ 1631static void 1632nds32_register_passes (void) 1633{ 1634 nds32_register_pass ( 1635 make_pass_nds32_fp_as_gp, 1636 PASS_POS_INSERT_BEFORE, 1637 "ira"); 1638 1639 nds32_register_pass ( 1640 make_pass_nds32_relax_opt, 1641 PASS_POS_INSERT_AFTER, 1642 "mach"); 1643} 1644 1645/* ------------------------------------------------------------------------ */ 1646 1647/* PART 3: Implement target hook stuff definitions. */ 1648 1649 1650/* Computing the Length of an Insn. 1651 Modifies the length assigned to instruction INSN. 1652 LEN is the initially computed length of the insn. */ 1653int 1654nds32_adjust_insn_length (rtx_insn *insn, int length) 1655{ 1656 int adjust_value = 0; 1657 switch (recog_memoized (insn)) 1658 { 1659 case CODE_FOR_call_internal: 1660 case CODE_FOR_call_value_internal: 1661 { 1662 if (NDS32_ALIGN_P ()) 1663 { 1664 rtx_insn *next_insn = next_active_insn (insn); 1665 if (next_insn && get_attr_length (next_insn) != 2) 1666 adjust_value += 2; 1667 } 1668 /* We need insert a nop after a noretun function call 1669 to prevent software breakpoint corrupt the next function. */ 1670 if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) 1671 { 1672 if (TARGET_16_BIT) 1673 adjust_value += 2; 1674 else 1675 adjust_value += 4; 1676 } 1677 } 1678 return length + adjust_value; 1679 1680 default: 1681 return length; 1682 } 1683} 1684 1685/* Storage Layout. */ 1686 1687/* This function will be called just before expansion into rtl. */ 1688static void 1689nds32_expand_to_rtl_hook (void) 1690{ 1691 /* We need to set strictly aligned situation. 1692 After that, the memory address checking in nds32_legitimate_address_p() 1693 will take alignment offset into consideration so that it will not create 1694 unaligned [base + offset] access during the rtl optimization. */ 1695 cfun->machine->strict_aligned_p = 1; 1696} 1697 1698 1699/* Register Usage. */ 1700 1701static void 1702nds32_conditional_register_usage (void) 1703{ 1704 int regno; 1705 1706 if (TARGET_LINUX_ABI) 1707 fixed_regs[TP_REGNUM] = 1; 1708 1709 if (TARGET_HARD_FLOAT) 1710 { 1711 for (regno = NDS32_FIRST_FPR_REGNUM; 1712 regno <= NDS32_LAST_FPR_REGNUM; regno++) 1713 { 1714 fixed_regs[regno] = 0; 1715 if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) 1716 call_used_regs[regno] = 1; 1717 else if (regno >= NDS32_FIRST_FPR_REGNUM + 22 1718 && regno < NDS32_FIRST_FPR_REGNUM + 48) 1719 call_used_regs[regno] = 1; 1720 else 1721 call_used_regs[regno] = 0; 1722 } 1723 } 1724 else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 1725 { 1726 for (regno = NDS32_FIRST_FPR_REGNUM; 1727 regno <= NDS32_LAST_FPR_REGNUM; 1728 regno++) 1729 fixed_regs[regno] = 0; 1730 } 1731} 1732 1733 1734/* Register Classes. */ 1735 1736static unsigned char 1737nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, 1738 machine_mode mode) 1739{ 1740 /* Return the maximum number of consecutive registers 1741 needed to represent "mode" in a register of "rclass". */ 1742 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 1743} 1744 1745static int 1746nds32_register_priority (int hard_regno) 1747{ 1748 /* Encourage to use r0-r7 for LRA when optimize for size. */ 1749 if (optimize_size) 1750 { 1751 if (hard_regno < 8) 1752 return 4; 1753 else if (hard_regno < 16) 1754 return 3; 1755 else if (hard_regno < 28) 1756 return 2; 1757 else 1758 return 1; 1759 } 1760 else 1761 { 1762 if (hard_regno > 27) 1763 return 1; 1764 else 1765 return 4; 1766 } 1767} 1768 1769static bool 1770nds32_can_change_mode_class (machine_mode from, 1771 machine_mode to, 1772 reg_class_t rclass) 1773{ 1774 /* Don't spill double-precision register to two singal-precision 1775 registers */ 1776 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 1777 && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) 1778 { 1779 return !reg_classes_intersect_p (rclass, FP_REGS); 1780 } 1781 1782 return true; 1783} 1784 1785 1786/* Stack Layout and Calling Conventions. */ 1787 1788/* There are three kinds of pointer concepts using in GCC compiler: 1789 1790 frame pointer: A pointer to the first location of local variables. 1791 stack pointer: A pointer to the top of a stack frame. 1792 argument pointer: A pointer to the incoming arguments. 1793 1794 In nds32 target calling convention, we are using 8-byte alignment. 1795 Besides, we would like to have each stack frame of a function includes: 1796 1797 [Block A] 1798 1. previous hard frame pointer 1799 2. return address 1800 3. callee-saved registers 1801 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() 1802 and save it at 1803 cfun->machine->callee_saved_area_padding_bytes) 1804 1805 [Block B] 1806 1. local variables 1807 2. spilling location 1808 3. <padding bytes> (it will be calculated by GCC itself) 1809 4. incoming arguments 1810 5. <padding bytes> (it will be calculated by GCC itself) 1811 1812 [Block C] 1813 1. <padding bytes> (it will be calculated by GCC itself) 1814 2. outgoing arguments 1815 1816 We 'wrap' these blocks together with 1817 hard frame pointer ($r28) and stack pointer ($r31). 1818 By applying the basic frame/stack/argument pointers concept, 1819 the layout of a stack frame shoule be like this: 1820 1821 | | 1822 old stack pointer -> ---- 1823 | | \ 1824 | | saved arguments for 1825 | | vararg functions 1826 | | / 1827 hard frame pointer -> -- 1828 & argument pointer | | \ 1829 | | previous hardware frame pointer 1830 | | return address 1831 | | callee-saved registers 1832 | | / 1833 frame pointer -> -- 1834 | | \ 1835 | | local variables 1836 | | and incoming arguments 1837 | | / 1838 -- 1839 | | \ 1840 | | outgoing 1841 | | arguments 1842 | | / 1843 stack pointer -> ---- 1844 1845 $SFP and $AP are used to represent frame pointer and arguments pointer, 1846 which will be both eliminated as hard frame pointer. */ 1847 1848/* -- Eliminating Frame Pointer and Arg Pointer. */ 1849 1850static bool 1851nds32_can_eliminate (const int from_reg, const int to_reg) 1852{ 1853 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 1854 return true; 1855 1856 if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) 1857 return true; 1858 1859 if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 1860 return true; 1861 1862 if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) 1863 return true; 1864 1865 return false; 1866} 1867 1868/* -- Passing Arguments in Registers. */ 1869 1870static rtx 1871nds32_function_arg (cumulative_args_t ca, const function_arg_info &arg) 1872{ 1873 unsigned int regno; 1874 CUMULATIVE_ARGS *cum = get_cumulative_args (ca); 1875 tree type = arg.type; 1876 machine_mode mode = arg.mode; 1877 1878 /* The last time this hook is called, 1879 it is called with an end marker. */ 1880 if (arg.end_marker_p ()) 1881 return NULL_RTX; 1882 1883 /* For nameless arguments, we need to take care it individually. */ 1884 if (!arg.named) 1885 { 1886 /* If we are under hard float abi, we have arguments passed on the 1887 stack and all situation can be handled by GCC itself. */ 1888 if (TARGET_HARD_FLOAT) 1889 return NULL_RTX; 1890 1891 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1892 { 1893 /* If we still have enough registers to pass argument, pick up 1894 next available register number. */ 1895 regno 1896 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1897 return gen_rtx_REG (mode, regno); 1898 } 1899 1900 /* No register available, return NULL_RTX. 1901 The compiler will use stack to pass argument instead. */ 1902 return NULL_RTX; 1903 } 1904 1905 /* The following is to handle named argument. 1906 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT 1907 are different. */ 1908 if (TARGET_HARD_FLOAT) 1909 { 1910 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR 1911 to pass argument. We have to further check TYPE and MODE so 1912 that we can determine which kind of register we shall use. */ 1913 1914 /* Note that we need to pass argument entirely in registers under 1915 hard float abi. */ 1916 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1917 && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type)) 1918 { 1919 /* Pick up the next available FPR register number. */ 1920 regno 1921 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type); 1922 return gen_rtx_REG (mode, regno); 1923 } 1924 else if (GET_MODE_CLASS (mode) != MODE_FLOAT 1925 && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1926 { 1927 /* Pick up the next available GPR register number. */ 1928 regno 1929 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1930 return gen_rtx_REG (mode, regno); 1931 } 1932 } 1933 else 1934 { 1935 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass 1936 argument. Since we allow to pass argument partially in registers, 1937 we can just return it if there are still registers available. */ 1938 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1939 { 1940 /* Pick up the next available register number. */ 1941 regno 1942 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1943 return gen_rtx_REG (mode, regno); 1944 } 1945 1946 } 1947 1948 /* No register available, return NULL_RTX. 1949 The compiler will use stack to pass argument instead. */ 1950 return NULL_RTX; 1951} 1952 1953static bool 1954nds32_must_pass_in_stack (const function_arg_info &arg) 1955{ 1956 /* Return true if a type must be passed in memory. 1957 If it is NOT using hard float abi, small aggregates can be 1958 passed in a register even we are calling a variadic function. 1959 So there is no need to take padding into consideration. */ 1960 if (TARGET_HARD_FLOAT) 1961 return must_pass_in_stack_var_size_or_pad (arg); 1962 else 1963 return must_pass_in_stack_var_size (arg); 1964} 1965 1966static int 1967nds32_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) 1968{ 1969 /* Returns the number of bytes at the beginning of an argument that 1970 must be put in registers. The value must be zero for arguments that are 1971 passed entirely in registers or that are entirely pushed on the stack. 1972 Besides, TARGET_FUNCTION_ARG for these arguments should return the 1973 first register to be used by the caller for this argument. */ 1974 unsigned int needed_reg_count; 1975 unsigned int remaining_reg_count; 1976 CUMULATIVE_ARGS *cum; 1977 1978 cum = get_cumulative_args (ca); 1979 1980 /* Under hard float abi, we better have argument entirely passed in 1981 registers or pushed on the stack so that we can reduce the complexity 1982 of dealing with cum->gpr_offset and cum->fpr_offset. */ 1983 if (TARGET_HARD_FLOAT) 1984 return 0; 1985 1986 /* If we have already runned out of argument registers, return zero 1987 so that the argument will be entirely pushed on the stack. */ 1988 if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) 1989 >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) 1990 return 0; 1991 1992 /* Calculate how many registers do we need for this argument. */ 1993 needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); 1994 1995 /* Calculate how many argument registers have left for passing argument. 1996 Note that we should count it from next available register number. */ 1997 remaining_reg_count 1998 = NDS32_MAX_GPR_REGS_FOR_ARGS 1999 - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, 2000 arg.mode, arg.type) 2001 - NDS32_GPR_ARG_FIRST_REGNUM); 2002 2003 /* Note that we have to return the nubmer of bytes, not registers count. */ 2004 if (needed_reg_count > remaining_reg_count) 2005 return remaining_reg_count * UNITS_PER_WORD; 2006 2007 return 0; 2008} 2009 2010static void 2011nds32_function_arg_advance (cumulative_args_t ca, 2012 const function_arg_info &arg) 2013{ 2014 CUMULATIVE_ARGS *cum = get_cumulative_args (ca); 2015 tree type = arg.type; 2016 machine_mode mode = arg.mode; 2017 2018 if (arg.named) 2019 { 2020 /* We need to further check TYPE and MODE so that we can determine 2021 which kind of register we shall advance. */ 2022 2023 /* Under hard float abi, we may advance FPR registers. */ 2024 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 2025 { 2026 cum->fpr_offset 2027 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type) 2028 - NDS32_FPR_ARG_FIRST_REGNUM 2029 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2030 } 2031 else 2032 { 2033 cum->gpr_offset 2034 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) 2035 - NDS32_GPR_ARG_FIRST_REGNUM 2036 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2037 } 2038 } 2039 else 2040 { 2041 /* If this nameless argument is NOT under TARGET_HARD_FLOAT, 2042 we can advance next register as well so that caller is 2043 able to pass arguments in registers and callee must be 2044 in charge of pushing all of them into stack. */ 2045 if (!TARGET_HARD_FLOAT) 2046 { 2047 cum->gpr_offset 2048 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) 2049 - NDS32_GPR_ARG_FIRST_REGNUM 2050 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2051 } 2052 } 2053} 2054 2055static unsigned int 2056nds32_function_arg_boundary (machine_mode mode, const_tree type) 2057{ 2058 return (nds32_needs_double_word_align (mode, type) 2059 ? NDS32_DOUBLE_WORD_ALIGNMENT 2060 : PARM_BOUNDARY); 2061} 2062 2063bool 2064nds32_vector_mode_supported_p (machine_mode mode) 2065{ 2066 if (mode == V4QImode 2067 || mode == V2HImode) 2068 return NDS32_EXT_DSP_P (); 2069 2070 return false; 2071} 2072 2073/* -- How Scalar Function Values Are Returned. */ 2074 2075static rtx 2076nds32_function_value (const_tree ret_type, 2077 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 2078 bool outgoing ATTRIBUTE_UNUSED) 2079{ 2080 machine_mode mode; 2081 int unsignedp; 2082 2083 mode = TYPE_MODE (ret_type); 2084 unsignedp = TYPE_UNSIGNED (ret_type); 2085 2086 if (INTEGRAL_TYPE_P (ret_type)) 2087 mode = promote_mode (ret_type, mode, &unsignedp); 2088 2089 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) 2090 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); 2091 else 2092 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); 2093} 2094 2095static rtx 2096nds32_libcall_value (machine_mode mode, 2097 const_rtx fun ATTRIBUTE_UNUSED) 2098{ 2099 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) 2100 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); 2101 2102 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); 2103} 2104 2105static bool 2106nds32_function_value_regno_p (const unsigned int regno) 2107{ 2108 if (regno == NDS32_GPR_RET_FIRST_REGNUM 2109 || (TARGET_HARD_FLOAT 2110 && regno == NDS32_FPR_RET_FIRST_REGNUM)) 2111 return true; 2112 2113 return false; 2114} 2115 2116/* -- How Large Values Are Returned. */ 2117 2118static bool 2119nds32_return_in_memory (const_tree type, 2120 const_tree fntype ATTRIBUTE_UNUSED) 2121{ 2122 /* Note that int_size_in_bytes can return -1 if the size can vary 2123 or is larger than an integer. */ 2124 HOST_WIDE_INT size = int_size_in_bytes (type); 2125 2126 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers, 2127 the return value is supposed to be in memory. We need to be aware of 2128 that the size may be -1. */ 2129 if (TREE_CODE (type) == COMPLEX_TYPE) 2130 if (size < 0 || size > 2 * UNITS_PER_WORD) 2131 return true; 2132 2133 /* If it is BLKmode and the total size cannot be hold within two registers, 2134 the return value is supposed to be in memory. We need to be aware of 2135 that the size may be -1. */ 2136 if (TYPE_MODE (type) == BLKmode) 2137 if (size < 0 || size > 2 * UNITS_PER_WORD) 2138 return true; 2139 2140 /* For other cases, having result in memory is unnecessary. */ 2141 return false; 2142} 2143 2144/* -- Function Entry and Exit. */ 2145 2146/* The content produced from this function 2147 will be placed before prologue body. */ 2148static void 2149nds32_asm_function_prologue (FILE *file) 2150{ 2151 int r; 2152 const char *func_name; 2153 tree attrs; 2154 tree name; 2155 2156 /* All stack frame information is supposed to be 2157 already computed when expanding prologue. 2158 The result is in cfun->machine. 2159 DO NOT call nds32_compute_stack_frame() here 2160 because it may corrupt the essential information. */ 2161 2162 fprintf (file, "\t! BEGIN PROLOGUE\n"); 2163 fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); 2164 fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); 2165 fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); 2166 fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); 2167 2168 /* Use df_regs_ever_live_p() to detect if the register 2169 is ever used in the current function. */ 2170 fprintf (file, "\t! registers ever_live: "); 2171 for (r = 0; r < 65; r++) 2172 { 2173 if (df_regs_ever_live_p (r)) 2174 fprintf (file, "%s, ", reg_names[r]); 2175 } 2176 fputc ('\n', file); 2177 2178 /* Display the attributes of this function. */ 2179 fprintf (file, "\t! function attributes: "); 2180 /* Get the attributes tree list. 2181 Note that GCC builds attributes list with reverse order. */ 2182 attrs = DECL_ATTRIBUTES (current_function_decl); 2183 2184 /* If there is no any attribute, print out "None". */ 2185 if (!attrs) 2186 fprintf (file, "None"); 2187 2188 /* If there are some attributes, try if we need to 2189 construct isr vector information. */ 2190 func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); 2191 nds32_construct_isr_vectors_information (attrs, func_name); 2192 2193 /* Display all attributes of this function. */ 2194 while (attrs) 2195 { 2196 name = TREE_PURPOSE (attrs); 2197 fprintf (file, "%s ", IDENTIFIER_POINTER (name)); 2198 2199 /* Pick up the next attribute. */ 2200 attrs = TREE_CHAIN (attrs); 2201 } 2202 fputc ('\n', file); 2203} 2204 2205/* After rtl prologue has been expanded, this function is used. */ 2206static void 2207nds32_asm_function_end_prologue (FILE *file) 2208{ 2209 fprintf (file, "\t! END PROLOGUE\n"); 2210} 2211 2212/* Before rtl epilogue has been expanded, this function is used. */ 2213static void 2214nds32_asm_function_begin_epilogue (FILE *file) 2215{ 2216 fprintf (file, "\t! BEGIN EPILOGUE\n"); 2217} 2218 2219/* The content produced from this function 2220 will be placed after epilogue body. */ 2221static void 2222nds32_asm_function_epilogue (FILE *file) 2223{ 2224 fprintf (file, "\t! END EPILOGUE\n"); 2225} 2226 2227static void 2228nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, 2229 HOST_WIDE_INT delta, 2230 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2231 tree function) 2232{ 2233 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); 2234 int this_regno; 2235 2236 assemble_start_function (thunk, fnname); 2237 /* Make sure unwind info is emitted for the thunk if needed. */ 2238 final_start_function (emit_barrier (), file, 1); 2239 2240 this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) 2241 ? 1 2242 : 0); 2243 2244 if (flag_pic) 2245 { 2246 fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); 2247 fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", 2248 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2249 fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", 2250 reg_names [PIC_OFFSET_TABLE_REGNUM], 2251 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2252 2253 if (TARGET_ISA_V3) 2254 fprintf (file, "\tadd5.pc\t$gp\n"); 2255 else 2256 { 2257 fprintf (file, "\tmfusr\t$ta, $pc\n"); 2258 fprintf (file, "\tadd\t%s, $ta, %s\n", 2259 reg_names [PIC_OFFSET_TABLE_REGNUM], 2260 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2261 } 2262 } 2263 2264 if (delta != 0) 2265 { 2266 if (satisfies_constraint_Is15 (GEN_INT (delta))) 2267 { 2268 fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n", 2269 this_regno, this_regno, delta); 2270 } 2271 else if (satisfies_constraint_Is20 (GEN_INT (delta))) 2272 { 2273 fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta); 2274 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); 2275 } 2276 else 2277 { 2278 fprintf (file, 2279 "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n", 2280 delta); 2281 fprintf (file, 2282 "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n", 2283 delta); 2284 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); 2285 } 2286 } 2287 2288 if (flag_pic) 2289 { 2290 fprintf (file, "\tla\t$ta, "); 2291 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); 2292 fprintf (file, "@PLT\n"); 2293 fprintf (file, "\t! epilogue\n"); 2294 fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", 2295 reg_names[PIC_OFFSET_TABLE_REGNUM], 2296 reg_names[STACK_POINTER_REGNUM]); 2297 fprintf (file, "\tbr\t$ta\n"); 2298 } 2299 else 2300 { 2301 fprintf (file, "\tb\t"); 2302 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); 2303 fprintf (file, "\n"); 2304 } 2305 2306 final_end_function (); 2307 assemble_end_function (thunk, fnname); 2308} 2309 2310/* -- Permitting tail calls. */ 2311 2312/* Return true if it is ok to do sibling call optimization. */ 2313static bool 2314nds32_function_ok_for_sibcall (tree decl, 2315 tree exp ATTRIBUTE_UNUSED) 2316{ 2317 /* The DECL is NULL if it is an indirect call. */ 2318 2319 /* 1. Do not apply sibling call if -mv3push is enabled, 2320 because pop25 instruction also represents return behavior. 2321 2. If this function is a isr function, do not apply sibling call 2322 because it may perform the behavior that user does not expect. 2323 3. If this function is a variadic function, do not apply sibling call 2324 because the stack layout may be a mess. 2325 4. We don't want to apply sibling call optimization for indirect 2326 sibcall because the pop behavior in epilogue may pollute the 2327 content of caller-saved regsiter when the register is used for 2328 indirect sibcall. 2329 5. In pic mode, it may use some registers for PLT call. */ 2330 return (!TARGET_V3PUSH 2331 && !nds32_isr_function_p (current_function_decl) 2332 && (cfun->machine->va_args_size == 0) 2333 && decl 2334 && !flag_pic); 2335} 2336 2337/* Determine whether we need to enable warning for function return check. */ 2338static bool 2339nds32_warn_func_return (tree decl) 2340{ 2341 /* Naked functions are implemented entirely in assembly, including the 2342 return sequence, so suppress warnings about this. */ 2343 return !nds32_naked_function_p (decl); 2344} 2345 2346 2347/* Implementing the Varargs Macros. */ 2348 2349static void 2350nds32_setup_incoming_varargs (cumulative_args_t ca, 2351 const function_arg_info &arg, 2352 int *pretend_args_size, 2353 int second_time ATTRIBUTE_UNUSED) 2354{ 2355 unsigned int total_args_regs; 2356 unsigned int num_of_used_regs; 2357 unsigned int remaining_reg_count; 2358 CUMULATIVE_ARGS *cum; 2359 2360 /* If we are under hard float abi, we do not need to set *pretend_args_size. 2361 So that all nameless arguments are pushed by caller and all situation 2362 can be handled by GCC itself. */ 2363 if (TARGET_HARD_FLOAT) 2364 return; 2365 2366 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, 2367 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. 2368 However, for nameless(anonymous) arguments, we should push them on the 2369 stack so that all the nameless arguments appear to have been passed 2370 consecutively in the memory for accessing. Hence, we need to check and 2371 exclude the registers that are used for named arguments. */ 2372 2373 cum = get_cumulative_args (ca); 2374 2375 /* ARG describes the last argument. 2376 We need those information to determine the remaining registers 2377 for varargs. */ 2378 total_args_regs 2379 = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; 2380 num_of_used_regs 2381 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) 2382 + NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); 2383 2384 remaining_reg_count = total_args_regs - num_of_used_regs; 2385 *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; 2386 2387 return; 2388} 2389 2390static bool 2391nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) 2392{ 2393 /* If this hook returns true, the named argument of FUNCTION_ARG is always 2394 true for named arguments, and false for unnamed arguments. */ 2395 return true; 2396} 2397 2398 2399/* Trampolines for Nested Functions. */ 2400 2401static void 2402nds32_asm_trampoline_template (FILE *f) 2403{ 2404 if (TARGET_REDUCED_REGS) 2405 { 2406 /* Trampoline is not supported on reduced-set registers yet. */ 2407 sorry ("a nested function is not supported for reduced registers"); 2408 } 2409 else 2410 { 2411 asm_fprintf (f, "\t! Trampoline code template\n"); 2412 asm_fprintf (f, "\t! This code fragment will be copied " 2413 "into stack on demand\n"); 2414 2415 asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); 2416 asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " 2417 "! load nested function address\n"); 2418 asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " 2419 "! load chain_value\n"); 2420 asm_fprintf (f, "\tjr\t$r15\n"); 2421 } 2422 2423 /* Preserve space ($pc + 16) for saving chain_value, 2424 nds32_trampoline_init will fill the value in this slot. */ 2425 asm_fprintf (f, "\t! space for saving chain_value\n"); 2426 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); 2427 2428 /* Preserve space ($pc + 20) for saving nested function address, 2429 nds32_trampoline_init will fill the value in this slot. */ 2430 asm_fprintf (f, "\t! space for saving nested function address\n"); 2431 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); 2432} 2433 2434/* Emit RTL insns to initialize the variable parts of a trampoline. */ 2435static void 2436nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 2437{ 2438 int i; 2439 2440 /* Nested function address. */ 2441 rtx fnaddr; 2442 /* The memory rtx that is going to 2443 be filled with chain_value. */ 2444 rtx chain_value_mem; 2445 /* The memory rtx that is going to 2446 be filled with nested function address. */ 2447 rtx nested_func_mem; 2448 2449 /* Start address of trampoline code in stack, for doing cache sync. */ 2450 rtx sync_cache_addr; 2451 /* Temporary register for sync instruction. */ 2452 rtx tmp_reg; 2453 /* Instruction-cache sync instruction, 2454 requesting an argument as starting address. */ 2455 rtx isync_insn; 2456 /* For convenience reason of doing comparison. */ 2457 int tramp_align_in_bytes; 2458 2459 /* Trampoline is not supported on reduced-set registers yet. */ 2460 if (TARGET_REDUCED_REGS) 2461 sorry ("a nested function is not supported for reduced registers"); 2462 2463 /* STEP 1: Copy trampoline code template into stack, 2464 fill up essential data into stack. */ 2465 2466 /* Extract nested function address rtx. */ 2467 fnaddr = XEXP (DECL_RTL (fndecl), 0); 2468 2469 /* m_tramp is memory rtx that is going to be filled with trampoline code. 2470 We have nds32_asm_trampoline_template() to emit template pattern. */ 2471 emit_block_move (m_tramp, assemble_trampoline_template (), 2472 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 2473 2474 /* After copying trampoline code into stack, 2475 fill chain_value into stack. */ 2476 chain_value_mem = adjust_address (m_tramp, SImode, 16); 2477 emit_move_insn (chain_value_mem, chain_value); 2478 /* After copying trampoline code int stack, 2479 fill nested function address into stack. */ 2480 nested_func_mem = adjust_address (m_tramp, SImode, 20); 2481 emit_move_insn (nested_func_mem, fnaddr); 2482 2483 /* STEP 2: Sync instruction-cache. */ 2484 2485 /* We have successfully filled trampoline code into stack. 2486 However, in order to execute code in stack correctly, 2487 we must sync instruction cache. */ 2488 sync_cache_addr = XEXP (m_tramp, 0); 2489 tmp_reg = gen_reg_rtx (SImode); 2490 isync_insn = gen_unspec_volatile_isync (tmp_reg); 2491 2492 /* Because nds32_cache_block_size is in bytes, 2493 we get trampoline alignment in bytes for convenient comparison. */ 2494 tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; 2495 2496 if (tramp_align_in_bytes >= nds32_cache_block_size 2497 && (tramp_align_in_bytes % nds32_cache_block_size) == 0) 2498 { 2499 /* Under this condition, the starting address of trampoline 2500 must be aligned to the starting address of each cache block 2501 and we do not have to worry about cross-boundary issue. */ 2502 for (i = 0; 2503 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) 2504 / nds32_cache_block_size; 2505 i++) 2506 { 2507 emit_move_insn (tmp_reg, 2508 plus_constant (Pmode, sync_cache_addr, 2509 nds32_cache_block_size * i)); 2510 emit_insn (isync_insn); 2511 } 2512 } 2513 else if (TRAMPOLINE_SIZE > nds32_cache_block_size) 2514 { 2515 /* The starting address of trampoline code 2516 may not be aligned to the cache block, 2517 so the trampoline code may be across two cache block. 2518 We need to sync the last element, which is 4-byte size, 2519 of trampoline template. */ 2520 for (i = 0; 2521 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) 2522 / nds32_cache_block_size; 2523 i++) 2524 { 2525 emit_move_insn (tmp_reg, 2526 plus_constant (Pmode, sync_cache_addr, 2527 nds32_cache_block_size * i)); 2528 emit_insn (isync_insn); 2529 } 2530 2531 /* The last element of trampoline template is 4-byte size. */ 2532 emit_move_insn (tmp_reg, 2533 plus_constant (Pmode, sync_cache_addr, 2534 TRAMPOLINE_SIZE - 4)); 2535 emit_insn (isync_insn); 2536 } 2537 else 2538 { 2539 /* This is the simplest case. 2540 Because TRAMPOLINE_SIZE is less than or 2541 equal to nds32_cache_block_size, 2542 we can just sync start address and 2543 the last element of trampoline code. */ 2544 2545 /* Sync starting address of tampoline code. */ 2546 emit_move_insn (tmp_reg, sync_cache_addr); 2547 emit_insn (isync_insn); 2548 /* Sync the last element, which is 4-byte size, 2549 of trampoline template. */ 2550 emit_move_insn (tmp_reg, 2551 plus_constant (Pmode, sync_cache_addr, 2552 TRAMPOLINE_SIZE - 4)); 2553 emit_insn (isync_insn); 2554 } 2555 2556 /* Set instruction serialization barrier 2557 to guarantee the correct operations. */ 2558 emit_insn (gen_unspec_volatile_isb ()); 2559} 2560 2561 2562/* Addressing Modes. */ 2563 2564static bool 2565nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) 2566{ 2567 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 2568 { 2569 /* When using floating-point instructions, 2570 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */ 2571 if ((mode == DFmode || mode == SFmode) 2572 && (GET_CODE (x) == SYMBOL_REF 2573 || GET_CODE(x) == CONST)) 2574 return false; 2575 2576 /* Allow [post_modify] addressing mode, when using FPU instructions. */ 2577 if (GET_CODE (x) == POST_MODIFY 2578 && mode == DFmode) 2579 { 2580 if (GET_CODE (XEXP (x, 0)) == REG 2581 && GET_CODE (XEXP (x, 1)) == PLUS) 2582 { 2583 rtx plus_op = XEXP (x, 1); 2584 rtx op0 = XEXP (plus_op, 0); 2585 rtx op1 = XEXP (plus_op, 1); 2586 2587 if (nds32_address_register_rtx_p (op0, strict) 2588 && CONST_INT_P (op1)) 2589 { 2590 if (satisfies_constraint_Is14 (op1)) 2591 { 2592 /* If it is not under strictly aligned situation, 2593 we can return true without checking alignment. */ 2594 if (!cfun->machine->strict_aligned_p) 2595 return true; 2596 /* Make sure address is word alignment. 2597 Currently we do not have 64-bit load/store yet, 2598 so we will use two 32-bit load/store instructions to do 2599 memory access and they are single word alignment. */ 2600 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1))) 2601 return true; 2602 } 2603 } 2604 } 2605 } 2606 } 2607 2608 /* For (mem:DI addr) or (mem:DF addr) case, 2609 we only allow 'addr' to be [reg], [symbol_ref], 2610 [const], or [reg + const_int] pattern. */ 2611 if (mode == DImode || mode == DFmode) 2612 { 2613 /* Allow [Reg + const_int] addressing mode. */ 2614 if (GET_CODE (x) == PLUS) 2615 { 2616 if (nds32_address_register_rtx_p (XEXP (x, 0), strict) 2617 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) 2618 && CONST_INT_P (XEXP (x, 1))) 2619 return true; 2620 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) 2621 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) 2622 && CONST_INT_P (XEXP (x, 0))) 2623 return true; 2624 } 2625 2626 /* Allow [post_inc] and [post_dec] addressing mode. */ 2627 if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) 2628 { 2629 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) 2630 return true; 2631 } 2632 2633 /* Now check [reg], [symbol_ref], and [const]. */ 2634 if (GET_CODE (x) != REG 2635 && GET_CODE (x) != SYMBOL_REF 2636 && GET_CODE (x) != CONST) 2637 return false; 2638 } 2639 2640 /* Check if 'x' is a valid address. */ 2641 switch (GET_CODE (x)) 2642 { 2643 case REG: 2644 /* (mem (reg A)) => [Ra] */ 2645 return nds32_address_register_rtx_p (x, strict); 2646 2647 case SYMBOL_REF: 2648 /* (mem (symbol_ref A)) => [symbol_ref] */ 2649 2650 if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) 2651 return false; 2652 2653 if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) 2654 return false; 2655 2656 /* If -mcmodel=large, the 'symbol_ref' is not a valid address 2657 during or after LRA/reload phase. */ 2658 if (TARGET_CMODEL_LARGE 2659 && (reload_completed 2660 || reload_in_progress 2661 || lra_in_progress)) 2662 return false; 2663 /* If -mcmodel=medium and the symbol references to rodata section, 2664 the 'symbol_ref' is not a valid address during or after 2665 LRA/reload phase. */ 2666 if (TARGET_CMODEL_MEDIUM 2667 && (NDS32_SYMBOL_REF_RODATA_P (x) 2668 || CONSTANT_POOL_ADDRESS_P (x)) 2669 && (reload_completed 2670 || reload_in_progress 2671 || lra_in_progress)) 2672 return false; 2673 2674 return true; 2675 2676 case CONST: 2677 /* (mem (const (...))) 2678 => [ + const_addr ], where const_addr = symbol_ref + const_int */ 2679 if (GET_CODE (XEXP (x, 0)) == PLUS) 2680 { 2681 rtx plus_op = XEXP (x, 0); 2682 2683 rtx op0 = XEXP (plus_op, 0); 2684 rtx op1 = XEXP (plus_op, 1); 2685 2686 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) 2687 { 2688 /* Now we see the [ + const_addr ] pattern, but we need 2689 some further checking. */ 2690 2691 if (flag_pic || SYMBOL_REF_TLS_MODEL (op0)) 2692 return false; 2693 2694 /* If -mcmodel=large, the 'const_addr' is not a valid address 2695 during or after LRA/reload phase. */ 2696 if (TARGET_CMODEL_LARGE 2697 && (reload_completed 2698 || reload_in_progress 2699 || lra_in_progress)) 2700 return false; 2701 /* If -mcmodel=medium and the symbol references to rodata section, 2702 the 'const_addr' is not a valid address during or after 2703 LRA/reload phase. */ 2704 if (TARGET_CMODEL_MEDIUM 2705 && NDS32_SYMBOL_REF_RODATA_P (op0) 2706 && (reload_completed 2707 || reload_in_progress 2708 || lra_in_progress)) 2709 return false; 2710 2711 /* At this point we can make sure 'const_addr' is a 2712 valid address. */ 2713 return true; 2714 } 2715 } 2716 2717 return false; 2718 2719 case POST_MODIFY: 2720 /* (mem (post_modify (reg) (plus (reg) (reg)))) 2721 => [Ra], Rb */ 2722 /* (mem (post_modify (reg) (plus (reg) (const_int)))) 2723 => [Ra], const_int */ 2724 if (GET_CODE (XEXP (x, 0)) == REG 2725 && GET_CODE (XEXP (x, 1)) == PLUS) 2726 { 2727 rtx plus_op = XEXP (x, 1); 2728 2729 rtx op0 = XEXP (plus_op, 0); 2730 rtx op1 = XEXP (plus_op, 1); 2731 2732 if (nds32_address_register_rtx_p (op0, strict) 2733 && nds32_legitimate_index_p (mode, op1, strict)) 2734 return true; 2735 else 2736 return false; 2737 } 2738 2739 return false; 2740 2741 case POST_INC: 2742 case POST_DEC: 2743 /* (mem (post_inc reg)) => [Ra], 1/2/4 */ 2744 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ 2745 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. 2746 We only need to deal with register Ra. */ 2747 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) 2748 return true; 2749 else 2750 return false; 2751 2752 case PLUS: 2753 /* (mem (plus reg const_int)) 2754 => [Ra + imm] */ 2755 /* (mem (plus reg reg)) 2756 => [Ra + Rb] */ 2757 /* (mem (plus (mult reg const_int) reg)) 2758 => [Ra + Rb << sv] */ 2759 if (nds32_address_register_rtx_p (XEXP (x, 0), strict) 2760 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) 2761 return true; 2762 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) 2763 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) 2764 return true; 2765 else 2766 return false; 2767 2768 case LO_SUM: 2769 /* (mem (lo_sum (reg) (symbol_ref))) */ 2770 /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ 2771 /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ 2772 /* The LO_SUM is a valid address if and only if we would like to 2773 generate 32-bit full address memory access with any of following 2774 circumstance: 2775 1. -mcmodel=large. 2776 2. -mcmodel=medium and the symbol_ref references to rodata. */ 2777 { 2778 rtx sym = NULL_RTX; 2779 2780 if (flag_pic) 2781 return false; 2782 2783 if (!REG_P (XEXP (x, 0))) 2784 return false; 2785 2786 if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) 2787 sym = XEXP (x, 1); 2788 else if (GET_CODE (XEXP (x, 1)) == CONST) 2789 { 2790 rtx plus = XEXP(XEXP (x, 1), 0); 2791 if (GET_CODE (plus) == PLUS) 2792 sym = XEXP (plus, 0); 2793 else if (GET_CODE (plus) == UNSPEC) 2794 sym = XVECEXP (plus, 0, 0); 2795 } 2796 else 2797 return false; 2798 2799 gcc_assert (GET_CODE (sym) == SYMBOL_REF); 2800 2801 if (TARGET_ICT_MODEL_LARGE 2802 && nds32_indirect_call_referenced_p (sym)) 2803 return true; 2804 2805 if (TARGET_CMODEL_LARGE) 2806 return true; 2807 else if (TARGET_CMODEL_MEDIUM 2808 && NDS32_SYMBOL_REF_RODATA_P (sym)) 2809 return true; 2810 else 2811 return false; 2812 } 2813 2814 default: 2815 return false; 2816 } 2817} 2818 2819static rtx 2820nds32_legitimize_address (rtx x, 2821 rtx oldx ATTRIBUTE_UNUSED, 2822 machine_mode mode ATTRIBUTE_UNUSED) 2823{ 2824 if (nds32_tls_referenced_p (x)) 2825 x = nds32_legitimize_tls_address (x); 2826 else if (flag_pic && SYMBOLIC_CONST_P (x)) 2827 x = nds32_legitimize_pic_address (x); 2828 else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) 2829 x = nds32_legitimize_ict_address (x); 2830 2831 return x; 2832} 2833 2834static bool 2835nds32_legitimate_constant_p (machine_mode mode, rtx x) 2836{ 2837 switch (GET_CODE (x)) 2838 { 2839 case CONST_DOUBLE: 2840 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 2841 && (mode == DFmode || mode == SFmode)) 2842 return false; 2843 break; 2844 case CONST: 2845 x = XEXP (x, 0); 2846 2847 if (GET_CODE (x) == PLUS) 2848 { 2849 if (!CONST_INT_P (XEXP (x, 1))) 2850 return false; 2851 x = XEXP (x, 0); 2852 } 2853 2854 if (GET_CODE (x) == UNSPEC) 2855 { 2856 switch (XINT (x, 1)) 2857 { 2858 case UNSPEC_GOT: 2859 case UNSPEC_GOTOFF: 2860 case UNSPEC_PLT: 2861 case UNSPEC_TLSGD: 2862 case UNSPEC_TLSLD: 2863 case UNSPEC_TLSIE: 2864 case UNSPEC_TLSLE: 2865 case UNSPEC_ICT: 2866 return false; 2867 default: 2868 return true; 2869 } 2870 } 2871 break; 2872 case SYMBOL_REF: 2873 /* TLS symbols need a call to resolve in 2874 precompute_register_parameters. */ 2875 if (SYMBOL_REF_TLS_MODEL (x)) 2876 return false; 2877 break; 2878 default: 2879 return true; 2880 } 2881 2882 return true; 2883} 2884 2885/* Reorgnize the UNSPEC CONST and return its direct symbol. */ 2886static rtx 2887nds32_delegitimize_address (rtx x) 2888{ 2889 x = delegitimize_mem_from_attrs (x); 2890 2891 if (GET_CODE(x) == CONST) 2892 { 2893 rtx inner = XEXP (x, 0); 2894 2895 /* Handle for GOTOFF. */ 2896 if (GET_CODE (inner) == PLUS) 2897 inner = XEXP (inner, 0); 2898 2899 if (GET_CODE (inner) == UNSPEC) 2900 { 2901 switch (XINT (inner, 1)) 2902 { 2903 case UNSPEC_GOTINIT: 2904 case UNSPEC_GOT: 2905 case UNSPEC_GOTOFF: 2906 case UNSPEC_PLT: 2907 case UNSPEC_TLSGD: 2908 case UNSPEC_TLSLD: 2909 case UNSPEC_TLSIE: 2910 case UNSPEC_TLSLE: 2911 case UNSPEC_ICT: 2912 x = XVECEXP (inner, 0, 0); 2913 break; 2914 default: 2915 break; 2916 } 2917 } 2918 } 2919 return x; 2920} 2921 2922static machine_mode 2923nds32_vectorize_preferred_simd_mode (scalar_mode mode) 2924{ 2925 if (!NDS32_EXT_DSP_P ()) 2926 return word_mode; 2927 2928 switch (mode) 2929 { 2930 case E_QImode: 2931 return V4QImode; 2932 case E_HImode: 2933 return V2HImode; 2934 default: 2935 return word_mode; 2936 } 2937} 2938 2939static bool 2940nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 2941{ 2942 switch (GET_CODE (x)) 2943 { 2944 case CONST: 2945 return !nds32_legitimate_constant_p (mode, x); 2946 case SYMBOL_REF: 2947 /* All symbols have to be accessed through gp-relative in PIC mode. */ 2948 /* We don't want to force symbol as constant pool in .text section, 2949 because we use the gp-relatived instruction to load in small 2950 or medium model. */ 2951 if (flag_pic 2952 || SYMBOL_REF_TLS_MODEL (x) 2953 || TARGET_CMODEL_SMALL 2954 || TARGET_CMODEL_MEDIUM) 2955 return true; 2956 break; 2957 case CONST_INT: 2958 case CONST_DOUBLE: 2959 if (flag_pic && (lra_in_progress || reload_completed)) 2960 return true; 2961 break; 2962 default: 2963 return false; 2964 } 2965 return false; 2966} 2967 2968 2969/* Condition Code Status. */ 2970 2971/* -- Representation of condition codes using registers. */ 2972 2973static void 2974nds32_canonicalize_comparison (int *code, 2975 rtx *op0 ATTRIBUTE_UNUSED, 2976 rtx *op1, 2977 bool op0_preserve_value ATTRIBUTE_UNUSED) 2978{ 2979 /* When the instruction combination pass tries to combine a comparison insn 2980 with its previous insns, it also transforms the operator in order to 2981 minimize its constant field. For example, it tries to transform a 2982 comparison insn from 2983 (set (reg:SI 54) 2984 (ltu:SI (reg:SI 52) 2985 (const_int 10 [0xa]))) 2986 to 2987 (set (reg:SI 54) 2988 (leu:SI (reg:SI 52) 2989 (const_int 9 [0x9]))) 2990 2991 However, the nds32 target only provides instructions supporting the LTU 2992 operation directly, and the implementation of the pattern "cbranchsi4" 2993 only expands the LTU form. In order to handle the non-LTU operations 2994 generated from passes other than the RTL expansion pass, we have to 2995 implement this hook to revert those changes. Since we only expand the LTU 2996 operator in the RTL expansion pass, we might only need to handle the LEU 2997 case, unless we find other optimization passes perform more aggressive 2998 transformations. */ 2999 3000 if (*code == LEU && CONST_INT_P (*op1)) 3001 { 3002 *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode); 3003 *code = LTU; 3004 } 3005} 3006 3007 3008/* Describing Relative Costs of Operations. */ 3009 3010static int 3011nds32_register_move_cost (machine_mode mode, 3012 reg_class_t from, 3013 reg_class_t to) 3014{ 3015 /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ 3016 if (TARGET_PIPELINE_GRAYWOLF) 3017 { 3018 if (GET_MODE_SIZE (mode) == 8) 3019 { 3020 /* DPR to GPR. */ 3021 if (from == FP_REGS && to != FP_REGS) 3022 return 3; 3023 /* GPR to DPR. */ 3024 if (from != FP_REGS && to == FP_REGS) 3025 return 2; 3026 } 3027 else 3028 { 3029 if ((from == FP_REGS && to != FP_REGS) 3030 || (from != FP_REGS && to == FP_REGS)) 3031 return 2; 3032 } 3033 } 3034 3035 if ((from == FP_REGS && to != FP_REGS) 3036 || (from != FP_REGS && to == FP_REGS)) 3037 return 3; 3038 else if (from == HIGH_REGS || to == HIGH_REGS) 3039 return optimize_size ? 6 : 2; 3040 else 3041 return 2; 3042} 3043 3044static int 3045nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 3046 reg_class_t rclass ATTRIBUTE_UNUSED, 3047 bool in ATTRIBUTE_UNUSED) 3048{ 3049 return 8; 3050} 3051 3052/* This target hook describes the relative costs of RTL expressions. 3053 Return 'true' when all subexpressions of x have been processed. 3054 Return 'false' to sum the costs of sub-rtx, plus cost of this operation. 3055 Refer to gcc/rtlanal.c for more information. */ 3056static bool 3057nds32_rtx_costs (rtx x, 3058 machine_mode mode, 3059 int outer_code, 3060 int opno, 3061 int *total, 3062 bool speed) 3063{ 3064 return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); 3065} 3066 3067static int 3068nds32_address_cost (rtx address, 3069 machine_mode mode, 3070 addr_space_t as, 3071 bool speed) 3072{ 3073 return nds32_address_cost_impl (address, mode, as, speed); 3074} 3075 3076 3077/* Dividing the Output into Sections (Texts, Data, . . . ). */ 3078 3079/* If references to a symbol or a constant must be treated differently 3080 depending on something about the variable or function named by the symbol 3081 (such as what section it is in), we use this hook to store flags 3082 in symbol_ref rtx. */ 3083static void 3084nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) 3085{ 3086 default_encode_section_info (decl, rtl, new_decl_p); 3087 3088 /* For the memory rtx, if it references to rodata section, we can store 3089 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the 3090 nds32_legitimate_address_p() can determine how to treat such symbol_ref 3091 based on -mcmodel=X and this information. */ 3092 if (MEM_P (rtl) && MEM_READONLY_P (rtl)) 3093 { 3094 rtx addr = XEXP (rtl, 0); 3095 3096 if (GET_CODE (addr) == SYMBOL_REF) 3097 { 3098 /* For (mem (symbol_ref X)) case. */ 3099 SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; 3100 } 3101 else if (GET_CODE (addr) == CONST 3102 && GET_CODE (XEXP (addr, 0)) == PLUS) 3103 { 3104 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ 3105 rtx plus_op = XEXP (addr, 0); 3106 rtx op0 = XEXP (plus_op, 0); 3107 rtx op1 = XEXP (plus_op, 1); 3108 3109 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) 3110 SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; 3111 } 3112 } 3113} 3114 3115 3116/* Defining the Output Assembler Language. */ 3117 3118/* -- The Overall Framework of an Assembler File. */ 3119 3120static void 3121nds32_asm_file_start (void) 3122{ 3123 default_file_start (); 3124 3125 if (flag_pic) 3126 fprintf (asm_out_file, "\t.pic\n"); 3127 3128 /* Tell assembler which ABI we are using. */ 3129 fprintf (asm_out_file, "\t! ABI version\n"); 3130 if (TARGET_HARD_FLOAT) 3131 fprintf (asm_out_file, "\t.abi_2fp_plus\n"); 3132 else 3133 fprintf (asm_out_file, "\t.abi_2\n"); 3134 3135 /* Tell assembler that this asm code is generated by compiler. */ 3136 fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); 3137 fprintf (asm_out_file, "\t.flag\tverbatim\n"); 3138 3139 /* Insert directive for linker to distinguish object's ict flag. */ 3140 if (!TARGET_LINUX_ABI) 3141 { 3142 if (TARGET_ICT_MODEL_LARGE) 3143 fprintf (asm_out_file, "\t.ict_model\tlarge\n"); 3144 else 3145 fprintf (asm_out_file, "\t.ict_model\tsmall\n"); 3146 } 3147 3148 /* We need to provide the size of each vector for interrupt handler 3149 under elf toolchain. */ 3150 if (!TARGET_LINUX_ABI) 3151 { 3152 fprintf (asm_out_file, "\t! This vector size directive is required " 3153 "for checking inconsistency on interrupt handler\n"); 3154 fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); 3155 } 3156 3157 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, 3158 the compiler may produce 'la $fp,_FP_BASE_' instruction 3159 at prologue for fp-as-gp optimization. 3160 We should emit weak reference of _FP_BASE_ to avoid undefined reference 3161 in case user does not pass '--relax' option to linker. */ 3162 if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) 3163 { 3164 fprintf (asm_out_file, "\t! This weak reference is required to do " 3165 "fp-as-gp link time optimization\n"); 3166 fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); 3167 } 3168 3169 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3170 3171 if (TARGET_ISA_V2) 3172 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); 3173 if (TARGET_ISA_V3) 3174 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); 3175 if (TARGET_ISA_V3M) 3176 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); 3177 3178 switch (nds32_cpu_option) 3179 { 3180 case CPU_N6: 3181 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); 3182 break; 3183 3184 case CPU_N7: 3185 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); 3186 break; 3187 3188 case CPU_N8: 3189 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); 3190 break; 3191 3192 case CPU_E8: 3193 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); 3194 break; 3195 3196 case CPU_N9: 3197 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); 3198 break; 3199 3200 case CPU_N10: 3201 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); 3202 break; 3203 3204 case CPU_GRAYWOLF: 3205 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); 3206 break; 3207 3208 case CPU_N12: 3209 case CPU_N13: 3210 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); 3211 break; 3212 3213 case CPU_SIMPLE: 3214 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); 3215 break; 3216 3217 default: 3218 gcc_unreachable (); 3219 } 3220 3221 if (TARGET_CMODEL_SMALL) 3222 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); 3223 if (TARGET_CMODEL_MEDIUM) 3224 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); 3225 if (TARGET_CMODEL_LARGE) 3226 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); 3227 3228 fprintf (asm_out_file, "\t! Endian setting\t: %s\n", 3229 ((TARGET_BIG_ENDIAN) ? "big-endian" 3230 : "little-endian")); 3231 fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n", 3232 ((TARGET_FPU_SINGLE) ? "Yes" 3233 : "No")); 3234 fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n", 3235 ((TARGET_FPU_DOUBLE) ? "Yes" 3236 : "No")); 3237 fprintf (asm_out_file, "\t! ABI version\t\t: %s\n", 3238 ((TARGET_HARD_FLOAT) ? "ABI2FP+" 3239 : "ABI2")); 3240 3241 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3242 3243 fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", 3244 ((TARGET_CMOV) ? "Yes" 3245 : "No")); 3246 fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", 3247 ((TARGET_EXT_PERF) ? "Yes" 3248 : "No")); 3249 fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", 3250 ((TARGET_EXT_PERF2) ? "Yes" 3251 : "No")); 3252 fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", 3253 ((TARGET_EXT_STRING) ? "Yes" 3254 : "No")); 3255 3256 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3257 3258 fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", 3259 ((TARGET_V3PUSH) ? "Yes" 3260 : "No")); 3261 fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", 3262 ((TARGET_16_BIT) ? "Yes" 3263 : "No")); 3264 fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", 3265 ((TARGET_REDUCED_REGS) ? "Yes" 3266 : "No")); 3267 3268 fprintf (asm_out_file, "\t! Support unaligned access\t\t: %s\n", 3269 (flag_unaligned_access ? "Yes" 3270 : "No")); 3271 3272 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3273 3274 if (optimize_size) 3275 fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); 3276 else if (optimize_fast) 3277 fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n"); 3278 else if (optimize_debug) 3279 fprintf (asm_out_file, "\t! Optimization level\t: -Og\n"); 3280 else 3281 fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); 3282 3283 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3284 3285 fprintf (asm_out_file, "\t! Cache block size\t: %d\n", 3286 nds32_cache_block_size); 3287 3288 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3289 3290 nds32_asm_file_start_for_isr (); 3291} 3292 3293static void 3294nds32_asm_file_end (void) 3295{ 3296 nds32_asm_file_end_for_isr (); 3297 3298 /* The NDS32 Linux stack is mapped non-executable by default, so add a 3299 .note.GNU-stack section. */ 3300 if (TARGET_LINUX_ABI) 3301 file_end_indicate_exec_stack (); 3302 3303 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3304} 3305 3306static bool 3307nds32_asm_output_addr_const_extra (FILE *file, rtx x) 3308{ 3309 if (GET_CODE (x) == UNSPEC) 3310 { 3311 switch (XINT (x, 1)) 3312 { 3313 case UNSPEC_GOTINIT: 3314 output_addr_const (file, XVECEXP (x, 0, 0)); 3315 break; 3316 case UNSPEC_GOTOFF: 3317 output_addr_const (file, XVECEXP (x, 0, 0)); 3318 fputs ("@GOTOFF", file); 3319 break; 3320 case UNSPEC_GOT: 3321 output_addr_const (file, XVECEXP (x, 0, 0)); 3322 fputs ("@GOT", file); 3323 break; 3324 case UNSPEC_PLT: 3325 output_addr_const (file, XVECEXP (x, 0, 0)); 3326 fputs ("@PLT", file); 3327 break; 3328 case UNSPEC_TLSGD: 3329 output_addr_const (file, XVECEXP (x, 0, 0)); 3330 fputs ("@TLSDESC", file); 3331 break; 3332 case UNSPEC_TLSLD: 3333 output_addr_const (file, XVECEXP (x, 0, 0)); 3334 fputs ("@TLSDESC", file); 3335 break; 3336 case UNSPEC_TLSIE: 3337 output_addr_const (file, XVECEXP (x, 0, 0)); 3338 fputs ("@GOTTPOFF", file); 3339 break; 3340 case UNSPEC_TLSLE: 3341 output_addr_const (file, XVECEXP (x, 0, 0)); 3342 fputs ("@TPOFF", file); 3343 break; 3344 case UNSPEC_ICT: 3345 output_addr_const (file, XVECEXP (x, 0, 0)); 3346 fputs ("@ICT", file); 3347 break; 3348 default: 3349 return false; 3350 } 3351 return true; 3352 } 3353 else 3354 return false; 3355} 3356 3357/* -- Output and Generation of Labels. */ 3358 3359static void 3360nds32_asm_globalize_label (FILE *stream, const char *name) 3361{ 3362 fputs ("\t.global\t", stream); 3363 assemble_name (stream, name); 3364 fputs ("\n", stream); 3365} 3366 3367/* -- Output of Assembler Instructions. */ 3368 3369static void 3370nds32_print_operand (FILE *stream, rtx x, int code) 3371{ 3372 HOST_WIDE_INT op_value = 0; 3373 HOST_WIDE_INT one_position; 3374 HOST_WIDE_INT zero_position; 3375 bool pick_lsb_p = false; 3376 bool pick_msb_p = false; 3377 int regno; 3378 3379 if (CONST_INT_P (x)) 3380 op_value = INTVAL (x); 3381 3382 switch (code) 3383 { 3384 case 0 : 3385 /* Do nothing special. */ 3386 break; 3387 3388 case 'b': 3389 /* Use exact_log2() to search the 0-bit position. */ 3390 gcc_assert (CONST_INT_P (x)); 3391 zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode)); 3392 gcc_assert (zero_position != -1); 3393 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position); 3394 3395 /* No need to handle following process, so return immediately. */ 3396 return; 3397 3398 case 'e': 3399 gcc_assert (MEM_P (x) 3400 && GET_CODE (XEXP (x, 0)) == PLUS 3401 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT); 3402 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1))); 3403 3404 /* No need to handle following process, so return immediately. */ 3405 return; 3406 3407 case 'v': 3408 gcc_assert (CONST_INT_P (x) 3409 && (INTVAL (x) == 0 3410 || INTVAL (x) == 8 3411 || INTVAL (x) == 16 3412 || INTVAL (x) == 24)); 3413 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); 3414 3415 /* No need to handle following process, so return immediately. */ 3416 return; 3417 3418 case 'B': 3419 /* Use exact_log2() to search the 1-bit position. */ 3420 gcc_assert (CONST_INT_P (x)); 3421 one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode)); 3422 gcc_assert (one_position != -1); 3423 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position); 3424 3425 /* No need to handle following process, so return immediately. */ 3426 return; 3427 3428 case 'L': 3429 /* X is supposed to be REG rtx. */ 3430 gcc_assert (REG_P (x)); 3431 /* Claim that we are going to pick LSB part of X. */ 3432 pick_lsb_p = true; 3433 break; 3434 3435 case 'H': 3436 /* X is supposed to be REG rtx. */ 3437 gcc_assert (REG_P (x)); 3438 /* Claim that we are going to pick MSB part of X. */ 3439 pick_msb_p = true; 3440 break; 3441 3442 case 'V': 3443 /* 'x' is supposed to be CONST_INT, get the value. */ 3444 gcc_assert (CONST_INT_P (x)); 3445 3446 /* According to the Andes architecture, 3447 the system/user register index range is 0 ~ 1023. 3448 In order to avoid conflict between user-specified-integer value 3449 and enum-specified-register value, 3450 the 'enum nds32_intrinsic_registers' value 3451 in nds32_intrinsic.h starts from 1024. */ 3452 if (op_value < 1024 && op_value >= 0) 3453 { 3454 /* If user gives integer value directly (0~1023), 3455 we just print out the value. */ 3456 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value); 3457 } 3458 else if (op_value < 0 3459 || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) 3460 + 1024)) 3461 { 3462 /* The enum index value for array size is out of range. */ 3463 error ("intrinsic register index is out of range"); 3464 } 3465 else 3466 { 3467 /* If user applies normal way with __NDS32_REG_XXX__ enum data, 3468 we can print out register name. Remember to substract 1024. */ 3469 fprintf (stream, "%s", 3470 nds32_intrinsic_register_names[op_value - 1024]); 3471 } 3472 3473 /* No need to handle following process, so return immediately. */ 3474 return; 3475 3476 case 'R': /* cctl valck */ 3477 /* Note the cctl divide to 5 group and share the same name table. */ 3478 if (op_value < 0 || op_value > 4) 3479 error ("CCTL intrinsic function subtype out of range!"); 3480 fprintf (stream, "%s", nds32_cctl_names[op_value]); 3481 return; 3482 3483 case 'T': /* cctl idxwbinv */ 3484 /* Note the cctl divide to 5 group and share the same name table. */ 3485 if (op_value < 0 || op_value > 4) 3486 error ("CCTL intrinsic function subtype out of range!"); 3487 fprintf (stream, "%s", nds32_cctl_names[op_value + 4]); 3488 return; 3489 3490 case 'U': /* cctl vawbinv */ 3491 /* Note the cctl divide to 5 group and share the same name table. */ 3492 if (op_value < 0 || op_value > 4) 3493 error ("CCTL intrinsic function subtype out of range!"); 3494 fprintf (stream, "%s", nds32_cctl_names[op_value + 8]); 3495 return; 3496 3497 case 'X': /* cctl idxread */ 3498 /* Note the cctl divide to 5 group and share the same name table. */ 3499 if (op_value < 0 || op_value > 4) 3500 error ("CCTL intrinsic function subtype out of range!"); 3501 fprintf (stream, "%s", nds32_cctl_names[op_value + 12]); 3502 return; 3503 3504 case 'W': /* cctl idxwitre */ 3505 /* Note the cctl divide to 5 group and share the same name table. */ 3506 if (op_value < 0 || op_value > 4) 3507 error ("CCTL intrinsic function subtype out of range!"); 3508 fprintf (stream, "%s", nds32_cctl_names[op_value + 16]); 3509 return; 3510 3511 case 'Z': /* dpref */ 3512 fprintf (stream, "%s", nds32_dpref_names[op_value]); 3513 return; 3514 3515 default : 3516 /* Unknown flag. */ 3517 output_operand_lossage ("invalid operand output code"); 3518 break; 3519 } 3520 3521 switch (GET_CODE (x)) 3522 { 3523 case LABEL_REF: 3524 output_addr_const (stream, x); 3525 break; 3526 3527 case SYMBOL_REF: 3528 output_addr_const (stream, x); 3529 3530 if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) 3531 fprintf (stream, "@ICT"); 3532 3533 break; 3534 3535 case REG: 3536 /* Print a Double-precision register name. */ 3537 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) 3538 && NDS32_IS_FPR_REGNUM (REGNO (x))) 3539 { 3540 regno = REGNO (x); 3541 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno)) 3542 { 3543 output_operand_lossage ("invalid operand for code '%c'", code); 3544 break; 3545 } 3546 fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1); 3547 break; 3548 } 3549 3550 /* Print LSB or MSB part of register pair if the 3551 constraint modifier 'L' or 'H' is specified. */ 3552 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) 3553 && NDS32_IS_GPR_REGNUM (REGNO (x))) 3554 { 3555 if ((pick_lsb_p && WORDS_BIG_ENDIAN) 3556 || (pick_msb_p && !WORDS_BIG_ENDIAN)) 3557 { 3558 /* If we would like to print out LSB register under big-endian, 3559 or print out MSB register under little-endian, we need to 3560 increase register number. */ 3561 regno = REGNO (x); 3562 regno++; 3563 fputs (reg_names[regno], stream); 3564 break; 3565 } 3566 } 3567 3568 /* Forbid using static chain register ($r16) 3569 on reduced-set registers configuration. */ 3570 if (TARGET_REDUCED_REGS 3571 && REGNO (x) == STATIC_CHAIN_REGNUM) 3572 sorry ("a nested function is not supported for reduced registers"); 3573 3574 /* Normal cases, print out register name. */ 3575 fputs (reg_names[REGNO (x)], stream); 3576 break; 3577 3578 case MEM: 3579 output_address (GET_MODE (x), XEXP (x, 0)); 3580 break; 3581 3582 case HIGH: 3583 if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE) 3584 { 3585 const REAL_VALUE_TYPE *rv; 3586 long val; 3587 gcc_assert (GET_MODE (x) == SFmode); 3588 3589 rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0)); 3590 REAL_VALUE_TO_TARGET_SINGLE (*rv, val); 3591 3592 fprintf (stream, "hi20(0x%lx)", val); 3593 } 3594 else 3595 gcc_unreachable (); 3596 break; 3597 3598 case CONST_DOUBLE: 3599 const REAL_VALUE_TYPE *rv; 3600 long val; 3601 gcc_assert (GET_MODE (x) == SFmode); 3602 3603 rv = CONST_DOUBLE_REAL_VALUE (x); 3604 REAL_VALUE_TO_TARGET_SINGLE (*rv, val); 3605 3606 fprintf (stream, "0x%lx", val); 3607 break; 3608 3609 case CODE_LABEL: 3610 case CONST_INT: 3611 case CONST: 3612 output_addr_const (stream, x); 3613 break; 3614 3615 case CONST_VECTOR: 3616 fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); 3617 break; 3618 3619 case LO_SUM: 3620 /* This is a special case for inline assembly using memory address 'p'. 3621 The inline assembly code is expected to use pesudo instruction 3622 for the operand. EX: la */ 3623 output_addr_const (stream, XEXP(x, 1)); 3624 break; 3625 3626 default: 3627 /* Generally, output_addr_const () is able to handle most cases. 3628 We want to see what CODE could appear, 3629 so we use gcc_unreachable() to stop it. */ 3630 debug_rtx (x); 3631 gcc_unreachable (); 3632 break; 3633 } 3634} 3635 3636static void 3637nds32_print_operand_address (FILE *stream, 3638 machine_mode mode ATTRIBUTE_UNUSED, 3639 rtx x) 3640{ 3641 rtx op0, op1; 3642 3643 switch (GET_CODE (x)) 3644 { 3645 case SYMBOL_REF: 3646 case CONST: 3647 /* [ + symbol_ref] */ 3648 /* [ + const_addr], where const_addr = symbol_ref + const_int */ 3649 fputs ("[ + ", stream); 3650 output_addr_const (stream, x); 3651 fputs ("]", stream); 3652 break; 3653 3654 case LO_SUM: 3655 /* This is a special case for inline assembly using memory operand 'm'. 3656 The inline assembly code is expected to use pesudo instruction 3657 for the operand. EX: [ls].[bhw] */ 3658 fputs ("[ + ", stream); 3659 op1 = XEXP (x, 1); 3660 output_addr_const (stream, op1); 3661 fputs ("]", stream); 3662 break; 3663 3664 case REG: 3665 /* Forbid using static chain register ($r16) 3666 on reduced-set registers configuration. */ 3667 if (TARGET_REDUCED_REGS 3668 && REGNO (x) == STATIC_CHAIN_REGNUM) 3669 sorry ("a nested function is not supported for reduced registers"); 3670 3671 /* [Ra] */ 3672 fprintf (stream, "[%s]", reg_names[REGNO (x)]); 3673 break; 3674 3675 case PLUS: 3676 op0 = XEXP (x, 0); 3677 op1 = XEXP (x, 1); 3678 3679 /* Checking op0, forbid using static chain register ($r16) 3680 on reduced-set registers configuration. */ 3681 if (TARGET_REDUCED_REGS 3682 && REG_P (op0) 3683 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3684 sorry ("a nested function is not supported for reduced registers"); 3685 /* Checking op1, forbid using static chain register ($r16) 3686 on reduced-set registers configuration. */ 3687 if (TARGET_REDUCED_REGS 3688 && REG_P (op1) 3689 && REGNO (op1) == STATIC_CHAIN_REGNUM) 3690 sorry ("a nested function is not supported for reduced registers"); 3691 3692 if (REG_P (op0) && CONST_INT_P (op1)) 3693 { 3694 /* [Ra + imm] */ 3695 fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]", 3696 reg_names[REGNO (op0)], INTVAL (op1)); 3697 } 3698 else if (REG_P (op0) && REG_P (op1)) 3699 { 3700 /* [Ra + Rb] */ 3701 fprintf (stream, "[%s + %s]", 3702 reg_names[REGNO (op0)], reg_names[REGNO (op1)]); 3703 } 3704 else if (GET_CODE (op0) == MULT && REG_P (op1)) 3705 { 3706 /* [Ra + Rb << sv] 3707 From observation, the pattern looks like: 3708 (plus:SI (mult:SI (reg:SI 58) 3709 (const_int 4 [0x4])) 3710 (reg/f:SI 57)) */ 3711 int sv; 3712 3713 /* We need to set sv to output shift value. */ 3714 if (INTVAL (XEXP (op0, 1)) == 1) 3715 sv = 0; 3716 else if (INTVAL (XEXP (op0, 1)) == 2) 3717 sv = 1; 3718 else if (INTVAL (XEXP (op0, 1)) == 4) 3719 sv = 2; 3720 else if (INTVAL (XEXP (op0, 1)) == 8) 3721 sv = 3; 3722 else 3723 gcc_unreachable (); 3724 3725 fprintf (stream, "[%s + %s << %d]", 3726 reg_names[REGNO (op1)], 3727 reg_names[REGNO (XEXP (op0, 0))], 3728 sv); 3729 } 3730 else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) 3731 { 3732 /* [Ra + Rb << sv] 3733 In normal, ASHIFT can be converted to MULT like above case. 3734 But when the address rtx does not go through canonicalize_address 3735 defined in fwprop, we'll need this case. */ 3736 int sv = INTVAL (XEXP (op0, 1)); 3737 gcc_assert (sv <= 3 && sv >=0); 3738 3739 fprintf (stream, "[%s + %s << %d]", 3740 reg_names[REGNO (op1)], 3741 reg_names[REGNO (XEXP (op0, 0))], 3742 sv); 3743 } 3744 else 3745 { 3746 /* The control flow is not supposed to be here. */ 3747 debug_rtx (x); 3748 gcc_unreachable (); 3749 } 3750 3751 break; 3752 3753 case POST_MODIFY: 3754 /* (post_modify (regA) (plus (regA) (regB))) 3755 (post_modify (regA) (plus (regA) (const_int))) 3756 We would like to extract 3757 regA and regB (or const_int) from plus rtx. */ 3758 op0 = XEXP (XEXP (x, 1), 0); 3759 op1 = XEXP (XEXP (x, 1), 1); 3760 3761 /* Checking op0, forbid using static chain register ($r16) 3762 on reduced-set registers configuration. */ 3763 if (TARGET_REDUCED_REGS 3764 && REG_P (op0) 3765 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3766 sorry ("a nested function is not supported for reduced registers"); 3767 /* Checking op1, forbid using static chain register ($r16) 3768 on reduced-set registers configuration. */ 3769 if (TARGET_REDUCED_REGS 3770 && REG_P (op1) 3771 && REGNO (op1) == STATIC_CHAIN_REGNUM) 3772 sorry ("a nested function is not supported for reduced registers"); 3773 3774 if (REG_P (op0) && REG_P (op1)) 3775 { 3776 /* [Ra], Rb */ 3777 fprintf (stream, "[%s], %s", 3778 reg_names[REGNO (op0)], reg_names[REGNO (op1)]); 3779 } 3780 else if (REG_P (op0) && CONST_INT_P (op1)) 3781 { 3782 /* [Ra], imm */ 3783 fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC, 3784 reg_names[REGNO (op0)], INTVAL (op1)); 3785 } 3786 else 3787 { 3788 /* The control flow is not supposed to be here. */ 3789 debug_rtx (x); 3790 gcc_unreachable (); 3791 } 3792 3793 break; 3794 3795 case POST_INC: 3796 case POST_DEC: 3797 op0 = XEXP (x, 0); 3798 3799 /* Checking op0, forbid using static chain register ($r16) 3800 on reduced-set registers configuration. */ 3801 if (TARGET_REDUCED_REGS 3802 && REG_P (op0) 3803 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3804 sorry ("a nested function is not supported for reduced registers"); 3805 3806 if (REG_P (op0)) 3807 { 3808 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" 3809 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. 3810 We only need to deal with register Ra. */ 3811 fprintf (stream, "[%s]", reg_names[REGNO (op0)]); 3812 } 3813 else 3814 { 3815 /* The control flow is not supposed to be here. */ 3816 debug_rtx (x); 3817 gcc_unreachable (); 3818 } 3819 3820 break; 3821 3822 default : 3823 /* Generally, output_addr_const () is able to handle most cases. 3824 We want to see what CODE could appear, 3825 so we use gcc_unreachable() to stop it. */ 3826 debug_rtx (x); 3827 gcc_unreachable (); 3828 break; 3829 } 3830} 3831 3832/* -- Assembler Commands for Exception Regions. */ 3833 3834static rtx 3835nds32_dwarf_register_span (rtx reg) 3836{ 3837 rtx dwarf_high, dwarf_low; 3838 rtx dwarf_single; 3839 machine_mode mode; 3840 int regno; 3841 3842 mode = GET_MODE (reg); 3843 regno = REGNO (reg); 3844 3845 /* We need to adjust dwarf register information for floating-point registers 3846 rather than using default register number mapping. */ 3847 if (regno >= NDS32_FIRST_FPR_REGNUM 3848 && regno <= NDS32_LAST_FPR_REGNUM) 3849 { 3850 if (mode == DFmode || mode == SCmode) 3851 { 3852 /* By default, GCC maps increasing register numbers to increasing 3853 memory locations, but paired FPRs in NDS32 target are always 3854 big-endian, i.e.: 3855 3856 fd0 : fs0 fs1 3857 (MSB) (LSB) 3858 3859 We must return parallel rtx to represent such layout. */ 3860 dwarf_high = gen_rtx_REG (word_mode, regno); 3861 dwarf_low = gen_rtx_REG (word_mode, regno + 1); 3862 return gen_rtx_PARALLEL (VOIDmode, 3863 gen_rtvec (2, dwarf_low, dwarf_high)); 3864 } 3865 else if (mode == DCmode) 3866 { 3867 rtx dwarf_high_re = gen_rtx_REG (word_mode, regno); 3868 rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1); 3869 rtx dwarf_high_im = gen_rtx_REG (word_mode, regno); 3870 rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1); 3871 return gen_rtx_PARALLEL (VOIDmode, 3872 gen_rtvec (4, dwarf_low_re, dwarf_high_re, 3873 dwarf_high_im, dwarf_low_im)); 3874 } 3875 else if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 3876 { 3877 return NULL_RTX; 3878 } 3879 else 3880 { 3881 /* We should not be here. */ 3882 gcc_unreachable (); 3883 } 3884 } 3885 3886 return NULL_RTX; 3887} 3888 3889/* Map internal gcc register numbers to DWARF2 register numbers. */ 3890 3891unsigned int 3892nds32_dbx_register_number (unsigned int regno) 3893{ 3894 /* The nds32 port in GDB maintains a mapping between dwarf register 3895 number and displayed register name. For backward compatibility to 3896 previous toolchain, currently our gdb still has four registers 3897 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler 3898 does not count those four registers in its register number table. 3899 So we have to add 4 on its register number and then create new 3900 dwarf information. Hopefully we can discard such workaround 3901 in the future. */ 3902 if (NDS32_IS_FPR_REGNUM (regno)) 3903 return regno + 4; 3904 3905 return regno; 3906} 3907 3908 3909/* Defining target-specific uses of __attribute__. */ 3910 3911/* Add some checking after merging attributes. */ 3912static tree 3913nds32_merge_decl_attributes (tree olddecl, tree newdecl) 3914{ 3915 tree combined_attrs; 3916 3917 /* Create combined attributes. */ 3918 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), 3919 DECL_ATTRIBUTES (newdecl)); 3920 3921 /* Since newdecl is acutally a duplicate of olddecl, 3922 we can take olddecl for some operations. */ 3923 if (TREE_CODE (olddecl) == FUNCTION_DECL) 3924 { 3925 /* Check isr-specific attributes conflict. */ 3926 nds32_check_isr_attrs_conflict (olddecl, combined_attrs); 3927 } 3928 3929 return combined_attrs; 3930} 3931 3932/* Add some checking when inserting attributes. */ 3933static void 3934nds32_insert_attributes (tree decl, tree *attributes) 3935{ 3936 /* A "indirect_call" function attribute implies "noinline" and "noclone" 3937 for elf toolchain to support ROM patch mechanism. */ 3938 if (TREE_CODE (decl) == FUNCTION_DECL 3939 && lookup_attribute ("indirect_call", *attributes) != NULL) 3940 { 3941 tree new_attrs = *attributes; 3942 3943 if (TARGET_LINUX_ABI) 3944 error("cannot use indirect_call attribute under linux toolchain"); 3945 3946 if (lookup_attribute ("noinline", new_attrs) == NULL) 3947 new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); 3948 if (lookup_attribute ("noclone", new_attrs) == NULL) 3949 new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); 3950 3951 if (!TREE_PUBLIC (decl)) 3952 error ("indirect_call attribute can%'t apply for static function"); 3953 3954 *attributes = new_attrs; 3955 } 3956 3957 /* For function declaration, we need to check isr-specific attributes: 3958 1. Call nds32_check_isr_attrs_conflict() to check any conflict. 3959 2. Check valid integer value for interrupt/exception. 3960 3. Check valid integer value for reset. 3961 4. Check valid function for nmi/warm. */ 3962 if (TREE_CODE (decl) == FUNCTION_DECL) 3963 { 3964 tree func_attrs; 3965 tree intr, excp, reset; 3966 3967 /* Pick up function attributes. */ 3968 func_attrs = *attributes; 3969 3970 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ 3971 nds32_check_isr_attrs_conflict (decl, func_attrs); 3972 3973 /* Now we are starting to check valid id value 3974 for interrupt/exception/reset. 3975 Note that we ONLY check its validity here. 3976 To construct isr vector information, it is still performed 3977 by nds32_construct_isr_vectors_information(). */ 3978 intr = lookup_attribute ("interrupt", func_attrs); 3979 excp = lookup_attribute ("exception", func_attrs); 3980 reset = lookup_attribute ("reset", func_attrs); 3981 3982 /* The following code may use attribute arguments. If there is no 3983 argument from source code, it will cause segmentation fault. 3984 Therefore, return dircetly and report error message later. */ 3985 if ((intr && TREE_VALUE (intr) == NULL) 3986 || (excp && TREE_VALUE (excp) == NULL) 3987 || (reset && TREE_VALUE (reset) == NULL)) 3988 return; 3989 3990 /* ------------------------------------------------------------- */ 3991 /* FIXME: 3992 FOR BACKWARD COMPATIBILITY, we need to support following patterns: 3993 3994 __attribute__((interrupt("XXX;YYY;id=ZZZ"))) 3995 __attribute__((exception("XXX;YYY;id=ZZZ"))) 3996 __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) 3997 3998 If interrupt/exception/reset appears and its argument is a 3999 STRING_CST, we will use other functions to parse string in the 4000 nds32_construct_isr_vectors_information() and then set necessary 4001 isr information in the nds32_isr_vectors[] array. Here we can 4002 just return immediately to avoid new-syntax checking. */ 4003 if (intr != NULL_TREE 4004 && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) 4005 return; 4006 if (excp != NULL_TREE 4007 && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) 4008 return; 4009 if (reset != NULL_TREE 4010 && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) 4011 return; 4012 /* ------------------------------------------------------------- */ 4013 4014 if (intr || excp) 4015 { 4016 /* Deal with interrupt/exception. */ 4017 tree id_list; 4018 unsigned int lower_bound, upper_bound; 4019 4020 /* The way to handle interrupt or exception is the same, 4021 we just need to take care of actual vector number. 4022 For interrupt(0..63), the actual vector number is (9..72). 4023 For exception(1..8), the actual vector number is (1..8). */ 4024 lower_bound = (intr) ? (0) : (1); 4025 upper_bound = (intr) ? (63) : (8); 4026 4027 /* Prepare id list so that we can traverse id value. */ 4028 id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); 4029 4030 /* 2. Check valid integer value for interrupt/exception. */ 4031 while (id_list) 4032 { 4033 tree id; 4034 4035 /* Pick up each vector id value. */ 4036 id = TREE_VALUE (id_list); 4037 /* Issue error if it is not a valid integer value. */ 4038 if (TREE_CODE (id) != INTEGER_CST 4039 || wi::ltu_p (wi::to_wide (id), lower_bound) 4040 || wi::gtu_p (wi::to_wide (id), upper_bound)) 4041 error ("invalid id value for interrupt/exception attribute"); 4042 4043 /* Advance to next id. */ 4044 id_list = TREE_CHAIN (id_list); 4045 } 4046 } 4047 else if (reset) 4048 { 4049 /* Deal with reset. */ 4050 tree id_list; 4051 tree id; 4052 tree nmi, warm; 4053 unsigned int lower_bound; 4054 unsigned int upper_bound; 4055 4056 /* Prepare id_list and identify id value so that 4057 we can check if total number of vectors is valid. */ 4058 id_list = TREE_VALUE (reset); 4059 id = TREE_VALUE (id_list); 4060 4061 /* The maximum numbers for user's interrupt is 64. */ 4062 lower_bound = 0; 4063 upper_bound = 64; 4064 4065 /* 3. Check valid integer value for reset. */ 4066 if (TREE_CODE (id) != INTEGER_CST 4067 || wi::ltu_p (wi::to_wide (id), lower_bound) 4068 || wi::gtu_p (wi::to_wide (id), upper_bound)) 4069 error ("invalid id value for reset attribute"); 4070 4071 /* 4. Check valid function for nmi/warm. */ 4072 nmi = lookup_attribute ("nmi", func_attrs); 4073 warm = lookup_attribute ("warm", func_attrs); 4074 4075 if (nmi != NULL_TREE) 4076 { 4077 tree nmi_func_list; 4078 tree nmi_func; 4079 4080 nmi_func_list = TREE_VALUE (nmi); 4081 nmi_func = TREE_VALUE (nmi_func_list); 4082 4083 /* Issue error if it is not a valid nmi function. */ 4084 if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) 4085 error ("invalid nmi function for reset attribute"); 4086 } 4087 4088 if (warm != NULL_TREE) 4089 { 4090 tree warm_func_list; 4091 tree warm_func; 4092 4093 warm_func_list = TREE_VALUE (warm); 4094 warm_func = TREE_VALUE (warm_func_list); 4095 4096 /* Issue error if it is not a valid warm function. */ 4097 if (TREE_CODE (warm_func) != IDENTIFIER_NODE) 4098 error ("invalid warm function for reset attribute"); 4099 } 4100 } 4101 else 4102 { 4103 /* No interrupt, exception, or reset attribute is set. */ 4104 return; 4105 } 4106 } 4107} 4108 4109static bool 4110nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, 4111 tree pop_target ATTRIBUTE_UNUSED) 4112{ 4113 /* Currently, we do not parse any pragma target by ourself, 4114 so just simply return false. */ 4115 return false; 4116} 4117 4118static void 4119nds32_option_override (void) 4120{ 4121 /* After all the command options have been parsed, 4122 we shall deal with some flags for changing compiler settings. */ 4123 4124 /* At first, we check if we have to strictly 4125 set some flags based on ISA family. */ 4126 if (TARGET_ISA_V2) 4127 { 4128 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ 4129 target_flags &= ~MASK_V3PUSH; 4130 } 4131 if (TARGET_ISA_V3) 4132 { 4133 /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ 4134 if (nds32_arch_option == ARCH_V3J) 4135 target_flags |= MASK_REDUCED_REGS; 4136 } 4137 if (TARGET_ISA_V3M) 4138 { 4139 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ 4140 target_flags |= MASK_REDUCED_REGS; 4141 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ 4142 target_flags &= ~MASK_EXT_PERF; 4143 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ 4144 target_flags &= ~MASK_EXT_PERF2; 4145 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ 4146 target_flags &= ~MASK_EXT_STRING; 4147 4148 if (flag_pic) 4149 error ("not support %<-fpic%> option for v3m toolchain"); 4150 } 4151 4152 /* See if we are using reduced-set registers: 4153 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 4154 If so, we must forbid using $r11~$r14, $r16~$r27. */ 4155 if (TARGET_REDUCED_REGS) 4156 { 4157 int r; 4158 4159 /* Prevent register allocator from 4160 choosing it as doing register allocation. */ 4161 for (r = 11; r <= 14; r++) 4162 fixed_regs[r] = call_used_regs[r] = 1; 4163 for (r = 16; r <= 27; r++) 4164 fixed_regs[r] = call_used_regs[r] = 1; 4165 } 4166 4167 /* See if user explicitly would like to use fp-as-gp optimization. 4168 If so, we must prevent $fp from being allocated 4169 during register allocation. */ 4170 if (TARGET_FORCE_FP_AS_GP) 4171 fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; 4172 4173 if (!TARGET_16_BIT) 4174 { 4175 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ 4176 target_flags &= ~MASK_V3PUSH; 4177 } 4178 4179 if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 4180 { 4181 if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F) 4182 error ("Disable FPU ISA, " 4183 "the ABI option must be enable %<-mfloat-abi=soft%>"); 4184 else 4185 error ("%<-mabi=2fp+%> option only support when FPU available, " 4186 "must be enable %<-mext-fpu-sp%> or %<-mext-fpu-dp%>"); 4187 } 4188 4189 nds32_init_rtx_costs (); 4190 4191 nds32_register_passes (); 4192} 4193 4194 4195/* Miscellaneous Parameters. */ 4196 4197static rtx_insn * 4198nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, 4199 vec<rtx> &inputs ATTRIBUTE_UNUSED, 4200 vec<const char *> &constraints ATTRIBUTE_UNUSED, 4201 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) 4202{ 4203 if (!flag_inline_asm_r15) 4204 { 4205 clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); 4206 SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); 4207 } 4208 return NULL; 4209} 4210 4211static void 4212nds32_init_builtins (void) 4213{ 4214 nds32_init_builtins_impl (); 4215} 4216 4217static tree 4218nds32_builtin_decl (unsigned code, bool initialize_p) 4219{ 4220 /* Implement in nds32-intrinsic.c. */ 4221 return nds32_builtin_decl_impl (code, initialize_p); 4222} 4223 4224static rtx 4225nds32_expand_builtin (tree exp, 4226 rtx target, 4227 rtx subtarget, 4228 machine_mode mode, 4229 int ignore) 4230{ 4231 return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); 4232} 4233 4234/* Implement TARGET_INIT_LIBFUNCS. */ 4235static void 4236nds32_init_libfuncs (void) 4237{ 4238 if (TARGET_LINUX_ABI) 4239 init_sync_libfuncs (UNITS_PER_WORD); 4240} 4241 4242/* ------------------------------------------------------------------------ */ 4243 4244/* PART 4: Implemet extern function definitions, 4245 the prototype is in nds32-protos.h. */ 4246 4247/* Run-time Target Specification. */ 4248 4249void 4250nds32_cpu_cpp_builtins(struct cpp_reader *pfile) 4251{ 4252#define builtin_define(TXT) cpp_define (pfile, TXT) 4253#define builtin_assert(TXT) cpp_assert (pfile, TXT) 4254 builtin_define ("__nds32__"); 4255 builtin_define ("__NDS32__"); 4256 4257 /* We need to provide builtin macro to describe the size of 4258 each vector for interrupt handler under elf toolchain. */ 4259 if (!TARGET_LINUX_ABI) 4260 { 4261 if (TARGET_ISR_VECTOR_SIZE_4_BYTE) 4262 builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); 4263 else 4264 builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); 4265 } 4266 4267 if (TARGET_HARD_FLOAT) 4268 builtin_define ("__NDS32_ABI_2FP_PLUS__"); 4269 else 4270 builtin_define ("__NDS32_ABI_2__"); 4271 4272 if (TARGET_ISA_V2) 4273 builtin_define ("__NDS32_ISA_V2__"); 4274 if (TARGET_ISA_V3) 4275 builtin_define ("__NDS32_ISA_V3__"); 4276 if (TARGET_ISA_V3M) 4277 builtin_define ("__NDS32_ISA_V3M__"); 4278 4279 if (TARGET_FPU_SINGLE) 4280 builtin_define ("__NDS32_EXT_FPU_SP__"); 4281 if (TARGET_FPU_DOUBLE) 4282 builtin_define ("__NDS32_EXT_FPU_DP__"); 4283 4284 if (TARGET_EXT_FPU_FMA) 4285 builtin_define ("__NDS32_EXT_FPU_FMA__"); 4286 if (NDS32_EXT_FPU_DOT_E) 4287 builtin_define ("__NDS32_EXT_FPU_DOT_E__"); 4288 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 4289 { 4290 switch (nds32_fp_regnum) 4291 { 4292 case 0: 4293 case 4: 4294 builtin_define ("__NDS32_EXT_FPU_CONFIG_0__"); 4295 break; 4296 case 1: 4297 case 5: 4298 builtin_define ("__NDS32_EXT_FPU_CONFIG_1__"); 4299 break; 4300 case 2: 4301 case 6: 4302 builtin_define ("__NDS32_EXT_FPU_CONFIG_2__"); 4303 break; 4304 case 3: 4305 case 7: 4306 builtin_define ("__NDS32_EXT_FPU_CONFIG_3__"); 4307 break; 4308 default: 4309 abort (); 4310 } 4311 } 4312 4313 if (TARGET_BIG_ENDIAN) 4314 builtin_define ("__NDS32_EB__"); 4315 else 4316 builtin_define ("__NDS32_EL__"); 4317 4318 if (TARGET_REDUCED_REGS) 4319 builtin_define ("__NDS32_REDUCED_REGS__"); 4320 if (TARGET_CMOV) 4321 builtin_define ("__NDS32_CMOV__"); 4322 if (TARGET_EXT_PERF) 4323 builtin_define ("__NDS32_EXT_PERF__"); 4324 if (TARGET_EXT_PERF2) 4325 builtin_define ("__NDS32_EXT_PERF2__"); 4326 if (TARGET_EXT_STRING) 4327 builtin_define ("__NDS32_EXT_STRING__"); 4328 if (TARGET_16_BIT) 4329 builtin_define ("__NDS32_16_BIT__"); 4330 if (TARGET_GP_DIRECT) 4331 builtin_define ("__NDS32_GP_DIRECT__"); 4332 if (TARGET_VH) 4333 builtin_define ("__NDS32_VH__"); 4334 if (NDS32_EXT_DSP_P ()) 4335 builtin_define ("__NDS32_EXT_DSP__"); 4336 4337 if (TARGET_BIG_ENDIAN) 4338 builtin_define ("__big_endian__"); 4339 4340 builtin_assert ("cpu=nds32"); 4341 builtin_assert ("machine=nds32"); 4342 4343 if (TARGET_HARD_FLOAT) 4344 builtin_define ("__NDS32_ABI_2FP_PLUS"); 4345 else 4346 builtin_define ("__NDS32_ABI_2"); 4347 4348#undef builtin_define 4349#undef builtin_assert 4350} 4351 4352 4353/* Defining Data Structures for Per-function Information. */ 4354 4355void 4356nds32_init_expanders (void) 4357{ 4358 /* Arrange to initialize and mark the machine per-function status. */ 4359 init_machine_status = nds32_init_machine_status; 4360} 4361 4362 4363/* Register Usage. */ 4364 4365/* -- Order of Allocation of Registers. */ 4366 4367void 4368nds32_adjust_reg_alloc_order (void) 4369{ 4370 const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER; 4371 4372 /* Copy the default register allocation order, which is designed 4373 to optimize for code size. */ 4374 memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order)); 4375 4376 /* Adjust few register allocation order when optimizing for speed. */ 4377 if (!optimize_size) 4378 { 4379 memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed, 4380 sizeof (nds32_reg_alloc_order_for_speed)); 4381 } 4382} 4383 4384/* -- How Values Fit in Registers. */ 4385 4386static unsigned 4387nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED, 4388 machine_mode mode) 4389{ 4390 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 4391} 4392 4393/* Implement TARGET_HARD_REGNO_MODE_OK. */ 4394 4395static bool 4396nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4397{ 4398 if (regno >= FIRST_PSEUDO_REGISTER) 4399 return true; 4400 4401 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno)) 4402 { 4403 if (NDS32_IS_EXT_FPR_REGNUM(regno)) 4404 return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode)); 4405 else if (mode == SFmode || mode == SImode) 4406 return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno); 4407 else if (mode == DFmode) 4408 return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno); 4409 4410 return false; 4411 } 4412 4413 /* Restrict double-word quantities to even register pairs. */ 4414 if (regno <= NDS32_LAST_GPR_REGNUM) 4415 return (targetm.hard_regno_nregs (regno, mode) == 1 4416 || !((regno) & 1)); 4417 4418 return false; 4419} 4420 4421/* Implement TARGET_MODES_TIEABLE_P. We can use general registers to 4422 tie QI/HI/SI modes together. */ 4423 4424static bool 4425nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) 4426{ 4427 if ((GET_MODE_CLASS (mode1) == MODE_INT 4428 && GET_MODE_CLASS (mode2) == MODE_INT) 4429 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD 4430 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) 4431 return true; 4432 4433 if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)) 4434 { 4435 if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE) 4436 && (mode1 == DFmode || mode2 == DFmode)) 4437 return false; 4438 else 4439 return true; 4440 } 4441 4442 return false; 4443} 4444 4445/* Register Classes. */ 4446 4447enum reg_class 4448nds32_regno_reg_class (int regno) 4449{ 4450 /* Refer to nds32.h for more register class details. */ 4451 4452 if (regno >= 0 && regno <= 7) 4453 return LOW_REGS; 4454 else if (regno >= 8 && regno <= 11) 4455 return MIDDLE_REGS; 4456 else if (regno >= 12 && regno <= 14) 4457 return HIGH_REGS; 4458 else if (regno == 15) 4459 return R15_TA_REG; 4460 else if (regno >= 16 && regno <= 19) 4461 return MIDDLE_REGS; 4462 else if (regno >= 20 && regno <= 31) 4463 return HIGH_REGS; 4464 else if (regno == 32 || regno == 33) 4465 { 4466 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't 4467 know how to allocate register for $SFP and $AP, just tell IRA they 4468 are GENERAL_REGS, and ARM do this hack too. */ 4469 return GENERAL_REGS; 4470 } 4471 else if (regno >= 34 && regno <= 97) 4472 return FP_REGS; 4473 else 4474 return NO_REGS; 4475} 4476 4477 4478/* Stack Layout and Calling Conventions. */ 4479 4480/* -- Basic Stack Layout. */ 4481 4482rtx 4483nds32_dynamic_chain_address (rtx frameaddr) 4484{ 4485 if (TARGET_V3PUSH) 4486 { 4487 /* If -mv3push is specified, we push $fp, $gp, and $lp into stack. 4488 We can access dynamic chain address from stack by [$fp - 12]. */ 4489 return plus_constant (Pmode, frameaddr, -12); 4490 } 4491 else 4492 { 4493 /* For general case we push $fp and $lp into stack at prologue. 4494 We can access dynamic chain address from stack by [$fp - 8]. */ 4495 return plus_constant (Pmode, frameaddr, -8); 4496 } 4497} 4498 4499rtx 4500nds32_return_addr_rtx (int count, 4501 rtx frameaddr) 4502{ 4503 int offset; 4504 rtx addr; 4505 4506 if (count != 0) 4507 { 4508 /* In nds32 ABI design, we can expect that $lp is always available 4509 from stack by [$fp - 4] location. */ 4510 offset = -4; 4511 addr = plus_constant (Pmode, frameaddr, offset); 4512 addr = memory_address (Pmode, addr); 4513 4514 return gen_rtx_MEM (Pmode, addr); 4515 } 4516 4517 /* If count == 0, it means we are at current frame, 4518 the return address is $r30 ($lp). */ 4519 return get_hard_reg_initial_val (Pmode, LP_REGNUM); 4520} 4521 4522/* -- Eliminating Frame Pointer and Arg Pointer. */ 4523 4524HOST_WIDE_INT 4525nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) 4526{ 4527 HOST_WIDE_INT offset; 4528 4529 /* Compute and setup stack frame size. 4530 The result will be in cfun->machine. */ 4531 nds32_compute_stack_frame (); 4532 4533 /* Remember to consider 4534 cfun->machine->callee_saved_area_gpr_padding_bytes and 4535 cfun->machine->eh_return_data_regs_size 4536 when calculating offset. */ 4537 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 4538 { 4539 offset = (cfun->machine->fp_size 4540 + cfun->machine->gp_size 4541 + cfun->machine->lp_size 4542 + cfun->machine->callee_saved_gpr_regs_size 4543 + cfun->machine->callee_saved_area_gpr_padding_bytes 4544 + cfun->machine->callee_saved_fpr_regs_size 4545 + cfun->machine->eh_return_data_regs_size 4546 + cfun->machine->local_size 4547 + cfun->machine->out_args_size); 4548 } 4549 else if (from_reg == ARG_POINTER_REGNUM 4550 && to_reg == HARD_FRAME_POINTER_REGNUM) 4551 { 4552 offset = 0; 4553 } 4554 else if (from_reg == FRAME_POINTER_REGNUM 4555 && to_reg == STACK_POINTER_REGNUM) 4556 { 4557 offset = (cfun->machine->local_size + cfun->machine->out_args_size); 4558 } 4559 else if (from_reg == FRAME_POINTER_REGNUM 4560 && to_reg == HARD_FRAME_POINTER_REGNUM) 4561 { 4562 offset = (-1) * (cfun->machine->fp_size 4563 + cfun->machine->gp_size 4564 + cfun->machine->lp_size 4565 + cfun->machine->callee_saved_gpr_regs_size 4566 + cfun->machine->callee_saved_area_gpr_padding_bytes 4567 + cfun->machine->callee_saved_fpr_regs_size 4568 + cfun->machine->eh_return_data_regs_size); 4569 } 4570 else 4571 { 4572 gcc_unreachable (); 4573 } 4574 4575 return offset; 4576} 4577 4578/* -- Passing Arguments in Registers. */ 4579 4580void 4581nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, 4582 tree fntype ATTRIBUTE_UNUSED, 4583 rtx libname ATTRIBUTE_UNUSED, 4584 tree fndecl ATTRIBUTE_UNUSED, 4585 int n_named_args ATTRIBUTE_UNUSED) 4586{ 4587 /* Initial available registers. The values are offset against 4588 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM 4589 for passing arguments. */ 4590 cum->gpr_offset = 0; 4591 cum->fpr_offset = 0; 4592} 4593 4594/* -- Function Entry and Exit. */ 4595 4596/* Function for normal multiple push prologue. */ 4597void 4598nds32_expand_prologue (void) 4599{ 4600 int fp_adjust; 4601 int sp_adjust; 4602 unsigned Rb, Re; 4603 4604 /* Compute and setup stack frame size. 4605 The result will be in cfun->machine. */ 4606 nds32_compute_stack_frame (); 4607 4608 /* Check frame_pointer_needed again to prevent fp is need after reload. */ 4609 if (frame_pointer_needed) 4610 cfun->machine->fp_as_gp_p = false; 4611 4612 /* If this is a variadic function, first we need to push argument 4613 registers that hold the unnamed argument value. */ 4614 if (cfun->machine->va_args_size != 0) 4615 { 4616 Rb = cfun->machine->va_args_first_regno; 4617 Re = cfun->machine->va_args_last_regno; 4618 /* No need to push $fp, $gp, or $lp. */ 4619 nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); 4620 4621 /* We may also need to adjust stack pointer for padding bytes 4622 because varargs may cause $sp not 8-byte aligned. */ 4623 if (cfun->machine->va_args_area_padding_bytes) 4624 { 4625 /* Generate sp adjustment instruction. */ 4626 sp_adjust = cfun->machine->va_args_area_padding_bytes; 4627 4628 nds32_emit_adjust_frame (stack_pointer_rtx, 4629 stack_pointer_rtx, 4630 -1 * sp_adjust); 4631 } 4632 } 4633 4634 /* If the function is 'naked', 4635 we do not have to generate prologue code fragment. */ 4636 if (cfun->machine->naked_p && !flag_pic) 4637 return; 4638 4639 /* Get callee_first_regno and callee_last_regno. */ 4640 Rb = cfun->machine->callee_saved_first_gpr_regno; 4641 Re = cfun->machine->callee_saved_last_gpr_regno; 4642 4643 /* If $fp, $gp, $lp, and all callee-save registers are NOT required 4644 to be saved, we don't have to create multiple push instruction. 4645 Otherwise, a multiple push instruction is needed. */ 4646 if (!(Rb == SP_REGNUM && Re == SP_REGNUM 4647 && cfun->machine->fp_size == 0 4648 && cfun->machine->gp_size == 0 4649 && cfun->machine->lp_size == 0)) 4650 { 4651 /* Create multiple push instruction rtx. */ 4652 nds32_emit_stack_push_multiple ( 4653 Rb, Re, 4654 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, 4655 false); 4656 } 4657 4658 /* Save eh data registers. */ 4659 if (cfun->machine->use_eh_return_p) 4660 { 4661 Rb = cfun->machine->eh_return_data_first_regno; 4662 Re = cfun->machine->eh_return_data_last_regno; 4663 4664 /* No need to push $fp, $gp, or $lp. 4665 Also, this is not variadic arguments push. */ 4666 nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false); 4667 } 4668 4669 /* Check frame_pointer_needed to see 4670 if we shall emit fp adjustment instruction. */ 4671 if (frame_pointer_needed) 4672 { 4673 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) 4674 + (4 * callee-saved-registers) 4675 + (4 * exception-handling-data-registers) 4676 Note: No need to adjust 4677 cfun->machine->callee_saved_area_gpr_padding_bytes, 4678 because, at this point, stack pointer is just 4679 at the position after push instruction. */ 4680 fp_adjust = cfun->machine->fp_size 4681 + cfun->machine->gp_size 4682 + cfun->machine->lp_size 4683 + cfun->machine->callee_saved_gpr_regs_size 4684 + cfun->machine->eh_return_data_regs_size; 4685 4686 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 4687 stack_pointer_rtx, 4688 fp_adjust); 4689 } 4690 4691 /* Save fpu registers. */ 4692 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4693 { 4694 /* When $sp moved to bottom of stack, we need to check whether 4695 the range of offset in the FPU instruction. */ 4696 int fpr_offset = cfun->machine->local_size 4697 + cfun->machine->out_args_size 4698 + cfun->machine->callee_saved_fpr_regs_size; 4699 4700 /* Check FPU instruction offset imm14s. */ 4701 if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset))) 4702 { 4703 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 4704 + cfun->machine->callee_saved_fpr_regs_size; 4705 4706 /* Save fpu registers, need to allocate stack space 4707 for fpu callee registers. And now $sp position 4708 on callee saved fpr registers. */ 4709 nds32_emit_adjust_frame (stack_pointer_rtx, 4710 stack_pointer_rtx, 4711 -1 * fpr_space); 4712 4713 /* Emit fpu store instruction, using [$sp + offset] store 4714 fpu registers. */ 4715 nds32_emit_push_fpr_callee_saved (0); 4716 4717 /* Adjust $sp = $sp - local_size - out_args_size. */ 4718 sp_adjust = cfun->machine->local_size 4719 + cfun->machine->out_args_size; 4720 4721 /* Allocate stack space for local size and out args size. */ 4722 nds32_emit_adjust_frame (stack_pointer_rtx, 4723 stack_pointer_rtx, 4724 -1 * sp_adjust); 4725 } 4726 else 4727 { 4728 /* Offset range in Is14, so $sp moved to bottom of stack. */ 4729 4730 /* Adjust $sp = $sp - local_size - out_args_size 4731 - callee_saved_area_gpr_padding_bytes 4732 - callee_saved_fpr_regs_size. */ 4733 sp_adjust = cfun->machine->local_size 4734 + cfun->machine->out_args_size 4735 + cfun->machine->callee_saved_area_gpr_padding_bytes 4736 + cfun->machine->callee_saved_fpr_regs_size; 4737 4738 nds32_emit_adjust_frame (stack_pointer_rtx, 4739 stack_pointer_rtx, 4740 -1 * sp_adjust); 4741 4742 /* Emit fpu store instruction, using [$sp + offset] store 4743 fpu registers. */ 4744 int fpr_position = cfun->machine->out_args_size 4745 + cfun->machine->local_size; 4746 nds32_emit_push_fpr_callee_saved (fpr_position); 4747 } 4748 } 4749 else 4750 { 4751 /* Adjust $sp = $sp - local_size - out_args_size 4752 - callee_saved_area_gpr_padding_bytes. */ 4753 sp_adjust = cfun->machine->local_size 4754 + cfun->machine->out_args_size 4755 + cfun->machine->callee_saved_area_gpr_padding_bytes; 4756 4757 /* sp_adjust value may be out of range of the addi instruction, 4758 create alternative add behavior with TA_REGNUM if necessary, 4759 using NEGATIVE value to tell that we are decreasing address. */ 4760 nds32_emit_adjust_frame (stack_pointer_rtx, 4761 stack_pointer_rtx, 4762 -1 * sp_adjust); 4763 } 4764 4765 /* Emit gp setup instructions for -fpic. */ 4766 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) 4767 nds32_emit_load_gp (); 4768 4769 /* If user applies -mno-sched-prolog-epilog option, 4770 we need to prevent instructions of function body from being 4771 scheduled with stack adjustment in prologue. */ 4772 if (!flag_sched_prolog_epilog) 4773 emit_insn (gen_blockage ()); 4774} 4775 4776/* Function for normal multiple pop epilogue. */ 4777void 4778nds32_expand_epilogue (bool sibcall_p) 4779{ 4780 int sp_adjust; 4781 unsigned Rb, Re; 4782 4783 /* Compute and setup stack frame size. 4784 The result will be in cfun->machine. */ 4785 nds32_compute_stack_frame (); 4786 4787 /* If user applies -mno-sched-prolog-epilog option, 4788 we need to prevent instructions of function body from being 4789 scheduled with stack adjustment in epilogue. */ 4790 if (!flag_sched_prolog_epilog) 4791 emit_insn (gen_blockage ()); 4792 4793 /* If the function is 'naked', we do not have to generate 4794 epilogue code fragment BUT 'ret' instruction. 4795 However, if this function is also a variadic function, 4796 we need to create adjust stack pointer before 'ret' instruction. */ 4797 if (cfun->machine->naked_p) 4798 { 4799 /* If this is a variadic function, we do not have to restore argument 4800 registers but need to adjust stack pointer back to previous stack 4801 frame location before return. */ 4802 if (cfun->machine->va_args_size != 0) 4803 { 4804 /* Generate sp adjustment instruction. 4805 We need to consider padding bytes here. */ 4806 sp_adjust = cfun->machine->va_args_size 4807 + cfun->machine->va_args_area_padding_bytes; 4808 4809 nds32_emit_adjust_frame (stack_pointer_rtx, 4810 stack_pointer_rtx, 4811 sp_adjust); 4812 } 4813 4814 /* Generate return instruction by using 'return_internal' pattern. 4815 Make sure this instruction is after gen_blockage(). */ 4816 if (!sibcall_p) 4817 { 4818 /* We need to further check attributes to determine whether 4819 there should be return instruction at epilogue. 4820 If the attribute naked exists but -mno-ret-in-naked-func 4821 is issued, there is NO need to generate return instruction. */ 4822 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 4823 return; 4824 4825 emit_jump_insn (gen_return_internal ()); 4826 } 4827 return; 4828 } 4829 4830 if (frame_pointer_needed) 4831 { 4832 /* Restore fpu registers. */ 4833 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4834 { 4835 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; 4836 4837 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) 4838 - (4 * callee-saved-registers) 4839 - (4 * exception-handling-data-registers) 4840 - (4 * callee-saved-gpr-registers padding byte) 4841 - (4 * callee-saved-fpr-registers) 4842 Note: we want to adjust stack pointer 4843 to the position for callee-saved fpr register, 4844 And restore fpu register use .bi instruction to adjust $sp 4845 from callee-saved fpr register to pop instruction. */ 4846 sp_adjust = cfun->machine->fp_size 4847 + cfun->machine->gp_size 4848 + cfun->machine->lp_size 4849 + cfun->machine->callee_saved_gpr_regs_size 4850 + cfun->machine->eh_return_data_regs_size 4851 + cfun->machine->callee_saved_area_gpr_padding_bytes 4852 + cfun->machine->callee_saved_fpr_regs_size; 4853 4854 nds32_emit_adjust_frame (stack_pointer_rtx, 4855 hard_frame_pointer_rtx, 4856 -1 * sp_adjust); 4857 4858 /* Emit fpu load instruction, using .bi instruction 4859 load fpu registers. */ 4860 nds32_emit_pop_fpr_callee_saved (gpr_padding); 4861 } 4862 else 4863 { 4864 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) 4865 - (4 * callee-saved-registers) 4866 - (4 * exception-handling-data-registers) 4867 Note: No need to adjust 4868 cfun->machine->callee_saved_area_gpr_padding_bytes, 4869 because we want to adjust stack pointer 4870 to the position for pop instruction. */ 4871 sp_adjust = cfun->machine->fp_size 4872 + cfun->machine->gp_size 4873 + cfun->machine->lp_size 4874 + cfun->machine->callee_saved_gpr_regs_size 4875 + cfun->machine->eh_return_data_regs_size; 4876 4877 nds32_emit_adjust_frame (stack_pointer_rtx, 4878 hard_frame_pointer_rtx, 4879 -1 * sp_adjust); 4880 } 4881 } 4882 else 4883 { 4884 /* Restore fpu registers. */ 4885 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4886 { 4887 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; 4888 4889 /* Adjust $sp = $sp + local_size + out_args_size. */ 4890 sp_adjust = cfun->machine->local_size 4891 + cfun->machine->out_args_size; 4892 4893 nds32_emit_adjust_frame (stack_pointer_rtx, 4894 stack_pointer_rtx, 4895 sp_adjust); 4896 4897 /* Emit fpu load instruction, using .bi instruction 4898 load fpu registers, and adjust $sp from callee-saved fpr register 4899 to callee-saved gpr register. */ 4900 nds32_emit_pop_fpr_callee_saved (gpr_padding); 4901 } 4902 else 4903 { 4904 /* If frame pointer is NOT needed, 4905 we cannot calculate the sp adjustment from frame pointer. 4906 Instead, we calculate the adjustment by local_size, 4907 out_args_size, and callee_saved_area_gpr_padding_bytes. 4908 Notice that such sp adjustment value may be out of range, 4909 so we have to deal with it as well. */ 4910 4911 /* Adjust $sp = $sp + local_size + out_args_size 4912 + callee_saved_area_gpr_padding_bytes. */ 4913 sp_adjust = cfun->machine->local_size 4914 + cfun->machine->out_args_size 4915 + cfun->machine->callee_saved_area_gpr_padding_bytes; 4916 4917 nds32_emit_adjust_frame (stack_pointer_rtx, 4918 stack_pointer_rtx, 4919 sp_adjust); 4920 } 4921 } 4922 4923 /* Restore eh data registers. */ 4924 if (cfun->machine->use_eh_return_p) 4925 { 4926 Rb = cfun->machine->eh_return_data_first_regno; 4927 Re = cfun->machine->eh_return_data_last_regno; 4928 4929 /* No need to pop $fp, $gp, or $lp. */ 4930 nds32_emit_stack_pop_multiple (Rb, Re, false, false, false); 4931 } 4932 4933 /* Get callee_first_regno and callee_last_regno. */ 4934 Rb = cfun->machine->callee_saved_first_gpr_regno; 4935 Re = cfun->machine->callee_saved_last_gpr_regno; 4936 4937 /* If $fp, $gp, $lp, and all callee-save registers are NOT required 4938 to be saved, we don't have to create multiple pop instruction. 4939 Otherwise, a multiple pop instruction is needed. */ 4940 if (!(Rb == SP_REGNUM && Re == SP_REGNUM 4941 && cfun->machine->fp_size == 0 4942 && cfun->machine->gp_size == 0 4943 && cfun->machine->lp_size == 0)) 4944 { 4945 /* Create multiple pop instruction rtx. */ 4946 nds32_emit_stack_pop_multiple ( 4947 Rb, Re, 4948 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); 4949 } 4950 4951 /* If this is a variadic function, we do not have to restore argument 4952 registers but need to adjust stack pointer back to previous stack 4953 frame location before return. */ 4954 if (cfun->machine->va_args_size != 0) 4955 { 4956 /* Generate sp adjustment instruction. 4957 We need to consider padding bytes here. */ 4958 sp_adjust = cfun->machine->va_args_size 4959 + cfun->machine->va_args_area_padding_bytes; 4960 4961 nds32_emit_adjust_frame (stack_pointer_rtx, 4962 stack_pointer_rtx, 4963 sp_adjust); 4964 } 4965 4966 /* If this function uses __builtin_eh_return, make stack adjustment 4967 for exception handler. */ 4968 if (cfun->machine->use_eh_return_p) 4969 { 4970 /* We need to unwind the stack by the offset computed by 4971 EH_RETURN_STACKADJ_RTX. However, at this point the CFA is 4972 based on SP. Ideally we would update the SP and define the 4973 CFA along the lines of: 4974 4975 SP = SP + EH_RETURN_STACKADJ_RTX 4976 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) 4977 4978 However the dwarf emitter only understands a constant 4979 register offset. 4980 4981 The solution chosen here is to use the otherwise $ta ($r15) 4982 as a temporary register to hold the current SP value. The 4983 CFA is described using $ta then SP is modified. */ 4984 4985 rtx ta_reg; 4986 rtx insn; 4987 4988 ta_reg = gen_rtx_REG (SImode, TA_REGNUM); 4989 4990 insn = emit_move_insn (ta_reg, stack_pointer_rtx); 4991 add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg); 4992 RTX_FRAME_RELATED_P (insn) = 1; 4993 4994 emit_insn (gen_addsi3 (stack_pointer_rtx, 4995 stack_pointer_rtx, 4996 EH_RETURN_STACKADJ_RTX)); 4997 4998 /* Ensure the assignment to $ta does not get optimized away. */ 4999 emit_use (ta_reg); 5000 } 5001 5002 /* Generate return instruction. */ 5003 if (!sibcall_p) 5004 emit_jump_insn (gen_return_internal ()); 5005} 5006 5007/* Function for v3push prologue. */ 5008void 5009nds32_expand_prologue_v3push (void) 5010{ 5011 int fp_adjust; 5012 int sp_adjust; 5013 int fpr_space = 0; 5014 unsigned Rb, Re; 5015 5016 /* Compute and setup stack frame size. 5017 The result will be in cfun->machine. */ 5018 nds32_compute_stack_frame (); 5019 5020 if (cfun->machine->callee_saved_gpr_regs_size > 0) 5021 df_set_regs_ever_live (FP_REGNUM, 1); 5022 5023 /* Check frame_pointer_needed again to prevent fp is need after reload. */ 5024 if (frame_pointer_needed) 5025 cfun->machine->fp_as_gp_p = false; 5026 5027 /* If the function is 'naked', 5028 we do not have to generate prologue code fragment. */ 5029 if (cfun->machine->naked_p && !flag_pic) 5030 return; 5031 5032 /* Get callee_first_regno and callee_last_regno. */ 5033 Rb = cfun->machine->callee_saved_first_gpr_regno; 5034 Re = cfun->machine->callee_saved_last_gpr_regno; 5035 5036 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, 5037 where imm8u has to be 8-byte alignment. */ 5038 sp_adjust = cfun->machine->local_size 5039 + cfun->machine->out_args_size 5040 + cfun->machine->callee_saved_area_gpr_padding_bytes 5041 + cfun->machine->callee_saved_fpr_regs_size; 5042 5043 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5044 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) 5045 { 5046 /* We can use 'push25 Re,imm8u'. */ 5047 5048 /* nds32_emit_stack_v3push(last_regno, sp_adjust), 5049 the pattern 'stack_v3push' is implemented in nds32.md. */ 5050 nds32_emit_stack_v3push (Rb, Re, sp_adjust); 5051 5052 /* Save fpu registers. */ 5053 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5054 { 5055 /* Calculate fpr position. */ 5056 int fpr_position = cfun->machine->local_size 5057 + cfun->machine->out_args_size; 5058 /* Emit fpu store instruction, using [$sp + offset] store 5059 fpu registers. */ 5060 nds32_emit_push_fpr_callee_saved (fpr_position); 5061 } 5062 5063 /* Check frame_pointer_needed to see 5064 if we shall emit fp adjustment instruction. */ 5065 if (frame_pointer_needed) 5066 { 5067 /* adjust $fp = $sp + 4 ($fp size) 5068 + 4 ($gp size) 5069 + 4 ($lp size) 5070 + (4 * n) (callee-saved registers) 5071 + sp_adjust ('push25 Re,imm8u') 5072 Note: Since we use 'push25 Re,imm8u', 5073 the position of stack pointer is further 5074 changed after push instruction. 5075 Hence, we need to take sp_adjust value 5076 into consideration. */ 5077 fp_adjust = cfun->machine->fp_size 5078 + cfun->machine->gp_size 5079 + cfun->machine->lp_size 5080 + cfun->machine->callee_saved_gpr_regs_size 5081 + sp_adjust; 5082 5083 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 5084 stack_pointer_rtx, 5085 fp_adjust); 5086 } 5087 } 5088 else 5089 { 5090 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5091 { 5092 /* Calculate fpr space. */ 5093 fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 5094 + cfun->machine->callee_saved_fpr_regs_size; 5095 5096 /* We have to use 'push25 Re, fpr_space', to pre-allocate 5097 callee saved fpr registers space. */ 5098 nds32_emit_stack_v3push (Rb, Re, fpr_space); 5099 nds32_emit_push_fpr_callee_saved (0); 5100 } 5101 else 5102 { 5103 /* We have to use 'push25 Re,0' and 5104 expand one more instruction to adjust $sp later. */ 5105 5106 /* nds32_emit_stack_v3push(last_regno, sp_adjust), 5107 the pattern 'stack_v3push' is implemented in nds32.md. */ 5108 nds32_emit_stack_v3push (Rb, Re, 0); 5109 } 5110 5111 /* Check frame_pointer_needed to see 5112 if we shall emit fp adjustment instruction. */ 5113 if (frame_pointer_needed) 5114 { 5115 /* adjust $fp = $sp + 4 ($fp size) 5116 + 4 ($gp size) 5117 + 4 ($lp size) 5118 + (4 * n) (callee-saved registers) 5119 Note: Since we use 'push25 Re,0', 5120 the stack pointer is just at the position 5121 after push instruction. 5122 No need to take sp_adjust into consideration. */ 5123 fp_adjust = cfun->machine->fp_size 5124 + cfun->machine->gp_size 5125 + cfun->machine->lp_size 5126 + cfun->machine->callee_saved_gpr_regs_size; 5127 5128 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5129 { 5130 /* We use 'push25 Re, fpr_space', the $sp is 5131 on callee saved fpr position, so need to consider 5132 fpr space. */ 5133 fp_adjust = fp_adjust + fpr_space; 5134 } 5135 5136 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 5137 stack_pointer_rtx, 5138 fp_adjust); 5139 } 5140 5141 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5142 { 5143 /* We use 'push25 Re, fpr_space', 5144 the $sp is on callee saved fpr position, 5145 no need to consider fpr space. */ 5146 sp_adjust = sp_adjust - fpr_space; 5147 } 5148 5149 /* Because we use 'push25 Re,0', 5150 we need to expand one more instruction to adjust $sp. 5151 using NEGATIVE value to tell that we are decreasing address. */ 5152 nds32_emit_adjust_frame (stack_pointer_rtx, 5153 stack_pointer_rtx, 5154 -1 * sp_adjust); 5155 } 5156 5157 /* Emit gp setup instructions for -fpic. */ 5158 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) 5159 nds32_emit_load_gp (); 5160 5161 /* Prevent the instruction scheduler from 5162 moving instructions across the boundary. */ 5163 emit_insn (gen_blockage ()); 5164} 5165 5166/* Function for v3pop epilogue. */ 5167void 5168nds32_expand_epilogue_v3pop (bool sibcall_p) 5169{ 5170 int sp_adjust; 5171 unsigned Rb, Re; 5172 5173 /* Compute and setup stack frame size. 5174 The result will be in cfun->machine. */ 5175 nds32_compute_stack_frame (); 5176 5177 /* Prevent the instruction scheduler from 5178 moving instructions across the boundary. */ 5179 emit_insn (gen_blockage ()); 5180 5181 /* If the function is 'naked', we do not have to generate 5182 epilogue code fragment BUT 'ret' instruction. */ 5183 if (cfun->machine->naked_p) 5184 { 5185 /* Generate return instruction by using 'return_internal' pattern. 5186 Make sure this instruction is after gen_blockage(). 5187 First we need to check this is a function without sibling call. */ 5188 if (!sibcall_p) 5189 { 5190 /* We need to further check attributes to determine whether 5191 there should be return instruction at epilogue. 5192 If the attribute naked exists but -mno-ret-in-naked-func 5193 is issued, there is NO need to generate return instruction. */ 5194 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 5195 return; 5196 5197 emit_jump_insn (gen_return_internal ()); 5198 } 5199 return; 5200 } 5201 5202 /* Get callee_first_regno and callee_last_regno. */ 5203 Rb = cfun->machine->callee_saved_first_gpr_regno; 5204 Re = cfun->machine->callee_saved_last_gpr_regno; 5205 5206 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, 5207 where imm8u has to be 8-byte alignment. */ 5208 sp_adjust = cfun->machine->local_size 5209 + cfun->machine->out_args_size 5210 + cfun->machine->callee_saved_area_gpr_padding_bytes 5211 + cfun->machine->callee_saved_fpr_regs_size; 5212 5213 /* We have to consider alloca issue as well. 5214 If the function does call alloca(), the stack pointer is not fixed. 5215 In that case, we cannot use 'pop25 Re,imm8u' directly. 5216 We have to caculate stack pointer from frame pointer 5217 and then use 'pop25 Re,0'. 5218 Of course, the frame_pointer_needed should be nonzero 5219 if the function calls alloca(). */ 5220 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5221 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) 5222 && !cfun->calls_alloca) 5223 { 5224 /* Restore fpu registers. */ 5225 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5226 { 5227 int fpr_position = cfun->machine->local_size 5228 + cfun->machine->out_args_size; 5229 /* Emit fpu load instruction, using [$sp + offset] restore 5230 fpu registers. */ 5231 nds32_emit_v3pop_fpr_callee_saved (fpr_position); 5232 } 5233 5234 /* We can use 'pop25 Re,imm8u'. */ 5235 5236 /* nds32_emit_stack_v3pop(last_regno, sp_adjust), 5237 the pattern 'stack_v3pop' is implementad in nds32.md. */ 5238 nds32_emit_stack_v3pop (Rb, Re, sp_adjust); 5239 } 5240 else 5241 { 5242 /* We have to use 'pop25 Re,0', and prior to it, 5243 we must expand one more instruction to adjust $sp. */ 5244 5245 if (frame_pointer_needed) 5246 { 5247 /* adjust $sp = $fp - 4 ($fp size) 5248 - 4 ($gp size) 5249 - 4 ($lp size) 5250 - (4 * n) (callee-saved registers) 5251 Note: No need to adjust 5252 cfun->machine->callee_saved_area_gpr_padding_bytes, 5253 because we want to adjust stack pointer 5254 to the position for pop instruction. */ 5255 sp_adjust = cfun->machine->fp_size 5256 + cfun->machine->gp_size 5257 + cfun->machine->lp_size 5258 + cfun->machine->callee_saved_gpr_regs_size; 5259 5260 /* Restore fpu registers. */ 5261 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5262 { 5263 /* Set $sp to callee saved fpr position, we need to restore 5264 fpr registers. */ 5265 sp_adjust = sp_adjust 5266 + cfun->machine->callee_saved_area_gpr_padding_bytes 5267 + cfun->machine->callee_saved_fpr_regs_size; 5268 5269 nds32_emit_adjust_frame (stack_pointer_rtx, 5270 hard_frame_pointer_rtx, 5271 -1 * sp_adjust); 5272 5273 /* Emit fpu load instruction, using [$sp + offset] restore 5274 fpu registers. */ 5275 nds32_emit_v3pop_fpr_callee_saved (0); 5276 } 5277 else 5278 { 5279 nds32_emit_adjust_frame (stack_pointer_rtx, 5280 hard_frame_pointer_rtx, 5281 -1 * sp_adjust); 5282 } 5283 } 5284 else 5285 { 5286 /* If frame pointer is NOT needed, 5287 we cannot calculate the sp adjustment from frame pointer. 5288 Instead, we calculate the adjustment by local_size, 5289 out_args_size, and callee_saved_area_padding_bytes. 5290 Notice that such sp adjustment value may be out of range, 5291 so we have to deal with it as well. */ 5292 5293 /* Adjust $sp = $sp + local_size + out_args_size 5294 + callee_saved_area_gpr_padding_bytes 5295 + callee_saved_fpr_regs_size. */ 5296 sp_adjust = cfun->machine->local_size 5297 + cfun->machine->out_args_size 5298 + cfun->machine->callee_saved_area_gpr_padding_bytes 5299 + cfun->machine->callee_saved_fpr_regs_size; 5300 5301 /* Restore fpu registers. */ 5302 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5303 { 5304 /* Set $sp to callee saved fpr position, we need to restore 5305 fpr registers. */ 5306 sp_adjust = sp_adjust 5307 - cfun->machine->callee_saved_area_gpr_padding_bytes 5308 - cfun->machine->callee_saved_fpr_regs_size; 5309 5310 nds32_emit_adjust_frame (stack_pointer_rtx, 5311 stack_pointer_rtx, 5312 sp_adjust); 5313 5314 /* Emit fpu load instruction, using [$sp + offset] restore 5315 fpu registers. */ 5316 nds32_emit_v3pop_fpr_callee_saved (0); 5317 } 5318 else 5319 { 5320 /* sp_adjust value may be out of range of the addi instruction, 5321 create alternative add behavior with TA_REGNUM if necessary, 5322 using POSITIVE value to tell that we are increasing 5323 address. */ 5324 nds32_emit_adjust_frame (stack_pointer_rtx, 5325 stack_pointer_rtx, 5326 sp_adjust); 5327 } 5328 } 5329 5330 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5331 { 5332 /* We have fpr need to restore, so $sp is set on callee saved fpr 5333 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */ 5334 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 5335 + cfun->machine->callee_saved_fpr_regs_size; 5336 nds32_emit_stack_v3pop (Rb, Re, fpr_space); 5337 } 5338 else 5339 { 5340 /* nds32_emit_stack_v3pop(last_regno, sp_adjust), 5341 the pattern 'stack_v3pop' is implementad in nds32.md. */ 5342 nds32_emit_stack_v3pop (Rb, Re, 0); 5343 } 5344 } 5345 /* Generate return instruction. */ 5346 emit_jump_insn (gen_pop25return ()); 5347} 5348 5349/* Return nonzero if this function is known to have a null epilogue. 5350 This allows the optimizer to omit jumps to jumps if no stack 5351 was created. */ 5352int 5353nds32_can_use_return_insn (void) 5354{ 5355 int sp_adjust; 5356 5357 /* Prior to reloading, we can't tell how many registers must be saved. 5358 Thus we cannot determine whether this function has null epilogue. */ 5359 if (!reload_completed) 5360 return 0; 5361 5362 /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, 5363 we cannot use return instruction. */ 5364 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 5365 return 0; 5366 5367 sp_adjust = cfun->machine->local_size 5368 + cfun->machine->out_args_size 5369 + cfun->machine->callee_saved_area_gpr_padding_bytes 5370 + cfun->machine->callee_saved_fpr_regs_size; 5371 if (!cfun->machine->fp_as_gp_p 5372 && satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5373 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) 5374 && !cfun->calls_alloca 5375 && NDS32_V3PUSH_AVAILABLE_P 5376 && !(TARGET_HARD_FLOAT 5377 && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM))) 5378 return 1; 5379 5380 /* If no stack was created, two conditions must be satisfied: 5381 1. This is a naked function. 5382 So there is no callee-saved, local size, or outgoing size. 5383 2. This is NOT a variadic function. 5384 So there is no pushing arguement registers into the stack. */ 5385 return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); 5386} 5387 5388scalar_int_mode 5389nds32_case_vector_shorten_mode (int min_offset, int max_offset, 5390 rtx body ATTRIBUTE_UNUSED) 5391{ 5392 if (min_offset < 0 || max_offset >= 0x2000) 5393 return SImode; 5394 else 5395 { 5396 /* The jump table maybe need to 2 byte alignment, 5397 so reserved 1 byte for check max_offset. */ 5398 if (max_offset >= 0xff) 5399 return HImode; 5400 else 5401 return QImode; 5402 } 5403} 5404 5405/* ------------------------------------------------------------------------ */ 5406 5407/* Return alignment for the label. */ 5408int 5409nds32_target_alignment (rtx_insn *label) 5410{ 5411 rtx_insn *insn; 5412 5413 if (!NDS32_ALIGN_P ()) 5414 return 0; 5415 5416 insn = next_active_insn (label); 5417 5418 /* Always align to 4 byte when first instruction after label is jump 5419 instruction since length for that might changed, so let's always align 5420 it for make sure we don't lose any perfomance here. */ 5421 if (insn == 0 5422 || (get_attr_length (insn) == 2 5423 && !JUMP_P (insn) && !CALL_P (insn))) 5424 return 0; 5425 else 5426 return 2; 5427} 5428 5429/* Return alignment for data. */ 5430unsigned int 5431nds32_data_alignment (tree data, 5432 unsigned int basic_align) 5433{ 5434 if ((basic_align < BITS_PER_WORD) 5435 && (TREE_CODE (data) == ARRAY_TYPE 5436 || TREE_CODE (data) == UNION_TYPE 5437 || TREE_CODE (data) == RECORD_TYPE)) 5438 return BITS_PER_WORD; 5439 else 5440 return basic_align; 5441} 5442 5443/* Return alignment for constant value. */ 5444static HOST_WIDE_INT 5445nds32_constant_alignment (const_tree constant, 5446 HOST_WIDE_INT basic_align) 5447{ 5448 /* Make string literal and constant for constructor to word align. */ 5449 if (((TREE_CODE (constant) == STRING_CST 5450 || TREE_CODE (constant) == CONSTRUCTOR 5451 || TREE_CODE (constant) == UNION_TYPE 5452 || TREE_CODE (constant) == RECORD_TYPE 5453 || TREE_CODE (constant) == ARRAY_TYPE) 5454 && basic_align < BITS_PER_WORD)) 5455 return BITS_PER_WORD; 5456 else 5457 return basic_align; 5458} 5459 5460/* Return alignment for local variable. */ 5461unsigned int 5462nds32_local_alignment (tree local ATTRIBUTE_UNUSED, 5463 unsigned int basic_align) 5464{ 5465 bool at_least_align_to_word = false; 5466 /* Make local array, struct and union at least align to word for make 5467 sure it can unroll memcpy when initialize by constant. */ 5468 switch (TREE_CODE (local)) 5469 { 5470 case ARRAY_TYPE: 5471 case RECORD_TYPE: 5472 case UNION_TYPE: 5473 at_least_align_to_word = true; 5474 break; 5475 default: 5476 at_least_align_to_word = false; 5477 break; 5478 } 5479 if (at_least_align_to_word 5480 && (basic_align < BITS_PER_WORD)) 5481 return BITS_PER_WORD; 5482 else 5483 return basic_align; 5484} 5485 5486bool 5487nds32_split_double_word_load_store_p(rtx *operands, bool load_p) 5488{ 5489 rtx mem = load_p ? operands[1] : operands[0]; 5490 /* Do split at split2 if -O0 or schedule 2 not enable. */ 5491 if (optimize == 0 || !flag_schedule_insns_after_reload) 5492 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); 5493 5494 /* Split double word load store after copy propgation. */ 5495 if (current_pass == NULL) 5496 return false; 5497 5498 const char *pass_name = current_pass->name; 5499 if (pass_name && ((strcmp (pass_name, "split3") == 0) 5500 || (strcmp (pass_name, "split5") == 0))) 5501 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); 5502 5503 return false; 5504} 5505 5506static bool 5507nds32_use_blocks_for_constant_p (machine_mode mode, 5508 const_rtx x ATTRIBUTE_UNUSED) 5509{ 5510 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 5511 && (mode == DFmode || mode == SFmode)) 5512 return true; 5513 else 5514 return false; 5515} 5516 5517/* ------------------------------------------------------------------------ */ 5518 5519/* PART 5: Initialize target hook structure and definitions. */ 5520 5521/* Controlling the Compilation Driver. */ 5522 5523 5524/* Run-time Target Specification. */ 5525 5526 5527/* Defining Data Structures for Per-function Information. */ 5528 5529 5530/* Storage Layout. */ 5531 5532#undef TARGET_PROMOTE_FUNCTION_MODE 5533#define TARGET_PROMOTE_FUNCTION_MODE \ 5534 default_promote_function_mode_always_promote 5535 5536#undef TARGET_EXPAND_TO_RTL_HOOK 5537#define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook 5538 5539#undef TARGET_CONSTANT_ALIGNMENT 5540#define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment 5541 5542 5543/* Layout of Source Language Data Types. */ 5544 5545 5546/* Register Usage. */ 5547 5548/* -- Basic Characteristics of Registers. */ 5549 5550#undef TARGET_CONDITIONAL_REGISTER_USAGE 5551#define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage 5552 5553/* -- Order of Allocation of Registers. */ 5554 5555/* -- How Values Fit in Registers. */ 5556 5557#undef TARGET_HARD_REGNO_NREGS 5558#define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs 5559 5560#undef TARGET_HARD_REGNO_MODE_OK 5561#define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok 5562 5563#undef TARGET_MODES_TIEABLE_P 5564#define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p 5565 5566/* -- Handling Leaf Functions. */ 5567 5568/* -- Registers That Form a Stack. */ 5569 5570 5571/* Register Classes. */ 5572 5573#undef TARGET_CLASS_MAX_NREGS 5574#define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs 5575 5576#undef TARGET_REGISTER_PRIORITY 5577#define TARGET_REGISTER_PRIORITY nds32_register_priority 5578 5579#undef TARGET_CAN_CHANGE_MODE_CLASS 5580#define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class 5581 5582 5583/* Obsolete Macros for Defining Constraints. */ 5584 5585 5586/* Stack Layout and Calling Conventions. */ 5587 5588/* -- Basic Stack Layout. */ 5589 5590/* -- Exception Handling Support. */ 5591 5592/* -- Specifying How Stack Checking is Done. */ 5593 5594/* -- Registers That Address the Stack Frame. */ 5595 5596/* -- Eliminating Frame Pointer and Arg Pointer. */ 5597 5598#undef TARGET_CAN_ELIMINATE 5599#define TARGET_CAN_ELIMINATE nds32_can_eliminate 5600 5601/* -- Passing Function Arguments on the Stack. */ 5602 5603/* -- Passing Arguments in Registers. */ 5604 5605#undef TARGET_FUNCTION_ARG 5606#define TARGET_FUNCTION_ARG nds32_function_arg 5607 5608#undef TARGET_MUST_PASS_IN_STACK 5609#define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack 5610 5611#undef TARGET_ARG_PARTIAL_BYTES 5612#define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes 5613 5614#undef TARGET_FUNCTION_ARG_ADVANCE 5615#define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance 5616 5617#undef TARGET_FUNCTION_ARG_BOUNDARY 5618#define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary 5619 5620#undef TARGET_VECTOR_MODE_SUPPORTED_P 5621#define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p 5622 5623/* -- How Scalar Function Values Are Returned. */ 5624 5625#undef TARGET_FUNCTION_VALUE 5626#define TARGET_FUNCTION_VALUE nds32_function_value 5627 5628#undef TARGET_LIBCALL_VALUE 5629#define TARGET_LIBCALL_VALUE nds32_libcall_value 5630 5631#undef TARGET_FUNCTION_VALUE_REGNO_P 5632#define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p 5633 5634/* -- How Large Values Are Returned. */ 5635 5636#undef TARGET_RETURN_IN_MEMORY 5637#define TARGET_RETURN_IN_MEMORY nds32_return_in_memory 5638 5639/* -- Caller-Saves Register Allocation. */ 5640 5641/* -- Function Entry and Exit. */ 5642 5643#undef TARGET_ASM_FUNCTION_PROLOGUE 5644#define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue 5645 5646#undef TARGET_ASM_FUNCTION_END_PROLOGUE 5647#define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue 5648 5649#undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE 5650#define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue 5651 5652#undef TARGET_ASM_FUNCTION_EPILOGUE 5653#define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue 5654 5655#undef TARGET_ASM_OUTPUT_MI_THUNK 5656#define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk 5657 5658#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 5659#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 5660 5661/* -- Generating Code for Profiling. */ 5662 5663/* -- Permitting tail calls. */ 5664 5665#undef TARGET_FUNCTION_OK_FOR_SIBCALL 5666#define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall 5667 5668#undef TARGET_WARN_FUNC_RETURN 5669#define TARGET_WARN_FUNC_RETURN nds32_warn_func_return 5670 5671/* Stack smashing protection. */ 5672 5673 5674/* Implementing the Varargs Macros. */ 5675 5676#undef TARGET_SETUP_INCOMING_VARARGS 5677#define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs 5678 5679#undef TARGET_STRICT_ARGUMENT_NAMING 5680#define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming 5681 5682 5683/* Trampolines for Nested Functions. */ 5684 5685#undef TARGET_ASM_TRAMPOLINE_TEMPLATE 5686#define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template 5687 5688#undef TARGET_TRAMPOLINE_INIT 5689#define TARGET_TRAMPOLINE_INIT nds32_trampoline_init 5690 5691 5692/* Implicit Calls to Library Routines. */ 5693 5694 5695/* Addressing Modes. */ 5696 5697#undef TARGET_LEGITIMATE_ADDRESS_P 5698#define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p 5699 5700#undef TARGET_LEGITIMIZE_ADDRESS 5701#define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address 5702 5703#undef TARGET_LEGITIMATE_CONSTANT_P 5704#define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p 5705 5706#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE 5707#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode 5708 5709#undef TARGET_CANNOT_FORCE_CONST_MEM 5710#define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem 5711 5712#undef TARGET_DELEGITIMIZE_ADDRESS 5713#define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address 5714 5715 5716/* Anchored Addresses. */ 5717 5718 5719/* Condition Code Status. */ 5720 5721/* -- Representation of condition codes using (cc0). */ 5722 5723/* -- Representation of condition codes using registers. */ 5724 5725#undef TARGET_CANONICALIZE_COMPARISON 5726#define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison 5727 5728/* -- Macros to control conditional execution. */ 5729 5730 5731/* Describing Relative Costs of Operations. */ 5732 5733#undef TARGET_REGISTER_MOVE_COST 5734#define TARGET_REGISTER_MOVE_COST nds32_register_move_cost 5735 5736#undef TARGET_MEMORY_MOVE_COST 5737#define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost 5738 5739#undef TARGET_RTX_COSTS 5740#define TARGET_RTX_COSTS nds32_rtx_costs 5741 5742#undef TARGET_ADDRESS_COST 5743#define TARGET_ADDRESS_COST nds32_address_cost 5744 5745 5746/* Adjusting the Instruction Scheduler. */ 5747 5748 5749/* Dividing the Output into Sections (Texts, Data, . . . ). */ 5750 5751#undef TARGET_ENCODE_SECTION_INFO 5752#define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info 5753 5754 5755/* Position Independent Code. */ 5756 5757 5758/* Defining the Output Assembler Language. */ 5759 5760/* -- The Overall Framework of an Assembler File. */ 5761 5762#undef TARGET_ASM_FILE_START 5763#define TARGET_ASM_FILE_START nds32_asm_file_start 5764#undef TARGET_ASM_FILE_END 5765#define TARGET_ASM_FILE_END nds32_asm_file_end 5766 5767/* -- Output of Data. */ 5768 5769#undef TARGET_ASM_ALIGNED_HI_OP 5770#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" 5771 5772#undef TARGET_ASM_ALIGNED_SI_OP 5773#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 5774 5775#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 5776#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra 5777 5778/* -- Output of Uninitialized Variables. */ 5779 5780/* -- Output and Generation of Labels. */ 5781 5782#undef TARGET_ASM_GLOBALIZE_LABEL 5783#define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label 5784 5785/* -- How Initialization Functions Are Handled. */ 5786 5787/* -- Macros Controlling Initialization Routines. */ 5788 5789/* -- Output of Assembler Instructions. */ 5790 5791#undef TARGET_PRINT_OPERAND 5792#define TARGET_PRINT_OPERAND nds32_print_operand 5793#undef TARGET_PRINT_OPERAND_ADDRESS 5794#define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address 5795 5796/* -- Output of Dispatch Tables. */ 5797 5798/* -- Assembler Commands for Exception Regions. */ 5799 5800#undef TARGET_DWARF_REGISTER_SPAN 5801#define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span 5802 5803/* -- Assembler Commands for Alignment. */ 5804 5805 5806/* Controlling Debugging Information Format. */ 5807 5808/* -- Macros Affecting All Debugging Formats. */ 5809 5810/* -- Specific Options for DBX Output. */ 5811 5812/* -- Open-Ended Hooks for DBX Format. */ 5813 5814/* -- File Names in DBX Format. */ 5815 5816/* -- Macros for DWARF Output. */ 5817 5818/* -- Macros for VMS Debug Format. */ 5819 5820 5821/* Cross Compilation and Floating Point. */ 5822 5823 5824/* Mode Switching Instructions. */ 5825 5826 5827/* Defining target-specific uses of __attribute__. */ 5828 5829#undef TARGET_ATTRIBUTE_TABLE 5830#define TARGET_ATTRIBUTE_TABLE nds32_attribute_table 5831 5832#undef TARGET_MERGE_DECL_ATTRIBUTES 5833#define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes 5834 5835#undef TARGET_INSERT_ATTRIBUTES 5836#define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes 5837 5838#undef TARGET_OPTION_PRAGMA_PARSE 5839#define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse 5840 5841#undef TARGET_OPTION_OVERRIDE 5842#define TARGET_OPTION_OVERRIDE nds32_option_override 5843 5844 5845/* Emulating TLS. */ 5846 5847#undef TARGET_HAVE_TLS 5848#define TARGET_HAVE_TLS TARGET_LINUX_ABI 5849 5850 5851/* Defining coprocessor specifics for MIPS targets. */ 5852 5853 5854/* Parameters for Precompiled Header Validity Checking. */ 5855 5856 5857/* C++ ABI parameters. */ 5858 5859 5860/* Adding support for named address spaces. */ 5861 5862 5863/* Miscellaneous Parameters. */ 5864 5865#undef TARGET_MD_ASM_ADJUST 5866#define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust 5867 5868#undef TARGET_INIT_BUILTINS 5869#define TARGET_INIT_BUILTINS nds32_init_builtins 5870 5871#undef TARGET_BUILTIN_DECL 5872#define TARGET_BUILTIN_DECL nds32_builtin_decl 5873 5874#undef TARGET_EXPAND_BUILTIN 5875#define TARGET_EXPAND_BUILTIN nds32_expand_builtin 5876 5877#undef TARGET_INIT_LIBFUNCS 5878#define TARGET_INIT_LIBFUNCS nds32_init_libfuncs 5879 5880#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 5881#define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p 5882 5883#undef TARGET_HAVE_SPECULATION_SAFE_VALUE 5884#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 5885 5886 5887/* ------------------------------------------------------------------------ */ 5888 5889/* Initialize the GCC target structure. */ 5890 5891struct gcc_target targetm = TARGET_INITIALIZER; 5892 5893/* ------------------------------------------------------------------------ */ 5894