1; Copyright (C) 2005-2020 Free Software Foundation, Inc.
2;
3; This file is part of GCC.
4;
5; GCC is free software; you can redistribute it and/or modify it under
6; the terms of the GNU General Public License as published by the Free
7; Software Foundation; either version 3, or (at your option) any later
8; version.
9;
10; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
11; WARRANTY; without even the implied warranty of MERCHANTABILITY or
12; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13; for more details.
14;
15; You should have received a copy of the GNU General Public License
16; along with GCC; see the file COPYING3.  If not see
17; <http://www.gnu.org/licenses/>.
18
19HeaderInclude
20config/ia64/ia64-opts.h
21
22; Which cpu are we scheduling for.
23Variable
24enum processor_type ia64_tune = PROCESSOR_ITANIUM2
25
26mbig-endian
27Target Report RejectNegative Mask(BIG_ENDIAN)
28Generate big endian code.
29
30mlittle-endian
31Target Report RejectNegative InverseMask(BIG_ENDIAN)
32Generate little endian code.
33
34mgnu-as
35Target Report Mask(GNU_AS)
36Generate code for GNU as.
37
38mgnu-ld
39Target Report Mask(GNU_LD)
40Generate code for GNU ld.
41
42mvolatile-asm-stop
43Target Report Mask(VOL_ASM_STOP)
44Emit stop bits before and after volatile extended asms.
45
46mregister-names
47Target Mask(REG_NAMES)
48Use in/loc/out register names.
49
50mno-sdata
51Target Report RejectNegative Mask(NO_SDATA)
52
53msdata
54Target Report RejectNegative InverseMask(NO_SDATA)
55Enable use of sdata/scommon/sbss.
56
57mno-pic
58Target Report RejectNegative Mask(NO_PIC)
59Generate code without GP reg.
60
61mconstant-gp
62Target Report RejectNegative Mask(CONST_GP)
63gp is constant (but save/restore gp on indirect calls).
64
65mauto-pic
66Target Report RejectNegative Mask(AUTO_PIC)
67Generate self-relocatable code.
68
69minline-float-divide-min-latency
70Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
71Generate inline floating point division, optimize for latency.
72
73minline-float-divide-max-throughput
74Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
75Generate inline floating point division, optimize for throughput.
76
77mno-inline-float-divide
78Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
79
80minline-int-divide-min-latency
81Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
82Generate inline integer division, optimize for latency.
83
84minline-int-divide-max-throughput
85Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
86Generate inline integer division, optimize for throughput.
87
88mno-inline-int-divide
89Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
90Do not inline integer division.
91
92minline-sqrt-min-latency
93Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
94Generate inline square root, optimize for latency.
95
96minline-sqrt-max-throughput
97Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
98Generate inline square root, optimize for throughput.
99
100mno-inline-sqrt
101Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
102Do not inline square root.
103
104mdwarf2-asm
105Target Report Mask(DWARF2_ASM)
106Enable DWARF line debug info via GNU as.
107
108mearly-stop-bits
109Target Report Mask(EARLY_STOP_BITS)
110Enable earlier placing stop bits for better scheduling.
111
112mfixed-range=
113Target RejectNegative Joined Var(ia64_deferred_options) Defer
114Specify range of registers to make fixed.
115
116mtls-size=
117Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
118Specify bit size of immediate TLS offsets.
119
120mtune=
121Target RejectNegative Joined Enum(ia64_tune) Var(ia64_tune)
122Schedule code for given CPU.
123
124Enum
125Name(ia64_tune) Type(enum processor_type)
126Known Itanium CPUs (for use with the -mtune= option):
127
128EnumValue
129Enum(ia64_tune) String(itanium2) Value(PROCESSOR_ITANIUM2)
130
131EnumValue
132Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
133
134msched-br-data-spec
135Target Report Var(mflag_sched_br_data_spec) Init(0)
136Use data speculation before reload.
137
138msched-ar-data-spec
139Target Report Var(mflag_sched_ar_data_spec) Init(1)
140Use data speculation after reload.
141
142msched-control-spec
143Target Report Var(mflag_sched_control_spec) Init(2)
144Use control speculation.
145
146msched-br-in-data-spec
147Target Report Var(mflag_sched_br_in_data_spec) Init(1)
148Use in block data speculation before reload.
149
150msched-ar-in-data-spec
151Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
152Use in block data speculation after reload.
153
154msched-in-control-spec
155Target Report Var(mflag_sched_in_control_spec) Init(1)
156Use in block control speculation.
157
158msched-spec-ldc
159Target Report Var(mflag_sched_spec_ldc) Init(1)
160Use simple data speculation check.
161
162msched-spec-control-ldc
163Target Report Var(mflag_sched_spec_control_ldc) Init(0)
164Use simple data speculation check for control speculation.
165
166msched-prefer-non-data-spec-insns
167Target WarnRemoved
168
169msched-prefer-non-control-spec-insns
170Target WarnRemoved
171
172msched-count-spec-in-critical-path
173Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
174Count speculative dependencies while calculating priority of instructions.
175
176msched-stop-bits-after-every-cycle
177Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
178Place a stop bit after every cycle when scheduling.
179
180msched-fp-mem-deps-zero-cost
181Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
182Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group.
183
184msched-max-memory-insns=
185Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
186Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts.  Default value is 1.
187
188msched-max-memory-insns-hard-limit
189Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
190Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached).
191
192msel-sched-dont-check-control-spec
193Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
194Don't generate checks for control speculation in selective scheduling.
195
196; This comment is to ensure we retain the blank line above.
197