1;; Scheduling description for Alpha EV4. 2;; Copyright (C) 2002-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20; On EV4 there are two classes of resources to consider: resources needed 21; to issue, and resources needed to execute. IBUS[01] are in the first 22; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second. 23; (There are a few other register-like resources, but ...) 24 25(define_automaton "ev4_0,ev4_1,ev4_2") 26(define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0") 27(define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1") 28(define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2") 29(define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1") 30 31; Assume type "multi" single issues. 32(define_insn_reservation "ev4_multi" 1 33 (and (eq_attr "tune" "ev4") 34 (eq_attr "type" "multi")) 35 "ev4_ib0+ev4_ib1") 36 37; Loads from L0 completes in three cycles. adjust_cost still factors 38; in user-specified memory latency, so return 1 here. 39(define_insn_reservation "ev4_ld" 1 40 (and (eq_attr "tune" "ev4") 41 (eq_attr "type" "ild,fld,ldsym,ld_l")) 42 "ev4_ib01+ev4_abox") 43 44; Stores can issue before the data (but not address) is ready. 45(define_insn_reservation "ev4_ist" 1 46 (and (eq_attr "tune" "ev4") 47 (eq_attr "type" "ist,st_c")) 48 "ev4_ib1+ev4_abox") 49 50(define_insn_reservation "ev4_fst" 1 51 (and (eq_attr "tune" "ev4") 52 (eq_attr "type" "fst")) 53 "ev4_ib0+ev4_abox") 54 55; Memory barrier blocks ABOX insns until it's acknowledged by the external 56; memory bus. This may be *quite* slow. Setting this to 4 cycles gets 57; about all the benefit without making the DFA too large. 58(define_insn_reservation "ev4_mb" 4 59 (and (eq_attr "tune" "ev4") 60 (eq_attr "type" "mb")) 61 "ev4_ib1+ev4_abox,ev4_abox*3") 62 63; Branches have no delay cost, but do tie up the unit for two cycles. 64(define_insn_reservation "ev4_ibr" 2 65 (and (eq_attr "tune" "ev4") 66 (eq_attr "type" "ibr,jsr")) 67 "ev4_ib1+ev4_bbox,ev4_bbox") 68 69(define_insn_reservation "ev4_callpal" 2 70 (and (eq_attr "tune" "ev4") 71 (eq_attr "type" "callpal")) 72 "ev4_ib1+ev4_bbox,ev4_bbox") 73 74(define_insn_reservation "ev4_fbr" 2 75 (and (eq_attr "tune" "ev4") 76 (eq_attr "type" "fbr")) 77 "ev4_ib0+ev4_bbox,ev4_bbox") 78 79; Arithmetic insns are normally have their results available after 80; two cycles. There are a number of exceptions. 81 82(define_insn_reservation "ev4_iaddlog" 2 83 (and (eq_attr "tune" "ev4") 84 (eq_attr "type" "iadd,ilog")) 85 "ev4_ib0+ev4_ebox") 86 87(define_bypass 1 88 "ev4_iaddlog" 89 "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi") 90 91(define_insn_reservation "ev4_shiftcm" 2 92 (and (eq_attr "tune" "ev4") 93 (eq_attr "type" "shift,icmov")) 94 "ev4_ib0+ev4_ebox") 95 96(define_insn_reservation "ev4_icmp" 2 97 (and (eq_attr "tune" "ev4") 98 (eq_attr "type" "icmp")) 99 "ev4_ib0+ev4_ebox") 100 101(define_bypass 1 "ev4_icmp" "ev4_ibr") 102 103(define_bypass 0 104 "ev4_iaddlog,ev4_shiftcm,ev4_icmp" 105 "ev4_ist" 106 "alpha_store_data_bypass_p") 107 108; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can 109; be issued exactly three cycles before an integer multiply completes". 110 111(define_insn_reservation "ev4_imulsi" 21 112 (and (eq_attr "tune" "ev4") 113 (and (eq_attr "type" "imul") 114 (eq_attr "opsize" "si"))) 115 "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") 116 117(define_bypass 20 "ev4_imulsi" "ev4_ist" "alpha_store_data_bypass_p") 118 119(define_insn_reservation "ev4_imuldi" 23 120 (and (eq_attr "tune" "ev4") 121 (and (eq_attr "type" "imul") 122 (eq_attr "opsize" "!si"))) 123 "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") 124 125(define_bypass 22 "ev4_imuldi" "ev4_ist" "alpha_store_data_bypass_p") 126 127; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. 128(define_insn_reservation "ev4_fpop" 6 129 (and (eq_attr "tune" "ev4") 130 (eq_attr "type" "fadd,fmul,fcpys,fcmov")) 131 "ev4_ib1+ev4_fbox") 132 133(define_bypass 4 "ev4_fpop" "ev4_fpop") 134 135; The floating point divider is not pipelined. Also, "no FPOP insn can be 136; issued exactly five or exactly six cycles before an fdiv insn completes". 137 138(define_insn_reservation "ev4_fdivsf" 34 139 (and (eq_attr "tune" "ev4") 140 (and (eq_attr "type" "fdiv") 141 (eq_attr "opsize" "si"))) 142 "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox") 143 144(define_insn_reservation "ev4_fdivdf" 63 145 (and (eq_attr "tune" "ev4") 146 (and (eq_attr "type" "fdiv") 147 (eq_attr "opsize" "di"))) 148 "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox") 149 150; Traps don't consume or produce data. 151(define_insn_reservation "ev4_misc" 1 152 (and (eq_attr "tune" "ev4") 153 (eq_attr "type" "misc")) 154 "ev4_ib1") 155