1/* riscv-opc.h. RISC-V instruction opcode and CSR macros. 2 Copyright (C) 2011-2022 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 3, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; see the file COPYING3. If not, 19 see <http://www.gnu.org/licenses/>. */ 20 21#ifndef RISCV_ENCODING_H 22#define RISCV_ENCODING_H 23/* Instruction opcode macros. */ 24#define MATCH_SLLI_RV32 0x1013 25#define MASK_SLLI_RV32 0xfe00707f 26#define MATCH_SRLI_RV32 0x5013 27#define MASK_SRLI_RV32 0xfe00707f 28#define MATCH_SRAI_RV32 0x40005013 29#define MASK_SRAI_RV32 0xfe00707f 30#define MATCH_FRFLAGS 0x102073 31#define MASK_FRFLAGS 0xfffff07f 32#define MATCH_FSFLAGS 0x101073 33#define MASK_FSFLAGS 0xfff0707f 34#define MATCH_FSFLAGSI 0x105073 35#define MASK_FSFLAGSI 0xfff0707f 36#define MATCH_FRRM 0x202073 37#define MASK_FRRM 0xfffff07f 38#define MATCH_FSRM 0x201073 39#define MASK_FSRM 0xfff0707f 40#define MATCH_FSRMI 0x205073 41#define MASK_FSRMI 0xfff0707f 42#define MATCH_FSCSR 0x301073 43#define MASK_FSCSR 0xfff0707f 44#define MATCH_FRCSR 0x302073 45#define MASK_FRCSR 0xfffff07f 46#define MATCH_RDCYCLE 0xc0002073 47#define MASK_RDCYCLE 0xfffff07f 48#define MATCH_RDTIME 0xc0102073 49#define MASK_RDTIME 0xfffff07f 50#define MATCH_RDINSTRET 0xc0202073 51#define MASK_RDINSTRET 0xfffff07f 52#define MATCH_RDCYCLEH 0xc8002073 53#define MASK_RDCYCLEH 0xfffff07f 54#define MATCH_RDTIMEH 0xc8102073 55#define MASK_RDTIMEH 0xfffff07f 56#define MATCH_RDINSTRETH 0xc8202073 57#define MASK_RDINSTRETH 0xfffff07f 58#define MATCH_SCALL 0x73 59#define MASK_SCALL 0xffffffff 60#define MATCH_SBREAK 0x100073 61#define MASK_SBREAK 0xffffffff 62#define MATCH_BEQ 0x63 63#define MASK_BEQ 0x707f 64#define MATCH_BNE 0x1063 65#define MASK_BNE 0x707f 66#define MATCH_BLT 0x4063 67#define MASK_BLT 0x707f 68#define MATCH_BGE 0x5063 69#define MASK_BGE 0x707f 70#define MATCH_BLTU 0x6063 71#define MASK_BLTU 0x707f 72#define MATCH_BGEU 0x7063 73#define MASK_BGEU 0x707f 74#define MATCH_JALR 0x67 75#define MASK_JALR 0x707f 76#define MATCH_JAL 0x6f 77#define MASK_JAL 0x7f 78#define MATCH_LUI 0x37 79#define MASK_LUI 0x7f 80#define MATCH_AUIPC 0x17 81#define MASK_AUIPC 0x7f 82#define MATCH_ADDI 0x13 83#define MASK_ADDI 0x707f 84#define MATCH_SLLI 0x1013 85#define MASK_SLLI 0xfc00707f 86#define MATCH_SLTI 0x2013 87#define MASK_SLTI 0x707f 88#define MATCH_SLTIU 0x3013 89#define MASK_SLTIU 0x707f 90#define MATCH_XORI 0x4013 91#define MASK_XORI 0x707f 92#define MATCH_SRLI 0x5013 93#define MASK_SRLI 0xfc00707f 94#define MATCH_SRAI 0x40005013 95#define MASK_SRAI 0xfc00707f 96#define MATCH_ORI 0x6013 97#define MASK_ORI 0x707f 98#define MATCH_ANDI 0x7013 99#define MASK_ANDI 0x707f 100#define MATCH_ADD 0x33 101#define MASK_ADD 0xfe00707f 102#define MATCH_SUB 0x40000033 103#define MASK_SUB 0xfe00707f 104#define MATCH_SLL 0x1033 105#define MASK_SLL 0xfe00707f 106#define MATCH_SLT 0x2033 107#define MASK_SLT 0xfe00707f 108#define MATCH_SLTU 0x3033 109#define MASK_SLTU 0xfe00707f 110#define MATCH_XOR 0x4033 111#define MASK_XOR 0xfe00707f 112#define MATCH_SRL 0x5033 113#define MASK_SRL 0xfe00707f 114#define MATCH_SRA 0x40005033 115#define MASK_SRA 0xfe00707f 116#define MATCH_OR 0x6033 117#define MASK_OR 0xfe00707f 118#define MATCH_AND 0x7033 119#define MASK_AND 0xfe00707f 120#define MATCH_ADDIW 0x1b 121#define MASK_ADDIW 0x707f 122#define MATCH_SLLIW 0x101b 123#define MASK_SLLIW 0xfe00707f 124#define MATCH_SRLIW 0x501b 125#define MASK_SRLIW 0xfe00707f 126#define MATCH_SRAIW 0x4000501b 127#define MASK_SRAIW 0xfe00707f 128#define MATCH_ADDW 0x3b 129#define MASK_ADDW 0xfe00707f 130#define MATCH_SUBW 0x4000003b 131#define MASK_SUBW 0xfe00707f 132#define MATCH_SLLW 0x103b 133#define MASK_SLLW 0xfe00707f 134#define MATCH_SRLW 0x503b 135#define MASK_SRLW 0xfe00707f 136#define MATCH_SRAW 0x4000503b 137#define MASK_SRAW 0xfe00707f 138#define MATCH_LB 0x3 139#define MASK_LB 0x707f 140#define MATCH_LH 0x1003 141#define MASK_LH 0x707f 142#define MATCH_LW 0x2003 143#define MASK_LW 0x707f 144#define MATCH_LD 0x3003 145#define MASK_LD 0x707f 146#define MATCH_LBU 0x4003 147#define MASK_LBU 0x707f 148#define MATCH_LHU 0x5003 149#define MASK_LHU 0x707f 150#define MATCH_LWU 0x6003 151#define MASK_LWU 0x707f 152#define MATCH_SB 0x23 153#define MASK_SB 0x707f 154#define MATCH_SH 0x1023 155#define MASK_SH 0x707f 156#define MATCH_SW 0x2023 157#define MASK_SW 0x707f 158#define MATCH_SD 0x3023 159#define MASK_SD 0x707f 160#define MATCH_PAUSE 0x0100000f 161#define MASK_PAUSE 0xffffffff 162#define MATCH_FENCE 0xf 163#define MASK_FENCE 0x707f 164#define MATCH_FENCE_I 0x100f 165#define MASK_FENCE_I 0x707f 166#define MATCH_FENCE_TSO 0x8330000f 167#define MASK_FENCE_TSO 0xfff0707f 168#define MATCH_MUL 0x2000033 169#define MASK_MUL 0xfe00707f 170#define MATCH_MULH 0x2001033 171#define MASK_MULH 0xfe00707f 172#define MATCH_MULHSU 0x2002033 173#define MASK_MULHSU 0xfe00707f 174#define MATCH_MULHU 0x2003033 175#define MASK_MULHU 0xfe00707f 176#define MATCH_DIV 0x2004033 177#define MASK_DIV 0xfe00707f 178#define MATCH_DIVU 0x2005033 179#define MASK_DIVU 0xfe00707f 180#define MATCH_REM 0x2006033 181#define MASK_REM 0xfe00707f 182#define MATCH_REMU 0x2007033 183#define MASK_REMU 0xfe00707f 184#define MATCH_MULW 0x200003b 185#define MASK_MULW 0xfe00707f 186#define MATCH_DIVW 0x200403b 187#define MASK_DIVW 0xfe00707f 188#define MATCH_DIVUW 0x200503b 189#define MASK_DIVUW 0xfe00707f 190#define MATCH_REMW 0x200603b 191#define MASK_REMW 0xfe00707f 192#define MATCH_REMUW 0x200703b 193#define MASK_REMUW 0xfe00707f 194#define MATCH_AMOADD_W 0x202f 195#define MASK_AMOADD_W 0xf800707f 196#define MATCH_AMOXOR_W 0x2000202f 197#define MASK_AMOXOR_W 0xf800707f 198#define MATCH_AMOOR_W 0x4000202f 199#define MASK_AMOOR_W 0xf800707f 200#define MATCH_AMOAND_W 0x6000202f 201#define MASK_AMOAND_W 0xf800707f 202#define MATCH_AMOMIN_W 0x8000202f 203#define MASK_AMOMIN_W 0xf800707f 204#define MATCH_AMOMAX_W 0xa000202f 205#define MASK_AMOMAX_W 0xf800707f 206#define MATCH_AMOMINU_W 0xc000202f 207#define MASK_AMOMINU_W 0xf800707f 208#define MATCH_AMOMAXU_W 0xe000202f 209#define MASK_AMOMAXU_W 0xf800707f 210#define MATCH_AMOSWAP_W 0x800202f 211#define MASK_AMOSWAP_W 0xf800707f 212#define MATCH_LR_W 0x1000202f 213#define MASK_LR_W 0xf9f0707f 214#define MATCH_SC_W 0x1800202f 215#define MASK_SC_W 0xf800707f 216#define MATCH_AMOADD_D 0x302f 217#define MASK_AMOADD_D 0xf800707f 218#define MATCH_AMOXOR_D 0x2000302f 219#define MASK_AMOXOR_D 0xf800707f 220#define MATCH_AMOOR_D 0x4000302f 221#define MASK_AMOOR_D 0xf800707f 222#define MATCH_AMOAND_D 0x6000302f 223#define MASK_AMOAND_D 0xf800707f 224#define MATCH_AMOMIN_D 0x8000302f 225#define MASK_AMOMIN_D 0xf800707f 226#define MATCH_AMOMAX_D 0xa000302f 227#define MASK_AMOMAX_D 0xf800707f 228#define MATCH_AMOMINU_D 0xc000302f 229#define MASK_AMOMINU_D 0xf800707f 230#define MATCH_AMOMAXU_D 0xe000302f 231#define MASK_AMOMAXU_D 0xf800707f 232#define MATCH_AMOSWAP_D 0x800302f 233#define MASK_AMOSWAP_D 0xf800707f 234#define MATCH_LR_D 0x1000302f 235#define MASK_LR_D 0xf9f0707f 236#define MATCH_SC_D 0x1800302f 237#define MASK_SC_D 0xf800707f 238#define MATCH_ECALL 0x73 239#define MASK_ECALL 0xffffffff 240#define MATCH_EBREAK 0x100073 241#define MASK_EBREAK 0xffffffff 242#define MATCH_URET 0x200073 243#define MASK_URET 0xffffffff 244#define MATCH_SRET 0x10200073 245#define MASK_SRET 0xffffffff 246#define MATCH_HRET 0x20200073 247#define MASK_HRET 0xffffffff 248#define MATCH_MRET 0x30200073 249#define MASK_MRET 0xffffffff 250#define MATCH_DRET 0x7b200073 251#define MASK_DRET 0xffffffff 252#define MATCH_SFENCE_VM 0x10400073 253#define MASK_SFENCE_VM 0xfff07fff 254#define MATCH_SFENCE_VMA 0x12000073 255#define MASK_SFENCE_VMA 0xfe007fff 256#define MATCH_WFI 0x10500073 257#define MASK_WFI 0xffffffff 258#define MATCH_CSRRW 0x1073 259#define MASK_CSRRW 0x707f 260#define MATCH_CSRRS 0x2073 261#define MASK_CSRRS 0x707f 262#define MATCH_CSRRC 0x3073 263#define MASK_CSRRC 0x707f 264#define MATCH_CSRRWI 0x5073 265#define MASK_CSRRWI 0x707f 266#define MATCH_CSRRSI 0x6073 267#define MASK_CSRRSI 0x707f 268#define MATCH_CSRRCI 0x7073 269#define MASK_CSRRCI 0x707f 270#define MATCH_FADD_S 0x53 271#define MASK_FADD_S 0xfe00007f 272#define MATCH_FSUB_S 0x8000053 273#define MASK_FSUB_S 0xfe00007f 274#define MATCH_FMUL_S 0x10000053 275#define MASK_FMUL_S 0xfe00007f 276#define MATCH_FDIV_S 0x18000053 277#define MASK_FDIV_S 0xfe00007f 278#define MATCH_FSGNJ_S 0x20000053 279#define MASK_FSGNJ_S 0xfe00707f 280#define MATCH_FSGNJN_S 0x20001053 281#define MASK_FSGNJN_S 0xfe00707f 282#define MATCH_FSGNJX_S 0x20002053 283#define MASK_FSGNJX_S 0xfe00707f 284#define MATCH_FMIN_S 0x28000053 285#define MASK_FMIN_S 0xfe00707f 286#define MATCH_FMAX_S 0x28001053 287#define MASK_FMAX_S 0xfe00707f 288#define MATCH_FSQRT_S 0x58000053 289#define MASK_FSQRT_S 0xfff0007f 290#define MATCH_FADD_D 0x2000053 291#define MASK_FADD_D 0xfe00007f 292#define MATCH_FSUB_D 0xa000053 293#define MASK_FSUB_D 0xfe00007f 294#define MATCH_FMUL_D 0x12000053 295#define MASK_FMUL_D 0xfe00007f 296#define MATCH_FDIV_D 0x1a000053 297#define MASK_FDIV_D 0xfe00007f 298#define MATCH_FSGNJ_D 0x22000053 299#define MASK_FSGNJ_D 0xfe00707f 300#define MATCH_FSGNJN_D 0x22001053 301#define MASK_FSGNJN_D 0xfe00707f 302#define MATCH_FSGNJX_D 0x22002053 303#define MASK_FSGNJX_D 0xfe00707f 304#define MATCH_FMIN_D 0x2a000053 305#define MASK_FMIN_D 0xfe00707f 306#define MATCH_FMAX_D 0x2a001053 307#define MASK_FMAX_D 0xfe00707f 308#define MATCH_FCVT_S_D 0x40100053 309#define MASK_FCVT_S_D 0xfff0007f 310#define MATCH_FCVT_D_S 0x42000053 311#define MASK_FCVT_D_S 0xfff0007f 312#define MATCH_FSQRT_D 0x5a000053 313#define MASK_FSQRT_D 0xfff0007f 314#define MATCH_FADD_Q 0x6000053 315#define MASK_FADD_Q 0xfe00007f 316#define MATCH_FSUB_Q 0xe000053 317#define MASK_FSUB_Q 0xfe00007f 318#define MATCH_FMUL_Q 0x16000053 319#define MASK_FMUL_Q 0xfe00007f 320#define MATCH_FDIV_Q 0x1e000053 321#define MASK_FDIV_Q 0xfe00007f 322#define MATCH_FSGNJ_Q 0x26000053 323#define MASK_FSGNJ_Q 0xfe00707f 324#define MATCH_FSGNJN_Q 0x26001053 325#define MASK_FSGNJN_Q 0xfe00707f 326#define MATCH_FSGNJX_Q 0x26002053 327#define MASK_FSGNJX_Q 0xfe00707f 328#define MATCH_FMIN_Q 0x2e000053 329#define MASK_FMIN_Q 0xfe00707f 330#define MATCH_FMAX_Q 0x2e001053 331#define MASK_FMAX_Q 0xfe00707f 332#define MATCH_FCVT_S_Q 0x40300053 333#define MASK_FCVT_S_Q 0xfff0007f 334#define MATCH_FCVT_Q_S 0x46000053 335#define MASK_FCVT_Q_S 0xfff0007f 336#define MATCH_FCVT_D_Q 0x42300053 337#define MASK_FCVT_D_Q 0xfff0007f 338#define MATCH_FCVT_Q_D 0x46100053 339#define MASK_FCVT_Q_D 0xfff0007f 340#define MATCH_FSQRT_Q 0x5e000053 341#define MASK_FSQRT_Q 0xfff0007f 342#define MATCH_FLE_S 0xa0000053 343#define MASK_FLE_S 0xfe00707f 344#define MATCH_FLT_S 0xa0001053 345#define MASK_FLT_S 0xfe00707f 346#define MATCH_FEQ_S 0xa0002053 347#define MASK_FEQ_S 0xfe00707f 348#define MATCH_FLE_D 0xa2000053 349#define MASK_FLE_D 0xfe00707f 350#define MATCH_FLT_D 0xa2001053 351#define MASK_FLT_D 0xfe00707f 352#define MATCH_FEQ_D 0xa2002053 353#define MASK_FEQ_D 0xfe00707f 354#define MATCH_FLE_Q 0xa6000053 355#define MASK_FLE_Q 0xfe00707f 356#define MATCH_FLT_Q 0xa6001053 357#define MASK_FLT_Q 0xfe00707f 358#define MATCH_FEQ_Q 0xa6002053 359#define MASK_FEQ_Q 0xfe00707f 360#define MATCH_FCVT_W_S 0xc0000053 361#define MASK_FCVT_W_S 0xfff0007f 362#define MATCH_FCVT_WU_S 0xc0100053 363#define MASK_FCVT_WU_S 0xfff0007f 364#define MATCH_FCVT_L_S 0xc0200053 365#define MASK_FCVT_L_S 0xfff0007f 366#define MATCH_FCVT_LU_S 0xc0300053 367#define MASK_FCVT_LU_S 0xfff0007f 368#define MATCH_FMV_X_S 0xe0000053 369#define MASK_FMV_X_S 0xfff0707f 370#define MATCH_FCLASS_S 0xe0001053 371#define MASK_FCLASS_S 0xfff0707f 372#define MATCH_FCVT_W_D 0xc2000053 373#define MASK_FCVT_W_D 0xfff0007f 374#define MATCH_FCVT_WU_D 0xc2100053 375#define MASK_FCVT_WU_D 0xfff0007f 376#define MATCH_FCVT_L_D 0xc2200053 377#define MASK_FCVT_L_D 0xfff0007f 378#define MATCH_FCVT_LU_D 0xc2300053 379#define MASK_FCVT_LU_D 0xfff0007f 380#define MATCH_FMV_X_D 0xe2000053 381#define MASK_FMV_X_D 0xfff0707f 382#define MATCH_FCLASS_D 0xe2001053 383#define MASK_FCLASS_D 0xfff0707f 384#define MATCH_FCVT_W_Q 0xc6000053 385#define MASK_FCVT_W_Q 0xfff0007f 386#define MATCH_FCVT_WU_Q 0xc6100053 387#define MASK_FCVT_WU_Q 0xfff0007f 388#define MATCH_FCVT_L_Q 0xc6200053 389#define MASK_FCVT_L_Q 0xfff0007f 390#define MATCH_FCVT_LU_Q 0xc6300053 391#define MASK_FCVT_LU_Q 0xfff0007f 392#define MATCH_FCLASS_Q 0xe6001053 393#define MASK_FCLASS_Q 0xfff0707f 394#define MATCH_FCVT_S_W 0xd0000053 395#define MASK_FCVT_S_W 0xfff0007f 396#define MATCH_FCVT_S_WU 0xd0100053 397#define MASK_FCVT_S_WU 0xfff0007f 398#define MATCH_FCVT_S_L 0xd0200053 399#define MASK_FCVT_S_L 0xfff0007f 400#define MATCH_FCVT_S_LU 0xd0300053 401#define MASK_FCVT_S_LU 0xfff0007f 402#define MATCH_FMV_S_X 0xf0000053 403#define MASK_FMV_S_X 0xfff0707f 404#define MATCH_FCVT_D_W 0xd2000053 405#define MASK_FCVT_D_W 0xfff0007f 406#define MATCH_FCVT_D_WU 0xd2100053 407#define MASK_FCVT_D_WU 0xfff0007f 408#define MATCH_FCVT_D_L 0xd2200053 409#define MASK_FCVT_D_L 0xfff0007f 410#define MATCH_FCVT_D_LU 0xd2300053 411#define MASK_FCVT_D_LU 0xfff0007f 412#define MATCH_FMV_D_X 0xf2000053 413#define MASK_FMV_D_X 0xfff0707f 414#define MATCH_FCVT_Q_W 0xd6000053 415#define MASK_FCVT_Q_W 0xfff0007f 416#define MATCH_FCVT_Q_WU 0xd6100053 417#define MASK_FCVT_Q_WU 0xfff0007f 418#define MATCH_FCVT_Q_L 0xd6200053 419#define MASK_FCVT_Q_L 0xfff0007f 420#define MATCH_FCVT_Q_LU 0xd6300053 421#define MASK_FCVT_Q_LU 0xfff0007f 422#define MATCH_CLZ 0x60001013 423#define MASK_CLZ 0xfff0707f 424#define MATCH_CTZ 0x60101013 425#define MASK_CTZ 0xfff0707f 426#define MATCH_CPOP 0x60201013 427#define MASK_CPOP 0xfff0707f 428#define MATCH_MIN 0xa004033 429#define MASK_MIN 0xfe00707f 430#define MATCH_MINU 0xa005033 431#define MASK_MINU 0xfe00707f 432#define MATCH_MAX 0xa006033 433#define MASK_MAX 0xfe00707f 434#define MATCH_MAXU 0xa007033 435#define MASK_MAXU 0xfe00707f 436#define MATCH_SEXT_B 0x60401013 437#define MASK_SEXT_B 0xfff0707f 438#define MATCH_SEXT_H 0x60501013 439#define MASK_SEXT_H 0xfff0707f 440#define MATCH_PACK 0x8004033 441#define MASK_PACK 0xfe00707f 442#define MATCH_PACKH 0x8007033 443#define MASK_PACKH 0xfe00707f 444#define MATCH_PACKW 0x800403b 445#define MASK_PACKW 0xfe00707f 446#define MATCH_ANDN 0x40007033 447#define MASK_ANDN 0xfe00707f 448#define MATCH_ORN 0x40006033 449#define MASK_ORN 0xfe00707f 450#define MATCH_XNOR 0x40004033 451#define MASK_XNOR 0xfe00707f 452#define MATCH_ROL 0x60001033 453#define MASK_ROL 0xfe00707f 454#define MATCH_ROR 0x60005033 455#define MASK_ROR 0xfe00707f 456#define MATCH_RORI 0x60005013 457#define MASK_RORI 0xfc00707f 458#define MATCH_GREVI 0x68005013 459#define MASK_GREVI 0xfc00707f 460#define MATCH_GORCI 0x28005013 461#define MASK_GORCI 0xfc00707f 462#define MATCH_SHFLI 0x8001013 463#define MASK_SHFLI 0xfe00707f 464#define MATCH_UNSHFLI 0x8005013 465#define MASK_UNSHFLI 0xfe00707f 466#define MATCH_CLZW 0x6000101b 467#define MASK_CLZW 0xfff0707f 468#define MATCH_CTZW 0x6010101b 469#define MASK_CTZW 0xfff0707f 470#define MATCH_CPOPW 0x6020101b 471#define MASK_CPOPW 0xfff0707f 472#define MATCH_ROLW 0x6000103b 473#define MASK_ROLW 0xfe00707f 474#define MATCH_RORW 0x6000503b 475#define MASK_RORW 0xfe00707f 476#define MATCH_RORIW 0x6000501b 477#define MASK_RORIW 0xfe00707f 478#define MATCH_SH1ADD 0x20002033 479#define MASK_SH1ADD 0xfe00707f 480#define MATCH_SH2ADD 0x20004033 481#define MASK_SH2ADD 0xfe00707f 482#define MATCH_SH3ADD 0x20006033 483#define MASK_SH3ADD 0xfe00707f 484#define MATCH_SH1ADD_UW 0x2000203b 485#define MASK_SH1ADD_UW 0xfe00707f 486#define MATCH_SH2ADD_UW 0x2000403b 487#define MASK_SH2ADD_UW 0xfe00707f 488#define MATCH_SH3ADD_UW 0x2000603b 489#define MASK_SH3ADD_UW 0xfe00707f 490#define MATCH_ADD_UW 0x800003b 491#define MASK_ADD_UW 0xfe00707f 492#define MATCH_SLLI_UW 0x800101b 493#define MASK_SLLI_UW 0xfc00707f 494#define MATCH_CLMUL 0xa001033 495#define MASK_CLMUL 0xfe00707f 496#define MATCH_CLMULH 0xa003033 497#define MASK_CLMULH 0xfe00707f 498#define MATCH_CLMULR 0xa002033 499#define MASK_CLMULR 0xfe00707f 500#define MATCH_XPERM4 0x28002033 501#define MASK_XPERM4 0xfe00707f 502#define MATCH_XPERM8 0x28004033 503#define MASK_XPERM8 0xfe00707f 504#define MATCH_BCLRI 0x48001013 505#define MASK_BCLRI 0xfc00707f 506#define MATCH_BSETI 0x28001013 507#define MASK_BSETI 0xfc00707f 508#define MATCH_BINVI 0x68001013 509#define MASK_BINVI 0xfc00707f 510#define MATCH_BEXTI 0x48005013 511#define MASK_BEXTI 0xfc00707f 512#define MATCH_BCLR 0x48001033 513#define MASK_BCLR 0xfe00707f 514#define MATCH_BSET 0x28001033 515#define MASK_BSET 0xfe00707f 516#define MATCH_BINV 0x68001033 517#define MASK_BINV 0xfe00707f 518#define MATCH_BEXT 0x48005033 519#define MASK_BEXT 0xfe00707f 520#define MATCH_FLW 0x2007 521#define MASK_FLW 0x707f 522#define MATCH_FLD 0x3007 523#define MASK_FLD 0x707f 524#define MATCH_FLQ 0x4007 525#define MASK_FLQ 0x707f 526#define MATCH_FSW 0x2027 527#define MASK_FSW 0x707f 528#define MATCH_FSD 0x3027 529#define MASK_FSD 0x707f 530#define MATCH_FSQ 0x4027 531#define MASK_FSQ 0x707f 532#define MATCH_FMADD_S 0x43 533#define MASK_FMADD_S 0x600007f 534#define MATCH_FMSUB_S 0x47 535#define MASK_FMSUB_S 0x600007f 536#define MATCH_FNMSUB_S 0x4b 537#define MASK_FNMSUB_S 0x600007f 538#define MATCH_FNMADD_S 0x4f 539#define MASK_FNMADD_S 0x600007f 540#define MATCH_FMADD_D 0x2000043 541#define MASK_FMADD_D 0x600007f 542#define MATCH_FMSUB_D 0x2000047 543#define MASK_FMSUB_D 0x600007f 544#define MATCH_FNMSUB_D 0x200004b 545#define MASK_FNMSUB_D 0x600007f 546#define MATCH_FNMADD_D 0x200004f 547#define MASK_FNMADD_D 0x600007f 548#define MATCH_FMADD_Q 0x6000043 549#define MASK_FMADD_Q 0x600007f 550#define MATCH_FMSUB_Q 0x6000047 551#define MASK_FMSUB_Q 0x600007f 552#define MATCH_FNMSUB_Q 0x600004b 553#define MASK_FNMSUB_Q 0x600007f 554#define MATCH_FNMADD_Q 0x600004f 555#define MASK_FNMADD_Q 0x600007f 556#define MATCH_C_ADDI4SPN 0x0 557#define MASK_C_ADDI4SPN 0xe003 558#define MATCH_C_FLD 0x2000 559#define MASK_C_FLD 0xe003 560#define MATCH_C_LW 0x4000 561#define MASK_C_LW 0xe003 562#define MATCH_C_FLW 0x6000 563#define MASK_C_FLW 0xe003 564#define MATCH_C_FSD 0xa000 565#define MASK_C_FSD 0xe003 566#define MATCH_C_SW 0xc000 567#define MASK_C_SW 0xe003 568#define MATCH_C_FSW 0xe000 569#define MASK_C_FSW 0xe003 570#define MATCH_C_ADDI 0x1 571#define MASK_C_ADDI 0xe003 572#define MATCH_C_JAL 0x2001 573#define MASK_C_JAL 0xe003 574#define MATCH_C_LI 0x4001 575#define MASK_C_LI 0xe003 576#define MATCH_C_LUI 0x6001 577#define MASK_C_LUI 0xe003 578#define MATCH_C_SRLI 0x8001 579#define MASK_C_SRLI 0xec03 580#define MATCH_C_SRLI64 0x8001 581#define MASK_C_SRLI64 0xfc7f 582#define MATCH_C_SRAI 0x8401 583#define MASK_C_SRAI 0xec03 584#define MATCH_C_SRAI64 0x8401 585#define MASK_C_SRAI64 0xfc7f 586#define MATCH_C_ANDI 0x8801 587#define MASK_C_ANDI 0xec03 588#define MATCH_C_SUB 0x8c01 589#define MASK_C_SUB 0xfc63 590#define MATCH_C_XOR 0x8c21 591#define MASK_C_XOR 0xfc63 592#define MATCH_C_OR 0x8c41 593#define MASK_C_OR 0xfc63 594#define MATCH_C_AND 0x8c61 595#define MASK_C_AND 0xfc63 596#define MATCH_C_SUBW 0x9c01 597#define MASK_C_SUBW 0xfc63 598#define MATCH_C_ADDW 0x9c21 599#define MASK_C_ADDW 0xfc63 600#define MATCH_C_J 0xa001 601#define MASK_C_J 0xe003 602#define MATCH_C_BEQZ 0xc001 603#define MASK_C_BEQZ 0xe003 604#define MATCH_C_BNEZ 0xe001 605#define MASK_C_BNEZ 0xe003 606#define MATCH_C_SLLI 0x2 607#define MASK_C_SLLI 0xe003 608#define MATCH_C_SLLI64 0x2 609#define MASK_C_SLLI64 0xf07f 610#define MATCH_C_FLDSP 0x2002 611#define MASK_C_FLDSP 0xe003 612#define MATCH_C_LWSP 0x4002 613#define MASK_C_LWSP 0xe003 614#define MATCH_C_FLWSP 0x6002 615#define MASK_C_FLWSP 0xe003 616#define MATCH_C_MV 0x8002 617#define MASK_C_MV 0xf003 618#define MATCH_C_ADD 0x9002 619#define MASK_C_ADD 0xf003 620#define MATCH_C_FSDSP 0xa002 621#define MASK_C_FSDSP 0xe003 622#define MATCH_C_SWSP 0xc002 623#define MASK_C_SWSP 0xe003 624#define MATCH_C_FSWSP 0xe002 625#define MASK_C_FSWSP 0xe003 626#define MATCH_C_NOP 0x1 627#define MASK_C_NOP 0xffff 628#define MATCH_C_ADDI16SP 0x6101 629#define MASK_C_ADDI16SP 0xef83 630#define MATCH_C_JR 0x8002 631#define MASK_C_JR 0xf07f 632#define MATCH_C_JALR 0x9002 633#define MASK_C_JALR 0xf07f 634#define MATCH_C_EBREAK 0x9002 635#define MASK_C_EBREAK 0xffff 636#define MATCH_C_LD 0x6000 637#define MASK_C_LD 0xe003 638#define MATCH_C_SD 0xe000 639#define MASK_C_SD 0xe003 640#define MATCH_C_ADDIW 0x2001 641#define MASK_C_ADDIW 0xe003 642#define MATCH_C_LDSP 0x6002 643#define MASK_C_LDSP 0xe003 644#define MATCH_C_SDSP 0xe002 645#define MASK_C_SDSP 0xe003 646#define MATCH_SM3P0 0x10801013 647#define MASK_SM3P0 0xfff0707f 648#define MATCH_SM3P1 0x10901013 649#define MASK_SM3P1 0xfff0707f 650#define MATCH_SHA256SUM0 0x10001013 651#define MASK_SHA256SUM0 0xfff0707f 652#define MATCH_SHA256SUM1 0x10101013 653#define MASK_SHA256SUM1 0xfff0707f 654#define MATCH_SHA256SIG0 0x10201013 655#define MASK_SHA256SIG0 0xfff0707f 656#define MATCH_SHA256SIG1 0x10301013 657#define MASK_SHA256SIG1 0xfff0707f 658#define MATCH_SHA512SUM0R 0x50000033 659#define MASK_SHA512SUM0R 0xfe00707f 660#define MATCH_SHA512SUM1R 0x52000033 661#define MASK_SHA512SUM1R 0xfe00707f 662#define MATCH_SHA512SIG0L 0x54000033 663#define MASK_SHA512SIG0L 0xfe00707f 664#define MATCH_SHA512SIG0H 0x5c000033 665#define MASK_SHA512SIG0H 0xfe00707f 666#define MATCH_SHA512SIG1L 0x56000033 667#define MASK_SHA512SIG1L 0xfe00707f 668#define MATCH_SHA512SIG1H 0x5e000033 669#define MASK_SHA512SIG1H 0xfe00707f 670#define MATCH_SM4ED 0x30000033 671#define MASK_SM4ED 0x3e00707f 672#define MATCH_SM4KS 0x34000033 673#define MASK_SM4KS 0x3e00707f 674#define MATCH_AES32ESMI 0x26000033 675#define MASK_AES32ESMI 0x3e00707f 676#define MATCH_AES32ESI 0x22000033 677#define MASK_AES32ESI 0x3e00707f 678#define MATCH_AES32DSMI 0x2e000033 679#define MASK_AES32DSMI 0x3e00707f 680#define MATCH_AES32DSI 0x2a000033 681#define MASK_AES32DSI 0x3e00707f 682#define MATCH_SHA512SUM0 0x10401013 683#define MASK_SHA512SUM0 0xfff0707f 684#define MATCH_SHA512SUM1 0x10501013 685#define MASK_SHA512SUM1 0xfff0707f 686#define MATCH_SHA512SIG0 0x10601013 687#define MASK_SHA512SIG0 0xfff0707f 688#define MATCH_SHA512SIG1 0x10701013 689#define MASK_SHA512SIG1 0xfff0707f 690#define MATCH_AES64KS1I 0x31001013 691#define MASK_AES64KS1I 0xff00707f 692#define MATCH_AES64IM 0x30001013 693#define MASK_AES64IM 0xfff0707f 694#define MATCH_AES64KS2 0x7e000033 695#define MASK_AES64KS2 0xfe00707f 696#define MATCH_AES64ESM 0x36000033 697#define MASK_AES64ESM 0xfe00707f 698#define MATCH_AES64ES 0x32000033 699#define MASK_AES64ES 0xfe00707f 700#define MATCH_AES64DSM 0x3e000033 701#define MASK_AES64DSM 0xfe00707f 702#define MATCH_AES64DS 0x3a000033 703#define MASK_AES64DS 0xfe00707f 704#define MATCH_FADD_H 0x4000053 705#define MASK_FADD_H 0xfe00007f 706#define MATCH_FSUB_H 0xc000053 707#define MASK_FSUB_H 0xfe00007f 708#define MATCH_FMUL_H 0x14000053 709#define MASK_FMUL_H 0xfe00007f 710#define MATCH_FDIV_H 0x1c000053 711#define MASK_FDIV_H 0xfe00007f 712#define MATCH_FSGNJ_H 0x24000053 713#define MASK_FSGNJ_H 0xfe00707f 714#define MATCH_FSGNJN_H 0x24001053 715#define MASK_FSGNJN_H 0xfe00707f 716#define MATCH_FSGNJX_H 0x24002053 717#define MASK_FSGNJX_H 0xfe00707f 718#define MATCH_FMIN_H 0x2c000053 719#define MASK_FMIN_H 0xfe00707f 720#define MATCH_FMAX_H 0x2c001053 721#define MASK_FMAX_H 0xfe00707f 722#define MATCH_FCVT_H_S 0x44000053 723#define MASK_FCVT_H_S 0xfff0007f 724#define MATCH_FCVT_S_H 0x40200053 725#define MASK_FCVT_S_H 0xfff0007f 726#define MATCH_FSQRT_H 0x5c000053 727#define MASK_FSQRT_H 0xfff0007f 728#define MATCH_FLE_H 0xa4000053 729#define MASK_FLE_H 0xfe00707f 730#define MATCH_FLT_H 0xa4001053 731#define MASK_FLT_H 0xfe00707f 732#define MATCH_FEQ_H 0xa4002053 733#define MASK_FEQ_H 0xfe00707f 734#define MATCH_FCVT_W_H 0xc4000053 735#define MASK_FCVT_W_H 0xfff0007f 736#define MATCH_FCVT_WU_H 0xc4100053 737#define MASK_FCVT_WU_H 0xfff0007f 738#define MATCH_FMV_X_H 0xe4000053 739#define MASK_FMV_X_H 0xfff0707f 740#define MATCH_FCLASS_H 0xe4001053 741#define MASK_FCLASS_H 0xfff0707f 742#define MATCH_FCVT_H_W 0xd4000053 743#define MASK_FCVT_H_W 0xfff0007f 744#define MATCH_FCVT_H_WU 0xd4100053 745#define MASK_FCVT_H_WU 0xfff0007f 746#define MATCH_FMV_H_X 0xf4000053 747#define MASK_FMV_H_X 0xfff0707f 748#define MATCH_FLH 0x1007 749#define MASK_FLH 0x707f 750#define MATCH_FSH 0x1027 751#define MASK_FSH 0x707f 752#define MATCH_FMADD_H 0x4000043 753#define MASK_FMADD_H 0x600007f 754#define MATCH_FMSUB_H 0x4000047 755#define MASK_FMSUB_H 0x600007f 756#define MATCH_FNMSUB_H 0x400004b 757#define MASK_FNMSUB_H 0x600007f 758#define MATCH_FNMADD_H 0x400004f 759#define MASK_FNMADD_H 0x600007f 760#define MATCH_FCVT_H_D 0x44100053 761#define MASK_FCVT_H_D 0xfff0007f 762#define MATCH_FCVT_D_H 0x42200053 763#define MASK_FCVT_D_H 0xfff0007f 764#define MATCH_FCVT_H_Q 0x44300053 765#define MASK_FCVT_H_Q 0xfff0007f 766#define MATCH_FCVT_Q_H 0x46200053 767#define MASK_FCVT_Q_H 0xfff0007f 768#define MATCH_FCVT_L_H 0xc4200053 769#define MASK_FCVT_L_H 0xfff0007f 770#define MATCH_FCVT_LU_H 0xc4300053 771#define MASK_FCVT_LU_H 0xfff0007f 772#define MATCH_FCVT_H_L 0xd4200053 773#define MASK_FCVT_H_L 0xfff0007f 774#define MATCH_FCVT_H_LU 0xd4300053 775#define MASK_FCVT_H_LU 0xfff0007f 776#define MATCH_VSETVL 0x80007057 777#define MASK_VSETVL 0xfe00707f 778#define MATCH_VSETIVLI 0xc0007057 779#define MASK_VSETIVLI 0xc000707f 780#define MATCH_VSETVLI 0x00007057 781#define MASK_VSETVLI 0x8000707f 782#define MATCH_VLMV 0x02b00007 783#define MASK_VLMV 0xfff0707f 784#define MATCH_VSMV 0x02b00027 785#define MASK_VSMV 0xfff0707f 786#define MATCH_VLE8V 0x00000007 787#define MASK_VLE8V 0xfdf0707f 788#define MATCH_VLE16V 0x00005007 789#define MASK_VLE16V 0xfdf0707f 790#define MATCH_VLE32V 0x00006007 791#define MASK_VLE32V 0xfdf0707f 792#define MATCH_VLE64V 0x00007007 793#define MASK_VLE64V 0xfdf0707f 794#define MATCH_VSE8V 0x00000027 795#define MASK_VSE8V 0xfdf0707f 796#define MATCH_VSE16V 0x00005027 797#define MASK_VSE16V 0xfdf0707f 798#define MATCH_VSE32V 0x00006027 799#define MASK_VSE32V 0xfdf0707f 800#define MATCH_VSE64V 0x00007027 801#define MASK_VSE64V 0xfdf0707f 802#define MATCH_VLSE8V 0x08000007 803#define MASK_VLSE8V 0xfc00707f 804#define MATCH_VLSE16V 0x08005007 805#define MASK_VLSE16V 0xfc00707f 806#define MATCH_VLSE32V 0x08006007 807#define MASK_VLSE32V 0xfc00707f 808#define MATCH_VLSE64V 0x08007007 809#define MASK_VLSE64V 0xfc00707f 810#define MATCH_VSSE8V 0x08000027 811#define MASK_VSSE8V 0xfc00707f 812#define MATCH_VSSE16V 0x08005027 813#define MASK_VSSE16V 0xfc00707f 814#define MATCH_VSSE32V 0x08006027 815#define MASK_VSSE32V 0xfc00707f 816#define MATCH_VSSE64V 0x08007027 817#define MASK_VSSE64V 0xfc00707f 818#define MATCH_VLOXEI8V 0x0c000007 819#define MASK_VLOXEI8V 0xfc00707f 820#define MATCH_VLOXEI16V 0x0c005007 821#define MASK_VLOXEI16V 0xfc00707f 822#define MATCH_VLOXEI32V 0x0c006007 823#define MASK_VLOXEI32V 0xfc00707f 824#define MATCH_VLOXEI64V 0x0c007007 825#define MASK_VLOXEI64V 0xfc00707f 826#define MATCH_VSOXEI8V 0x0c000027 827#define MASK_VSOXEI8V 0xfc00707f 828#define MATCH_VSOXEI16V 0x0c005027 829#define MASK_VSOXEI16V 0xfc00707f 830#define MATCH_VSOXEI32V 0x0c006027 831#define MASK_VSOXEI32V 0xfc00707f 832#define MATCH_VSOXEI64V 0x0c007027 833#define MASK_VSOXEI64V 0xfc00707f 834#define MATCH_VLUXEI8V 0x04000007 835#define MASK_VLUXEI8V 0xfc00707f 836#define MATCH_VLUXEI16V 0x04005007 837#define MASK_VLUXEI16V 0xfc00707f 838#define MATCH_VLUXEI32V 0x04006007 839#define MASK_VLUXEI32V 0xfc00707f 840#define MATCH_VLUXEI64V 0x04007007 841#define MASK_VLUXEI64V 0xfc00707f 842#define MATCH_VSUXEI8V 0x04000027 843#define MASK_VSUXEI8V 0xfc00707f 844#define MATCH_VSUXEI16V 0x04005027 845#define MASK_VSUXEI16V 0xfc00707f 846#define MATCH_VSUXEI32V 0x04006027 847#define MASK_VSUXEI32V 0xfc00707f 848#define MATCH_VSUXEI64V 0x04007027 849#define MASK_VSUXEI64V 0xfc00707f 850#define MATCH_VLE8FFV 0x01000007 851#define MASK_VLE8FFV 0xfdf0707f 852#define MATCH_VLE16FFV 0x01005007 853#define MASK_VLE16FFV 0xfdf0707f 854#define MATCH_VLE32FFV 0x01006007 855#define MASK_VLE32FFV 0xfdf0707f 856#define MATCH_VLE64FFV 0x01007007 857#define MASK_VLE64FFV 0xfdf0707f 858#define MATCH_VLSEG2E8V 0x20000007 859#define MASK_VLSEG2E8V 0xfdf0707f 860#define MATCH_VSSEG2E8V 0x20000027 861#define MASK_VSSEG2E8V 0xfdf0707f 862#define MATCH_VLSEG3E8V 0x40000007 863#define MASK_VLSEG3E8V 0xfdf0707f 864#define MATCH_VSSEG3E8V 0x40000027 865#define MASK_VSSEG3E8V 0xfdf0707f 866#define MATCH_VLSEG4E8V 0x60000007 867#define MASK_VLSEG4E8V 0xfdf0707f 868#define MATCH_VSSEG4E8V 0x60000027 869#define MASK_VSSEG4E8V 0xfdf0707f 870#define MATCH_VLSEG5E8V 0x80000007 871#define MASK_VLSEG5E8V 0xfdf0707f 872#define MATCH_VSSEG5E8V 0x80000027 873#define MASK_VSSEG5E8V 0xfdf0707f 874#define MATCH_VLSEG6E8V 0xa0000007 875#define MASK_VLSEG6E8V 0xfdf0707f 876#define MATCH_VSSEG6E8V 0xa0000027 877#define MASK_VSSEG6E8V 0xfdf0707f 878#define MATCH_VLSEG7E8V 0xc0000007 879#define MASK_VLSEG7E8V 0xfdf0707f 880#define MATCH_VSSEG7E8V 0xc0000027 881#define MASK_VSSEG7E8V 0xfdf0707f 882#define MATCH_VLSEG8E8V 0xe0000007 883#define MASK_VLSEG8E8V 0xfdf0707f 884#define MATCH_VSSEG8E8V 0xe0000027 885#define MASK_VSSEG8E8V 0xfdf0707f 886#define MATCH_VLSEG2E16V 0x20005007 887#define MASK_VLSEG2E16V 0xfdf0707f 888#define MATCH_VSSEG2E16V 0x20005027 889#define MASK_VSSEG2E16V 0xfdf0707f 890#define MATCH_VLSEG3E16V 0x40005007 891#define MASK_VLSEG3E16V 0xfdf0707f 892#define MATCH_VSSEG3E16V 0x40005027 893#define MASK_VSSEG3E16V 0xfdf0707f 894#define MATCH_VLSEG4E16V 0x60005007 895#define MASK_VLSEG4E16V 0xfdf0707f 896#define MATCH_VSSEG4E16V 0x60005027 897#define MASK_VSSEG4E16V 0xfdf0707f 898#define MATCH_VLSEG5E16V 0x80005007 899#define MASK_VLSEG5E16V 0xfdf0707f 900#define MATCH_VSSEG5E16V 0x80005027 901#define MASK_VSSEG5E16V 0xfdf0707f 902#define MATCH_VLSEG6E16V 0xa0005007 903#define MASK_VLSEG6E16V 0xfdf0707f 904#define MATCH_VSSEG6E16V 0xa0005027 905#define MASK_VSSEG6E16V 0xfdf0707f 906#define MATCH_VLSEG7E16V 0xc0005007 907#define MASK_VLSEG7E16V 0xfdf0707f 908#define MATCH_VSSEG7E16V 0xc0005027 909#define MASK_VSSEG7E16V 0xfdf0707f 910#define MATCH_VLSEG8E16V 0xe0005007 911#define MASK_VLSEG8E16V 0xfdf0707f 912#define MATCH_VSSEG8E16V 0xe0005027 913#define MASK_VSSEG8E16V 0xfdf0707f 914#define MATCH_VLSEG2E32V 0x20006007 915#define MASK_VLSEG2E32V 0xfdf0707f 916#define MATCH_VSSEG2E32V 0x20006027 917#define MASK_VSSEG2E32V 0xfdf0707f 918#define MATCH_VLSEG3E32V 0x40006007 919#define MASK_VLSEG3E32V 0xfdf0707f 920#define MATCH_VSSEG3E32V 0x40006027 921#define MASK_VSSEG3E32V 0xfdf0707f 922#define MATCH_VLSEG4E32V 0x60006007 923#define MASK_VLSEG4E32V 0xfdf0707f 924#define MATCH_VSSEG4E32V 0x60006027 925#define MASK_VSSEG4E32V 0xfdf0707f 926#define MATCH_VLSEG5E32V 0x80006007 927#define MASK_VLSEG5E32V 0xfdf0707f 928#define MATCH_VSSEG5E32V 0x80006027 929#define MASK_VSSEG5E32V 0xfdf0707f 930#define MATCH_VLSEG6E32V 0xa0006007 931#define MASK_VLSEG6E32V 0xfdf0707f 932#define MATCH_VSSEG6E32V 0xa0006027 933#define MASK_VSSEG6E32V 0xfdf0707f 934#define MATCH_VLSEG7E32V 0xc0006007 935#define MASK_VLSEG7E32V 0xfdf0707f 936#define MATCH_VSSEG7E32V 0xc0006027 937#define MASK_VSSEG7E32V 0xfdf0707f 938#define MATCH_VLSEG8E32V 0xe0006007 939#define MASK_VLSEG8E32V 0xfdf0707f 940#define MATCH_VSSEG8E32V 0xe0006027 941#define MASK_VSSEG8E32V 0xfdf0707f 942#define MATCH_VLSEG2E64V 0x20007007 943#define MASK_VLSEG2E64V 0xfdf0707f 944#define MATCH_VSSEG2E64V 0x20007027 945#define MASK_VSSEG2E64V 0xfdf0707f 946#define MATCH_VLSEG3E64V 0x40007007 947#define MASK_VLSEG3E64V 0xfdf0707f 948#define MATCH_VSSEG3E64V 0x40007027 949#define MASK_VSSEG3E64V 0xfdf0707f 950#define MATCH_VLSEG4E64V 0x60007007 951#define MASK_VLSEG4E64V 0xfdf0707f 952#define MATCH_VSSEG4E64V 0x60007027 953#define MASK_VSSEG4E64V 0xfdf0707f 954#define MATCH_VLSEG5E64V 0x80007007 955#define MASK_VLSEG5E64V 0xfdf0707f 956#define MATCH_VSSEG5E64V 0x80007027 957#define MASK_VSSEG5E64V 0xfdf0707f 958#define MATCH_VLSEG6E64V 0xa0007007 959#define MASK_VLSEG6E64V 0xfdf0707f 960#define MATCH_VSSEG6E64V 0xa0007027 961#define MASK_VSSEG6E64V 0xfdf0707f 962#define MATCH_VLSEG7E64V 0xc0007007 963#define MASK_VLSEG7E64V 0xfdf0707f 964#define MATCH_VSSEG7E64V 0xc0007027 965#define MASK_VSSEG7E64V 0xfdf0707f 966#define MATCH_VLSEG8E64V 0xe0007007 967#define MASK_VLSEG8E64V 0xfdf0707f 968#define MATCH_VSSEG8E64V 0xe0007027 969#define MASK_VSSEG8E64V 0xfdf0707f 970#define MATCH_VLSSEG2E8V 0x28000007 971#define MASK_VLSSEG2E8V 0xfc00707f 972#define MATCH_VSSSEG2E8V 0x28000027 973#define MASK_VSSSEG2E8V 0xfc00707f 974#define MATCH_VLSSEG3E8V 0x48000007 975#define MASK_VLSSEG3E8V 0xfc00707f 976#define MATCH_VSSSEG3E8V 0x48000027 977#define MASK_VSSSEG3E8V 0xfc00707f 978#define MATCH_VLSSEG4E8V 0x68000007 979#define MASK_VLSSEG4E8V 0xfc00707f 980#define MATCH_VSSSEG4E8V 0x68000027 981#define MASK_VSSSEG4E8V 0xfc00707f 982#define MATCH_VLSSEG5E8V 0x88000007 983#define MASK_VLSSEG5E8V 0xfc00707f 984#define MATCH_VSSSEG5E8V 0x88000027 985#define MASK_VSSSEG5E8V 0xfc00707f 986#define MATCH_VLSSEG6E8V 0xa8000007 987#define MASK_VLSSEG6E8V 0xfc00707f 988#define MATCH_VSSSEG6E8V 0xa8000027 989#define MASK_VSSSEG6E8V 0xfc00707f 990#define MATCH_VLSSEG7E8V 0xc8000007 991#define MASK_VLSSEG7E8V 0xfc00707f 992#define MATCH_VSSSEG7E8V 0xc8000027 993#define MASK_VSSSEG7E8V 0xfc00707f 994#define MATCH_VLSSEG8E8V 0xe8000007 995#define MASK_VLSSEG8E8V 0xfc00707f 996#define MATCH_VSSSEG8E8V 0xe8000027 997#define MASK_VSSSEG8E8V 0xfc00707f 998#define MATCH_VLSSEG2E16V 0x28005007 999#define MASK_VLSSEG2E16V 0xfc00707f 1000#define MATCH_VSSSEG2E16V 0x28005027 1001#define MASK_VSSSEG2E16V 0xfc00707f 1002#define MATCH_VLSSEG3E16V 0x48005007 1003#define MASK_VLSSEG3E16V 0xfc00707f 1004#define MATCH_VSSSEG3E16V 0x48005027 1005#define MASK_VSSSEG3E16V 0xfc00707f 1006#define MATCH_VLSSEG4E16V 0x68005007 1007#define MASK_VLSSEG4E16V 0xfc00707f 1008#define MATCH_VSSSEG4E16V 0x68005027 1009#define MASK_VSSSEG4E16V 0xfc00707f 1010#define MATCH_VLSSEG5E16V 0x88005007 1011#define MASK_VLSSEG5E16V 0xfc00707f 1012#define MATCH_VSSSEG5E16V 0x88005027 1013#define MASK_VSSSEG5E16V 0xfc00707f 1014#define MATCH_VLSSEG6E16V 0xa8005007 1015#define MASK_VLSSEG6E16V 0xfc00707f 1016#define MATCH_VSSSEG6E16V 0xa8005027 1017#define MASK_VSSSEG6E16V 0xfc00707f 1018#define MATCH_VLSSEG7E16V 0xc8005007 1019#define MASK_VLSSEG7E16V 0xfc00707f 1020#define MATCH_VSSSEG7E16V 0xc8005027 1021#define MASK_VSSSEG7E16V 0xfc00707f 1022#define MATCH_VLSSEG8E16V 0xe8005007 1023#define MASK_VLSSEG8E16V 0xfc00707f 1024#define MATCH_VSSSEG8E16V 0xe8005027 1025#define MASK_VSSSEG8E16V 0xfc00707f 1026#define MATCH_VLSSEG2E32V 0x28006007 1027#define MASK_VLSSEG2E32V 0xfc00707f 1028#define MATCH_VSSSEG2E32V 0x28006027 1029#define MASK_VSSSEG2E32V 0xfc00707f 1030#define MATCH_VLSSEG3E32V 0x48006007 1031#define MASK_VLSSEG3E32V 0xfc00707f 1032#define MATCH_VSSSEG3E32V 0x48006027 1033#define MASK_VSSSEG3E32V 0xfc00707f 1034#define MATCH_VLSSEG4E32V 0x68006007 1035#define MASK_VLSSEG4E32V 0xfc00707f 1036#define MATCH_VSSSEG4E32V 0x68006027 1037#define MASK_VSSSEG4E32V 0xfc00707f 1038#define MATCH_VLSSEG5E32V 0x88006007 1039#define MASK_VLSSEG5E32V 0xfc00707f 1040#define MATCH_VSSSEG5E32V 0x88006027 1041#define MASK_VSSSEG5E32V 0xfc00707f 1042#define MATCH_VLSSEG6E32V 0xa8006007 1043#define MASK_VLSSEG6E32V 0xfc00707f 1044#define MATCH_VSSSEG6E32V 0xa8006027 1045#define MASK_VSSSEG6E32V 0xfc00707f 1046#define MATCH_VLSSEG7E32V 0xc8006007 1047#define MASK_VLSSEG7E32V 0xfc00707f 1048#define MATCH_VSSSEG7E32V 0xc8006027 1049#define MASK_VSSSEG7E32V 0xfc00707f 1050#define MATCH_VLSSEG8E32V 0xe8006007 1051#define MASK_VLSSEG8E32V 0xfc00707f 1052#define MATCH_VSSSEG8E32V 0xe8006027 1053#define MASK_VSSSEG8E32V 0xfc00707f 1054#define MATCH_VLSSEG2E64V 0x28007007 1055#define MASK_VLSSEG2E64V 0xfc00707f 1056#define MATCH_VSSSEG2E64V 0x28007027 1057#define MASK_VSSSEG2E64V 0xfc00707f 1058#define MATCH_VLSSEG3E64V 0x48007007 1059#define MASK_VLSSEG3E64V 0xfc00707f 1060#define MATCH_VSSSEG3E64V 0x48007027 1061#define MASK_VSSSEG3E64V 0xfc00707f 1062#define MATCH_VLSSEG4E64V 0x68007007 1063#define MASK_VLSSEG4E64V 0xfc00707f 1064#define MATCH_VSSSEG4E64V 0x68007027 1065#define MASK_VSSSEG4E64V 0xfc00707f 1066#define MATCH_VLSSEG5E64V 0x88007007 1067#define MASK_VLSSEG5E64V 0xfc00707f 1068#define MATCH_VSSSEG5E64V 0x88007027 1069#define MASK_VSSSEG5E64V 0xfc00707f 1070#define MATCH_VLSSEG6E64V 0xa8007007 1071#define MASK_VLSSEG6E64V 0xfc00707f 1072#define MATCH_VSSSEG6E64V 0xa8007027 1073#define MASK_VSSSEG6E64V 0xfc00707f 1074#define MATCH_VLSSEG7E64V 0xc8007007 1075#define MASK_VLSSEG7E64V 0xfc00707f 1076#define MATCH_VSSSEG7E64V 0xc8007027 1077#define MASK_VSSSEG7E64V 0xfc00707f 1078#define MATCH_VLSSEG8E64V 0xe8007007 1079#define MASK_VLSSEG8E64V 0xfc00707f 1080#define MATCH_VSSSEG8E64V 0xe8007027 1081#define MASK_VSSSEG8E64V 0xfc00707f 1082#define MATCH_VLOXSEG2EI8V 0x2c000007 1083#define MASK_VLOXSEG2EI8V 0xfc00707f 1084#define MATCH_VSOXSEG2EI8V 0x2c000027 1085#define MASK_VSOXSEG2EI8V 0xfc00707f 1086#define MATCH_VLOXSEG3EI8V 0x4c000007 1087#define MASK_VLOXSEG3EI8V 0xfc00707f 1088#define MATCH_VSOXSEG3EI8V 0x4c000027 1089#define MASK_VSOXSEG3EI8V 0xfc00707f 1090#define MATCH_VLOXSEG4EI8V 0x6c000007 1091#define MASK_VLOXSEG4EI8V 0xfc00707f 1092#define MATCH_VSOXSEG4EI8V 0x6c000027 1093#define MASK_VSOXSEG4EI8V 0xfc00707f 1094#define MATCH_VLOXSEG5EI8V 0x8c000007 1095#define MASK_VLOXSEG5EI8V 0xfc00707f 1096#define MATCH_VSOXSEG5EI8V 0x8c000027 1097#define MASK_VSOXSEG5EI8V 0xfc00707f 1098#define MATCH_VLOXSEG6EI8V 0xac000007 1099#define MASK_VLOXSEG6EI8V 0xfc00707f 1100#define MATCH_VSOXSEG6EI8V 0xac000027 1101#define MASK_VSOXSEG6EI8V 0xfc00707f 1102#define MATCH_VLOXSEG7EI8V 0xcc000007 1103#define MASK_VLOXSEG7EI8V 0xfc00707f 1104#define MATCH_VSOXSEG7EI8V 0xcc000027 1105#define MASK_VSOXSEG7EI8V 0xfc00707f 1106#define MATCH_VLOXSEG8EI8V 0xec000007 1107#define MASK_VLOXSEG8EI8V 0xfc00707f 1108#define MATCH_VSOXSEG8EI8V 0xec000027 1109#define MASK_VSOXSEG8EI8V 0xfc00707f 1110#define MATCH_VLUXSEG2EI8V 0x24000007 1111#define MASK_VLUXSEG2EI8V 0xfc00707f 1112#define MATCH_VSUXSEG2EI8V 0x24000027 1113#define MASK_VSUXSEG2EI8V 0xfc00707f 1114#define MATCH_VLUXSEG3EI8V 0x44000007 1115#define MASK_VLUXSEG3EI8V 0xfc00707f 1116#define MATCH_VSUXSEG3EI8V 0x44000027 1117#define MASK_VSUXSEG3EI8V 0xfc00707f 1118#define MATCH_VLUXSEG4EI8V 0x64000007 1119#define MASK_VLUXSEG4EI8V 0xfc00707f 1120#define MATCH_VSUXSEG4EI8V 0x64000027 1121#define MASK_VSUXSEG4EI8V 0xfc00707f 1122#define MATCH_VLUXSEG5EI8V 0x84000007 1123#define MASK_VLUXSEG5EI8V 0xfc00707f 1124#define MATCH_VSUXSEG5EI8V 0x84000027 1125#define MASK_VSUXSEG5EI8V 0xfc00707f 1126#define MATCH_VLUXSEG6EI8V 0xa4000007 1127#define MASK_VLUXSEG6EI8V 0xfc00707f 1128#define MATCH_VSUXSEG6EI8V 0xa4000027 1129#define MASK_VSUXSEG6EI8V 0xfc00707f 1130#define MATCH_VLUXSEG7EI8V 0xc4000007 1131#define MASK_VLUXSEG7EI8V 0xfc00707f 1132#define MATCH_VSUXSEG7EI8V 0xc4000027 1133#define MASK_VSUXSEG7EI8V 0xfc00707f 1134#define MATCH_VLUXSEG8EI8V 0xe4000007 1135#define MASK_VLUXSEG8EI8V 0xfc00707f 1136#define MATCH_VSUXSEG8EI8V 0xe4000027 1137#define MASK_VSUXSEG8EI8V 0xfc00707f 1138#define MATCH_VLOXSEG2EI16V 0x2c005007 1139#define MASK_VLOXSEG2EI16V 0xfc00707f 1140#define MATCH_VSOXSEG2EI16V 0x2c005027 1141#define MASK_VSOXSEG2EI16V 0xfc00707f 1142#define MATCH_VLOXSEG3EI16V 0x4c005007 1143#define MASK_VLOXSEG3EI16V 0xfc00707f 1144#define MATCH_VSOXSEG3EI16V 0x4c005027 1145#define MASK_VSOXSEG3EI16V 0xfc00707f 1146#define MATCH_VLOXSEG4EI16V 0x6c005007 1147#define MASK_VLOXSEG4EI16V 0xfc00707f 1148#define MATCH_VSOXSEG4EI16V 0x6c005027 1149#define MASK_VSOXSEG4EI16V 0xfc00707f 1150#define MATCH_VLOXSEG5EI16V 0x8c005007 1151#define MASK_VLOXSEG5EI16V 0xfc00707f 1152#define MATCH_VSOXSEG5EI16V 0x8c005027 1153#define MASK_VSOXSEG5EI16V 0xfc00707f 1154#define MATCH_VLOXSEG6EI16V 0xac005007 1155#define MASK_VLOXSEG6EI16V 0xfc00707f 1156#define MATCH_VSOXSEG6EI16V 0xac005027 1157#define MASK_VSOXSEG6EI16V 0xfc00707f 1158#define MATCH_VLOXSEG7EI16V 0xcc005007 1159#define MASK_VLOXSEG7EI16V 0xfc00707f 1160#define MATCH_VSOXSEG7EI16V 0xcc005027 1161#define MASK_VSOXSEG7EI16V 0xfc00707f 1162#define MATCH_VLOXSEG8EI16V 0xec005007 1163#define MASK_VLOXSEG8EI16V 0xfc00707f 1164#define MATCH_VSOXSEG8EI16V 0xec005027 1165#define MASK_VSOXSEG8EI16V 0xfc00707f 1166#define MATCH_VLUXSEG2EI16V 0x24005007 1167#define MASK_VLUXSEG2EI16V 0xfc00707f 1168#define MATCH_VSUXSEG2EI16V 0x24005027 1169#define MASK_VSUXSEG2EI16V 0xfc00707f 1170#define MATCH_VLUXSEG3EI16V 0x44005007 1171#define MASK_VLUXSEG3EI16V 0xfc00707f 1172#define MATCH_VSUXSEG3EI16V 0x44005027 1173#define MASK_VSUXSEG3EI16V 0xfc00707f 1174#define MATCH_VLUXSEG4EI16V 0x64005007 1175#define MASK_VLUXSEG4EI16V 0xfc00707f 1176#define MATCH_VSUXSEG4EI16V 0x64005027 1177#define MASK_VSUXSEG4EI16V 0xfc00707f 1178#define MATCH_VLUXSEG5EI16V 0x84005007 1179#define MASK_VLUXSEG5EI16V 0xfc00707f 1180#define MATCH_VSUXSEG5EI16V 0x84005027 1181#define MASK_VSUXSEG5EI16V 0xfc00707f 1182#define MATCH_VLUXSEG6EI16V 0xa4005007 1183#define MASK_VLUXSEG6EI16V 0xfc00707f 1184#define MATCH_VSUXSEG6EI16V 0xa4005027 1185#define MASK_VSUXSEG6EI16V 0xfc00707f 1186#define MATCH_VLUXSEG7EI16V 0xc4005007 1187#define MASK_VLUXSEG7EI16V 0xfc00707f 1188#define MATCH_VSUXSEG7EI16V 0xc4005027 1189#define MASK_VSUXSEG7EI16V 0xfc00707f 1190#define MATCH_VLUXSEG8EI16V 0xe4005007 1191#define MASK_VLUXSEG8EI16V 0xfc00707f 1192#define MATCH_VSUXSEG8EI16V 0xe4005027 1193#define MASK_VSUXSEG8EI16V 0xfc00707f 1194#define MATCH_VLOXSEG2EI32V 0x2c006007 1195#define MASK_VLOXSEG2EI32V 0xfc00707f 1196#define MATCH_VSOXSEG2EI32V 0x2c006027 1197#define MASK_VSOXSEG2EI32V 0xfc00707f 1198#define MATCH_VLOXSEG3EI32V 0x4c006007 1199#define MASK_VLOXSEG3EI32V 0xfc00707f 1200#define MATCH_VSOXSEG3EI32V 0x4c006027 1201#define MASK_VSOXSEG3EI32V 0xfc00707f 1202#define MATCH_VLOXSEG4EI32V 0x6c006007 1203#define MASK_VLOXSEG4EI32V 0xfc00707f 1204#define MATCH_VSOXSEG4EI32V 0x6c006027 1205#define MASK_VSOXSEG4EI32V 0xfc00707f 1206#define MATCH_VLOXSEG5EI32V 0x8c006007 1207#define MASK_VLOXSEG5EI32V 0xfc00707f 1208#define MATCH_VSOXSEG5EI32V 0x8c006027 1209#define MASK_VSOXSEG5EI32V 0xfc00707f 1210#define MATCH_VLOXSEG6EI32V 0xac006007 1211#define MASK_VLOXSEG6EI32V 0xfc00707f 1212#define MATCH_VSOXSEG6EI32V 0xac006027 1213#define MASK_VSOXSEG6EI32V 0xfc00707f 1214#define MATCH_VLOXSEG7EI32V 0xcc006007 1215#define MASK_VLOXSEG7EI32V 0xfc00707f 1216#define MATCH_VSOXSEG7EI32V 0xcc006027 1217#define MASK_VSOXSEG7EI32V 0xfc00707f 1218#define MATCH_VLOXSEG8EI32V 0xec006007 1219#define MASK_VLOXSEG8EI32V 0xfc00707f 1220#define MATCH_VSOXSEG8EI32V 0xec006027 1221#define MASK_VSOXSEG8EI32V 0xfc00707f 1222#define MATCH_VLUXSEG2EI32V 0x24006007 1223#define MASK_VLUXSEG2EI32V 0xfc00707f 1224#define MATCH_VSUXSEG2EI32V 0x24006027 1225#define MASK_VSUXSEG2EI32V 0xfc00707f 1226#define MATCH_VLUXSEG3EI32V 0x44006007 1227#define MASK_VLUXSEG3EI32V 0xfc00707f 1228#define MATCH_VSUXSEG3EI32V 0x44006027 1229#define MASK_VSUXSEG3EI32V 0xfc00707f 1230#define MATCH_VLUXSEG4EI32V 0x64006007 1231#define MASK_VLUXSEG4EI32V 0xfc00707f 1232#define MATCH_VSUXSEG4EI32V 0x64006027 1233#define MASK_VSUXSEG4EI32V 0xfc00707f 1234#define MATCH_VLUXSEG5EI32V 0x84006007 1235#define MASK_VLUXSEG5EI32V 0xfc00707f 1236#define MATCH_VSUXSEG5EI32V 0x84006027 1237#define MASK_VSUXSEG5EI32V 0xfc00707f 1238#define MATCH_VLUXSEG6EI32V 0xa4006007 1239#define MASK_VLUXSEG6EI32V 0xfc00707f 1240#define MATCH_VSUXSEG6EI32V 0xa4006027 1241#define MASK_VSUXSEG6EI32V 0xfc00707f 1242#define MATCH_VLUXSEG7EI32V 0xc4006007 1243#define MASK_VLUXSEG7EI32V 0xfc00707f 1244#define MATCH_VSUXSEG7EI32V 0xc4006027 1245#define MASK_VSUXSEG7EI32V 0xfc00707f 1246#define MATCH_VLUXSEG8EI32V 0xe4006007 1247#define MASK_VLUXSEG8EI32V 0xfc00707f 1248#define MATCH_VSUXSEG8EI32V 0xe4006027 1249#define MASK_VSUXSEG8EI32V 0xfc00707f 1250#define MATCH_VLOXSEG2EI64V 0x2c007007 1251#define MASK_VLOXSEG2EI64V 0xfc00707f 1252#define MATCH_VSOXSEG2EI64V 0x2c007027 1253#define MASK_VSOXSEG2EI64V 0xfc00707f 1254#define MATCH_VLOXSEG3EI64V 0x4c007007 1255#define MASK_VLOXSEG3EI64V 0xfc00707f 1256#define MATCH_VSOXSEG3EI64V 0x4c007027 1257#define MASK_VSOXSEG3EI64V 0xfc00707f 1258#define MATCH_VLOXSEG4EI64V 0x6c007007 1259#define MASK_VLOXSEG4EI64V 0xfc00707f 1260#define MATCH_VSOXSEG4EI64V 0x6c007027 1261#define MASK_VSOXSEG4EI64V 0xfc00707f 1262#define MATCH_VLOXSEG5EI64V 0x8c007007 1263#define MASK_VLOXSEG5EI64V 0xfc00707f 1264#define MATCH_VSOXSEG5EI64V 0x8c007027 1265#define MASK_VSOXSEG5EI64V 0xfc00707f 1266#define MATCH_VLOXSEG6EI64V 0xac007007 1267#define MASK_VLOXSEG6EI64V 0xfc00707f 1268#define MATCH_VSOXSEG6EI64V 0xac007027 1269#define MASK_VSOXSEG6EI64V 0xfc00707f 1270#define MATCH_VLOXSEG7EI64V 0xcc007007 1271#define MASK_VLOXSEG7EI64V 0xfc00707f 1272#define MATCH_VSOXSEG7EI64V 0xcc007027 1273#define MASK_VSOXSEG7EI64V 0xfc00707f 1274#define MATCH_VLOXSEG8EI64V 0xec007007 1275#define MASK_VLOXSEG8EI64V 0xfc00707f 1276#define MATCH_VSOXSEG8EI64V 0xec007027 1277#define MASK_VSOXSEG8EI64V 0xfc00707f 1278#define MATCH_VLUXSEG2EI64V 0x24007007 1279#define MASK_VLUXSEG2EI64V 0xfc00707f 1280#define MATCH_VSUXSEG2EI64V 0x24007027 1281#define MASK_VSUXSEG2EI64V 0xfc00707f 1282#define MATCH_VLUXSEG3EI64V 0x44007007 1283#define MASK_VLUXSEG3EI64V 0xfc00707f 1284#define MATCH_VSUXSEG3EI64V 0x44007027 1285#define MASK_VSUXSEG3EI64V 0xfc00707f 1286#define MATCH_VLUXSEG4EI64V 0x64007007 1287#define MASK_VLUXSEG4EI64V 0xfc00707f 1288#define MATCH_VSUXSEG4EI64V 0x64007027 1289#define MASK_VSUXSEG4EI64V 0xfc00707f 1290#define MATCH_VLUXSEG5EI64V 0x84007007 1291#define MASK_VLUXSEG5EI64V 0xfc00707f 1292#define MATCH_VSUXSEG5EI64V 0x84007027 1293#define MASK_VSUXSEG5EI64V 0xfc00707f 1294#define MATCH_VLUXSEG6EI64V 0xa4007007 1295#define MASK_VLUXSEG6EI64V 0xfc00707f 1296#define MATCH_VSUXSEG6EI64V 0xa4007027 1297#define MASK_VSUXSEG6EI64V 0xfc00707f 1298#define MATCH_VLUXSEG7EI64V 0xc4007007 1299#define MASK_VLUXSEG7EI64V 0xfc00707f 1300#define MATCH_VSUXSEG7EI64V 0xc4007027 1301#define MASK_VSUXSEG7EI64V 0xfc00707f 1302#define MATCH_VLUXSEG8EI64V 0xe4007007 1303#define MASK_VLUXSEG8EI64V 0xfc00707f 1304#define MATCH_VSUXSEG8EI64V 0xe4007027 1305#define MASK_VSUXSEG8EI64V 0xfc00707f 1306#define MATCH_VLSEG2E8FFV 0x21000007 1307#define MASK_VLSEG2E8FFV 0xfdf0707f 1308#define MATCH_VLSEG3E8FFV 0x41000007 1309#define MASK_VLSEG3E8FFV 0xfdf0707f 1310#define MATCH_VLSEG4E8FFV 0x61000007 1311#define MASK_VLSEG4E8FFV 0xfdf0707f 1312#define MATCH_VLSEG5E8FFV 0x81000007 1313#define MASK_VLSEG5E8FFV 0xfdf0707f 1314#define MATCH_VLSEG6E8FFV 0xa1000007 1315#define MASK_VLSEG6E8FFV 0xfdf0707f 1316#define MATCH_VLSEG7E8FFV 0xc1000007 1317#define MASK_VLSEG7E8FFV 0xfdf0707f 1318#define MATCH_VLSEG8E8FFV 0xe1000007 1319#define MASK_VLSEG8E8FFV 0xfdf0707f 1320#define MATCH_VLSEG2E16FFV 0x21005007 1321#define MASK_VLSEG2E16FFV 0xfdf0707f 1322#define MATCH_VLSEG3E16FFV 0x41005007 1323#define MASK_VLSEG3E16FFV 0xfdf0707f 1324#define MATCH_VLSEG4E16FFV 0x61005007 1325#define MASK_VLSEG4E16FFV 0xfdf0707f 1326#define MATCH_VLSEG5E16FFV 0x81005007 1327#define MASK_VLSEG5E16FFV 0xfdf0707f 1328#define MATCH_VLSEG6E16FFV 0xa1005007 1329#define MASK_VLSEG6E16FFV 0xfdf0707f 1330#define MATCH_VLSEG7E16FFV 0xc1005007 1331#define MASK_VLSEG7E16FFV 0xfdf0707f 1332#define MATCH_VLSEG8E16FFV 0xe1005007 1333#define MASK_VLSEG8E16FFV 0xfdf0707f 1334#define MATCH_VLSEG2E32FFV 0x21006007 1335#define MASK_VLSEG2E32FFV 0xfdf0707f 1336#define MATCH_VLSEG3E32FFV 0x41006007 1337#define MASK_VLSEG3E32FFV 0xfdf0707f 1338#define MATCH_VLSEG4E32FFV 0x61006007 1339#define MASK_VLSEG4E32FFV 0xfdf0707f 1340#define MATCH_VLSEG5E32FFV 0x81006007 1341#define MASK_VLSEG5E32FFV 0xfdf0707f 1342#define MATCH_VLSEG6E32FFV 0xa1006007 1343#define MASK_VLSEG6E32FFV 0xfdf0707f 1344#define MATCH_VLSEG7E32FFV 0xc1006007 1345#define MASK_VLSEG7E32FFV 0xfdf0707f 1346#define MATCH_VLSEG8E32FFV 0xe1006007 1347#define MASK_VLSEG8E32FFV 0xfdf0707f 1348#define MATCH_VLSEG2E64FFV 0x21007007 1349#define MASK_VLSEG2E64FFV 0xfdf0707f 1350#define MATCH_VLSEG3E64FFV 0x41007007 1351#define MASK_VLSEG3E64FFV 0xfdf0707f 1352#define MATCH_VLSEG4E64FFV 0x61007007 1353#define MASK_VLSEG4E64FFV 0xfdf0707f 1354#define MATCH_VLSEG5E64FFV 0x81007007 1355#define MASK_VLSEG5E64FFV 0xfdf0707f 1356#define MATCH_VLSEG6E64FFV 0xa1007007 1357#define MASK_VLSEG6E64FFV 0xfdf0707f 1358#define MATCH_VLSEG7E64FFV 0xc1007007 1359#define MASK_VLSEG7E64FFV 0xfdf0707f 1360#define MATCH_VLSEG8E64FFV 0xe1007007 1361#define MASK_VLSEG8E64FFV 0xfdf0707f 1362#define MATCH_VL1RE8V 0x02800007 1363#define MASK_VL1RE8V 0xfff0707f 1364#define MATCH_VL1RE16V 0x02805007 1365#define MASK_VL1RE16V 0xfff0707f 1366#define MATCH_VL1RE32V 0x02806007 1367#define MASK_VL1RE32V 0xfff0707f 1368#define MATCH_VL1RE64V 0x02807007 1369#define MASK_VL1RE64V 0xfff0707f 1370#define MATCH_VL2RE8V 0x22800007 1371#define MASK_VL2RE8V 0xfff0707f 1372#define MATCH_VL2RE16V 0x22805007 1373#define MASK_VL2RE16V 0xfff0707f 1374#define MATCH_VL2RE32V 0x22806007 1375#define MASK_VL2RE32V 0xfff0707f 1376#define MATCH_VL2RE64V 0x22807007 1377#define MASK_VL2RE64V 0xfff0707f 1378#define MATCH_VL4RE8V 0x62800007 1379#define MASK_VL4RE8V 0xfff0707f 1380#define MATCH_VL4RE16V 0x62805007 1381#define MASK_VL4RE16V 0xfff0707f 1382#define MATCH_VL4RE32V 0x62806007 1383#define MASK_VL4RE32V 0xfff0707f 1384#define MATCH_VL4RE64V 0x62807007 1385#define MASK_VL4RE64V 0xfff0707f 1386#define MATCH_VL8RE8V 0xe2800007 1387#define MASK_VL8RE8V 0xfff0707f 1388#define MATCH_VL8RE16V 0xe2805007 1389#define MASK_VL8RE16V 0xfff0707f 1390#define MATCH_VL8RE32V 0xe2806007 1391#define MASK_VL8RE32V 0xfff0707f 1392#define MATCH_VL8RE64V 0xe2807007 1393#define MASK_VL8RE64V 0xfff0707f 1394#define MATCH_VS1RV 0x02800027 1395#define MASK_VS1RV 0xfff0707f 1396#define MATCH_VS2RV 0x22800027 1397#define MASK_VS2RV 0xfff0707f 1398#define MATCH_VS4RV 0x62800027 1399#define MASK_VS4RV 0xfff0707f 1400#define MATCH_VS8RV 0xe2800027 1401#define MASK_VS8RV 0xfff0707f 1402#define MATCH_VADDVV 0x00000057 1403#define MASK_VADDVV 0xfc00707f 1404#define MATCH_VADDVX 0x00004057 1405#define MASK_VADDVX 0xfc00707f 1406#define MATCH_VADDVI 0x00003057 1407#define MASK_VADDVI 0xfc00707f 1408#define MATCH_VSUBVV 0x08000057 1409#define MASK_VSUBVV 0xfc00707f 1410#define MATCH_VSUBVX 0x08004057 1411#define MASK_VSUBVX 0xfc00707f 1412#define MATCH_VRSUBVX 0x0c004057 1413#define MASK_VRSUBVX 0xfc00707f 1414#define MATCH_VRSUBVI 0x0c003057 1415#define MASK_VRSUBVI 0xfc00707f 1416#define MATCH_VWCVTXXV 0xc4006057 1417#define MASK_VWCVTXXV 0xfc0ff07f 1418#define MATCH_VWCVTUXXV 0xc0006057 1419#define MASK_VWCVTUXXV 0xfc0ff07f 1420#define MATCH_VWADDVV 0xc4002057 1421#define MASK_VWADDVV 0xfc00707f 1422#define MATCH_VWADDVX 0xc4006057 1423#define MASK_VWADDVX 0xfc00707f 1424#define MATCH_VWSUBVV 0xcc002057 1425#define MASK_VWSUBVV 0xfc00707f 1426#define MATCH_VWSUBVX 0xcc006057 1427#define MASK_VWSUBVX 0xfc00707f 1428#define MATCH_VWADDWV 0xd4002057 1429#define MASK_VWADDWV 0xfc00707f 1430#define MATCH_VWADDWX 0xd4006057 1431#define MASK_VWADDWX 0xfc00707f 1432#define MATCH_VWSUBWV 0xdc002057 1433#define MASK_VWSUBWV 0xfc00707f 1434#define MATCH_VWSUBWX 0xdc006057 1435#define MASK_VWSUBWX 0xfc00707f 1436#define MATCH_VWADDUVV 0xc0002057 1437#define MASK_VWADDUVV 0xfc00707f 1438#define MATCH_VWADDUVX 0xc0006057 1439#define MASK_VWADDUVX 0xfc00707f 1440#define MATCH_VWSUBUVV 0xc8002057 1441#define MASK_VWSUBUVV 0xfc00707f 1442#define MATCH_VWSUBUVX 0xc8006057 1443#define MASK_VWSUBUVX 0xfc00707f 1444#define MATCH_VWADDUWV 0xd0002057 1445#define MASK_VWADDUWV 0xfc00707f 1446#define MATCH_VWADDUWX 0xd0006057 1447#define MASK_VWADDUWX 0xfc00707f 1448#define MATCH_VWSUBUWV 0xd8002057 1449#define MASK_VWSUBUWV 0xfc00707f 1450#define MATCH_VWSUBUWX 0xd8006057 1451#define MASK_VWSUBUWX 0xfc00707f 1452#define MATCH_VZEXT_VF8 0x48012057 1453#define MASK_VZEXT_VF8 0xfc0ff07f 1454#define MATCH_VSEXT_VF8 0x4801a057 1455#define MASK_VSEXT_VF8 0xfc0ff07f 1456#define MATCH_VZEXT_VF4 0x48022057 1457#define MASK_VZEXT_VF4 0xfc0ff07f 1458#define MATCH_VSEXT_VF4 0x4802a057 1459#define MASK_VSEXT_VF4 0xfc0ff07f 1460#define MATCH_VZEXT_VF2 0x48032057 1461#define MASK_VZEXT_VF2 0xfc0ff07f 1462#define MATCH_VSEXT_VF2 0x4803a057 1463#define MASK_VSEXT_VF2 0xfc0ff07f 1464#define MATCH_VADCVVM 0x40000057 1465#define MASK_VADCVVM 0xfe00707f 1466#define MATCH_VADCVXM 0x40004057 1467#define MASK_VADCVXM 0xfe00707f 1468#define MATCH_VADCVIM 0x40003057 1469#define MASK_VADCVIM 0xfe00707f 1470#define MATCH_VMADCVVM 0x44000057 1471#define MASK_VMADCVVM 0xfe00707f 1472#define MATCH_VMADCVXM 0x44004057 1473#define MASK_VMADCVXM 0xfe00707f 1474#define MATCH_VMADCVIM 0x44003057 1475#define MASK_VMADCVIM 0xfe00707f 1476#define MATCH_VMADCVV 0x46000057 1477#define MASK_VMADCVV 0xfe00707f 1478#define MATCH_VMADCVX 0x46004057 1479#define MASK_VMADCVX 0xfe00707f 1480#define MATCH_VMADCVI 0x46003057 1481#define MASK_VMADCVI 0xfe00707f 1482#define MATCH_VSBCVVM 0x48000057 1483#define MASK_VSBCVVM 0xfe00707f 1484#define MATCH_VSBCVXM 0x48004057 1485#define MASK_VSBCVXM 0xfe00707f 1486#define MATCH_VMSBCVVM 0x4c000057 1487#define MASK_VMSBCVVM 0xfe00707f 1488#define MATCH_VMSBCVXM 0x4c004057 1489#define MASK_VMSBCVXM 0xfe00707f 1490#define MATCH_VMSBCVV 0x4e000057 1491#define MASK_VMSBCVV 0xfe00707f 1492#define MATCH_VMSBCVX 0x4e004057 1493#define MASK_VMSBCVX 0xfe00707f 1494#define MATCH_VNOTV 0x2c0fb057 1495#define MASK_VNOTV 0xfc0ff07f 1496#define MATCH_VANDVV 0x24000057 1497#define MASK_VANDVV 0xfc00707f 1498#define MATCH_VANDVX 0x24004057 1499#define MASK_VANDVX 0xfc00707f 1500#define MATCH_VANDVI 0x24003057 1501#define MASK_VANDVI 0xfc00707f 1502#define MATCH_VORVV 0x28000057 1503#define MASK_VORVV 0xfc00707f 1504#define MATCH_VORVX 0x28004057 1505#define MASK_VORVX 0xfc00707f 1506#define MATCH_VORVI 0x28003057 1507#define MASK_VORVI 0xfc00707f 1508#define MATCH_VXORVV 0x2c000057 1509#define MASK_VXORVV 0xfc00707f 1510#define MATCH_VXORVX 0x2c004057 1511#define MASK_VXORVX 0xfc00707f 1512#define MATCH_VXORVI 0x2c003057 1513#define MASK_VXORVI 0xfc00707f 1514#define MATCH_VSLLVV 0x94000057 1515#define MASK_VSLLVV 0xfc00707f 1516#define MATCH_VSLLVX 0x94004057 1517#define MASK_VSLLVX 0xfc00707f 1518#define MATCH_VSLLVI 0x94003057 1519#define MASK_VSLLVI 0xfc00707f 1520#define MATCH_VSRLVV 0xa0000057 1521#define MASK_VSRLVV 0xfc00707f 1522#define MATCH_VSRLVX 0xa0004057 1523#define MASK_VSRLVX 0xfc00707f 1524#define MATCH_VSRLVI 0xa0003057 1525#define MASK_VSRLVI 0xfc00707f 1526#define MATCH_VSRAVV 0xa4000057 1527#define MASK_VSRAVV 0xfc00707f 1528#define MATCH_VSRAVX 0xa4004057 1529#define MASK_VSRAVX 0xfc00707f 1530#define MATCH_VSRAVI 0xa4003057 1531#define MASK_VSRAVI 0xfc00707f 1532#define MATCH_VNCVTXXW 0xb0004057 1533#define MASK_VNCVTXXW 0xfc0ff07f 1534#define MATCH_VNSRLWV 0xb0000057 1535#define MASK_VNSRLWV 0xfc00707f 1536#define MATCH_VNSRLWX 0xb0004057 1537#define MASK_VNSRLWX 0xfc00707f 1538#define MATCH_VNSRLWI 0xb0003057 1539#define MASK_VNSRLWI 0xfc00707f 1540#define MATCH_VNSRAWV 0xb4000057 1541#define MASK_VNSRAWV 0xfc00707f 1542#define MATCH_VNSRAWX 0xb4004057 1543#define MASK_VNSRAWX 0xfc00707f 1544#define MATCH_VNSRAWI 0xb4003057 1545#define MASK_VNSRAWI 0xfc00707f 1546#define MATCH_VMSEQVV 0x60000057 1547#define MASK_VMSEQVV 0xfc00707f 1548#define MATCH_VMSEQVX 0x60004057 1549#define MASK_VMSEQVX 0xfc00707f 1550#define MATCH_VMSEQVI 0x60003057 1551#define MASK_VMSEQVI 0xfc00707f 1552#define MATCH_VMSNEVV 0x64000057 1553#define MASK_VMSNEVV 0xfc00707f 1554#define MATCH_VMSNEVX 0x64004057 1555#define MASK_VMSNEVX 0xfc00707f 1556#define MATCH_VMSNEVI 0x64003057 1557#define MASK_VMSNEVI 0xfc00707f 1558#define MATCH_VMSLTVV 0x6c000057 1559#define MASK_VMSLTVV 0xfc00707f 1560#define MATCH_VMSLTVX 0x6c004057 1561#define MASK_VMSLTVX 0xfc00707f 1562#define MATCH_VMSLTUVV 0x68000057 1563#define MASK_VMSLTUVV 0xfc00707f 1564#define MATCH_VMSLTUVX 0x68004057 1565#define MASK_VMSLTUVX 0xfc00707f 1566#define MATCH_VMSLEVV 0x74000057 1567#define MASK_VMSLEVV 0xfc00707f 1568#define MATCH_VMSLEVX 0x74004057 1569#define MASK_VMSLEVX 0xfc00707f 1570#define MATCH_VMSLEVI 0x74003057 1571#define MASK_VMSLEVI 0xfc00707f 1572#define MATCH_VMSLEUVV 0x70000057 1573#define MASK_VMSLEUVV 0xfc00707f 1574#define MATCH_VMSLEUVX 0x70004057 1575#define MASK_VMSLEUVX 0xfc00707f 1576#define MATCH_VMSLEUVI 0x70003057 1577#define MASK_VMSLEUVI 0xfc00707f 1578#define MATCH_VMSGTVX 0x7c004057 1579#define MASK_VMSGTVX 0xfc00707f 1580#define MATCH_VMSGTVI 0x7c003057 1581#define MASK_VMSGTVI 0xfc00707f 1582#define MATCH_VMSGTUVX 0x78004057 1583#define MASK_VMSGTUVX 0xfc00707f 1584#define MATCH_VMSGTUVI 0x78003057 1585#define MASK_VMSGTUVI 0xfc00707f 1586#define MATCH_VMINVV 0x14000057 1587#define MASK_VMINVV 0xfc00707f 1588#define MATCH_VMINVX 0x14004057 1589#define MASK_VMINVX 0xfc00707f 1590#define MATCH_VMAXVV 0x1c000057 1591#define MASK_VMAXVV 0xfc00707f 1592#define MATCH_VMAXVX 0x1c004057 1593#define MASK_VMAXVX 0xfc00707f 1594#define MATCH_VMINUVV 0x10000057 1595#define MASK_VMINUVV 0xfc00707f 1596#define MATCH_VMINUVX 0x10004057 1597#define MASK_VMINUVX 0xfc00707f 1598#define MATCH_VMAXUVV 0x18000057 1599#define MASK_VMAXUVV 0xfc00707f 1600#define MATCH_VMAXUVX 0x18004057 1601#define MASK_VMAXUVX 0xfc00707f 1602#define MATCH_VMULVV 0x94002057 1603#define MASK_VMULVV 0xfc00707f 1604#define MATCH_VMULVX 0x94006057 1605#define MASK_VMULVX 0xfc00707f 1606#define MATCH_VMULHVV 0x9c002057 1607#define MASK_VMULHVV 0xfc00707f 1608#define MATCH_VMULHVX 0x9c006057 1609#define MASK_VMULHVX 0xfc00707f 1610#define MATCH_VMULHUVV 0x90002057 1611#define MASK_VMULHUVV 0xfc00707f 1612#define MATCH_VMULHUVX 0x90006057 1613#define MASK_VMULHUVX 0xfc00707f 1614#define MATCH_VMULHSUVV 0x98002057 1615#define MASK_VMULHSUVV 0xfc00707f 1616#define MATCH_VMULHSUVX 0x98006057 1617#define MASK_VMULHSUVX 0xfc00707f 1618#define MATCH_VWMULVV 0xec002057 1619#define MASK_VWMULVV 0xfc00707f 1620#define MATCH_VWMULVX 0xec006057 1621#define MASK_VWMULVX 0xfc00707f 1622#define MATCH_VWMULUVV 0xe0002057 1623#define MASK_VWMULUVV 0xfc00707f 1624#define MATCH_VWMULUVX 0xe0006057 1625#define MASK_VWMULUVX 0xfc00707f 1626#define MATCH_VWMULSUVV 0xe8002057 1627#define MASK_VWMULSUVV 0xfc00707f 1628#define MATCH_VWMULSUVX 0xe8006057 1629#define MASK_VWMULSUVX 0xfc00707f 1630#define MATCH_VMACCVV 0xb4002057 1631#define MASK_VMACCVV 0xfc00707f 1632#define MATCH_VMACCVX 0xb4006057 1633#define MASK_VMACCVX 0xfc00707f 1634#define MATCH_VNMSACVV 0xbc002057 1635#define MASK_VNMSACVV 0xfc00707f 1636#define MATCH_VNMSACVX 0xbc006057 1637#define MASK_VNMSACVX 0xfc00707f 1638#define MATCH_VMADDVV 0xa4002057 1639#define MASK_VMADDVV 0xfc00707f 1640#define MATCH_VMADDVX 0xa4006057 1641#define MASK_VMADDVX 0xfc00707f 1642#define MATCH_VNMSUBVV 0xac002057 1643#define MASK_VNMSUBVV 0xfc00707f 1644#define MATCH_VNMSUBVX 0xac006057 1645#define MASK_VNMSUBVX 0xfc00707f 1646#define MATCH_VWMACCUVV 0xf0002057 1647#define MASK_VWMACCUVV 0xfc00707f 1648#define MATCH_VWMACCUVX 0xf0006057 1649#define MASK_VWMACCUVX 0xfc00707f 1650#define MATCH_VWMACCVV 0xf4002057 1651#define MASK_VWMACCVV 0xfc00707f 1652#define MATCH_VWMACCVX 0xf4006057 1653#define MASK_VWMACCVX 0xfc00707f 1654#define MATCH_VWMACCSUVV 0xfc002057 1655#define MASK_VWMACCSUVV 0xfc00707f 1656#define MATCH_VWMACCSUVX 0xfc006057 1657#define MASK_VWMACCSUVX 0xfc00707f 1658#define MATCH_VWMACCUSVX 0xf8006057 1659#define MASK_VWMACCUSVX 0xfc00707f 1660#define MATCH_VQMACCUVV 0xf0000057 1661#define MASK_VQMACCUVV 0xfc00707f 1662#define MATCH_VQMACCUVX 0xf0004057 1663#define MASK_VQMACCUVX 0xfc00707f 1664#define MATCH_VQMACCVV 0xf4000057 1665#define MASK_VQMACCVV 0xfc00707f 1666#define MATCH_VQMACCVX 0xf4004057 1667#define MASK_VQMACCVX 0xfc00707f 1668#define MATCH_VQMACCSUVV 0xfc000057 1669#define MASK_VQMACCSUVV 0xfc00707f 1670#define MATCH_VQMACCSUVX 0xfc004057 1671#define MASK_VQMACCSUVX 0xfc00707f 1672#define MATCH_VQMACCUSVX 0xf8004057 1673#define MASK_VQMACCUSVX 0xfc00707f 1674#define MATCH_VDIVVV 0x84002057 1675#define MASK_VDIVVV 0xfc00707f 1676#define MATCH_VDIVVX 0x84006057 1677#define MASK_VDIVVX 0xfc00707f 1678#define MATCH_VDIVUVV 0x80002057 1679#define MASK_VDIVUVV 0xfc00707f 1680#define MATCH_VDIVUVX 0x80006057 1681#define MASK_VDIVUVX 0xfc00707f 1682#define MATCH_VREMVV 0x8c002057 1683#define MASK_VREMVV 0xfc00707f 1684#define MATCH_VREMVX 0x8c006057 1685#define MASK_VREMVX 0xfc00707f 1686#define MATCH_VREMUVV 0x88002057 1687#define MASK_VREMUVV 0xfc00707f 1688#define MATCH_VREMUVX 0x88006057 1689#define MASK_VREMUVX 0xfc00707f 1690#define MATCH_VMERGEVVM 0x5c000057 1691#define MASK_VMERGEVVM 0xfe00707f 1692#define MATCH_VMERGEVXM 0x5c004057 1693#define MASK_VMERGEVXM 0xfe00707f 1694#define MATCH_VMERGEVIM 0x5c003057 1695#define MASK_VMERGEVIM 0xfe00707f 1696#define MATCH_VMVVV 0x5e000057 1697#define MASK_VMVVV 0xfff0707f 1698#define MATCH_VMVVX 0x5e004057 1699#define MASK_VMVVX 0xfff0707f 1700#define MATCH_VMVVI 0x5e003057 1701#define MASK_VMVVI 0xfff0707f 1702#define MATCH_VSADDUVV 0x80000057 1703#define MASK_VSADDUVV 0xfc00707f 1704#define MATCH_VSADDUVX 0x80004057 1705#define MASK_VSADDUVX 0xfc00707f 1706#define MATCH_VSADDUVI 0x80003057 1707#define MASK_VSADDUVI 0xfc00707f 1708#define MATCH_VSADDVV 0x84000057 1709#define MASK_VSADDVV 0xfc00707f 1710#define MATCH_VSADDVX 0x84004057 1711#define MASK_VSADDVX 0xfc00707f 1712#define MATCH_VSADDVI 0x84003057 1713#define MASK_VSADDVI 0xfc00707f 1714#define MATCH_VSSUBUVV 0x88000057 1715#define MASK_VSSUBUVV 0xfc00707f 1716#define MATCH_VSSUBUVX 0x88004057 1717#define MASK_VSSUBUVX 0xfc00707f 1718#define MATCH_VSSUBVV 0x8c000057 1719#define MASK_VSSUBVV 0xfc00707f 1720#define MATCH_VSSUBVX 0x8c004057 1721#define MASK_VSSUBVX 0xfc00707f 1722#define MATCH_VAADDUVV 0x20002057 1723#define MASK_VAADDUVV 0xfc00707f 1724#define MATCH_VAADDUVX 0x20006057 1725#define MASK_VAADDUVX 0xfc00707f 1726#define MATCH_VAADDVV 0x24002057 1727#define MASK_VAADDVV 0xfc00707f 1728#define MATCH_VAADDVX 0x24006057 1729#define MASK_VAADDVX 0xfc00707f 1730#define MATCH_VASUBUVV 0x28002057 1731#define MASK_VASUBUVV 0xfc00707f 1732#define MATCH_VASUBUVX 0x28006057 1733#define MASK_VASUBUVX 0xfc00707f 1734#define MATCH_VASUBVV 0x2c002057 1735#define MASK_VASUBVV 0xfc00707f 1736#define MATCH_VASUBVX 0x2c006057 1737#define MASK_VASUBVX 0xfc00707f 1738#define MATCH_VSMULVV 0x9c000057 1739#define MASK_VSMULVV 0xfc00707f 1740#define MATCH_VSMULVX 0x9c004057 1741#define MASK_VSMULVX 0xfc00707f 1742#define MATCH_VSSRLVV 0xa8000057 1743#define MASK_VSSRLVV 0xfc00707f 1744#define MATCH_VSSRLVX 0xa8004057 1745#define MASK_VSSRLVX 0xfc00707f 1746#define MATCH_VSSRLVI 0xa8003057 1747#define MASK_VSSRLVI 0xfc00707f 1748#define MATCH_VSSRAVV 0xac000057 1749#define MASK_VSSRAVV 0xfc00707f 1750#define MATCH_VSSRAVX 0xac004057 1751#define MASK_VSSRAVX 0xfc00707f 1752#define MATCH_VSSRAVI 0xac003057 1753#define MASK_VSSRAVI 0xfc00707f 1754#define MATCH_VNCLIPUWV 0xb8000057 1755#define MASK_VNCLIPUWV 0xfc00707f 1756#define MATCH_VNCLIPUWX 0xb8004057 1757#define MASK_VNCLIPUWX 0xfc00707f 1758#define MATCH_VNCLIPUWI 0xb8003057 1759#define MASK_VNCLIPUWI 0xfc00707f 1760#define MATCH_VNCLIPWV 0xbc000057 1761#define MASK_VNCLIPWV 0xfc00707f 1762#define MATCH_VNCLIPWX 0xbc004057 1763#define MASK_VNCLIPWX 0xfc00707f 1764#define MATCH_VNCLIPWI 0xbc003057 1765#define MASK_VNCLIPWI 0xfc00707f 1766#define MATCH_VFADDVV 0x00001057 1767#define MASK_VFADDVV 0xfc00707f 1768#define MATCH_VFADDVF 0x00005057 1769#define MASK_VFADDVF 0xfc00707f 1770#define MATCH_VFSUBVV 0x08001057 1771#define MASK_VFSUBVV 0xfc00707f 1772#define MATCH_VFSUBVF 0x08005057 1773#define MASK_VFSUBVF 0xfc00707f 1774#define MATCH_VFRSUBVF 0x9c005057 1775#define MASK_VFRSUBVF 0xfc00707f 1776#define MATCH_VFWADDVV 0xc0001057 1777#define MASK_VFWADDVV 0xfc00707f 1778#define MATCH_VFWADDVF 0xc0005057 1779#define MASK_VFWADDVF 0xfc00707f 1780#define MATCH_VFWSUBVV 0xc8001057 1781#define MASK_VFWSUBVV 0xfc00707f 1782#define MATCH_VFWSUBVF 0xc8005057 1783#define MASK_VFWSUBVF 0xfc00707f 1784#define MATCH_VFWADDWV 0xd0001057 1785#define MASK_VFWADDWV 0xfc00707f 1786#define MATCH_VFWADDWF 0xd0005057 1787#define MASK_VFWADDWF 0xfc00707f 1788#define MATCH_VFWSUBWV 0xd8001057 1789#define MASK_VFWSUBWV 0xfc00707f 1790#define MATCH_VFWSUBWF 0xd8005057 1791#define MASK_VFWSUBWF 0xfc00707f 1792#define MATCH_VFMULVV 0x90001057 1793#define MASK_VFMULVV 0xfc00707f 1794#define MATCH_VFMULVF 0x90005057 1795#define MASK_VFMULVF 0xfc00707f 1796#define MATCH_VFDIVVV 0x80001057 1797#define MASK_VFDIVVV 0xfc00707f 1798#define MATCH_VFDIVVF 0x80005057 1799#define MASK_VFDIVVF 0xfc00707f 1800#define MATCH_VFRDIVVF 0x84005057 1801#define MASK_VFRDIVVF 0xfc00707f 1802#define MATCH_VFWMULVV 0xe0001057 1803#define MASK_VFWMULVV 0xfc00707f 1804#define MATCH_VFWMULVF 0xe0005057 1805#define MASK_VFWMULVF 0xfc00707f 1806#define MATCH_VFMADDVV 0xa0001057 1807#define MASK_VFMADDVV 0xfc00707f 1808#define MATCH_VFMADDVF 0xa0005057 1809#define MASK_VFMADDVF 0xfc00707f 1810#define MATCH_VFNMADDVV 0xa4001057 1811#define MASK_VFNMADDVV 0xfc00707f 1812#define MATCH_VFNMADDVF 0xa4005057 1813#define MASK_VFNMADDVF 0xfc00707f 1814#define MATCH_VFMSUBVV 0xa8001057 1815#define MASK_VFMSUBVV 0xfc00707f 1816#define MATCH_VFMSUBVF 0xa8005057 1817#define MASK_VFMSUBVF 0xfc00707f 1818#define MATCH_VFNMSUBVV 0xac001057 1819#define MASK_VFNMSUBVV 0xfc00707f 1820#define MATCH_VFNMSUBVF 0xac005057 1821#define MASK_VFNMSUBVF 0xfc00707f 1822#define MATCH_VFMACCVV 0xb0001057 1823#define MASK_VFMACCVV 0xfc00707f 1824#define MATCH_VFMACCVF 0xb0005057 1825#define MASK_VFMACCVF 0xfc00707f 1826#define MATCH_VFNMACCVV 0xb4001057 1827#define MASK_VFNMACCVV 0xfc00707f 1828#define MATCH_VFNMACCVF 0xb4005057 1829#define MASK_VFNMACCVF 0xfc00707f 1830#define MATCH_VFMSACVV 0xb8001057 1831#define MASK_VFMSACVV 0xfc00707f 1832#define MATCH_VFMSACVF 0xb8005057 1833#define MASK_VFMSACVF 0xfc00707f 1834#define MATCH_VFNMSACVV 0xbc001057 1835#define MASK_VFNMSACVV 0xfc00707f 1836#define MATCH_VFNMSACVF 0xbc005057 1837#define MASK_VFNMSACVF 0xfc00707f 1838#define MATCH_VFWMACCVV 0xf0001057 1839#define MASK_VFWMACCVV 0xfc00707f 1840#define MATCH_VFWMACCVF 0xf0005057 1841#define MASK_VFWMACCVF 0xfc00707f 1842#define MATCH_VFWNMACCVV 0xf4001057 1843#define MASK_VFWNMACCVV 0xfc00707f 1844#define MATCH_VFWNMACCVF 0xf4005057 1845#define MASK_VFWNMACCVF 0xfc00707f 1846#define MATCH_VFWMSACVV 0xf8001057 1847#define MASK_VFWMSACVV 0xfc00707f 1848#define MATCH_VFWMSACVF 0xf8005057 1849#define MASK_VFWMSACVF 0xfc00707f 1850#define MATCH_VFWNMSACVV 0xfc001057 1851#define MASK_VFWNMSACVV 0xfc00707f 1852#define MATCH_VFWNMSACVF 0xfc005057 1853#define MASK_VFWNMSACVF 0xfc00707f 1854#define MATCH_VFSQRTV 0x4c001057 1855#define MASK_VFSQRTV 0xfc0ff07f 1856#define MATCH_VFRSQRT7V 0x4c021057 1857#define MASK_VFRSQRT7V 0xfc0ff07f 1858#define MATCH_VFREC7V 0x4c029057 1859#define MASK_VFREC7V 0xfc0ff07f 1860#define MATCH_VFCLASSV 0x4c081057 1861#define MASK_VFCLASSV 0xfc0ff07f 1862#define MATCH_VFMINVV 0x10001057 1863#define MASK_VFMINVV 0xfc00707f 1864#define MATCH_VFMINVF 0x10005057 1865#define MASK_VFMINVF 0xfc00707f 1866#define MATCH_VFMAXVV 0x18001057 1867#define MASK_VFMAXVV 0xfc00707f 1868#define MATCH_VFMAXVF 0x18005057 1869#define MASK_VFMAXVF 0xfc00707f 1870#define MATCH_VFSGNJVV 0x20001057 1871#define MASK_VFSGNJVV 0xfc00707f 1872#define MATCH_VFSGNJVF 0x20005057 1873#define MASK_VFSGNJVF 0xfc00707f 1874#define MATCH_VFSGNJNVV 0x24001057 1875#define MASK_VFSGNJNVV 0xfc00707f 1876#define MATCH_VFSGNJNVF 0x24005057 1877#define MASK_VFSGNJNVF 0xfc00707f 1878#define MATCH_VFSGNJXVV 0x28001057 1879#define MASK_VFSGNJXVV 0xfc00707f 1880#define MATCH_VFSGNJXVF 0x28005057 1881#define MASK_VFSGNJXVF 0xfc00707f 1882#define MATCH_VMFEQVV 0x60001057 1883#define MASK_VMFEQVV 0xfc00707f 1884#define MATCH_VMFEQVF 0x60005057 1885#define MASK_VMFEQVF 0xfc00707f 1886#define MATCH_VMFNEVV 0x70001057 1887#define MASK_VMFNEVV 0xfc00707f 1888#define MATCH_VMFNEVF 0x70005057 1889#define MASK_VMFNEVF 0xfc00707f 1890#define MATCH_VMFLTVV 0x6c001057 1891#define MASK_VMFLTVV 0xfc00707f 1892#define MATCH_VMFLTVF 0x6c005057 1893#define MASK_VMFLTVF 0xfc00707f 1894#define MATCH_VMFLEVV 0x64001057 1895#define MASK_VMFLEVV 0xfc00707f 1896#define MATCH_VMFLEVF 0x64005057 1897#define MASK_VMFLEVF 0xfc00707f 1898#define MATCH_VMFGTVF 0x74005057 1899#define MASK_VMFGTVF 0xfc00707f 1900#define MATCH_VMFGEVF 0x7c005057 1901#define MASK_VMFGEVF 0xfc00707f 1902#define MATCH_VFMERGEVFM 0x5c005057 1903#define MASK_VFMERGEVFM 0xfe00707f 1904#define MATCH_VFMVVF 0x5e005057 1905#define MASK_VFMVVF 0xfff0707f 1906#define MATCH_VFCVTXUFV 0x48001057 1907#define MASK_VFCVTXUFV 0xfc0ff07f 1908#define MATCH_VFCVTXFV 0x48009057 1909#define MASK_VFCVTXFV 0xfc0ff07f 1910#define MATCH_VFCVTFXUV 0x48011057 1911#define MASK_VFCVTFXUV 0xfc0ff07f 1912#define MATCH_VFCVTFXV 0x48019057 1913#define MASK_VFCVTFXV 0xfc0ff07f 1914#define MATCH_VFCVTRTZXUFV 0x48031057 1915#define MASK_VFCVTRTZXUFV 0xfc0ff07f 1916#define MATCH_VFCVTRTZXFV 0x48039057 1917#define MASK_VFCVTRTZXFV 0xfc0ff07f 1918#define MATCH_VFWCVTXUFV 0x48041057 1919#define MASK_VFWCVTXUFV 0xfc0ff07f 1920#define MATCH_VFWCVTXFV 0x48049057 1921#define MASK_VFWCVTXFV 0xfc0ff07f 1922#define MATCH_VFWCVTFXUV 0x48051057 1923#define MASK_VFWCVTFXUV 0xfc0ff07f 1924#define MATCH_VFWCVTFXV 0x48059057 1925#define MASK_VFWCVTFXV 0xfc0ff07f 1926#define MATCH_VFWCVTFFV 0x48061057 1927#define MASK_VFWCVTFFV 0xfc0ff07f 1928#define MATCH_VFWCVTRTZXUFV 0x48071057 1929#define MASK_VFWCVTRTZXUFV 0xfc0ff07f 1930#define MATCH_VFWCVTRTZXFV 0x48079057 1931#define MASK_VFWCVTRTZXFV 0xfc0ff07f 1932#define MATCH_VFNCVTXUFW 0x48081057 1933#define MASK_VFNCVTXUFW 0xfc0ff07f 1934#define MATCH_VFNCVTXFW 0x48089057 1935#define MASK_VFNCVTXFW 0xfc0ff07f 1936#define MATCH_VFNCVTFXUW 0x48091057 1937#define MASK_VFNCVTFXUW 0xfc0ff07f 1938#define MATCH_VFNCVTFXW 0x48099057 1939#define MASK_VFNCVTFXW 0xfc0ff07f 1940#define MATCH_VFNCVTFFW 0x480a1057 1941#define MASK_VFNCVTFFW 0xfc0ff07f 1942#define MATCH_VFNCVTRODFFW 0x480a9057 1943#define MASK_VFNCVTRODFFW 0xfc0ff07f 1944#define MATCH_VFNCVTRTZXUFW 0x480b1057 1945#define MASK_VFNCVTRTZXUFW 0xfc0ff07f 1946#define MATCH_VFNCVTRTZXFW 0x480b9057 1947#define MASK_VFNCVTRTZXFW 0xfc0ff07f 1948#define MATCH_VREDSUMVS 0x00002057 1949#define MASK_VREDSUMVS 0xfc00707f 1950#define MATCH_VREDMAXVS 0x1c002057 1951#define MASK_VREDMAXVS 0xfc00707f 1952#define MATCH_VREDMAXUVS 0x18002057 1953#define MASK_VREDMAXUVS 0xfc00707f 1954#define MATCH_VREDMINVS 0x14002057 1955#define MASK_VREDMINVS 0xfc00707f 1956#define MATCH_VREDMINUVS 0x10002057 1957#define MASK_VREDMINUVS 0xfc00707f 1958#define MATCH_VREDANDVS 0x04002057 1959#define MASK_VREDANDVS 0xfc00707f 1960#define MATCH_VREDORVS 0x08002057 1961#define MASK_VREDORVS 0xfc00707f 1962#define MATCH_VREDXORVS 0x0c002057 1963#define MASK_VREDXORVS 0xfc00707f 1964#define MATCH_VWREDSUMUVS 0xc0000057 1965#define MASK_VWREDSUMUVS 0xfc00707f 1966#define MATCH_VWREDSUMVS 0xc4000057 1967#define MASK_VWREDSUMVS 0xfc00707f 1968#define MATCH_VFREDOSUMVS 0x0c001057 1969#define MASK_VFREDOSUMVS 0xfc00707f 1970#define MATCH_VFREDUSUMVS 0x04001057 1971#define MASK_VFREDUSUMVS 0xfc00707f 1972#define MATCH_VFREDMAXVS 0x1c001057 1973#define MASK_VFREDMAXVS 0xfc00707f 1974#define MATCH_VFREDMINVS 0x14001057 1975#define MASK_VFREDMINVS 0xfc00707f 1976#define MATCH_VFWREDOSUMVS 0xcc001057 1977#define MASK_VFWREDOSUMVS 0xfc00707f 1978#define MATCH_VFWREDUSUMVS 0xc4001057 1979#define MASK_VFWREDUSUMVS 0xfc00707f 1980#define MATCH_VMANDMM 0x66002057 1981#define MASK_VMANDMM 0xfe00707f 1982#define MATCH_VMNANDMM 0x76002057 1983#define MASK_VMNANDMM 0xfe00707f 1984#define MATCH_VMANDNMM 0x62002057 1985#define MASK_VMANDNMM 0xfe00707f 1986#define MATCH_VMXORMM 0x6e002057 1987#define MASK_VMXORMM 0xfe00707f 1988#define MATCH_VMORMM 0x6a002057 1989#define MASK_VMORMM 0xfe00707f 1990#define MATCH_VMNORMM 0x7a002057 1991#define MASK_VMNORMM 0xfe00707f 1992#define MATCH_VMORNMM 0x72002057 1993#define MASK_VMORNMM 0xfe00707f 1994#define MATCH_VMXNORMM 0x7e002057 1995#define MASK_VMXNORMM 0xfe00707f 1996#define MATCH_VCPOPM 0x40082057 1997#define MASK_VCPOPM 0xfc0ff07f 1998#define MATCH_VFIRSTM 0x4008a057 1999#define MASK_VFIRSTM 0xfc0ff07f 2000#define MATCH_VMSBFM 0x5000a057 2001#define MASK_VMSBFM 0xfc0ff07f 2002#define MATCH_VMSIFM 0x5001a057 2003#define MASK_VMSIFM 0xfc0ff07f 2004#define MATCH_VMSOFM 0x50012057 2005#define MASK_VMSOFM 0xfc0ff07f 2006#define MATCH_VIOTAM 0x50082057 2007#define MASK_VIOTAM 0xfc0ff07f 2008#define MATCH_VIDV 0x5008a057 2009#define MASK_VIDV 0xfdfff07f 2010#define MATCH_VMVXS 0x42002057 2011#define MASK_VMVXS 0xfe0ff07f 2012#define MATCH_VMVSX 0x42006057 2013#define MASK_VMVSX 0xfff0707f 2014#define MATCH_VFMVFS 0x42001057 2015#define MASK_VFMVFS 0xfe0ff07f 2016#define MATCH_VFMVSF 0x42005057 2017#define MASK_VFMVSF 0xfff0707f 2018#define MATCH_VSLIDEUPVX 0x38004057 2019#define MASK_VSLIDEUPVX 0xfc00707f 2020#define MATCH_VSLIDEUPVI 0x38003057 2021#define MASK_VSLIDEUPVI 0xfc00707f 2022#define MATCH_VSLIDEDOWNVX 0x3c004057 2023#define MASK_VSLIDEDOWNVX 0xfc00707f 2024#define MATCH_VSLIDEDOWNVI 0x3c003057 2025#define MASK_VSLIDEDOWNVI 0xfc00707f 2026#define MATCH_VSLIDE1UPVX 0x38006057 2027#define MASK_VSLIDE1UPVX 0xfc00707f 2028#define MATCH_VSLIDE1DOWNVX 0x3c006057 2029#define MASK_VSLIDE1DOWNVX 0xfc00707f 2030#define MATCH_VFSLIDE1UPVF 0x38005057 2031#define MASK_VFSLIDE1UPVF 0xfc00707f 2032#define MATCH_VFSLIDE1DOWNVF 0x3c005057 2033#define MASK_VFSLIDE1DOWNVF 0xfc00707f 2034#define MATCH_VRGATHERVV 0x30000057 2035#define MASK_VRGATHERVV 0xfc00707f 2036#define MATCH_VRGATHERVX 0x30004057 2037#define MASK_VRGATHERVX 0xfc00707f 2038#define MATCH_VRGATHERVI 0x30003057 2039#define MASK_VRGATHERVI 0xfc00707f 2040#define MATCH_VRGATHEREI16VV 0x38000057 2041#define MASK_VRGATHEREI16VV 0xfc00707f 2042#define MATCH_VCOMPRESSVM 0x5e002057 2043#define MASK_VCOMPRESSVM 0xfe00707f 2044#define MATCH_VMV1RV 0x9e003057 2045#define MASK_VMV1RV 0xfe0ff07f 2046#define MATCH_VMV2RV 0x9e00b057 2047#define MASK_VMV2RV 0xfe0ff07f 2048#define MATCH_VMV4RV 0x9e01b057 2049#define MASK_VMV4RV 0xfe0ff07f 2050#define MATCH_VMV8RV 0x9e03b057 2051#define MASK_VMV8RV 0xfe0ff07f 2052#define MATCH_VDOTVV 0xe4000057 2053#define MASK_VDOTVV 0xfc00707f 2054#define MATCH_VDOTUVV 0xe0000057 2055#define MASK_VDOTUVV 0xfc00707f 2056#define MATCH_VFDOTVV 0xe4001057 2057#define MASK_VFDOTVV 0xfc00707f 2058/* Svinval instruction. */ 2059#define MATCH_SINVAL_VMA 0x16000073 2060#define MASK_SINVAL_VMA 0xfe007fff 2061#define MATCH_SFENCE_W_INVAL 0x18000073 2062#define MASK_SFENCE_W_INVAL 0xffffffff 2063#define MATCH_SFENCE_INVAL_IR 0x18100073 2064#define MASK_SFENCE_INVAL_IR 0xffffffff 2065#define MATCH_HINVAL_VVMA 0x26000073 2066#define MASK_HINVAL_VVMA 0xfe007fff 2067#define MATCH_HINVAL_GVMA 0x66000073 2068#define MASK_HINVAL_GVMA 0xfe007fff 2069/* Hypervisor instruction. */ 2070#define MATCH_HFENCE_VVMA 0x22000073 2071#define MASK_HFENCE_VVMA 0xfe007fff 2072#define MATCH_HFENCE_GVMA 0x62000073 2073#define MASK_HFENCE_GVMA 0xfe007fff 2074#define MATCH_HLV_B 0x60004073 2075#define MASK_HLV_B 0xfff0707f 2076#define MATCH_HLV_H 0x64004073 2077#define MASK_HLV_H 0xfff0707f 2078#define MATCH_HLV_W 0x68004073 2079#define MASK_HLV_W 0xfff0707f 2080#define MATCH_HLV_D 0x6c004073 2081#define MASK_HLV_D 0xfff0707f 2082#define MATCH_HLV_BU 0x60104073 2083#define MASK_HLV_BU 0xfff0707f 2084#define MATCH_HLV_HU 0x64104073 2085#define MASK_HLV_HU 0xfff0707f 2086#define MATCH_HLV_WU 0x68104073 2087#define MASK_HLV_WU 0xfff0707f 2088#define MATCH_HLVX_HU 0x64304073 2089#define MASK_HLVX_HU 0xfff0707f 2090#define MATCH_HLVX_WU 0x68304073 2091#define MASK_HLVX_WU 0xfff0707f 2092#define MATCH_HSV_B 0x62004073 2093#define MASK_HSV_B 0xfe007fff 2094#define MATCH_HSV_H 0x66004073 2095#define MASK_HSV_H 0xfe007fff 2096#define MATCH_HSV_W 0x6a004073 2097#define MASK_HSV_W 0xfe007fff 2098#define MATCH_HSV_D 0x6e004073 2099#define MASK_HSV_D 0xfe007fff 2100/* Zicbop hint instructions. */ 2101#define MATCH_PREFETCH_I 0x6013 2102#define MASK_PREFETCH_I 0x1f07fff 2103#define MATCH_PREFETCH_R 0x106013 2104#define MASK_PREFETCH_R 0x1f07fff 2105#define MATCH_PREFETCH_W 0x306013 2106#define MASK_PREFETCH_W 0x1f07fff 2107/* Zicbom/Zicboz instructions. */ 2108#define MATCH_CBO_CLEAN 0x10200f 2109#define MASK_CBO_CLEAN 0xfff07fff 2110#define MATCH_CBO_FLUSH 0x20200f 2111#define MASK_CBO_FLUSH 0xfff07fff 2112#define MATCH_CBO_INVAL 0x200f 2113#define MASK_CBO_INVAL 0xfff07fff 2114#define MATCH_CBO_ZERO 0x40200f 2115#define MASK_CBO_ZERO 0xfff07fff 2116/* Unprivileged Counter/Timers CSR addresses. */ 2117#define CSR_CYCLE 0xc00 2118#define CSR_TIME 0xc01 2119#define CSR_INSTRET 0xc02 2120#define CSR_HPMCOUNTER3 0xc03 2121#define CSR_HPMCOUNTER4 0xc04 2122#define CSR_HPMCOUNTER5 0xc05 2123#define CSR_HPMCOUNTER6 0xc06 2124#define CSR_HPMCOUNTER7 0xc07 2125#define CSR_HPMCOUNTER8 0xc08 2126#define CSR_HPMCOUNTER9 0xc09 2127#define CSR_HPMCOUNTER10 0xc0a 2128#define CSR_HPMCOUNTER11 0xc0b 2129#define CSR_HPMCOUNTER12 0xc0c 2130#define CSR_HPMCOUNTER13 0xc0d 2131#define CSR_HPMCOUNTER14 0xc0e 2132#define CSR_HPMCOUNTER15 0xc0f 2133#define CSR_HPMCOUNTER16 0xc10 2134#define CSR_HPMCOUNTER17 0xc11 2135#define CSR_HPMCOUNTER18 0xc12 2136#define CSR_HPMCOUNTER19 0xc13 2137#define CSR_HPMCOUNTER20 0xc14 2138#define CSR_HPMCOUNTER21 0xc15 2139#define CSR_HPMCOUNTER22 0xc16 2140#define CSR_HPMCOUNTER23 0xc17 2141#define CSR_HPMCOUNTER24 0xc18 2142#define CSR_HPMCOUNTER25 0xc19 2143#define CSR_HPMCOUNTER26 0xc1a 2144#define CSR_HPMCOUNTER27 0xc1b 2145#define CSR_HPMCOUNTER28 0xc1c 2146#define CSR_HPMCOUNTER29 0xc1d 2147#define CSR_HPMCOUNTER30 0xc1e 2148#define CSR_HPMCOUNTER31 0xc1f 2149#define CSR_CYCLEH 0xc80 2150#define CSR_TIMEH 0xc81 2151#define CSR_INSTRETH 0xc82 2152#define CSR_HPMCOUNTER3H 0xc83 2153#define CSR_HPMCOUNTER4H 0xc84 2154#define CSR_HPMCOUNTER5H 0xc85 2155#define CSR_HPMCOUNTER6H 0xc86 2156#define CSR_HPMCOUNTER7H 0xc87 2157#define CSR_HPMCOUNTER8H 0xc88 2158#define CSR_HPMCOUNTER9H 0xc89 2159#define CSR_HPMCOUNTER10H 0xc8a 2160#define CSR_HPMCOUNTER11H 0xc8b 2161#define CSR_HPMCOUNTER12H 0xc8c 2162#define CSR_HPMCOUNTER13H 0xc8d 2163#define CSR_HPMCOUNTER14H 0xc8e 2164#define CSR_HPMCOUNTER15H 0xc8f 2165#define CSR_HPMCOUNTER16H 0xc90 2166#define CSR_HPMCOUNTER17H 0xc91 2167#define CSR_HPMCOUNTER18H 0xc92 2168#define CSR_HPMCOUNTER19H 0xc93 2169#define CSR_HPMCOUNTER20H 0xc94 2170#define CSR_HPMCOUNTER21H 0xc95 2171#define CSR_HPMCOUNTER22H 0xc96 2172#define CSR_HPMCOUNTER23H 0xc97 2173#define CSR_HPMCOUNTER24H 0xc98 2174#define CSR_HPMCOUNTER25H 0xc99 2175#define CSR_HPMCOUNTER26H 0xc9a 2176#define CSR_HPMCOUNTER27H 0xc9b 2177#define CSR_HPMCOUNTER28H 0xc9c 2178#define CSR_HPMCOUNTER29H 0xc9d 2179#define CSR_HPMCOUNTER30H 0xc9e 2180#define CSR_HPMCOUNTER31H 0xc9f 2181/* Privileged Supervisor CSR addresses. */ 2182#define CSR_SSTATUS 0x100 2183#define CSR_SIE 0x104 2184#define CSR_STVEC 0x105 2185#define CSR_SCOUNTEREN 0x106 2186#define CSR_SENVCFG 0x10a 2187#define CSR_SSCRATCH 0x140 2188#define CSR_SEPC 0x141 2189#define CSR_SCAUSE 0x142 2190#define CSR_STVAL 0x143 2191#define CSR_SIP 0x144 2192#define CSR_SATP 0x180 2193/* Privileged Machine CSR addresses. */ 2194#define CSR_MVENDORID 0xf11 2195#define CSR_MARCHID 0xf12 2196#define CSR_MIMPID 0xf13 2197#define CSR_MHARTID 0xf14 2198#define CSR_MCONFIGPTR 0xf15 2199#define CSR_MSTATUS 0x300 2200#define CSR_MISA 0x301 2201#define CSR_MEDELEG 0x302 2202#define CSR_MIDELEG 0x303 2203#define CSR_MIE 0x304 2204#define CSR_MTVEC 0x305 2205#define CSR_MCOUNTEREN 0x306 2206#define CSR_MSTATUSH 0x310 2207#define CSR_MSCRATCH 0x340 2208#define CSR_MEPC 0x341 2209#define CSR_MCAUSE 0x342 2210#define CSR_MTVAL 0x343 2211#define CSR_MIP 0x344 2212#define CSR_MTINST 0x34a 2213#define CSR_MTVAL2 0x34b 2214#define CSR_MENVCFG 0x30a 2215#define CSR_MENVCFGH 0x31a 2216#define CSR_MSECCFG 0x747 2217#define CSR_MSECCFGH 0x757 2218#define CSR_PMPCFG0 0x3a0 2219#define CSR_PMPCFG1 0x3a1 2220#define CSR_PMPCFG2 0x3a2 2221#define CSR_PMPCFG3 0x3a3 2222#define CSR_PMPCFG4 0x3a4 2223#define CSR_PMPCFG5 0x3a5 2224#define CSR_PMPCFG6 0x3a6 2225#define CSR_PMPCFG7 0x3a7 2226#define CSR_PMPCFG8 0x3a8 2227#define CSR_PMPCFG9 0x3a9 2228#define CSR_PMPCFG10 0x3aa 2229#define CSR_PMPCFG11 0x3ab 2230#define CSR_PMPCFG12 0x3ac 2231#define CSR_PMPCFG13 0x3ad 2232#define CSR_PMPCFG14 0x3ae 2233#define CSR_PMPCFG15 0x3af 2234#define CSR_PMPADDR0 0x3b0 2235#define CSR_PMPADDR1 0x3b1 2236#define CSR_PMPADDR2 0x3b2 2237#define CSR_PMPADDR3 0x3b3 2238#define CSR_PMPADDR4 0x3b4 2239#define CSR_PMPADDR5 0x3b5 2240#define CSR_PMPADDR6 0x3b6 2241#define CSR_PMPADDR7 0x3b7 2242#define CSR_PMPADDR8 0x3b8 2243#define CSR_PMPADDR9 0x3b9 2244#define CSR_PMPADDR10 0x3ba 2245#define CSR_PMPADDR11 0x3bb 2246#define CSR_PMPADDR12 0x3bc 2247#define CSR_PMPADDR13 0x3bd 2248#define CSR_PMPADDR14 0x3be 2249#define CSR_PMPADDR15 0x3bf 2250#define CSR_PMPADDR16 0x3c0 2251#define CSR_PMPADDR17 0x3c1 2252#define CSR_PMPADDR18 0x3c2 2253#define CSR_PMPADDR19 0x3c3 2254#define CSR_PMPADDR20 0x3c4 2255#define CSR_PMPADDR21 0x3c5 2256#define CSR_PMPADDR22 0x3c6 2257#define CSR_PMPADDR23 0x3c7 2258#define CSR_PMPADDR24 0x3c8 2259#define CSR_PMPADDR25 0x3c9 2260#define CSR_PMPADDR26 0x3ca 2261#define CSR_PMPADDR27 0x3cb 2262#define CSR_PMPADDR28 0x3cc 2263#define CSR_PMPADDR29 0x3cd 2264#define CSR_PMPADDR30 0x3ce 2265#define CSR_PMPADDR31 0x3cf 2266#define CSR_PMPADDR32 0x3d0 2267#define CSR_PMPADDR33 0x3d1 2268#define CSR_PMPADDR34 0x3d2 2269#define CSR_PMPADDR35 0x3d3 2270#define CSR_PMPADDR36 0x3d4 2271#define CSR_PMPADDR37 0x3d5 2272#define CSR_PMPADDR38 0x3d6 2273#define CSR_PMPADDR39 0x3d7 2274#define CSR_PMPADDR40 0x3d8 2275#define CSR_PMPADDR41 0x3d9 2276#define CSR_PMPADDR42 0x3da 2277#define CSR_PMPADDR43 0x3db 2278#define CSR_PMPADDR44 0x3dc 2279#define CSR_PMPADDR45 0x3dd 2280#define CSR_PMPADDR46 0x3de 2281#define CSR_PMPADDR47 0x3df 2282#define CSR_PMPADDR48 0x3e0 2283#define CSR_PMPADDR49 0x3e1 2284#define CSR_PMPADDR50 0x3e2 2285#define CSR_PMPADDR51 0x3e3 2286#define CSR_PMPADDR52 0x3e4 2287#define CSR_PMPADDR53 0x3e5 2288#define CSR_PMPADDR54 0x3e6 2289#define CSR_PMPADDR55 0x3e7 2290#define CSR_PMPADDR56 0x3e8 2291#define CSR_PMPADDR57 0x3e9 2292#define CSR_PMPADDR58 0x3ea 2293#define CSR_PMPADDR59 0x3eb 2294#define CSR_PMPADDR60 0x3ec 2295#define CSR_PMPADDR61 0x3ed 2296#define CSR_PMPADDR62 0x3ee 2297#define CSR_PMPADDR63 0x3ef 2298#define CSR_MCYCLE 0xb00 2299#define CSR_MINSTRET 0xb02 2300#define CSR_MHPMCOUNTER3 0xb03 2301#define CSR_MHPMCOUNTER4 0xb04 2302#define CSR_MHPMCOUNTER5 0xb05 2303#define CSR_MHPMCOUNTER6 0xb06 2304#define CSR_MHPMCOUNTER7 0xb07 2305#define CSR_MHPMCOUNTER8 0xb08 2306#define CSR_MHPMCOUNTER9 0xb09 2307#define CSR_MHPMCOUNTER10 0xb0a 2308#define CSR_MHPMCOUNTER11 0xb0b 2309#define CSR_MHPMCOUNTER12 0xb0c 2310#define CSR_MHPMCOUNTER13 0xb0d 2311#define CSR_MHPMCOUNTER14 0xb0e 2312#define CSR_MHPMCOUNTER15 0xb0f 2313#define CSR_MHPMCOUNTER16 0xb10 2314#define CSR_MHPMCOUNTER17 0xb11 2315#define CSR_MHPMCOUNTER18 0xb12 2316#define CSR_MHPMCOUNTER19 0xb13 2317#define CSR_MHPMCOUNTER20 0xb14 2318#define CSR_MHPMCOUNTER21 0xb15 2319#define CSR_MHPMCOUNTER22 0xb16 2320#define CSR_MHPMCOUNTER23 0xb17 2321#define CSR_MHPMCOUNTER24 0xb18 2322#define CSR_MHPMCOUNTER25 0xb19 2323#define CSR_MHPMCOUNTER26 0xb1a 2324#define CSR_MHPMCOUNTER27 0xb1b 2325#define CSR_MHPMCOUNTER28 0xb1c 2326#define CSR_MHPMCOUNTER29 0xb1d 2327#define CSR_MHPMCOUNTER30 0xb1e 2328#define CSR_MHPMCOUNTER31 0xb1f 2329#define CSR_MCYCLEH 0xb80 2330#define CSR_MINSTRETH 0xb82 2331#define CSR_MHPMCOUNTER3H 0xb83 2332#define CSR_MHPMCOUNTER4H 0xb84 2333#define CSR_MHPMCOUNTER5H 0xb85 2334#define CSR_MHPMCOUNTER6H 0xb86 2335#define CSR_MHPMCOUNTER7H 0xb87 2336#define CSR_MHPMCOUNTER8H 0xb88 2337#define CSR_MHPMCOUNTER9H 0xb89 2338#define CSR_MHPMCOUNTER10H 0xb8a 2339#define CSR_MHPMCOUNTER11H 0xb8b 2340#define CSR_MHPMCOUNTER12H 0xb8c 2341#define CSR_MHPMCOUNTER13H 0xb8d 2342#define CSR_MHPMCOUNTER14H 0xb8e 2343#define CSR_MHPMCOUNTER15H 0xb8f 2344#define CSR_MHPMCOUNTER16H 0xb90 2345#define CSR_MHPMCOUNTER17H 0xb91 2346#define CSR_MHPMCOUNTER18H 0xb92 2347#define CSR_MHPMCOUNTER19H 0xb93 2348#define CSR_MHPMCOUNTER20H 0xb94 2349#define CSR_MHPMCOUNTER21H 0xb95 2350#define CSR_MHPMCOUNTER22H 0xb96 2351#define CSR_MHPMCOUNTER23H 0xb97 2352#define CSR_MHPMCOUNTER24H 0xb98 2353#define CSR_MHPMCOUNTER25H 0xb99 2354#define CSR_MHPMCOUNTER26H 0xb9a 2355#define CSR_MHPMCOUNTER27H 0xb9b 2356#define CSR_MHPMCOUNTER28H 0xb9c 2357#define CSR_MHPMCOUNTER29H 0xb9d 2358#define CSR_MHPMCOUNTER30H 0xb9e 2359#define CSR_MHPMCOUNTER31H 0xb9f 2360#define CSR_MCOUNTINHIBIT 0x320 2361#define CSR_MHPMEVENT3 0x323 2362#define CSR_MHPMEVENT4 0x324 2363#define CSR_MHPMEVENT5 0x325 2364#define CSR_MHPMEVENT6 0x326 2365#define CSR_MHPMEVENT7 0x327 2366#define CSR_MHPMEVENT8 0x328 2367#define CSR_MHPMEVENT9 0x329 2368#define CSR_MHPMEVENT10 0x32a 2369#define CSR_MHPMEVENT11 0x32b 2370#define CSR_MHPMEVENT12 0x32c 2371#define CSR_MHPMEVENT13 0x32d 2372#define CSR_MHPMEVENT14 0x32e 2373#define CSR_MHPMEVENT15 0x32f 2374#define CSR_MHPMEVENT16 0x330 2375#define CSR_MHPMEVENT17 0x331 2376#define CSR_MHPMEVENT18 0x332 2377#define CSR_MHPMEVENT19 0x333 2378#define CSR_MHPMEVENT20 0x334 2379#define CSR_MHPMEVENT21 0x335 2380#define CSR_MHPMEVENT22 0x336 2381#define CSR_MHPMEVENT23 0x337 2382#define CSR_MHPMEVENT24 0x338 2383#define CSR_MHPMEVENT25 0x339 2384#define CSR_MHPMEVENT26 0x33a 2385#define CSR_MHPMEVENT27 0x33b 2386#define CSR_MHPMEVENT28 0x33c 2387#define CSR_MHPMEVENT29 0x33d 2388#define CSR_MHPMEVENT30 0x33e 2389#define CSR_MHPMEVENT31 0x33f 2390/* Privileged Hypervisor CSR addresses. */ 2391#define CSR_HSTATUS 0x600 2392#define CSR_HEDELEG 0x602 2393#define CSR_HIDELEG 0x603 2394#define CSR_HIE 0x604 2395#define CSR_HCOUNTEREN 0x606 2396#define CSR_HGEIE 0x607 2397#define CSR_HTVAL 0x643 2398#define CSR_HIP 0x644 2399#define CSR_HVIP 0x645 2400#define CSR_HTINST 0x64a 2401#define CSR_HGEIP 0xe12 2402#define CSR_HENVCFG 0x60a 2403#define CSR_HENVCFGH 0x61a 2404#define CSR_HGATP 0x680 2405#define CSR_HTIMEDELTA 0x605 2406#define CSR_HTIMEDELTAH 0x615 2407#define CSR_VSSTATUS 0x200 2408#define CSR_VSIE 0x204 2409#define CSR_VSTVEC 0x205 2410#define CSR_VSSCRATCH 0x240 2411#define CSR_VSEPC 0x241 2412#define CSR_VSCAUSE 0x242 2413#define CSR_VSTVAL 0x243 2414#define CSR_VSIP 0x244 2415#define CSR_VSATP 0x280 2416/* Droppped CSR addresses. */ 2417#define CSR_MBASE 0x380 2418#define CSR_MBOUND 0x381 2419#define CSR_MIBASE 0x382 2420#define CSR_MIBOUND 0x383 2421#define CSR_MDBASE 0x384 2422#define CSR_MDBOUND 0x385 2423#define CSR_MSCOUNTEREN 0x321 2424#define CSR_MHCOUNTEREN 0x322 2425#define CSR_USTATUS 0x0 2426#define CSR_UIE 0x4 2427#define CSR_UTVEC 0x5 2428#define CSR_USCRATCH 0x40 2429#define CSR_UEPC 0x41 2430#define CSR_UCAUSE 0x42 2431#define CSR_UTVAL 0x43 2432#define CSR_UIP 0x44 2433#define CSR_SEDELEG 0x102 2434#define CSR_SIDELEG 0x103 2435/* Smstateen extension */ 2436#define CSR_MSTATEEN0 0x30c 2437#define CSR_MSTATEEN1 0x30d 2438#define CSR_MSTATEEN2 0x30e 2439#define CSR_MSTATEEN3 0x30f 2440#define CSR_SSTATEEN0 0x10c 2441#define CSR_SSTATEEN1 0x10d 2442#define CSR_SSTATEEN2 0x10e 2443#define CSR_SSTATEEN3 0x10f 2444#define CSR_HSTATEEN0 0x60c 2445#define CSR_HSTATEEN1 0x60d 2446#define CSR_HSTATEEN2 0x60e 2447#define CSR_HSTATEEN3 0x60f 2448#define CSR_MSTATEEN0H 0x31c 2449#define CSR_MSTATEEN1H 0x31d 2450#define CSR_MSTATEEN2H 0x31e 2451#define CSR_MSTATEEN3H 0x31f 2452#define CSR_HSTATEEN0H 0x61c 2453#define CSR_HSTATEEN1H 0x61d 2454#define CSR_HSTATEEN2H 0x61e 2455#define CSR_HSTATEEN3H 0x61f 2456/* Sscofpmf extension */ 2457#define CSR_SCOUNTOVF 0xda0 2458#define CSR_MHPMEVENT3H 0x723 2459#define CSR_MHPMEVENT4H 0x724 2460#define CSR_MHPMEVENT5H 0x725 2461#define CSR_MHPMEVENT6H 0x726 2462#define CSR_MHPMEVENT7H 0x727 2463#define CSR_MHPMEVENT8H 0x728 2464#define CSR_MHPMEVENT9H 0x729 2465#define CSR_MHPMEVENT10H 0x72a 2466#define CSR_MHPMEVENT11H 0x72b 2467#define CSR_MHPMEVENT12H 0x72c 2468#define CSR_MHPMEVENT13H 0x72d 2469#define CSR_MHPMEVENT14H 0x72e 2470#define CSR_MHPMEVENT15H 0x72f 2471#define CSR_MHPMEVENT16H 0x730 2472#define CSR_MHPMEVENT17H 0x731 2473#define CSR_MHPMEVENT18H 0x732 2474#define CSR_MHPMEVENT19H 0x733 2475#define CSR_MHPMEVENT20H 0x734 2476#define CSR_MHPMEVENT21H 0x735 2477#define CSR_MHPMEVENT22H 0x736 2478#define CSR_MHPMEVENT23H 0x737 2479#define CSR_MHPMEVENT24H 0x738 2480#define CSR_MHPMEVENT25H 0x739 2481#define CSR_MHPMEVENT26H 0x73a 2482#define CSR_MHPMEVENT27H 0x73b 2483#define CSR_MHPMEVENT28H 0x73c 2484#define CSR_MHPMEVENT29H 0x73d 2485#define CSR_MHPMEVENT30H 0x73e 2486#define CSR_MHPMEVENT31H 0x73f 2487/* Sstc extension */ 2488#define CSR_STIMECMP 0x14d 2489#define CSR_STIMECMPH 0x15d 2490#define CSR_VSTIMECMP 0x24d 2491#define CSR_VSTIMECMPH 0x25d 2492/* Unprivileged Floating-Point CSR addresses. */ 2493#define CSR_FFLAGS 0x1 2494#define CSR_FRM 0x2 2495#define CSR_FCSR 0x3 2496/* Unprivileged Debug CSR addresses. */ 2497#define CSR_DCSR 0x7b0 2498#define CSR_DPC 0x7b1 2499#define CSR_DSCRATCH0 0x7b2 2500#define CSR_DSCRATCH1 0x7b3 2501#define CSR_TSELECT 0x7a0 2502#define CSR_TDATA1 0x7a1 2503#define CSR_TDATA2 0x7a2 2504#define CSR_TDATA3 0x7a3 2505#define CSR_TINFO 0x7a4 2506#define CSR_TCONTROL 0x7a5 2507#define CSR_HCONTEXT 0x6a8 2508#define CSR_SCONTEXT 0x5a8 2509#define CSR_MCONTEXT 0x7a8 2510#define CSR_MSCONTEXT 0x7aa 2511/* Unprivileged Scalar Crypto CSR addresses. */ 2512#define CSR_SEED 0x015 2513/* Unprivileged Vector CSR addresses. */ 2514#define CSR_VSTART 0x008 2515#define CSR_VXSAT 0x009 2516#define CSR_VXRM 0x00a 2517#define CSR_VCSR 0x00f 2518#define CSR_VL 0xc20 2519#define CSR_VTYPE 0xc21 2520#define CSR_VLENB 0xc22 2521#endif /* RISCV_ENCODING_H */ 2522#ifdef DECLARE_INSN 2523DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) 2524DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) 2525DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) 2526DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) 2527DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) 2528DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) 2529DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) 2530DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) 2531DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) 2532DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) 2533DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) 2534DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) 2535DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) 2536DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) 2537DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) 2538DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) 2539DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) 2540DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) 2541DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) 2542DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 2543DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 2544DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 2545DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 2546DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 2547DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 2548DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 2549DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 2550DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 2551DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 2552DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 2553DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 2554DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 2555DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 2556DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 2557DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 2558DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 2559DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 2560DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 2561DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 2562DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 2563DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 2564DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 2565DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 2566DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 2567DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 2568DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 2569DECLARE_INSN(or, MATCH_OR, MASK_OR) 2570DECLARE_INSN(and, MATCH_AND, MASK_AND) 2571DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 2572DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 2573DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 2574DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 2575DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 2576DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 2577DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 2578DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 2579DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 2580DECLARE_INSN(lb, MATCH_LB, MASK_LB) 2581DECLARE_INSN(lh, MATCH_LH, MASK_LH) 2582DECLARE_INSN(lw, MATCH_LW, MASK_LW) 2583DECLARE_INSN(ld, MATCH_LD, MASK_LD) 2584DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 2585DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 2586DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 2587DECLARE_INSN(sb, MATCH_SB, MASK_SB) 2588DECLARE_INSN(sh, MATCH_SH, MASK_SH) 2589DECLARE_INSN(sw, MATCH_SW, MASK_SW) 2590DECLARE_INSN(sd, MATCH_SD, MASK_SD) 2591DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) 2592DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 2593DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 2594DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 2595DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 2596DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 2597DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 2598DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 2599DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 2600DECLARE_INSN(rem, MATCH_REM, MASK_REM) 2601DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 2602DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 2603DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 2604DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 2605DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 2606DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 2607DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 2608DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 2609DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 2610DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 2611DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 2612DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 2613DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 2614DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 2615DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 2616DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 2617DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 2618DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 2619DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 2620DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 2621DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 2622DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 2623DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 2624DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 2625DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 2626DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 2627DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 2628DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 2629DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 2630DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 2631DECLARE_INSN(uret, MATCH_URET, MASK_URET) 2632DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 2633DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) 2634DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 2635DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 2636DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) 2637DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 2638DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 2639DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 2640DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 2641DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 2642DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 2643DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 2644DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 2645DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 2646DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 2647DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 2648DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 2649DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 2650DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 2651DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 2652DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 2653DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 2654DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 2655DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 2656DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 2657DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 2658DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 2659DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 2660DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 2661DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 2662DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 2663DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 2664DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 2665DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 2666DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 2667DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 2668DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 2669DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 2670DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 2671DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 2672DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 2673DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 2674DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 2675DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 2676DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 2677DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 2678DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 2679DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 2680DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 2681DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 2682DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 2683DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 2684DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 2685DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 2686DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 2687DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 2688DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 2689DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 2690DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 2691DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 2692DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 2693DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 2694DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 2695DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 2696DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 2697DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 2698DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 2699DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 2700DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 2701DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 2702DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 2703DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 2704DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 2705DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 2706DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 2707DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 2708DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 2709DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 2710DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 2711DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 2712DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 2713DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 2714DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 2715DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 2716DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 2717DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 2718DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 2719DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 2720DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 2721DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) 2722DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) 2723DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) 2724DECLARE_INSN(min, MATCH_MIN, MASK_MIN) 2725DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) 2726DECLARE_INSN(max, MATCH_MAX, MASK_MAX) 2727DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) 2728DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) 2729DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) 2730DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) 2731DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) 2732DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) 2733DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) 2734DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) 2735DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) 2736DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) 2737DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) 2738DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) 2739DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) 2740DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) 2741DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) 2742DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) 2743DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) 2744DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) 2745DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) 2746DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) 2747DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) 2748DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) 2749DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) 2750DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) 2751DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) 2752DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) 2753DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) 2754DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) 2755DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) 2756DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4) 2757DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8) 2758DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) 2759DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) 2760DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) 2761DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) 2762DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) 2763DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) 2764DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) 2765DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) 2766DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 2767DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 2768DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 2769DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 2770DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 2771DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 2772DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 2773DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 2774DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 2775DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 2776DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 2777DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 2778DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 2779DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 2780DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 2781DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 2782DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 2783DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 2784DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 2785DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 2786DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 2787DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 2788DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 2789DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 2790DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 2791DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 2792DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 2793DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 2794DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 2795DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 2796DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 2797DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 2798DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 2799DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 2800DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 2801DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 2802DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 2803DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 2804DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 2805DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 2806DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 2807DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 2808DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 2809DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 2810DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 2811DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 2812DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 2813DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 2814DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 2815DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 2816DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 2817DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 2818DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 2819DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 2820DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 2821DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 2822DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 2823DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 2824DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 2825DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 2826DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA) 2827DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL) 2828DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR) 2829DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA) 2830DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA) 2831DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) 2832DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) 2833DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) 2834DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) 2835DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) 2836DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) 2837DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) 2838DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) 2839DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) 2840DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) 2841DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) 2842DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) 2843DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) 2844DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) 2845DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) 2846/* Zicbop instructions. */ 2847DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R); 2848DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W); 2849DECLARE_INSN(prefetch_i, MATCH_PREFETCH_I, MASK_PREFETCH_I); 2850/* Zicbom/Zicboz instructions. */ 2851DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN); 2852DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH); 2853DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL); 2854DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO); 2855#endif /* DECLARE_INSN */ 2856#ifdef DECLARE_CSR 2857/* Unprivileged Counter/Timers CSRs. */ 2858DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2859DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2860DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2861DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2862DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2863DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2864DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2865DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2866DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2867DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2868DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2869DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2870DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2871DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2872DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2873DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2874DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2875DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2876DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2877DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2878DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2879DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2880DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2881DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2882DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2883DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2884DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2885DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2886DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2887DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2888DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2889DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2890DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2891DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2892DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2893DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2894DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2895DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2896DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2897DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2898DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2899DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2900DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2901DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2902DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2903DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2904DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2905DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2906DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2907DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2908DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2909DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2910DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2911DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2912DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2913DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2914DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2915DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2916DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2917DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2918DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2919DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2920DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2921DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2922/* Privileged Supervisor CSRs. */ 2923DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2924DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2925DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2926DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2927DECLARE_CSR(senvcfg, CSR_SENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2928DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2929DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2930DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2931DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2932DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2933DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2934/* Privileged Machine CSRs. */ 2935DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2936DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2937DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2938DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2939DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2940DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2941DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2942DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2943DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2944DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2945DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2946DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2947DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2948DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2949DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2950DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2951DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2952DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 2953DECLARE_CSR(mtinst, CSR_MTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2954DECLARE_CSR(mtval2, CSR_MTVAL2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2955DECLARE_CSR(menvcfg, CSR_MENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2956DECLARE_CSR(menvcfgh, CSR_MENVCFGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2957DECLARE_CSR(mseccfg, CSR_MSECCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2958DECLARE_CSR(mseccfgh, CSR_MSECCFGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2959DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2960DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2961DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2962DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2963DECLARE_CSR(pmpcfg4, CSR_PMPCFG4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2964DECLARE_CSR(pmpcfg5, CSR_PMPCFG5, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2965DECLARE_CSR(pmpcfg6, CSR_PMPCFG6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2966DECLARE_CSR(pmpcfg7, CSR_PMPCFG7, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2967DECLARE_CSR(pmpcfg8, CSR_PMPCFG8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2968DECLARE_CSR(pmpcfg9, CSR_PMPCFG9, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2969DECLARE_CSR(pmpcfg10, CSR_PMPCFG10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2970DECLARE_CSR(pmpcfg11, CSR_PMPCFG11, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2971DECLARE_CSR(pmpcfg12, CSR_PMPCFG12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2972DECLARE_CSR(pmpcfg13, CSR_PMPCFG13, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2973DECLARE_CSR(pmpcfg14, CSR_PMPCFG14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2974DECLARE_CSR(pmpcfg15, CSR_PMPCFG15, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2975DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2976DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2977DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2978DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2979DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2980DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2981DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2982DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2983DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2984DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2985DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2986DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2987DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2988DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2989DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2990DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) 2991DECLARE_CSR(pmpaddr16, CSR_PMPADDR16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2992DECLARE_CSR(pmpaddr17, CSR_PMPADDR17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2993DECLARE_CSR(pmpaddr18, CSR_PMPADDR18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2994DECLARE_CSR(pmpaddr19, CSR_PMPADDR19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2995DECLARE_CSR(pmpaddr20, CSR_PMPADDR20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2996DECLARE_CSR(pmpaddr21, CSR_PMPADDR21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2997DECLARE_CSR(pmpaddr22, CSR_PMPADDR22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2998DECLARE_CSR(pmpaddr23, CSR_PMPADDR23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 2999DECLARE_CSR(pmpaddr24, CSR_PMPADDR24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3000DECLARE_CSR(pmpaddr25, CSR_PMPADDR25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3001DECLARE_CSR(pmpaddr26, CSR_PMPADDR26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3002DECLARE_CSR(pmpaddr27, CSR_PMPADDR27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3003DECLARE_CSR(pmpaddr28, CSR_PMPADDR28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3004DECLARE_CSR(pmpaddr29, CSR_PMPADDR29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3005DECLARE_CSR(pmpaddr30, CSR_PMPADDR30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3006DECLARE_CSR(pmpaddr31, CSR_PMPADDR31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3007DECLARE_CSR(pmpaddr32, CSR_PMPADDR32, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3008DECLARE_CSR(pmpaddr33, CSR_PMPADDR33, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3009DECLARE_CSR(pmpaddr34, CSR_PMPADDR34, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3010DECLARE_CSR(pmpaddr35, CSR_PMPADDR35, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3011DECLARE_CSR(pmpaddr36, CSR_PMPADDR36, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3012DECLARE_CSR(pmpaddr37, CSR_PMPADDR37, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3013DECLARE_CSR(pmpaddr38, CSR_PMPADDR38, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3014DECLARE_CSR(pmpaddr39, CSR_PMPADDR39, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3015DECLARE_CSR(pmpaddr40, CSR_PMPADDR40, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3016DECLARE_CSR(pmpaddr41, CSR_PMPADDR41, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3017DECLARE_CSR(pmpaddr42, CSR_PMPADDR42, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3018DECLARE_CSR(pmpaddr43, CSR_PMPADDR43, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3019DECLARE_CSR(pmpaddr44, CSR_PMPADDR44, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3020DECLARE_CSR(pmpaddr45, CSR_PMPADDR45, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3021DECLARE_CSR(pmpaddr46, CSR_PMPADDR46, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3022DECLARE_CSR(pmpaddr47, CSR_PMPADDR47, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3023DECLARE_CSR(pmpaddr48, CSR_PMPADDR48, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3024DECLARE_CSR(pmpaddr49, CSR_PMPADDR49, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3025DECLARE_CSR(pmpaddr50, CSR_PMPADDR50, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3026DECLARE_CSR(pmpaddr51, CSR_PMPADDR51, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3027DECLARE_CSR(pmpaddr52, CSR_PMPADDR52, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3028DECLARE_CSR(pmpaddr53, CSR_PMPADDR53, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3029DECLARE_CSR(pmpaddr54, CSR_PMPADDR54, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3030DECLARE_CSR(pmpaddr55, CSR_PMPADDR55, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3031DECLARE_CSR(pmpaddr56, CSR_PMPADDR56, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3032DECLARE_CSR(pmpaddr57, CSR_PMPADDR57, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3033DECLARE_CSR(pmpaddr58, CSR_PMPADDR58, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3034DECLARE_CSR(pmpaddr59, CSR_PMPADDR59, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3035DECLARE_CSR(pmpaddr60, CSR_PMPADDR60, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3036DECLARE_CSR(pmpaddr61, CSR_PMPADDR61, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3037DECLARE_CSR(pmpaddr62, CSR_PMPADDR62, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3038DECLARE_CSR(pmpaddr63, CSR_PMPADDR63, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT) 3039DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3040DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3041DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3042DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3043DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3044DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3045DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3046DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3047DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3048DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3049DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3050DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3051DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3052DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3053DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3054DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3055DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3056DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3057DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3058DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3059DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3060DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3061DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3062DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3063DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3064DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3065DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3066DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3067DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3068DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3069DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3070DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3071DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3072DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3073DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3074DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3075DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3076DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3077DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3078DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3079DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3080DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3081DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3082DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3083DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3084DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3085DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3086DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3087DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3088DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3089DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3090DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3091DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3092DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3093DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3094DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3095DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3096DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3097DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3098DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3099DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3100DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3101DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT) 3102DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3103DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3104DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3105DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3106DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3107DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3108DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3109DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3110DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3111DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3112DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3113DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3114DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3115DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3116DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3117DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3118DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3119DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3120DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3121DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3122DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3123DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3124DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3125DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3126DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3127DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3128DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3129DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3130DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT) 3131/* Privileged Hypervisor CSRs. */ 3132DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3133DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3134DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3135DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3136DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3137DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3138DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3139DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3140DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3141DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3142DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3143DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3144DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3145DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3146DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3147DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3148DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3149DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3150DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3151DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3152DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3153DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3154DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3155DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3156DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3157/* Smstateen extension */ 3158DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3159DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3160DECLARE_CSR(mstateen2, CSR_MSTATEEN2, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3161DECLARE_CSR(mstateen3, CSR_MSTATEEN3, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3162DECLARE_CSR(sstateen0, CSR_SSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3163DECLARE_CSR(sstateen1, CSR_SSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3164DECLARE_CSR(sstateen2, CSR_SSTATEEN2, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3165DECLARE_CSR(sstateen3, CSR_SSTATEEN3, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3166DECLARE_CSR(hstateen0, CSR_HSTATEEN0, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3167DECLARE_CSR(hstateen1, CSR_HSTATEEN1, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3168DECLARE_CSR(hstateen2, CSR_HSTATEEN2, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3169DECLARE_CSR(hstateen3, CSR_HSTATEEN3, CSR_CLASS_SMSTATEEN_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3170DECLARE_CSR(mstateen0h, CSR_MSTATEEN0H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3171DECLARE_CSR(mstateen1h, CSR_MSTATEEN1H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3172DECLARE_CSR(mstateen2h, CSR_MSTATEEN2H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3173DECLARE_CSR(mstateen3h, CSR_MSTATEEN3H, CSR_CLASS_SMSTATEEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3174DECLARE_CSR(hstateen0h, CSR_HSTATEEN0H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3175DECLARE_CSR(hstateen1h, CSR_HSTATEEN1H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3176DECLARE_CSR(hstateen2h, CSR_HSTATEEN2H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3177DECLARE_CSR(hstateen3h, CSR_HSTATEEN3H, CSR_CLASS_SMSTATEEN_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3178/* Sscofpmf extension */ 3179DECLARE_CSR(scountovf, CSR_SCOUNTOVF, CSR_CLASS_SSCOFPMF, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3180DECLARE_CSR(mhpmevent3h, CSR_MHPMEVENT3H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3181DECLARE_CSR(mhpmevent4h, CSR_MHPMEVENT4H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3182DECLARE_CSR(mhpmevent5h, CSR_MHPMEVENT5H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3183DECLARE_CSR(mhpmevent6h, CSR_MHPMEVENT6H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3184DECLARE_CSR(mhpmevent7h, CSR_MHPMEVENT7H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3185DECLARE_CSR(mhpmevent8h, CSR_MHPMEVENT8H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3186DECLARE_CSR(mhpmevent9h, CSR_MHPMEVENT9H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3187DECLARE_CSR(mhpmevent10h, CSR_MHPMEVENT10H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3188DECLARE_CSR(mhpmevent11h, CSR_MHPMEVENT11H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3189DECLARE_CSR(mhpmevent12h, CSR_MHPMEVENT12H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3190DECLARE_CSR(mhpmevent13h, CSR_MHPMEVENT13H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3191DECLARE_CSR(mhpmevent14h, CSR_MHPMEVENT14H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3192DECLARE_CSR(mhpmevent15h, CSR_MHPMEVENT15H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3193DECLARE_CSR(mhpmevent16h, CSR_MHPMEVENT16H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3194DECLARE_CSR(mhpmevent17h, CSR_MHPMEVENT17H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3195DECLARE_CSR(mhpmevent18h, CSR_MHPMEVENT18H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3196DECLARE_CSR(mhpmevent19h, CSR_MHPMEVENT19H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3197DECLARE_CSR(mhpmevent20h, CSR_MHPMEVENT20H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3198DECLARE_CSR(mhpmevent21h, CSR_MHPMEVENT21H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3199DECLARE_CSR(mhpmevent22h, CSR_MHPMEVENT22H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3200DECLARE_CSR(mhpmevent23h, CSR_MHPMEVENT23H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3201DECLARE_CSR(mhpmevent24h, CSR_MHPMEVENT24H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3202DECLARE_CSR(mhpmevent25h, CSR_MHPMEVENT25H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3203DECLARE_CSR(mhpmevent26h, CSR_MHPMEVENT26H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3204DECLARE_CSR(mhpmevent27h, CSR_MHPMEVENT27H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3205DECLARE_CSR(mhpmevent28h, CSR_MHPMEVENT28H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3206DECLARE_CSR(mhpmevent29h, CSR_MHPMEVENT29H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3207DECLARE_CSR(mhpmevent30h, CSR_MHPMEVENT30H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3208DECLARE_CSR(mhpmevent31h, CSR_MHPMEVENT31H, CSR_CLASS_SSCOFPMF_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3209/* Sstc extension */ 3210DECLARE_CSR(stimecmp, CSR_STIMECMP, CSR_CLASS_SSTC, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3211DECLARE_CSR(stimecmph, CSR_STIMECMPH, CSR_CLASS_SSTC_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3212DECLARE_CSR(vstimecmp, CSR_VSTIMECMP, CSR_CLASS_SSTC_AND_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3213DECLARE_CSR(vstimecmph, CSR_VSTIMECMPH, CSR_CLASS_SSTC_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3214/* Dropped CSRs. */ 3215DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3216DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3217DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3218DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3219DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3220DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3221DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3222DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3223DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3224DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3225DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3226DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3227DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3228DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3229DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) 3230DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3231DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3232DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P12) 3233/* Unprivileged Floating-Point CSRs. */ 3234DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3235DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3236DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3237/* Unprivileged Debug CSRs. */ 3238DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3239DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3240DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3241DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3242DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3243DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3244DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3245DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3246DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3247DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3248DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3249DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3250DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3251DECLARE_CSR(mscontext, CSR_MSCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3252/* Unprivileged Scalar Crypto CSRs. */ 3253DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3254/* Unprivileged Vector CSRs. */ 3255DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3256DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3257DECLARE_CSR(vxrm, CSR_VXRM, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3258DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3259DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3260DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3261DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3262#endif /* DECLARE_CSR */ 3263#ifdef DECLARE_CSR_ALIAS 3264DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3265DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3266DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3267DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3268DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10) 3269DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3270DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3271DECLARE_CSR_ALIAS(mcontrol6, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3272DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3273DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3274DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3275DECLARE_CSR_ALIAS(tmexttrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3276DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3277DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) 3278#endif /* DECLARE_CSR_ALIAS */ 3279