1/* tc-xtensa.c -- Assemble Xtensa instructions. 2 Copyright (C) 2003-2022 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21#include "as.h" 22#include <limits.h> 23#include "sb.h" 24#include "safe-ctype.h" 25#include "tc-xtensa.h" 26#include "subsegs.h" 27#include "xtensa-relax.h" 28#include "dwarf2dbg.h" 29#include "xtensa-istack.h" 30#include "xtensa-config.h" 31#include "elf/xtensa.h" 32 33/* Provide default values for new configuration settings. */ 34#ifndef XTHAL_ABI_WINDOWED 35#define XTHAL_ABI_WINDOWED 0 36#endif 37 38#ifndef XTHAL_ABI_CALL0 39#define XTHAL_ABI_CALL0 1 40#endif 41 42#ifndef XTENSA_MARCH_EARLIEST 43#define XTENSA_MARCH_EARLIEST 0 44#endif 45 46#ifndef uint32 47#define uint32 unsigned int 48#endif 49#ifndef int32 50#define int32 signed int 51#endif 52 53/* Notes: 54 55 Naming conventions (used somewhat inconsistently): 56 The xtensa_ functions are exported 57 The xg_ functions are internal 58 59 We also have a couple of different extensibility mechanisms. 60 1) The idiom replacement: 61 This is used when a line is first parsed to 62 replace an instruction pattern with another instruction 63 It is currently limited to replacements of instructions 64 with constant operands. 65 2) The xtensa-relax.c mechanism that has stronger instruction 66 replacement patterns. When an instruction's immediate field 67 does not fit the next instruction sequence is attempted. 68 In addition, "narrow" opcodes are supported this way. */ 69 70 71/* Define characters with special meanings to GAS. */ 72const char comment_chars[] = "#"; 73const char line_comment_chars[] = "#"; 74const char line_separator_chars[] = ";"; 75const char EXP_CHARS[] = "eE"; 76const char FLT_CHARS[] = "rRsSfFdDxXpP"; 77 78 79/* Flags to indicate whether the hardware supports the density and 80 absolute literals options. */ 81 82bool density_supported; 83bool absolute_literals_supported; 84 85static unsigned microarch_earliest; 86 87static vliw_insn cur_vinsn; 88 89unsigned xtensa_num_pipe_stages; 90unsigned xtensa_fetch_width; 91 92static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; 93 94/* Some functions are only valid in the front end. This variable 95 allows us to assert that we haven't crossed over into the 96 back end. */ 97static bool past_xtensa_end = false; 98 99/* Flags for properties of the last instruction in a segment. */ 100#define FLAG_IS_A0_WRITER 0x1 101#define FLAG_IS_BAD_LOOPEND 0x2 102 103 104/* We define a special segment names ".literal" to place literals 105 into. The .fini and .init sections are special because they 106 contain code that is moved together by the linker. We give them 107 their own special .fini.literal and .init.literal sections. */ 108 109#define LITERAL_SECTION_NAME xtensa_section_rename (".literal") 110#define LIT4_SECTION_NAME xtensa_section_rename (".lit4") 111#define INIT_SECTION_NAME xtensa_section_rename (".init") 112#define FINI_SECTION_NAME xtensa_section_rename (".fini") 113 114 115/* This type is used for the directive_stack to keep track of the 116 state of the literal collection pools. If lit_prefix is set, it is 117 used to determine the literal section names; otherwise, the literal 118 sections are determined based on the current text section. The 119 lit_seg and lit4_seg fields cache these literal sections, with the 120 current_text_seg field used a tag to indicate whether the cached 121 values are valid. */ 122 123typedef struct lit_state_struct 124{ 125 char *lit_prefix; 126 segT current_text_seg; 127 segT lit_seg; 128 segT lit4_seg; 129} lit_state; 130 131static lit_state default_lit_sections; 132 133 134/* We keep a list of literal segments. The seg_list type is the node 135 for this list. The literal_head pointer is the head of the list, 136 with the literal_head_h dummy node at the start. */ 137 138typedef struct seg_list_struct 139{ 140 struct seg_list_struct *next; 141 segT seg; 142} seg_list; 143 144static seg_list literal_head_h; 145static seg_list *literal_head = &literal_head_h; 146 147 148/* Lists of symbols. We keep a list of symbols that label the current 149 instruction, so that we can adjust the symbols when inserting alignment 150 for various instructions. We also keep a list of all the symbols on 151 literals, so that we can fix up those symbols when the literals are 152 later moved into the text sections. */ 153 154typedef struct sym_list_struct 155{ 156 struct sym_list_struct *next; 157 symbolS *sym; 158} sym_list; 159 160static sym_list *insn_labels = NULL; 161static sym_list *free_insn_labels = NULL; 162static sym_list *saved_insn_labels = NULL; 163 164static sym_list *literal_syms; 165 166 167/* Flags to determine whether to prefer const16 or l32r 168 if both options are available. */ 169int prefer_const16 = 0; 170int prefer_l32r = 0; 171 172/* Global flag to indicate when we are emitting literals. */ 173int generating_literals = 0; 174 175/* The following PROPERTY table definitions are copied from 176 <elf/xtensa.h> and must be kept in sync with the code there. */ 177 178/* Flags in the property tables to specify whether blocks of memory 179 are literals, instructions, data, or unreachable. For 180 instructions, blocks that begin loop targets and branch targets are 181 designated. Blocks that do not allow density, instruction 182 reordering or transformation are also specified. Finally, for 183 branch targets, branch target alignment priority is included. 184 Alignment of the next block is specified in the current block 185 and the size of the current block does not include any fill required 186 to align to the next block. */ 187 188#define XTENSA_PROP_LITERAL 0x00000001 189#define XTENSA_PROP_INSN 0x00000002 190#define XTENSA_PROP_DATA 0x00000004 191#define XTENSA_PROP_UNREACHABLE 0x00000008 192/* Instruction only properties at beginning of code. */ 193#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 194#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 195/* Instruction only properties about code. */ 196#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 197#define XTENSA_PROP_INSN_NO_REORDER 0x00000080 198/* Historically, NO_TRANSFORM was a property of instructions, 199 but it should apply to literals under certain circumstances. */ 200#define XTENSA_PROP_NO_TRANSFORM 0x00000100 201 202/* Branch target alignment information. This transmits information 203 to the linker optimization about the priority of aligning a 204 particular block for branch target alignment: None, low priority, 205 high priority, or required. These only need to be checked in 206 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 207 Common usage is 208 209 switch (GET_XTENSA_PROP_BT_ALIGN (flags)) 210 case XTENSA_PROP_BT_ALIGN_NONE: 211 case XTENSA_PROP_BT_ALIGN_LOW: 212 case XTENSA_PROP_BT_ALIGN_HIGH: 213 case XTENSA_PROP_BT_ALIGN_REQUIRE: 214*/ 215#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 216 217/* No branch target alignment. */ 218#define XTENSA_PROP_BT_ALIGN_NONE 0x0 219/* Low priority branch target alignment. */ 220#define XTENSA_PROP_BT_ALIGN_LOW 0x1 221/* High priority branch target alignment. */ 222#define XTENSA_PROP_BT_ALIGN_HIGH 0x2 223/* Required branch target alignment. */ 224#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 225 226#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 227 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 228 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 229 230 231/* Alignment is specified in the block BEFORE the one that needs 232 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 233 get the required alignment specified as a power of 2. Use 234 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 235 alignment. Be careful of side effects since the SET will evaluate 236 flags twice. Also, note that the SIZE of a block in the property 237 table does not include the alignment size, so the alignment fill 238 must be calculated to determine if two blocks are contiguous. 239 TEXT_ALIGN is not currently implemented but is a placeholder for a 240 possible future implementation. */ 241 242#define XTENSA_PROP_ALIGN 0x00000800 243 244#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 245 246#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 247 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 248 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 249 250#define XTENSA_PROP_INSN_ABSLIT 0x00020000 251 252 253/* Structure for saving instruction and alignment per-fragment data 254 that will be written to the object file. This structure is 255 equivalent to the actual data that will be written out to the file 256 but is easier to use. We provide a conversion to file flags 257 in frag_flags_to_number. */ 258 259typedef struct frag_flags_struct frag_flags; 260 261struct frag_flags_struct 262{ 263 /* is_literal should only be used after xtensa_move_literals. 264 If you need to check if you are generating a literal fragment, 265 then use the generating_literals global. */ 266 267 unsigned is_literal : 1; 268 unsigned is_insn : 1; 269 unsigned is_data : 1; 270 unsigned is_unreachable : 1; 271 272 /* is_specific_opcode implies no_transform. */ 273 unsigned is_no_transform : 1; 274 275 struct 276 { 277 unsigned is_loop_target : 1; 278 unsigned is_branch_target : 1; /* Branch targets have a priority. */ 279 unsigned bt_align_priority : 2; 280 281 unsigned is_no_density : 1; 282 /* no_longcalls flag does not need to be placed in the object file. */ 283 284 unsigned is_no_reorder : 1; 285 286 /* Uses absolute literal addressing for l32r. */ 287 unsigned is_abslit : 1; 288 } insn; 289 unsigned is_align : 1; 290 unsigned alignment : 5; 291}; 292 293 294/* Structure for saving information about a block of property data 295 for frags that have the same flags. */ 296struct xtensa_block_info_struct 297{ 298 segT sec; 299 bfd_vma offset; 300 size_t size; 301 frag_flags flags; 302 struct xtensa_block_info_struct *next; 303}; 304 305 306/* Structure for saving the current state before emitting literals. */ 307typedef struct emit_state_struct 308{ 309 const char *name; 310 segT now_seg; 311 subsegT now_subseg; 312 int generating_literals; 313} emit_state; 314 315 316/* Opcode placement information */ 317 318typedef unsigned long long bitfield; 319#define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) 320#define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) 321#define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) 322 323#define MAX_FORMATS 32 324 325typedef struct op_placement_info_struct 326{ 327 int num_formats; 328 /* A number describing how restrictive the issue is for this 329 opcode. For example, an opcode that fits lots of different 330 formats has a high freedom, as does an opcode that fits 331 only one format but many slots in that format. The most 332 restrictive is the opcode that fits only one slot in one 333 format. */ 334 int issuef; 335 xtensa_format narrowest; 336 char narrowest_size; 337 char narrowest_slot; 338 339 /* formats is a bitfield with the Nth bit set 340 if the opcode fits in the Nth xtensa_format. */ 341 bitfield formats; 342 343 /* slots[N]'s Mth bit is set if the op fits in the 344 Mth slot of the Nth xtensa_format. */ 345 bitfield slots[MAX_FORMATS]; 346 347 /* A count of the number of slots in a given format 348 an op can fit (i.e., the bitcount of the slot field above). */ 349 char slots_in_format[MAX_FORMATS]; 350 351} op_placement_info, *op_placement_info_table; 352 353op_placement_info_table op_placement_table; 354 355 356/* Extra expression types. */ 357 358#define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ 359#define O_hi16 O_md2 /* use high 16 bits of symbolic value */ 360#define O_lo16 O_md3 /* use low 16 bits of symbolic value */ 361#define O_pcrel O_md4 /* value is a PC-relative offset */ 362#define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ 363#define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ 364#define O_tlscall O_md7 /* TLS_CALL relocation */ 365#define O_tpoff O_md8 /* TPOFF relocation */ 366#define O_dtpoff O_md9 /* DTPOFF relocation */ 367 368struct suffix_reloc_map 369{ 370 const char *suffix; 371 int length; 372 bfd_reloc_code_real_type reloc; 373 operatorT operator; 374}; 375 376#define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } 377 378static struct suffix_reloc_map suffix_relocs[] = 379{ 380 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), 381 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), 382 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), 383 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), 384 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), 385 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), 386 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), 387 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), 388 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), 389}; 390 391 392/* Directives. */ 393 394typedef enum 395{ 396 directive_none = 0, 397 directive_literal, 398 directive_density, 399 directive_transform, 400 directive_freeregs, 401 directive_longcalls, 402 directive_literal_prefix, 403 directive_schedule, 404 directive_absolute_literals, 405 directive_last_directive 406} directiveE; 407 408typedef struct 409{ 410 const char *name; 411 bool can_be_negated; 412} directive_infoS; 413 414const directive_infoS directive_info[] = 415{ 416 { "none", false }, 417 { "literal", false }, 418 { "density", true }, 419 { "transform", true }, 420 { "freeregs", false }, 421 { "longcalls", true }, 422 { "literal_prefix", false }, 423 { "schedule", true }, 424 { "absolute-literals", true } 425}; 426 427bool directive_state[] = 428{ 429 false, /* none */ 430 false, /* literal */ 431 false, /* density */ 432 true, /* transform */ 433 false, /* freeregs */ 434 false, /* longcalls */ 435 false, /* literal_prefix */ 436 false, /* schedule */ 437 false /* absolute_literals */ 438}; 439 440/* A circular list of all potential and actual literal pool locations 441 in a segment. */ 442struct litpool_frag 443{ 444 struct litpool_frag *next; 445 struct litpool_frag *prev; 446 fragS *fragP; 447 addressT addr; 448 short priority; /* 1, 2, or 3 -- 1 is highest */ 449 short original_priority; 450 int literal_count; 451}; 452 453/* Map a segment to its litpool_frag list. */ 454struct litpool_seg 455{ 456 struct litpool_seg *next; 457 asection *seg; 458 struct litpool_frag frag_list; 459 int frag_count; /* since last litpool location */ 460}; 461 462static struct litpool_seg litpool_seg_list; 463 464/* Limit maximal size of auto litpool by half of the j range. */ 465#define MAX_AUTO_POOL_LITERALS 16384 466 467/* Limit maximal size of explicit literal pool by l32r range. */ 468#define MAX_EXPLICIT_POOL_LITERALS 65536 469 470#define MAX_POOL_LITERALS \ 471 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS) 472 473/* Directive functions. */ 474 475static void xtensa_begin_directive (int); 476static void xtensa_end_directive (int); 477static void xtensa_literal_prefix (void); 478static void xtensa_literal_position (int); 479static void xtensa_literal_pseudo (int); 480static void xtensa_frequency_pseudo (int); 481static void xtensa_elf_cons (int); 482static void xtensa_leb128 (int); 483 484/* Parsing and Idiom Translation. */ 485 486static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); 487 488/* Various Other Internal Functions. */ 489 490extern bool xg_is_single_relaxable_insn (TInsn *, TInsn *, bool); 491static bool xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); 492static void xtensa_mark_literal_pool_location (void); 493static addressT get_expanded_loop_offset (xtensa_opcode); 494static fragS *get_literal_pool_location (segT); 495static void set_literal_pool_location (segT, fragS *); 496static void xtensa_set_frag_assembly_state (fragS *); 497static void finish_vinsn (vliw_insn *); 498static bool emit_single_op (TInsn *); 499static int total_frag_text_expansion (fragS *); 500static bool use_trampolines = true; 501static void xtensa_check_frag_count (void); 502static void xtensa_create_trampoline_frag (bool); 503static void xtensa_maybe_create_trampoline_frag (void); 504struct trampoline_frag; 505static int init_trampoline_frag (fragS *); 506static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset); 507static void xtensa_maybe_create_literal_pool_frag (bool, bool); 508static bool auto_litpools = false; 509static int auto_litpool_limit = 0; 510static bool xtensa_is_init_fini (segT seg); 511 512/* Alignment Functions. */ 513 514static int get_text_align_power (unsigned); 515static int get_text_align_max_fill_size (int, bool, bool); 516static int branch_align_power (segT); 517 518/* Helpers for xtensa_relax_frag(). */ 519 520static long relax_frag_add_nop (fragS *); 521 522/* Accessors for additional per-subsegment information. */ 523 524static unsigned get_last_insn_flags (segT, subsegT); 525static void set_last_insn_flags (segT, subsegT, unsigned, bool); 526static float get_subseg_total_freq (segT, subsegT); 527static float get_subseg_target_freq (segT, subsegT); 528static void set_subseg_freq (segT, subsegT, float, float); 529 530/* Segment list functions. */ 531 532static void xtensa_move_literals (void); 533static void xtensa_reorder_segments (void); 534static void xtensa_switch_to_literal_fragment (emit_state *); 535static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); 536static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); 537static void xtensa_restore_emit_state (emit_state *); 538static segT cache_literal_section (bool); 539 540/* op_placement_info functions. */ 541 542static void init_op_placement_info_table (void); 543extern bool opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); 544static int xg_get_single_size (xtensa_opcode); 545static xtensa_format xg_get_single_format (xtensa_opcode); 546static int xg_get_single_slot (xtensa_opcode); 547 548/* TInsn and IStack functions. */ 549 550static bool tinsn_has_symbolic_operands (const TInsn *); 551static bool tinsn_has_invalid_symbolic_operands (const TInsn *); 552static bool tinsn_has_complex_operands (const TInsn *); 553static bool tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); 554static bool tinsn_check_arguments (const TInsn *); 555static void tinsn_from_chars (TInsn *, char *, int); 556static void tinsn_immed_from_frag (TInsn *, fragS *, int); 557static int get_num_stack_text_bytes (IStack *); 558static int get_num_stack_literal_bytes (IStack *); 559static bool tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); 560 561/* vliw_insn functions. */ 562 563static void xg_init_vinsn (vliw_insn *); 564static void xg_copy_vinsn (vliw_insn *, vliw_insn *); 565static void xg_clear_vinsn (vliw_insn *); 566static bool vinsn_has_specific_opcodes (vliw_insn *); 567static void xg_free_vinsn (vliw_insn *); 568static bool vinsn_to_insnbuf 569 (vliw_insn *, char *, fragS *, bool); 570static void vinsn_from_chars (vliw_insn *, char *); 571 572/* Expression Utilities. */ 573 574bool expr_is_const (const expressionS *); 575offsetT get_expr_const (const expressionS *); 576void set_expr_const (expressionS *, offsetT); 577bool expr_is_register (const expressionS *); 578offsetT get_expr_register (const expressionS *); 579void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); 580bool expr_is_equal (expressionS *, expressionS *); 581static void copy_expr (expressionS *, const expressionS *); 582 583/* Section renaming. */ 584 585static void build_section_rename (const char *); 586 587 588/* ISA imported from bfd. */ 589extern xtensa_isa xtensa_default_isa; 590 591extern int target_big_endian; 592 593static xtensa_opcode xtensa_addi_opcode; 594static xtensa_opcode xtensa_addmi_opcode; 595static xtensa_opcode xtensa_call0_opcode; 596static xtensa_opcode xtensa_call4_opcode; 597static xtensa_opcode xtensa_call8_opcode; 598static xtensa_opcode xtensa_call12_opcode; 599static xtensa_opcode xtensa_callx0_opcode; 600static xtensa_opcode xtensa_callx4_opcode; 601static xtensa_opcode xtensa_callx8_opcode; 602static xtensa_opcode xtensa_callx12_opcode; 603static xtensa_opcode xtensa_const16_opcode; 604static xtensa_opcode xtensa_entry_opcode; 605static xtensa_opcode xtensa_extui_opcode; 606static xtensa_opcode xtensa_movi_opcode; 607static xtensa_opcode xtensa_movi_n_opcode; 608static xtensa_opcode xtensa_isync_opcode; 609static xtensa_opcode xtensa_j_opcode; 610static xtensa_opcode xtensa_jx_opcode; 611static xtensa_opcode xtensa_l32r_opcode; 612static xtensa_opcode xtensa_loop_opcode; 613static xtensa_opcode xtensa_loopnez_opcode; 614static xtensa_opcode xtensa_loopgtz_opcode; 615static xtensa_opcode xtensa_nop_opcode; 616static xtensa_opcode xtensa_nop_n_opcode; 617static xtensa_opcode xtensa_or_opcode; 618static xtensa_opcode xtensa_ret_opcode; 619static xtensa_opcode xtensa_ret_n_opcode; 620static xtensa_opcode xtensa_retw_opcode; 621static xtensa_opcode xtensa_retw_n_opcode; 622static xtensa_opcode xtensa_rsr_lcount_opcode; 623static xtensa_opcode xtensa_waiti_opcode; 624static int config_max_slots = 0; 625 626 627/* Command-line Options. */ 628 629bool use_literal_section = true; 630enum flix_level produce_flix = FLIX_ALL; 631static bool align_targets = true; 632static bool warn_unaligned_branch_targets = false; 633static bool has_a0_b_retw = false; 634static bool workaround_a0_b_retw = false; 635static bool workaround_b_j_loop_end = false; 636static bool workaround_short_loop = false; 637static bool maybe_has_short_loop = false; 638static bool workaround_close_loop_end = false; 639static bool maybe_has_close_loop_end = false; 640static bool enforce_three_byte_loop_align = false; 641static bool opt_linkrelax = true; 642 643/* When workaround_short_loops is TRUE, all loops with early exits must 644 have at least 3 instructions. workaround_all_short_loops is a modifier 645 to the workaround_short_loop flag. In addition to the 646 workaround_short_loop actions, all straightline loopgtz and loopnez 647 must have at least 3 instructions. */ 648 649static bool workaround_all_short_loops = false; 650 651/* Generate individual property section for every section. 652 This option is defined in BDF library. */ 653extern bool elf32xtensa_separate_props; 654 655/* Xtensa ABI. 656 This option is defined in BDF library. */ 657extern int elf32xtensa_abi; 658 659static void 660xtensa_setup_hw_workarounds (int earliest, int latest) 661{ 662 if (earliest > latest) 663 as_fatal (_("illegal range of target hardware versions")); 664 665 /* Enable all workarounds for pre-T1050.0 hardware. */ 666 if (earliest < 105000 || latest < 105000) 667 { 668 workaround_a0_b_retw |= true; 669 workaround_b_j_loop_end |= true; 670 workaround_short_loop |= true; 671 workaround_close_loop_end |= true; 672 workaround_all_short_loops |= true; 673 enforce_three_byte_loop_align = true; 674 } 675} 676 677 678enum 679{ 680 option_density = OPTION_MD_BASE, 681 option_no_density, 682 683 option_flix, 684 option_no_generate_flix, 685 option_no_flix, 686 687 option_relax, 688 option_no_relax, 689 690 option_link_relax, 691 option_no_link_relax, 692 693 option_generics, 694 option_no_generics, 695 696 option_transform, 697 option_no_transform, 698 699 option_text_section_literals, 700 option_no_text_section_literals, 701 702 option_absolute_literals, 703 option_no_absolute_literals, 704 705 option_align_targets, 706 option_no_align_targets, 707 708 option_warn_unaligned_targets, 709 710 option_longcalls, 711 option_no_longcalls, 712 713 option_workaround_a0_b_retw, 714 option_no_workaround_a0_b_retw, 715 716 option_workaround_b_j_loop_end, 717 option_no_workaround_b_j_loop_end, 718 719 option_workaround_short_loop, 720 option_no_workaround_short_loop, 721 722 option_workaround_all_short_loops, 723 option_no_workaround_all_short_loops, 724 725 option_workaround_close_loop_end, 726 option_no_workaround_close_loop_end, 727 728 option_no_workarounds, 729 730 option_rename_section_name, 731 732 option_prefer_l32r, 733 option_prefer_const16, 734 735 option_target_hardware, 736 737 option_trampolines, 738 option_no_trampolines, 739 740 option_auto_litpools, 741 option_no_auto_litpools, 742 option_auto_litpool_limit, 743 744 option_separate_props, 745 option_no_separate_props, 746 747 option_abi_windowed, 748 option_abi_call0, 749}; 750 751const char *md_shortopts = ""; 752 753struct option md_longopts[] = 754{ 755 { "density", no_argument, NULL, option_density }, 756 { "no-density", no_argument, NULL, option_no_density }, 757 758 { "flix", no_argument, NULL, option_flix }, 759 { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, 760 { "no-allow-flix", no_argument, NULL, option_no_flix }, 761 762 /* Both "relax" and "generics" are deprecated and treated as equivalent 763 to the "transform" option. */ 764 { "relax", no_argument, NULL, option_relax }, 765 { "no-relax", no_argument, NULL, option_no_relax }, 766 { "generics", no_argument, NULL, option_generics }, 767 { "no-generics", no_argument, NULL, option_no_generics }, 768 769 { "transform", no_argument, NULL, option_transform }, 770 { "no-transform", no_argument, NULL, option_no_transform }, 771 { "text-section-literals", no_argument, NULL, option_text_section_literals }, 772 { "no-text-section-literals", no_argument, NULL, 773 option_no_text_section_literals }, 774 { "absolute-literals", no_argument, NULL, option_absolute_literals }, 775 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, 776 /* This option was changed from -align-target to -target-align 777 because it conflicted with the "-al" option. */ 778 { "target-align", no_argument, NULL, option_align_targets }, 779 { "no-target-align", no_argument, NULL, option_no_align_targets }, 780 { "warn-unaligned-targets", no_argument, NULL, 781 option_warn_unaligned_targets }, 782 { "longcalls", no_argument, NULL, option_longcalls }, 783 { "no-longcalls", no_argument, NULL, option_no_longcalls }, 784 785 { "no-workaround-a0-b-retw", no_argument, NULL, 786 option_no_workaround_a0_b_retw }, 787 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, 788 789 { "no-workaround-b-j-loop-end", no_argument, NULL, 790 option_no_workaround_b_j_loop_end }, 791 { "workaround-b-j-loop-end", no_argument, NULL, 792 option_workaround_b_j_loop_end }, 793 794 { "no-workaround-short-loops", no_argument, NULL, 795 option_no_workaround_short_loop }, 796 { "workaround-short-loops", no_argument, NULL, 797 option_workaround_short_loop }, 798 799 { "no-workaround-all-short-loops", no_argument, NULL, 800 option_no_workaround_all_short_loops }, 801 { "workaround-all-short-loop", no_argument, NULL, 802 option_workaround_all_short_loops }, 803 804 { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, 805 { "prefer-const16", no_argument, NULL, option_prefer_const16 }, 806 807 { "no-workarounds", no_argument, NULL, option_no_workarounds }, 808 809 { "no-workaround-close-loop-end", no_argument, NULL, 810 option_no_workaround_close_loop_end }, 811 { "workaround-close-loop-end", no_argument, NULL, 812 option_workaround_close_loop_end }, 813 814 { "rename-section", required_argument, NULL, option_rename_section_name }, 815 816 { "link-relax", no_argument, NULL, option_link_relax }, 817 { "no-link-relax", no_argument, NULL, option_no_link_relax }, 818 819 { "target-hardware", required_argument, NULL, option_target_hardware }, 820 821 { "trampolines", no_argument, NULL, option_trampolines }, 822 { "no-trampolines", no_argument, NULL, option_no_trampolines }, 823 824 { "auto-litpools", no_argument, NULL, option_auto_litpools }, 825 { "no-auto-litpools", no_argument, NULL, option_no_auto_litpools }, 826 { "auto-litpool-limit", required_argument, NULL, option_auto_litpool_limit }, 827 828 { "separate-prop-tables", no_argument, NULL, option_separate_props }, 829 830 { "abi-windowed", no_argument, NULL, option_abi_windowed }, 831 { "abi-call0", no_argument, NULL, option_abi_call0 }, 832 833 { NULL, no_argument, NULL, 0 } 834}; 835 836size_t md_longopts_size = sizeof md_longopts; 837 838 839int 840md_parse_option (int c, const char *arg) 841{ 842 switch (c) 843 { 844 case option_density: 845 as_warn (_("--density option is ignored")); 846 return 1; 847 case option_no_density: 848 as_warn (_("--no-density option is ignored")); 849 return 1; 850 case option_link_relax: 851 opt_linkrelax = true; 852 return 1; 853 case option_no_link_relax: 854 opt_linkrelax = false; 855 return 1; 856 case option_flix: 857 produce_flix = FLIX_ALL; 858 return 1; 859 case option_no_generate_flix: 860 produce_flix = FLIX_NO_GENERATE; 861 return 1; 862 case option_no_flix: 863 produce_flix = FLIX_NONE; 864 return 1; 865 case option_generics: 866 as_warn (_("--generics is deprecated; use --transform instead")); 867 return md_parse_option (option_transform, arg); 868 case option_no_generics: 869 as_warn (_("--no-generics is deprecated; use --no-transform instead")); 870 return md_parse_option (option_no_transform, arg); 871 case option_relax: 872 as_warn (_("--relax is deprecated; use --transform instead")); 873 return md_parse_option (option_transform, arg); 874 case option_no_relax: 875 as_warn (_("--no-relax is deprecated; use --no-transform instead")); 876 return md_parse_option (option_no_transform, arg); 877 case option_longcalls: 878 directive_state[directive_longcalls] = true; 879 return 1; 880 case option_no_longcalls: 881 directive_state[directive_longcalls] = false; 882 return 1; 883 case option_text_section_literals: 884 use_literal_section = false; 885 return 1; 886 case option_no_text_section_literals: 887 use_literal_section = true; 888 return 1; 889 case option_absolute_literals: 890 if (!absolute_literals_supported) 891 { 892 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); 893 return 0; 894 } 895 directive_state[directive_absolute_literals] = true; 896 return 1; 897 case option_no_absolute_literals: 898 directive_state[directive_absolute_literals] = false; 899 return 1; 900 901 case option_workaround_a0_b_retw: 902 workaround_a0_b_retw = true; 903 return 1; 904 case option_no_workaround_a0_b_retw: 905 workaround_a0_b_retw = false; 906 return 1; 907 case option_workaround_b_j_loop_end: 908 workaround_b_j_loop_end = true; 909 return 1; 910 case option_no_workaround_b_j_loop_end: 911 workaround_b_j_loop_end = false; 912 return 1; 913 914 case option_workaround_short_loop: 915 workaround_short_loop = true; 916 return 1; 917 case option_no_workaround_short_loop: 918 workaround_short_loop = false; 919 return 1; 920 921 case option_workaround_all_short_loops: 922 workaround_all_short_loops = true; 923 return 1; 924 case option_no_workaround_all_short_loops: 925 workaround_all_short_loops = false; 926 return 1; 927 928 case option_workaround_close_loop_end: 929 workaround_close_loop_end = true; 930 return 1; 931 case option_no_workaround_close_loop_end: 932 workaround_close_loop_end = false; 933 return 1; 934 935 case option_no_workarounds: 936 workaround_a0_b_retw = false; 937 workaround_b_j_loop_end = false; 938 workaround_short_loop = false; 939 workaround_all_short_loops = false; 940 workaround_close_loop_end = false; 941 return 1; 942 943 case option_align_targets: 944 align_targets = true; 945 return 1; 946 case option_no_align_targets: 947 align_targets = false; 948 return 1; 949 950 case option_warn_unaligned_targets: 951 warn_unaligned_branch_targets = true; 952 return 1; 953 954 case option_rename_section_name: 955 build_section_rename (arg); 956 return 1; 957 958 case 'Q': 959 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 960 should be emitted or not. FIXME: Not implemented. */ 961 return 1; 962 963 case option_prefer_l32r: 964 if (prefer_const16) 965 as_fatal (_("prefer-l32r conflicts with prefer-const16")); 966 prefer_l32r = 1; 967 return 1; 968 969 case option_prefer_const16: 970 if (prefer_l32r) 971 as_fatal (_("prefer-const16 conflicts with prefer-l32r")); 972 prefer_const16 = 1; 973 return 1; 974 975 case option_target_hardware: 976 { 977 int earliest, latest = 0; 978 char *end; 979 if (*arg == 0 || *arg == '-') 980 as_fatal (_("invalid target hardware version")); 981 982 earliest = strtol (arg, &end, 0); 983 984 if (*end == 0) 985 latest = earliest; 986 else if (*end == '-') 987 { 988 if (*++end == 0) 989 as_fatal (_("invalid target hardware version")); 990 latest = strtol (end, &end, 0); 991 } 992 if (*end != 0) 993 as_fatal (_("invalid target hardware version")); 994 995 xtensa_setup_hw_workarounds (earliest, latest); 996 return 1; 997 } 998 999 case option_transform: 1000 /* This option has no affect other than to use the defaults, 1001 which are already set. */ 1002 return 1; 1003 1004 case option_no_transform: 1005 /* This option turns off all transformations of any kind. 1006 However, because we want to preserve the state of other 1007 directives, we only change its own field. Thus, before 1008 you perform any transformation, always check if transform 1009 is available. If you use the functions we provide for this 1010 purpose, you will be ok. */ 1011 directive_state[directive_transform] = false; 1012 return 1; 1013 1014 case option_trampolines: 1015 use_trampolines = true; 1016 return 1; 1017 1018 case option_no_trampolines: 1019 use_trampolines = false; 1020 return 1; 1021 1022 case option_auto_litpools: 1023 auto_litpools = true; 1024 use_literal_section = false; 1025 if (auto_litpool_limit <= 0) 1026 auto_litpool_limit = MAX_AUTO_POOL_LITERALS / 2; 1027 return 1; 1028 1029 case option_no_auto_litpools: 1030 auto_litpools = false; 1031 auto_litpool_limit = -1; 1032 return 1; 1033 1034 case option_auto_litpool_limit: 1035 { 1036 int value = 0; 1037 char *end; 1038 if (auto_litpool_limit < 0) 1039 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit")); 1040 if (*arg == 0 || *arg == '-') 1041 as_fatal (_("invalid auto-litpool-limit argument")); 1042 value = strtol (arg, &end, 10); 1043 if (*end != 0) 1044 as_fatal (_("invalid auto-litpool-limit argument")); 1045 if (value < 100 || value > 10000) 1046 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)")); 1047 auto_litpool_limit = value; 1048 auto_litpools = true; 1049 use_literal_section = false; 1050 return 1; 1051 } 1052 1053 case option_separate_props: 1054 elf32xtensa_separate_props = true; 1055 return 1; 1056 1057 case option_no_separate_props: 1058 elf32xtensa_separate_props = false; 1059 return 1; 1060 1061 case option_abi_windowed: 1062 elf32xtensa_abi = XTHAL_ABI_WINDOWED; 1063 return 1; 1064 1065 case option_abi_call0: 1066 elf32xtensa_abi = XTHAL_ABI_CALL0; 1067 return 1; 1068 1069 default: 1070 return 0; 1071 } 1072} 1073 1074 1075void 1076md_show_usage (FILE *stream) 1077{ 1078 fputs ("\n\ 1079Xtensa options:\n\ 1080 --[no-]text-section-literals\n\ 1081 [Do not] put literals in the text section\n\ 1082 --[no-]absolute-literals\n\ 1083 [Do not] default to use non-PC-relative literals\n\ 1084 --[no-]target-align [Do not] try to align branch targets\n\ 1085 --[no-]longcalls [Do not] emit 32-bit call sequences\n\ 1086 --[no-]transform [Do not] transform instructions\n\ 1087 --flix both allow hand-written and generate flix bundles\n\ 1088 --no-generate-flix allow hand-written but do not generate\n\ 1089 flix bundles\n\ 1090 --no-allow-flix neither allow hand-written nor generate\n\ 1091 flix bundles\n\ 1092 --rename-section old=new Rename section 'old' to 'new'\n\ 1093 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ 1094 when jumps do not reach their targets\n\ 1095 --[no-]auto-litpools [Do not] automatically create literal pools\n\ 1096 --auto-litpool-limit=<value>\n\ 1097 (range 100-10000) Maximum number of blocks of\n\ 1098 instructions to emit between literal pool\n\ 1099 locations; implies --auto-litpools flag\n\ 1100 --[no-]separate-prop-tables\n\ 1101 [Do not] place Xtensa property records into\n\ 1102 individual property sections for each section.\n\ 1103 Default is to generate single property section.\n", stream); 1104} 1105 1106 1107/* Functions related to the list of current label symbols. */ 1108 1109static void 1110xtensa_add_insn_label (symbolS *sym) 1111{ 1112 sym_list *l; 1113 1114 if (!free_insn_labels) 1115 l = XNEW (sym_list); 1116 else 1117 { 1118 l = free_insn_labels; 1119 free_insn_labels = l->next; 1120 } 1121 1122 l->sym = sym; 1123 l->next = insn_labels; 1124 insn_labels = l; 1125} 1126 1127 1128static void 1129xtensa_clear_insn_labels (void) 1130{ 1131 sym_list **pl; 1132 1133 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1134 ; 1135 *pl = insn_labels; 1136 insn_labels = NULL; 1137} 1138 1139 1140static void 1141xtensa_move_labels (fragS *new_frag, valueT new_offset) 1142{ 1143 sym_list *lit; 1144 1145 for (lit = insn_labels; lit; lit = lit->next) 1146 { 1147 symbolS *lit_sym = lit->sym; 1148 S_SET_VALUE (lit_sym, new_offset); 1149 symbol_set_frag (lit_sym, new_frag); 1150 } 1151} 1152 1153 1154/* Directive data and functions. */ 1155 1156typedef struct state_stackS_struct 1157{ 1158 directiveE directive; 1159 bool negated; 1160 bool old_state; 1161 const char *file; 1162 unsigned int line; 1163 const void *datum; 1164 struct state_stackS_struct *prev; 1165} state_stackS; 1166 1167state_stackS *directive_state_stack; 1168 1169const pseudo_typeS md_pseudo_table[] = 1170{ 1171 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ 1172 { "literal_position", xtensa_literal_position, 0 }, 1173 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ 1174 { "long", xtensa_elf_cons, 4 }, 1175 { "word", xtensa_elf_cons, 4 }, 1176 { "4byte", xtensa_elf_cons, 4 }, 1177 { "short", xtensa_elf_cons, 2 }, 1178 { "2byte", xtensa_elf_cons, 2 }, 1179 { "sleb128", xtensa_leb128, 1}, 1180 { "uleb128", xtensa_leb128, 0}, 1181 { "begin", xtensa_begin_directive, 0 }, 1182 { "end", xtensa_end_directive, 0 }, 1183 { "literal", xtensa_literal_pseudo, 0 }, 1184 { "frequency", xtensa_frequency_pseudo, 0 }, 1185 { NULL, 0, 0 }, 1186}; 1187 1188 1189static bool 1190use_transform (void) 1191{ 1192 /* After md_end, you should be checking frag by frag, rather 1193 than state directives. */ 1194 gas_assert (!past_xtensa_end); 1195 return directive_state[directive_transform]; 1196} 1197 1198 1199static bool 1200do_align_targets (void) 1201{ 1202 /* Do not use this function after md_end; just look at align_targets 1203 instead. There is no target-align directive, so alignment is either 1204 enabled for all frags or not done at all. */ 1205 gas_assert (!past_xtensa_end); 1206 return align_targets && use_transform (); 1207} 1208 1209 1210static void 1211directive_push (directiveE directive, bool negated, const void *datum) 1212{ 1213 const char *file; 1214 unsigned int line; 1215 state_stackS *stack = XNEW (state_stackS); 1216 1217 file = as_where (&line); 1218 1219 stack->directive = directive; 1220 stack->negated = negated; 1221 stack->old_state = directive_state[directive]; 1222 stack->file = file; 1223 stack->line = line; 1224 stack->datum = datum; 1225 stack->prev = directive_state_stack; 1226 directive_state_stack = stack; 1227 1228 directive_state[directive] = !negated; 1229} 1230 1231 1232static void 1233directive_pop (directiveE *directive, 1234 bool *negated, 1235 const char **file, 1236 unsigned int *line, 1237 const void **datum) 1238{ 1239 state_stackS *top = directive_state_stack; 1240 1241 if (!directive_state_stack) 1242 { 1243 as_bad (_("unmatched .end directive")); 1244 *directive = directive_none; 1245 return; 1246 } 1247 1248 directive_state[directive_state_stack->directive] = top->old_state; 1249 *directive = top->directive; 1250 *negated = top->negated; 1251 *file = top->file; 1252 *line = top->line; 1253 *datum = top->datum; 1254 directive_state_stack = top->prev; 1255 free (top); 1256} 1257 1258 1259static void 1260directive_balance (void) 1261{ 1262 while (directive_state_stack) 1263 { 1264 directiveE directive; 1265 bool negated; 1266 const char *file; 1267 unsigned int line; 1268 const void *datum; 1269 1270 directive_pop (&directive, &negated, &file, &line, &datum); 1271 as_warn_where ((char *) file, line, 1272 _(".begin directive with no matching .end directive")); 1273 } 1274} 1275 1276 1277static bool 1278inside_directive (directiveE dir) 1279{ 1280 state_stackS *top = directive_state_stack; 1281 1282 while (top && top->directive != dir) 1283 top = top->prev; 1284 1285 return (top != NULL); 1286} 1287 1288 1289static void 1290get_directive (directiveE *directive, bool *negated) 1291{ 1292 int len; 1293 unsigned i; 1294 const char *directive_string; 1295 1296 if (!startswith (input_line_pointer, "no-")) 1297 *negated = false; 1298 else 1299 { 1300 *negated = true; 1301 input_line_pointer += 3; 1302 } 1303 1304 len = strspn (input_line_pointer, 1305 "abcdefghijklmnopqrstuvwxyz_-/0123456789."); 1306 1307 /* This code is a hack to make .begin [no-][generics|relax] exactly 1308 equivalent to .begin [no-]transform. We should remove it when 1309 we stop accepting those options. */ 1310 1311 if (startswith (input_line_pointer, "generics")) 1312 { 1313 as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); 1314 directive_string = "transform"; 1315 } 1316 else if (startswith (input_line_pointer, "relax")) 1317 { 1318 as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); 1319 directive_string = "transform"; 1320 } 1321 else 1322 directive_string = input_line_pointer; 1323 1324 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) 1325 { 1326 if (strncmp (directive_string, directive_info[i].name, len) == 0) 1327 { 1328 input_line_pointer += len; 1329 *directive = (directiveE) i; 1330 if (*negated && !directive_info[i].can_be_negated) 1331 as_bad (_("directive %s cannot be negated"), 1332 directive_info[i].name); 1333 return; 1334 } 1335 } 1336 1337 as_bad (_("unknown directive")); 1338 *directive = (directiveE) XTENSA_UNDEFINED; 1339} 1340 1341 1342static void 1343xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) 1344{ 1345 directiveE directive; 1346 bool negated; 1347 emit_state *state; 1348 lit_state *ls; 1349 1350 get_directive (&directive, &negated); 1351 if (directive == (directiveE) XTENSA_UNDEFINED) 1352 { 1353 discard_rest_of_line (); 1354 return; 1355 } 1356 1357 if (cur_vinsn.inside_bundle) 1358 as_bad (_("directives are not valid inside bundles")); 1359 1360 switch (directive) 1361 { 1362 case directive_literal: 1363 if (!inside_directive (directive_literal)) 1364 { 1365 /* Previous labels go with whatever follows this directive, not with 1366 the literal, so save them now. */ 1367 saved_insn_labels = insn_labels; 1368 insn_labels = NULL; 1369 } 1370 as_warn (_(".begin literal is deprecated; use .literal instead")); 1371 state = XNEW (emit_state); 1372 xtensa_switch_to_literal_fragment (state); 1373 directive_push (directive_literal, negated, state); 1374 break; 1375 1376 case directive_literal_prefix: 1377 /* Have to flush pending output because a movi relaxed to an l32r 1378 might produce a literal. */ 1379 md_flush_pending_output (); 1380 /* Check to see if the current fragment is a literal 1381 fragment. If it is, then this operation is not allowed. */ 1382 if (generating_literals) 1383 { 1384 as_bad (_("cannot set literal_prefix inside literal fragment")); 1385 return; 1386 } 1387 1388 /* Allocate the literal state for this section and push 1389 onto the directive stack. */ 1390 ls = XNEW (lit_state); 1391 gas_assert (ls); 1392 1393 *ls = default_lit_sections; 1394 directive_push (directive_literal_prefix, negated, ls); 1395 1396 /* Process the new prefix. */ 1397 xtensa_literal_prefix (); 1398 break; 1399 1400 case directive_freeregs: 1401 /* This information is currently unused, but we'll accept the statement 1402 and just discard the rest of the line. This won't check the syntax, 1403 but it will accept every correct freeregs directive. */ 1404 input_line_pointer += strcspn (input_line_pointer, "\n"); 1405 directive_push (directive_freeregs, negated, 0); 1406 break; 1407 1408 case directive_schedule: 1409 md_flush_pending_output (); 1410 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 1411 frag_now->fr_symbol, frag_now->fr_offset, NULL); 1412 directive_push (directive_schedule, negated, 0); 1413 xtensa_set_frag_assembly_state (frag_now); 1414 break; 1415 1416 case directive_density: 1417 as_warn (_(".begin [no-]density is ignored")); 1418 break; 1419 1420 case directive_absolute_literals: 1421 md_flush_pending_output (); 1422 if (!absolute_literals_supported && !negated) 1423 { 1424 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1425 break; 1426 } 1427 xtensa_set_frag_assembly_state (frag_now); 1428 directive_push (directive, negated, 0); 1429 break; 1430 1431 default: 1432 md_flush_pending_output (); 1433 xtensa_set_frag_assembly_state (frag_now); 1434 directive_push (directive, negated, 0); 1435 break; 1436 } 1437 1438 demand_empty_rest_of_line (); 1439} 1440 1441 1442static void 1443xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) 1444{ 1445 directiveE begin_directive, end_directive; 1446 bool begin_negated, end_negated; 1447 const char *file; 1448 unsigned int line; 1449 emit_state *state; 1450 emit_state **state_ptr; 1451 lit_state *s; 1452 1453 if (cur_vinsn.inside_bundle) 1454 as_bad (_("directives are not valid inside bundles")); 1455 1456 get_directive (&end_directive, &end_negated); 1457 1458 md_flush_pending_output (); 1459 1460 switch ((int) end_directive) 1461 { 1462 case XTENSA_UNDEFINED: 1463 discard_rest_of_line (); 1464 return; 1465 1466 case (int) directive_density: 1467 as_warn (_(".end [no-]density is ignored")); 1468 demand_empty_rest_of_line (); 1469 break; 1470 1471 case (int) directive_absolute_literals: 1472 if (!absolute_literals_supported && !end_negated) 1473 { 1474 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1475 demand_empty_rest_of_line (); 1476 return; 1477 } 1478 break; 1479 1480 default: 1481 break; 1482 } 1483 1484 state_ptr = &state; /* use state_ptr to avoid type-punning warning */ 1485 directive_pop (&begin_directive, &begin_negated, &file, &line, 1486 (const void **) state_ptr); 1487 1488 if (begin_directive != directive_none) 1489 { 1490 if (begin_directive != end_directive || begin_negated != end_negated) 1491 { 1492 as_bad (_("does not match begin %s%s at %s:%d"), 1493 begin_negated ? "no-" : "", 1494 directive_info[begin_directive].name, file, line); 1495 } 1496 else 1497 { 1498 switch (end_directive) 1499 { 1500 case directive_literal: 1501 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); 1502 xtensa_restore_emit_state (state); 1503 xtensa_set_frag_assembly_state (frag_now); 1504 free (state); 1505 if (!inside_directive (directive_literal)) 1506 { 1507 /* Restore the list of current labels. */ 1508 xtensa_clear_insn_labels (); 1509 insn_labels = saved_insn_labels; 1510 } 1511 break; 1512 1513 case directive_literal_prefix: 1514 /* Restore the default collection sections from saved state. */ 1515 s = (lit_state *) state; 1516 gas_assert (s); 1517 default_lit_sections = *s; 1518 1519 /* Free the state storage. */ 1520 free (s->lit_prefix); 1521 free (s); 1522 break; 1523 1524 case directive_schedule: 1525 case directive_freeregs: 1526 break; 1527 1528 default: 1529 xtensa_set_frag_assembly_state (frag_now); 1530 break; 1531 } 1532 } 1533 } 1534 1535 demand_empty_rest_of_line (); 1536} 1537 1538 1539/* Place an aligned literal fragment at the current location. */ 1540 1541static void 1542xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) 1543{ 1544 md_flush_pending_output (); 1545 1546 if (inside_directive (directive_literal)) 1547 as_warn (_(".literal_position inside literal directive; ignoring")); 1548 xtensa_mark_literal_pool_location (); 1549 1550 demand_empty_rest_of_line (); 1551 xtensa_clear_insn_labels (); 1552} 1553 1554 1555/* Support .literal label, expr, ... */ 1556 1557static void 1558xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) 1559{ 1560 emit_state state; 1561 char *p, *base_name; 1562 char c; 1563 1564 if (inside_directive (directive_literal)) 1565 { 1566 as_bad (_(".literal not allowed inside .begin literal region")); 1567 ignore_rest_of_line (); 1568 return; 1569 } 1570 1571 md_flush_pending_output (); 1572 1573 /* Previous labels go with whatever follows this directive, not with 1574 the literal, so save them now. */ 1575 saved_insn_labels = insn_labels; 1576 insn_labels = NULL; 1577 1578 base_name = input_line_pointer; 1579 1580 xtensa_switch_to_literal_fragment (&state); 1581 1582 /* All literals are aligned to four-byte boundaries. */ 1583 frag_align (2, 0, 0); 1584 record_alignment (now_seg, 2); 1585 1586 c = get_symbol_name (&base_name); 1587 /* Just after name is now '\0'. */ 1588 p = input_line_pointer; 1589 *p = c; 1590 SKIP_WHITESPACE_AFTER_NAME (); 1591 1592 if (*input_line_pointer != ',' && *input_line_pointer != ':') 1593 { 1594 as_bad (_("expected comma or colon after symbol name; " 1595 "rest of line ignored")); 1596 ignore_rest_of_line (); 1597 xtensa_restore_emit_state (&state); 1598 return; 1599 } 1600 1601 *p = 0; 1602 colon (base_name); 1603 *p = c; 1604 1605 input_line_pointer++; /* skip ',' or ':' */ 1606 1607 xtensa_elf_cons (4); 1608 1609 xtensa_restore_emit_state (&state); 1610 1611 /* Restore the list of current labels. */ 1612 xtensa_clear_insn_labels (); 1613 insn_labels = saved_insn_labels; 1614} 1615 1616 1617static void 1618xtensa_literal_prefix (void) 1619{ 1620 char *name; 1621 int len; 1622 1623 /* Parse the new prefix from the input_line_pointer. */ 1624 SKIP_WHITESPACE (); 1625 len = strspn (input_line_pointer, 1626 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1627 "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); 1628 1629 /* Get a null-terminated copy of the name. */ 1630 name = xmemdup0 (input_line_pointer, len); 1631 1632 /* Skip the name in the input line. */ 1633 input_line_pointer += len; 1634 1635 default_lit_sections.lit_prefix = name; 1636 1637 /* Clear cached literal sections, since the prefix has changed. */ 1638 default_lit_sections.lit_seg = NULL; 1639 default_lit_sections.lit4_seg = NULL; 1640} 1641 1642 1643/* Support ".frequency branch_target_frequency fall_through_frequency". */ 1644 1645static void 1646xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) 1647{ 1648 float fall_through_f, target_f; 1649 1650 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); 1651 if (fall_through_f < 0) 1652 { 1653 as_bad (_("fall through frequency must be greater than 0")); 1654 ignore_rest_of_line (); 1655 return; 1656 } 1657 1658 target_f = (float) strtod (input_line_pointer, &input_line_pointer); 1659 if (target_f < 0) 1660 { 1661 as_bad (_("branch target frequency must be greater than 0")); 1662 ignore_rest_of_line (); 1663 return; 1664 } 1665 1666 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); 1667 1668 demand_empty_rest_of_line (); 1669} 1670 1671 1672/* Like normal .long/.short/.word, except support @plt, etc. 1673 Clobbers input_line_pointer, checks end-of-line. */ 1674 1675static void 1676xtensa_elf_cons (int nbytes) 1677{ 1678 expressionS exp; 1679 bfd_reloc_code_real_type reloc; 1680 1681 md_flush_pending_output (); 1682 1683 if (cur_vinsn.inside_bundle) 1684 as_bad (_("directives are not valid inside bundles")); 1685 1686 if (is_it_end_of_statement ()) 1687 { 1688 demand_empty_rest_of_line (); 1689 return; 1690 } 1691 1692 do 1693 { 1694 expression (&exp); 1695 if (exp.X_op == O_symbol 1696 && *input_line_pointer == '@' 1697 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) 1698 != BFD_RELOC_NONE)) 1699 { 1700 reloc_howto_type *reloc_howto = 1701 bfd_reloc_type_lookup (stdoutput, reloc); 1702 1703 if (reloc == BFD_RELOC_UNUSED || !reloc_howto) 1704 as_bad (_("unsupported relocation")); 1705 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP 1706 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 1707 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 1708 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) 1709 as_bad (_("opcode-specific %s relocation used outside " 1710 "an instruction"), reloc_howto->name); 1711 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) 1712 as_bad (ngettext ("%s relocations do not fit in %d byte", 1713 "%s relocations do not fit in %d bytes", 1714 nbytes), 1715 reloc_howto->name, nbytes); 1716 else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC 1717 || reloc == BFD_RELOC_XTENSA_TLS_ARG 1718 || reloc == BFD_RELOC_XTENSA_TLS_CALL) 1719 as_bad (_("invalid use of %s relocation"), reloc_howto->name); 1720 else 1721 { 1722 char *p = frag_more ((int) nbytes); 1723 xtensa_set_frag_assembly_state (frag_now); 1724 fix_new_exp (frag_now, p - frag_now->fr_literal, 1725 nbytes, &exp, reloc_howto->pc_relative, reloc); 1726 } 1727 } 1728 else 1729 { 1730 xtensa_set_frag_assembly_state (frag_now); 1731 emit_expr (&exp, (unsigned int) nbytes); 1732 } 1733 } 1734 while (*input_line_pointer++ == ','); 1735 1736 input_line_pointer--; /* Put terminator back into stream. */ 1737 demand_empty_rest_of_line (); 1738} 1739 1740static bool is_leb128_expr; 1741 1742static void 1743xtensa_leb128 (int sign) 1744{ 1745 is_leb128_expr = true; 1746 s_leb128 (sign); 1747 is_leb128_expr = false; 1748} 1749 1750 1751/* Parsing and Idiom Translation. */ 1752 1753/* Parse @plt, etc. and return the desired relocation. */ 1754static bfd_reloc_code_real_type 1755xtensa_elf_suffix (char **str_p, expressionS *exp_p) 1756{ 1757 char ident[20]; 1758 char *str = *str_p; 1759 char *str2; 1760 int ch; 1761 int len; 1762 unsigned int i; 1763 1764 if (*str++ != '@') 1765 return BFD_RELOC_NONE; 1766 1767 for (ch = *str, str2 = ident; 1768 (str2 < ident + sizeof (ident) - 1 1769 && (ISALNUM (ch) || ch == '@')); 1770 ch = *++str) 1771 { 1772 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); 1773 } 1774 1775 *str2 = '\0'; 1776 len = str2 - ident; 1777 1778 ch = ident[0]; 1779 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) 1780 if (ch == suffix_relocs[i].suffix[0] 1781 && len == suffix_relocs[i].length 1782 && memcmp (ident, suffix_relocs[i].suffix, suffix_relocs[i].length) == 0) 1783 { 1784 /* Now check for "identifier@suffix+constant". */ 1785 if (*str == '-' || *str == '+') 1786 { 1787 char *orig_line = input_line_pointer; 1788 expressionS new_exp; 1789 1790 input_line_pointer = str; 1791 expression (&new_exp); 1792 if (new_exp.X_op == O_constant) 1793 { 1794 exp_p->X_add_number += new_exp.X_add_number; 1795 str = input_line_pointer; 1796 } 1797 1798 if (&input_line_pointer != str_p) 1799 input_line_pointer = orig_line; 1800 } 1801 1802 *str_p = str; 1803 return suffix_relocs[i].reloc; 1804 } 1805 1806 return BFD_RELOC_UNUSED; 1807} 1808 1809 1810/* Find the matching operator type. */ 1811static operatorT 1812map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) 1813{ 1814 operatorT operator = O_illegal; 1815 unsigned int i; 1816 1817 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) 1818 { 1819 if (suffix_relocs[i].reloc == reloc) 1820 { 1821 operator = suffix_relocs[i].operator; 1822 break; 1823 } 1824 } 1825 gas_assert (operator != O_illegal); 1826 return operator; 1827} 1828 1829 1830/* Find the matching reloc type. */ 1831static bfd_reloc_code_real_type 1832map_operator_to_reloc (unsigned char operator, bool is_literal) 1833{ 1834 unsigned int i; 1835 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; 1836 1837 for (i = 0; i < ARRAY_SIZE (suffix_relocs); i++) 1838 { 1839 if (suffix_relocs[i].operator == operator) 1840 { 1841 reloc = suffix_relocs[i].reloc; 1842 break; 1843 } 1844 } 1845 1846 if (is_literal) 1847 { 1848 if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) 1849 return BFD_RELOC_XTENSA_TLSDESC_FN; 1850 else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) 1851 return BFD_RELOC_XTENSA_TLSDESC_ARG; 1852 } 1853 1854 if (reloc == BFD_RELOC_UNUSED) 1855 return BFD_RELOC_32; 1856 1857 return reloc; 1858} 1859 1860 1861static const char * 1862expression_end (const char *name) 1863{ 1864 while (1) 1865 { 1866 switch (*name) 1867 { 1868 case '}': 1869 case ';': 1870 case '\0': 1871 case ',': 1872 case ':': 1873 return name; 1874 case ' ': 1875 case '\t': 1876 ++name; 1877 continue; 1878 default: 1879 return 0; 1880 } 1881 } 1882} 1883 1884 1885#define ERROR_REG_NUM ((unsigned) -1) 1886 1887static unsigned 1888tc_get_register (const char *prefix) 1889{ 1890 unsigned reg; 1891 const char *next_expr; 1892 const char *old_line_pointer; 1893 1894 SKIP_WHITESPACE (); 1895 old_line_pointer = input_line_pointer; 1896 1897 if (*input_line_pointer == '$') 1898 ++input_line_pointer; 1899 1900 /* Accept "sp" as a synonym for "a1". */ 1901 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' 1902 && expression_end (input_line_pointer + 2)) 1903 { 1904 input_line_pointer += 2; 1905 return 1; /* AR[1] */ 1906 } 1907 1908 while (*input_line_pointer++ == *prefix++) 1909 ; 1910 --input_line_pointer; 1911 --prefix; 1912 1913 if (*prefix) 1914 { 1915 as_bad (_("bad register name: %s"), old_line_pointer); 1916 return ERROR_REG_NUM; 1917 } 1918 1919 if (!ISDIGIT ((unsigned char) *input_line_pointer)) 1920 { 1921 as_bad (_("bad register number: %s"), input_line_pointer); 1922 return ERROR_REG_NUM; 1923 } 1924 1925 reg = 0; 1926 1927 while (ISDIGIT ((int) *input_line_pointer)) 1928 reg = reg * 10 + *input_line_pointer++ - '0'; 1929 1930 if (!(next_expr = expression_end (input_line_pointer))) 1931 { 1932 as_bad (_("bad register name: %s"), old_line_pointer); 1933 return ERROR_REG_NUM; 1934 } 1935 1936 input_line_pointer = (char *) next_expr; 1937 1938 return reg; 1939} 1940 1941 1942static void 1943expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) 1944{ 1945 xtensa_isa isa = xtensa_default_isa; 1946 1947 /* Check if this is an immediate operand. */ 1948 if (xtensa_operand_is_register (isa, opc, opnd) == 0) 1949 { 1950 bfd_reloc_code_real_type reloc; 1951 segT t = expression (tok); 1952 1953 if (t == absolute_section 1954 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) 1955 { 1956 gas_assert (tok->X_op == O_constant); 1957 tok->X_op = O_symbol; 1958 tok->X_add_symbol = &abs_symbol; 1959 } 1960 1961 if ((tok->X_op == O_constant || tok->X_op == O_symbol) 1962 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 1963 != BFD_RELOC_NONE)) 1964 { 1965 switch (reloc) 1966 { 1967 case BFD_RELOC_LO16: 1968 if (tok->X_op == O_constant) 1969 { 1970 tok->X_add_number &= 0xffff; 1971 return; 1972 } 1973 break; 1974 case BFD_RELOC_HI16: 1975 if (tok->X_op == O_constant) 1976 { 1977 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; 1978 return; 1979 } 1980 break; 1981 case BFD_RELOC_UNUSED: 1982 as_bad (_("unsupported relocation")); 1983 return; 1984 case BFD_RELOC_32_PCREL: 1985 as_bad (_("pcrel relocation not allowed in an instruction")); 1986 return; 1987 default: 1988 break; 1989 } 1990 tok->X_op = map_suffix_reloc_to_operator (reloc); 1991 } 1992 } 1993 else 1994 { 1995 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); 1996 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); 1997 1998 if (reg != ERROR_REG_NUM) /* Already errored */ 1999 { 2000 uint32 buf = reg; 2001 if (xtensa_operand_encode (isa, opc, opnd, &buf)) 2002 as_bad (_("register number out of range")); 2003 } 2004 2005 tok->X_op = O_register; 2006 tok->X_add_symbol = 0; 2007 tok->X_add_number = reg; 2008 } 2009} 2010 2011 2012/* Split up the arguments for an opcode or pseudo-op. */ 2013 2014static int 2015tokenize_arguments (char **args, char *str) 2016{ 2017 char *old_input_line_pointer; 2018 bool saw_comma = false; 2019 bool saw_arg = false; 2020 bool saw_colon = false; 2021 int num_args = 0; 2022 char *arg_end, *arg; 2023 int arg_len; 2024 2025 /* Save and restore input_line_pointer around this function. */ 2026 old_input_line_pointer = input_line_pointer; 2027 input_line_pointer = str; 2028 2029 while (*input_line_pointer) 2030 { 2031 SKIP_WHITESPACE (); 2032 switch (*input_line_pointer) 2033 { 2034 case '\0': 2035 case '}': 2036 goto fini; 2037 2038 case ':': 2039 input_line_pointer++; 2040 if (saw_comma || saw_colon || !saw_arg) 2041 goto err; 2042 saw_colon = true; 2043 break; 2044 2045 case ',': 2046 input_line_pointer++; 2047 if (saw_comma || saw_colon || !saw_arg) 2048 goto err; 2049 saw_comma = true; 2050 break; 2051 2052 default: 2053 if (!saw_comma && !saw_colon && saw_arg) 2054 goto err; 2055 2056 arg_end = input_line_pointer + 1; 2057 while (!expression_end (arg_end)) 2058 arg_end += 1; 2059 2060 arg_len = arg_end - input_line_pointer; 2061 arg = XNEWVEC (char, (saw_colon ? 1 : 0) + arg_len + 1); 2062 args[num_args] = arg; 2063 2064 if (saw_colon) 2065 *arg++ = ':'; 2066 strncpy (arg, input_line_pointer, arg_len); 2067 arg[arg_len] = '\0'; 2068 2069 input_line_pointer = arg_end; 2070 num_args += 1; 2071 saw_comma = false; 2072 saw_colon = false; 2073 saw_arg = true; 2074 break; 2075 } 2076 } 2077 2078 fini: 2079 if (saw_comma || saw_colon) 2080 goto err; 2081 input_line_pointer = old_input_line_pointer; 2082 return num_args; 2083 2084 err: 2085 if (saw_comma) 2086 as_bad (_("extra comma")); 2087 else if (saw_colon) 2088 as_bad (_("extra colon")); 2089 else if (!saw_arg) 2090 as_bad (_("missing argument")); 2091 else 2092 as_bad (_("missing comma or colon")); 2093 input_line_pointer = old_input_line_pointer; 2094 return -1; 2095} 2096 2097 2098/* Parse the arguments to an opcode. Return TRUE on error. */ 2099 2100static bool 2101parse_arguments (TInsn *insn, int num_args, char **arg_strings) 2102{ 2103 expressionS *tok, *last_tok; 2104 xtensa_opcode opcode = insn->opcode; 2105 bool had_error = true; 2106 xtensa_isa isa = xtensa_default_isa; 2107 int n, num_regs = 0; 2108 int opcode_operand_count; 2109 int opnd_cnt, last_opnd_cnt; 2110 unsigned int next_reg = 0; 2111 char *old_input_line_pointer; 2112 2113 if (insn->insn_type == ITYPE_LITERAL) 2114 opcode_operand_count = 1; 2115 else 2116 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); 2117 2118 tok = insn->tok; 2119 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); 2120 2121 /* Save and restore input_line_pointer around this function. */ 2122 old_input_line_pointer = input_line_pointer; 2123 2124 last_tok = 0; 2125 last_opnd_cnt = -1; 2126 opnd_cnt = 0; 2127 2128 /* Skip invisible operands. */ 2129 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) 2130 { 2131 opnd_cnt += 1; 2132 tok++; 2133 } 2134 2135 for (n = 0; n < num_args; n++) 2136 { 2137 input_line_pointer = arg_strings[n]; 2138 if (*input_line_pointer == ':') 2139 { 2140 xtensa_regfile opnd_rf; 2141 input_line_pointer++; 2142 if (num_regs == 0) 2143 goto err; 2144 gas_assert (opnd_cnt > 0); 2145 num_regs--; 2146 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); 2147 if (next_reg 2148 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) 2149 as_warn (_("incorrect register number, ignoring")); 2150 next_reg++; 2151 } 2152 else 2153 { 2154 if (opnd_cnt >= opcode_operand_count) 2155 { 2156 as_warn (_("too many arguments")); 2157 goto err; 2158 } 2159 gas_assert (opnd_cnt < MAX_INSN_ARGS); 2160 2161 expression_maybe_register (opcode, opnd_cnt, tok); 2162 next_reg = tok->X_add_number + 1; 2163 2164 if (tok->X_op == O_illegal || tok->X_op == O_absent) 2165 goto err; 2166 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) 2167 { 2168 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; 2169 /* minus 1 because we are seeing one right now */ 2170 } 2171 else 2172 num_regs = 0; 2173 2174 last_tok = tok; 2175 last_opnd_cnt = opnd_cnt; 2176 demand_empty_rest_of_line (); 2177 2178 do 2179 { 2180 opnd_cnt += 1; 2181 tok++; 2182 } 2183 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); 2184 } 2185 } 2186 2187 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) 2188 goto err; 2189 2190 insn->ntok = tok - insn->tok; 2191 had_error = false; 2192 2193 err: 2194 input_line_pointer = old_input_line_pointer; 2195 return had_error; 2196} 2197 2198 2199static int 2200get_invisible_operands (TInsn *insn) 2201{ 2202 xtensa_isa isa = xtensa_default_isa; 2203 static xtensa_insnbuf slotbuf = NULL; 2204 xtensa_format fmt; 2205 xtensa_opcode opc = insn->opcode; 2206 int slot, opnd, fmt_found; 2207 unsigned val; 2208 2209 if (!slotbuf) 2210 slotbuf = xtensa_insnbuf_alloc (isa); 2211 2212 /* Find format/slot where this can be encoded. */ 2213 fmt_found = 0; 2214 slot = 0; 2215 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 2216 { 2217 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 2218 { 2219 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) 2220 { 2221 fmt_found = 1; 2222 break; 2223 } 2224 } 2225 if (fmt_found) break; 2226 } 2227 2228 if (!fmt_found) 2229 { 2230 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); 2231 return -1; 2232 } 2233 2234 /* First encode all the visible operands 2235 (to deal with shared field operands). */ 2236 for (opnd = 0; opnd < insn->ntok; opnd++) 2237 { 2238 if (xtensa_operand_is_visible (isa, opc, opnd) == 1 2239 && (insn->tok[opnd].X_op == O_register 2240 || insn->tok[opnd].X_op == O_constant)) 2241 { 2242 val = insn->tok[opnd].X_add_number; 2243 xtensa_operand_encode (isa, opc, opnd, &val); 2244 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); 2245 } 2246 } 2247 2248 /* Then pull out the values for the invisible ones. */ 2249 for (opnd = 0; opnd < insn->ntok; opnd++) 2250 { 2251 if (xtensa_operand_is_visible (isa, opc, opnd) == 0) 2252 { 2253 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); 2254 xtensa_operand_decode (isa, opc, opnd, &val); 2255 insn->tok[opnd].X_add_number = val; 2256 if (xtensa_operand_is_register (isa, opc, opnd) == 1) 2257 insn->tok[opnd].X_op = O_register; 2258 else 2259 insn->tok[opnd].X_op = O_constant; 2260 } 2261 } 2262 2263 return 0; 2264} 2265 2266 2267static void 2268xg_reverse_shift_count (char **cnt_argp) 2269{ 2270 char *cnt_arg, *new_arg; 2271 cnt_arg = *cnt_argp; 2272 2273 /* replace the argument with "31-(argument)" */ 2274 new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL); 2275 2276 free (cnt_arg); 2277 *cnt_argp = new_arg; 2278} 2279 2280 2281/* If "arg" is a constant expression, return non-zero with the value 2282 in *valp. */ 2283 2284static int 2285xg_arg_is_constant (char *arg, offsetT *valp) 2286{ 2287 expressionS exp; 2288 char *save_ptr = input_line_pointer; 2289 2290 input_line_pointer = arg; 2291 expression (&exp); 2292 input_line_pointer = save_ptr; 2293 2294 if (exp.X_op == O_constant) 2295 { 2296 *valp = exp.X_add_number; 2297 return 1; 2298 } 2299 2300 return 0; 2301} 2302 2303 2304static void 2305xg_replace_opname (char **popname, const char *newop) 2306{ 2307 free (*popname); 2308 *popname = xstrdup (newop); 2309} 2310 2311 2312static int 2313xg_check_num_args (int *pnum_args, 2314 int expected_num, 2315 char *opname, 2316 char **arg_strings) 2317{ 2318 int num_args = *pnum_args; 2319 2320 if (num_args < expected_num) 2321 { 2322 as_bad (_("not enough operands (%d) for '%s'; expected %d"), 2323 num_args, opname, expected_num); 2324 return -1; 2325 } 2326 2327 if (num_args > expected_num) 2328 { 2329 as_warn (_("too many operands (%d) for '%s'; expected %d"), 2330 num_args, opname, expected_num); 2331 while (num_args-- > expected_num) 2332 { 2333 free (arg_strings[num_args]); 2334 arg_strings[num_args] = 0; 2335 } 2336 *pnum_args = expected_num; 2337 return -1; 2338 } 2339 2340 return 0; 2341} 2342 2343 2344/* If the register is not specified as part of the opcode, 2345 then get it from the operand and move it to the opcode. */ 2346 2347static int 2348xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) 2349{ 2350 xtensa_isa isa = xtensa_default_isa; 2351 xtensa_sysreg sr; 2352 char *opname, *new_opname; 2353 const char *sr_name; 2354 int is_user, is_write; 2355 2356 opname = *popname; 2357 if (*opname == '_') 2358 opname += 1; 2359 is_user = (opname[1] == 'u'); 2360 is_write = (opname[0] == 'w'); 2361 2362 /* Opname == [rw]ur or [rwx]sr... */ 2363 2364 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2365 return -1; 2366 2367 /* Check if the argument is a symbolic register name. */ 2368 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); 2369 /* Handle WSR to "INTSET" as a special case. */ 2370 if (sr == XTENSA_UNDEFINED && is_write && !is_user 2371 && !strcasecmp (arg_strings[1], "intset")) 2372 sr = xtensa_sysreg_lookup_name (isa, "interrupt"); 2373 if (sr == XTENSA_UNDEFINED 2374 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) 2375 { 2376 /* Maybe it's a register number.... */ 2377 offsetT val; 2378 if (!xg_arg_is_constant (arg_strings[1], &val)) 2379 { 2380 as_bad (_("invalid register '%s' for '%s' instruction"), 2381 arg_strings[1], opname); 2382 return -1; 2383 } 2384 sr = xtensa_sysreg_lookup (isa, val, is_user); 2385 if (sr == XTENSA_UNDEFINED) 2386 { 2387 as_bad (_("invalid register number (%ld) for '%s' instruction"), 2388 (long) val, opname); 2389 return -1; 2390 } 2391 } 2392 2393 /* Remove the last argument, which is now part of the opcode. */ 2394 free (arg_strings[1]); 2395 arg_strings[1] = 0; 2396 *pnum_args = 1; 2397 2398 /* Translate the opcode. */ 2399 sr_name = xtensa_sysreg_name (isa, sr); 2400 /* Another special case for "WSR.INTSET".... */ 2401 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) 2402 sr_name = "intset"; 2403 new_opname = concat (*popname, ".", sr_name, (char *) NULL); 2404 free (*popname); 2405 *popname = new_opname; 2406 2407 return 0; 2408} 2409 2410 2411static int 2412xtensa_translate_old_userreg_ops (char **popname) 2413{ 2414 xtensa_isa isa = xtensa_default_isa; 2415 xtensa_sysreg sr; 2416 char *opname, *new_opname; 2417 const char *sr_name; 2418 bool has_underbar = false; 2419 2420 opname = *popname; 2421 if (opname[0] == '_') 2422 { 2423 has_underbar = true; 2424 opname += 1; 2425 } 2426 2427 sr = xtensa_sysreg_lookup_name (isa, opname + 1); 2428 if (sr != XTENSA_UNDEFINED) 2429 { 2430 /* The new default name ("nnn") is different from the old default 2431 name ("URnnn"). The old default is handled below, and we don't 2432 want to recognize [RW]nnn, so do nothing if the name is the (new) 2433 default. */ 2434 static char namebuf[10]; 2435 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); 2436 if (strcmp (namebuf, opname + 1) == 0) 2437 return 0; 2438 } 2439 else 2440 { 2441 offsetT val; 2442 char *end; 2443 2444 /* Only continue if the reg name is "URnnn". */ 2445 if (opname[1] != 'u' || opname[2] != 'r') 2446 return 0; 2447 val = strtoul (opname + 3, &end, 10); 2448 if (*end != '\0') 2449 return 0; 2450 2451 sr = xtensa_sysreg_lookup (isa, val, 1); 2452 if (sr == XTENSA_UNDEFINED) 2453 { 2454 as_bad (_("invalid register number (%ld) for '%s'"), 2455 (long) val, opname); 2456 return -1; 2457 } 2458 } 2459 2460 /* Translate the opcode. */ 2461 sr_name = xtensa_sysreg_name (isa, sr); 2462 new_opname = XNEWVEC (char, strlen (sr_name) + 6); 2463 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), 2464 opname[0], sr_name); 2465 free (*popname); 2466 *popname = new_opname; 2467 2468 return 0; 2469} 2470 2471 2472static int 2473xtensa_translate_zero_immed (const char *old_op, 2474 const char *new_op, 2475 char **popname, 2476 int *pnum_args, 2477 char **arg_strings) 2478{ 2479 char *opname; 2480 offsetT val; 2481 2482 opname = *popname; 2483 gas_assert (opname[0] != '_'); 2484 2485 if (strcmp (opname, old_op) != 0) 2486 return 0; 2487 2488 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2489 return -1; 2490 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) 2491 { 2492 xg_replace_opname (popname, new_op); 2493 free (arg_strings[1]); 2494 arg_strings[1] = arg_strings[2]; 2495 arg_strings[2] = 0; 2496 *pnum_args = 2; 2497 } 2498 2499 return 0; 2500} 2501 2502 2503/* If the instruction is an idiom (i.e., a built-in macro), translate it. 2504 Returns non-zero if an error was found. */ 2505 2506static int 2507xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) 2508{ 2509 char *opname = *popname; 2510 bool has_underbar = false; 2511 2512 if (*opname == '_') 2513 { 2514 has_underbar = true; 2515 opname += 1; 2516 } 2517 2518 if (strcmp (opname, "mov") == 0) 2519 { 2520 if (use_transform () && !has_underbar && density_supported) 2521 xg_replace_opname (popname, "mov.n"); 2522 else 2523 { 2524 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2525 return -1; 2526 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2527 arg_strings[2] = xstrdup (arg_strings[1]); 2528 *pnum_args = 3; 2529 } 2530 return 0; 2531 } 2532 2533 /* Without an operand, this is given a default immediate operand of 0. */ 2534 if ((strcmp (opname, "simcall") == 0 && microarch_earliest >= 280000)) 2535 { 2536 if (*pnum_args == 0) 2537 { 2538 arg_strings[0] = (char *) xmalloc (2); 2539 strcpy (arg_strings[0], "0"); 2540 *pnum_args = 1; 2541 } 2542 return 0; 2543 } 2544 2545 if (strcmp (opname, "bbsi.l") == 0) 2546 { 2547 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2548 return -1; 2549 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); 2550 if (target_big_endian) 2551 xg_reverse_shift_count (&arg_strings[1]); 2552 return 0; 2553 } 2554 2555 if (strcmp (opname, "bbci.l") == 0) 2556 { 2557 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2558 return -1; 2559 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); 2560 if (target_big_endian) 2561 xg_reverse_shift_count (&arg_strings[1]); 2562 return 0; 2563 } 2564 2565 /* Don't do anything special with NOPs inside FLIX instructions. They 2566 are handled elsewhere. Real NOP instructions are always available 2567 in configurations with FLIX, so this should never be an issue but 2568 check for it anyway. */ 2569 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED 2570 && strcmp (opname, "nop") == 0) 2571 { 2572 if (use_transform () && !has_underbar && density_supported) 2573 xg_replace_opname (popname, "nop.n"); 2574 else 2575 { 2576 if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) 2577 return -1; 2578 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2579 arg_strings[0] = xstrdup ("a1"); 2580 arg_strings[1] = xstrdup ("a1"); 2581 arg_strings[2] = xstrdup ("a1"); 2582 *pnum_args = 3; 2583 } 2584 return 0; 2585 } 2586 2587 /* Recognize [RW]UR and [RWX]SR. */ 2588 if ((((opname[0] == 'r' || opname[0] == 'w') 2589 && (opname[1] == 'u' || opname[1] == 's')) 2590 || (opname[0] == 'x' && opname[1] == 's')) 2591 && opname[2] == 'r' 2592 && opname[3] == '\0') 2593 return xg_translate_sysreg_op (popname, pnum_args, arg_strings); 2594 2595 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and 2596 [RW]<name> if <name> is the non-default name of a user register. */ 2597 if ((opname[0] == 'r' || opname[0] == 'w') 2598 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) 2599 return xtensa_translate_old_userreg_ops (popname); 2600 2601 /* Relax branches that don't allow comparisons against an immediate value 2602 of zero to the corresponding branches with implicit zero immediates. */ 2603 if (!has_underbar && use_transform ()) 2604 { 2605 if (xtensa_translate_zero_immed ("bnei", "bnez", popname, 2606 pnum_args, arg_strings)) 2607 return -1; 2608 2609 if (xtensa_translate_zero_immed ("beqi", "beqz", popname, 2610 pnum_args, arg_strings)) 2611 return -1; 2612 2613 if (xtensa_translate_zero_immed ("bgei", "bgez", popname, 2614 pnum_args, arg_strings)) 2615 return -1; 2616 2617 if (xtensa_translate_zero_immed ("blti", "bltz", popname, 2618 pnum_args, arg_strings)) 2619 return -1; 2620 } 2621 2622 return 0; 2623} 2624 2625 2626/* Functions for dealing with the Xtensa ISA. */ 2627 2628/* Currently the assembler only allows us to use a single target per 2629 fragment. Because of this, only one operand for a given 2630 instruction may be symbolic. If there is a PC-relative operand, 2631 the last one is chosen. Otherwise, the result is the number of the 2632 last immediate operand, and if there are none of those, we fail and 2633 return -1. */ 2634 2635static int 2636get_relaxable_immed (xtensa_opcode opcode) 2637{ 2638 int last_immed = -1; 2639 int noperands, opi; 2640 2641 if (opcode == XTENSA_UNDEFINED) 2642 return -1; 2643 2644 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); 2645 for (opi = noperands - 1; opi >= 0; opi--) 2646 { 2647 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) 2648 continue; 2649 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) 2650 return opi; 2651 if (last_immed == -1 2652 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) 2653 last_immed = opi; 2654 } 2655 return last_immed; 2656} 2657 2658 2659static xtensa_opcode 2660get_opcode_from_buf (const char *buf, int slot) 2661{ 2662 static xtensa_insnbuf insnbuf = NULL; 2663 static xtensa_insnbuf slotbuf = NULL; 2664 xtensa_isa isa = xtensa_default_isa; 2665 xtensa_format fmt; 2666 2667 if (!insnbuf) 2668 { 2669 insnbuf = xtensa_insnbuf_alloc (isa); 2670 slotbuf = xtensa_insnbuf_alloc (isa); 2671 } 2672 2673 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); 2674 fmt = xtensa_format_decode (isa, insnbuf); 2675 if (fmt == XTENSA_UNDEFINED) 2676 return XTENSA_UNDEFINED; 2677 2678 if (slot >= xtensa_format_num_slots (isa, fmt)) 2679 return XTENSA_UNDEFINED; 2680 2681 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 2682 return xtensa_opcode_decode (isa, fmt, slot, slotbuf); 2683} 2684 2685 2686#ifdef TENSILICA_DEBUG 2687 2688/* For debugging, print out the mapping of opcode numbers to opcodes. */ 2689 2690static void 2691xtensa_print_insn_table (void) 2692{ 2693 int num_opcodes, num_operands; 2694 xtensa_opcode opcode; 2695 xtensa_isa isa = xtensa_default_isa; 2696 2697 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); 2698 for (opcode = 0; opcode < num_opcodes; opcode++) 2699 { 2700 int opn; 2701 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); 2702 num_operands = xtensa_opcode_num_operands (isa, opcode); 2703 for (opn = 0; opn < num_operands; opn++) 2704 { 2705 if (xtensa_operand_is_visible (isa, opcode, opn) == 0) 2706 continue; 2707 if (xtensa_operand_is_register (isa, opcode, opn) == 1) 2708 { 2709 xtensa_regfile opnd_rf = 2710 xtensa_operand_regfile (isa, opcode, opn); 2711 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); 2712 } 2713 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) 2714 fputs ("[lLr] ", stderr); 2715 else 2716 fputs ("i ", stderr); 2717 } 2718 fprintf (stderr, "\n"); 2719 } 2720} 2721 2722 2723static void 2724print_vliw_insn (xtensa_insnbuf vbuf) 2725{ 2726 xtensa_isa isa = xtensa_default_isa; 2727 xtensa_format f = xtensa_format_decode (isa, vbuf); 2728 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); 2729 int op; 2730 2731 fprintf (stderr, "format = %d\n", f); 2732 2733 for (op = 0; op < xtensa_format_num_slots (isa, f); op++) 2734 { 2735 xtensa_opcode opcode; 2736 const char *opname; 2737 int operands; 2738 2739 xtensa_format_get_slot (isa, f, op, vbuf, sbuf); 2740 opcode = xtensa_opcode_decode (isa, f, op, sbuf); 2741 opname = xtensa_opcode_name (isa, opcode); 2742 2743 fprintf (stderr, "op in slot %i is %s;\n", op, opname); 2744 fprintf (stderr, " operands = "); 2745 for (operands = 0; 2746 operands < xtensa_opcode_num_operands (isa, opcode); 2747 operands++) 2748 { 2749 unsigned int val; 2750 if (xtensa_operand_is_visible (isa, opcode, operands) == 0) 2751 continue; 2752 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); 2753 xtensa_operand_decode (isa, opcode, operands, &val); 2754 fprintf (stderr, "%d ", val); 2755 } 2756 fprintf (stderr, "\n"); 2757 } 2758 xtensa_insnbuf_free (isa, sbuf); 2759} 2760 2761#endif /* TENSILICA_DEBUG */ 2762 2763 2764static bool 2765is_direct_call_opcode (xtensa_opcode opcode) 2766{ 2767 xtensa_isa isa = xtensa_default_isa; 2768 int n, num_operands; 2769 2770 if (xtensa_opcode_is_call (isa, opcode) != 1) 2771 return false; 2772 2773 num_operands = xtensa_opcode_num_operands (isa, opcode); 2774 for (n = 0; n < num_operands; n++) 2775 { 2776 if (xtensa_operand_is_register (isa, opcode, n) == 0 2777 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) 2778 return true; 2779 } 2780 return false; 2781} 2782 2783 2784/* Convert from BFD relocation type code to slot and operand number. 2785 Returns non-zero on failure. */ 2786 2787static int 2788decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bool *is_alt) 2789{ 2790 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP 2791 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 2792 { 2793 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; 2794 *is_alt = false; 2795 } 2796 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 2797 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) 2798 { 2799 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; 2800 *is_alt = true; 2801 } 2802 else 2803 return -1; 2804 2805 return 0; 2806} 2807 2808 2809/* Convert from slot number to BFD relocation type code for the 2810 standard PC-relative relocations. Return BFD_RELOC_NONE on 2811 failure. */ 2812 2813static bfd_reloc_code_real_type 2814encode_reloc (int slot) 2815{ 2816 if (slot < 0 || slot > 14) 2817 return BFD_RELOC_NONE; 2818 2819 return BFD_RELOC_XTENSA_SLOT0_OP + slot; 2820} 2821 2822 2823/* Convert from slot numbers to BFD relocation type code for the 2824 "alternate" relocations. Return BFD_RELOC_NONE on failure. */ 2825 2826static bfd_reloc_code_real_type 2827encode_alt_reloc (int slot) 2828{ 2829 if (slot < 0 || slot > 14) 2830 return BFD_RELOC_NONE; 2831 2832 return BFD_RELOC_XTENSA_SLOT0_ALT + slot; 2833} 2834 2835 2836static void 2837xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, 2838 xtensa_format fmt, 2839 int slot, 2840 xtensa_opcode opcode, 2841 int operand, 2842 uint32 value, 2843 const char *file, 2844 unsigned int line) 2845{ 2846 uint32 valbuf = value; 2847 2848 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 2849 { 2850 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) 2851 == 1) 2852 as_bad_where ((char *) file, line, 2853 _("operand %d of '%s' has out of range value '%u'"), 2854 operand + 1, 2855 xtensa_opcode_name (xtensa_default_isa, opcode), 2856 value); 2857 else 2858 as_bad_where ((char *) file, line, 2859 _("operand %d of '%s' has invalid value '%u'"), 2860 operand + 1, 2861 xtensa_opcode_name (xtensa_default_isa, opcode), 2862 value); 2863 return; 2864 } 2865 2866 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, 2867 slotbuf, valbuf); 2868} 2869 2870 2871static uint32 2872xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, 2873 xtensa_format fmt, 2874 int slot, 2875 xtensa_opcode opcode, 2876 int opnum) 2877{ 2878 uint32 val = 0; 2879 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, 2880 fmt, slot, slotbuf, &val); 2881 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); 2882 return val; 2883} 2884 2885 2886/* Checks for rules from xtensa-relax tables. */ 2887 2888/* The routine xg_instruction_matches_option_term must return TRUE 2889 when a given option term is true. The meaning of all of the option 2890 terms is given interpretation by this function. */ 2891 2892static bool 2893xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) 2894{ 2895 if (strcmp (option->option_name, "realnop") == 0 2896 || startswith (option->option_name, "IsaUse")) 2897 { 2898 /* These conditions were evaluated statically when building the 2899 relaxation table. There's no need to reevaluate them now. */ 2900 return true; 2901 } 2902 else if (strcmp (option->option_name, "FREEREG") == 0) 2903 return insn->extra_arg.X_op == O_register; 2904 else 2905 { 2906 as_fatal (_("internal error: unknown option name '%s'"), 2907 option->option_name); 2908 } 2909} 2910 2911 2912static bool 2913xg_instruction_matches_or_options (TInsn *insn, 2914 const ReqOrOptionList *or_option) 2915{ 2916 const ReqOrOption *option; 2917 /* Must match each of the AND terms. */ 2918 for (option = or_option; option != NULL; option = option->next) 2919 { 2920 if (xg_instruction_matches_option_term (insn, option)) 2921 return true; 2922 } 2923 return false; 2924} 2925 2926 2927static bool 2928xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) 2929{ 2930 const ReqOption *req_options; 2931 /* Must match each of the AND terms. */ 2932 for (req_options = options; 2933 req_options != NULL; 2934 req_options = req_options->next) 2935 { 2936 /* Must match one of the OR clauses. */ 2937 if (!xg_instruction_matches_or_options (insn, 2938 req_options->or_option_terms)) 2939 return false; 2940 } 2941 return true; 2942} 2943 2944 2945/* Return the transition rule that matches or NULL if none matches. */ 2946 2947static bool 2948xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) 2949{ 2950 PreconditionList *condition_l; 2951 2952 if (rule->opcode != insn->opcode) 2953 return false; 2954 2955 for (condition_l = rule->conditions; 2956 condition_l != NULL; 2957 condition_l = condition_l->next) 2958 { 2959 expressionS *exp1; 2960 expressionS *exp2; 2961 Precondition *cond = condition_l->precond; 2962 2963 switch (cond->typ) 2964 { 2965 case OP_CONSTANT: 2966 /* The expression must be the constant. */ 2967 gas_assert (cond->op_num < insn->ntok); 2968 exp1 = &insn->tok[cond->op_num]; 2969 if (expr_is_const (exp1)) 2970 { 2971 switch (cond->cmp) 2972 { 2973 case OP_EQUAL: 2974 if (get_expr_const (exp1) != cond->op_data) 2975 return false; 2976 break; 2977 case OP_NOTEQUAL: 2978 if (get_expr_const (exp1) == cond->op_data) 2979 return false; 2980 break; 2981 default: 2982 return false; 2983 } 2984 } 2985 else if (expr_is_register (exp1)) 2986 { 2987 switch (cond->cmp) 2988 { 2989 case OP_EQUAL: 2990 if (get_expr_register (exp1) != cond->op_data) 2991 return false; 2992 break; 2993 case OP_NOTEQUAL: 2994 if (get_expr_register (exp1) == cond->op_data) 2995 return false; 2996 break; 2997 default: 2998 return false; 2999 } 3000 } 3001 else 3002 return false; 3003 break; 3004 3005 case OP_OPERAND: 3006 gas_assert (cond->op_num < insn->ntok); 3007 gas_assert (cond->op_data < insn->ntok); 3008 exp1 = &insn->tok[cond->op_num]; 3009 exp2 = &insn->tok[cond->op_data]; 3010 3011 switch (cond->cmp) 3012 { 3013 case OP_EQUAL: 3014 if (!expr_is_equal (exp1, exp2)) 3015 return false; 3016 break; 3017 case OP_NOTEQUAL: 3018 if (expr_is_equal (exp1, exp2)) 3019 return false; 3020 break; 3021 } 3022 break; 3023 3024 case OP_LITERAL: 3025 case OP_LABEL: 3026 default: 3027 return false; 3028 } 3029 } 3030 if (!xg_instruction_matches_options (insn, rule->options)) 3031 return false; 3032 3033 return true; 3034} 3035 3036 3037static int 3038transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) 3039{ 3040 bool a_greater = false; 3041 bool b_greater = false; 3042 3043 ReqOptionList *l_a = a->options; 3044 ReqOptionList *l_b = b->options; 3045 3046 /* We only care if they both are the same except for 3047 a const16 vs. an l32r. */ 3048 3049 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) 3050 { 3051 ReqOrOptionList *l_or_a = l_a->or_option_terms; 3052 ReqOrOptionList *l_or_b = l_b->or_option_terms; 3053 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) 3054 { 3055 if (l_or_a->is_true != l_or_b->is_true) 3056 return 0; 3057 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) 3058 { 3059 /* This is the case we care about. */ 3060 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 3061 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) 3062 { 3063 if (prefer_const16) 3064 a_greater = true; 3065 else 3066 b_greater = true; 3067 } 3068 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 3069 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) 3070 { 3071 if (prefer_const16) 3072 b_greater = true; 3073 else 3074 a_greater = true; 3075 } 3076 else 3077 return 0; 3078 } 3079 l_or_a = l_or_a->next; 3080 l_or_b = l_or_b->next; 3081 } 3082 if (l_or_a || l_or_b) 3083 return 0; 3084 3085 l_a = l_a->next; 3086 l_b = l_b->next; 3087 } 3088 if (l_a || l_b) 3089 return 0; 3090 3091 /* Incomparable if the substitution was used differently in two cases. */ 3092 if (a_greater && b_greater) 3093 return 0; 3094 3095 if (b_greater) 3096 return 1; 3097 if (a_greater) 3098 return -1; 3099 3100 return 0; 3101} 3102 3103 3104static TransitionRule * 3105xg_instruction_match (TInsn *insn) 3106{ 3107 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); 3108 TransitionList *l; 3109 gas_assert (insn->opcode < table->num_opcodes); 3110 3111 /* Walk through all of the possible transitions. */ 3112 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3113 { 3114 TransitionRule *rule = l->rule; 3115 if (xg_instruction_matches_rule (insn, rule)) 3116 return rule; 3117 } 3118 return NULL; 3119} 3120 3121 3122/* Various Other Internal Functions. */ 3123 3124static bool 3125is_unique_insn_expansion (TransitionRule *r) 3126{ 3127 if (!r->to_instr || r->to_instr->next != NULL) 3128 return false; 3129 if (r->to_instr->typ != INSTR_INSTR) 3130 return false; 3131 return true; 3132} 3133 3134 3135/* Check if there is exactly one relaxation for INSN that converts it to 3136 another instruction of equal or larger size. If so, and if TARG is 3137 non-null, go ahead and generate the relaxed instruction into TARG. If 3138 NARROW_ONLY is true, then only consider relaxations that widen a narrow 3139 instruction, i.e., ignore relaxations that convert to an instruction of 3140 equal size. In some contexts where this function is used, only 3141 a single widening is allowed and the NARROW_ONLY argument is used to 3142 exclude cases like ADDI being "widened" to an ADDMI, which may 3143 later be relaxed to an ADDMI/ADDI pair. */ 3144 3145bool 3146xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bool narrow_only) 3147{ 3148 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3149 TransitionList *l; 3150 TransitionRule *match = 0; 3151 3152 gas_assert (insn->insn_type == ITYPE_INSN); 3153 gas_assert (insn->opcode < table->num_opcodes); 3154 3155 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3156 { 3157 TransitionRule *rule = l->rule; 3158 3159 if (xg_instruction_matches_rule (insn, rule) 3160 && is_unique_insn_expansion (rule) 3161 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) 3162 <= xg_get_single_size (rule->to_instr->opcode))) 3163 { 3164 if (match) 3165 return false; 3166 match = rule; 3167 } 3168 } 3169 if (!match) 3170 return false; 3171 3172 if (targ) 3173 xg_build_to_insn (targ, insn, match->to_instr); 3174 return true; 3175} 3176 3177 3178/* Return the maximum number of bytes this opcode can expand to. */ 3179 3180static int 3181xg_get_max_insn_widen_size (xtensa_opcode opcode) 3182{ 3183 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3184 TransitionList *l; 3185 int max_size = xg_get_single_size (opcode); 3186 3187 gas_assert (opcode < table->num_opcodes); 3188 3189 for (l = table->table[opcode]; l != NULL; l = l->next) 3190 { 3191 TransitionRule *rule = l->rule; 3192 BuildInstr *build_list; 3193 int this_size = 0; 3194 3195 if (!rule) 3196 continue; 3197 build_list = rule->to_instr; 3198 if (is_unique_insn_expansion (rule)) 3199 { 3200 gas_assert (build_list->typ == INSTR_INSTR); 3201 this_size = xg_get_max_insn_widen_size (build_list->opcode); 3202 } 3203 else 3204 for (; build_list != NULL; build_list = build_list->next) 3205 { 3206 switch (build_list->typ) 3207 { 3208 case INSTR_INSTR: 3209 this_size += xg_get_single_size (build_list->opcode); 3210 break; 3211 case INSTR_LITERAL_DEF: 3212 case INSTR_LABEL_DEF: 3213 default: 3214 break; 3215 } 3216 } 3217 if (this_size > max_size) 3218 max_size = this_size; 3219 } 3220 return max_size; 3221} 3222 3223 3224/* Return the maximum number of literal bytes this opcode can generate. */ 3225 3226static int 3227xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) 3228{ 3229 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3230 TransitionList *l; 3231 int max_size = 0; 3232 3233 gas_assert (opcode < table->num_opcodes); 3234 3235 for (l = table->table[opcode]; l != NULL; l = l->next) 3236 { 3237 TransitionRule *rule = l->rule; 3238 BuildInstr *build_list; 3239 int this_size = 0; 3240 3241 if (!rule) 3242 continue; 3243 build_list = rule->to_instr; 3244 if (is_unique_insn_expansion (rule)) 3245 { 3246 gas_assert (build_list->typ == INSTR_INSTR); 3247 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); 3248 } 3249 else 3250 for (; build_list != NULL; build_list = build_list->next) 3251 { 3252 switch (build_list->typ) 3253 { 3254 case INSTR_LITERAL_DEF: 3255 /* Hard-coded 4-byte literal. */ 3256 this_size += 4; 3257 break; 3258 case INSTR_INSTR: 3259 case INSTR_LABEL_DEF: 3260 default: 3261 break; 3262 } 3263 } 3264 if (this_size > max_size) 3265 max_size = this_size; 3266 } 3267 return max_size; 3268} 3269 3270 3271static bool 3272xg_is_relaxable_insn (TInsn *insn, int lateral_steps) 3273{ 3274 int steps_taken = 0; 3275 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3276 TransitionList *l; 3277 3278 gas_assert (insn->insn_type == ITYPE_INSN); 3279 gas_assert (insn->opcode < table->num_opcodes); 3280 3281 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3282 { 3283 TransitionRule *rule = l->rule; 3284 3285 if (xg_instruction_matches_rule (insn, rule)) 3286 { 3287 if (steps_taken == lateral_steps) 3288 return true; 3289 steps_taken++; 3290 } 3291 } 3292 return false; 3293} 3294 3295 3296static symbolS * 3297get_special_literal_symbol (void) 3298{ 3299 static symbolS *sym = NULL; 3300 3301 if (sym == NULL) 3302 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); 3303 return sym; 3304} 3305 3306 3307static symbolS * 3308get_special_label_symbol (void) 3309{ 3310 static symbolS *sym = NULL; 3311 3312 if (sym == NULL) 3313 sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); 3314 return sym; 3315} 3316 3317 3318static bool 3319xg_valid_literal_expression (const expressionS *exp) 3320{ 3321 switch (exp->X_op) 3322 { 3323 case O_constant: 3324 case O_symbol: 3325 case O_big: 3326 case O_uminus: 3327 case O_subtract: 3328 case O_pltrel: 3329 case O_pcrel: 3330 case O_tlsfunc: 3331 case O_tlsarg: 3332 case O_tpoff: 3333 case O_dtpoff: 3334 return true; 3335 default: 3336 return false; 3337 } 3338} 3339 3340 3341/* This will check to see if the value can be converted into the 3342 operand type. It will return TRUE if it does not fit. */ 3343 3344static bool 3345xg_check_operand (int32 value, xtensa_opcode opcode, int operand) 3346{ 3347 uint32 valbuf = value; 3348 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 3349 return true; 3350 return false; 3351} 3352 3353 3354/* Assumes: All immeds are constants. Check that all constants fit 3355 into their immeds; return FALSE if not. */ 3356 3357static bool 3358xg_immeds_fit (const TInsn *insn) 3359{ 3360 xtensa_isa isa = xtensa_default_isa; 3361 int i; 3362 3363 int n = insn->ntok; 3364 gas_assert (insn->insn_type == ITYPE_INSN); 3365 for (i = 0; i < n; ++i) 3366 { 3367 const expressionS *exp = &insn->tok[i]; 3368 3369 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3370 continue; 3371 3372 switch (exp->X_op) 3373 { 3374 case O_register: 3375 case O_constant: 3376 if (xg_check_operand (exp->X_add_number, insn->opcode, i)) 3377 return false; 3378 break; 3379 3380 default: 3381 /* The symbol should have a fixup associated with it. */ 3382 gas_assert (false); 3383 break; 3384 } 3385 } 3386 return true; 3387} 3388 3389 3390/* This should only be called after we have an initial 3391 estimate of the addresses. */ 3392 3393static bool 3394xg_symbolic_immeds_fit (const TInsn *insn, 3395 segT pc_seg, 3396 fragS *pc_frag, 3397 offsetT pc_offset, 3398 long stretch) 3399{ 3400 xtensa_isa isa = xtensa_default_isa; 3401 symbolS *symbolP; 3402 fragS *sym_frag; 3403 offsetT target, pc; 3404 uint32 new_offset; 3405 int i; 3406 int n = insn->ntok; 3407 3408 gas_assert (insn->insn_type == ITYPE_INSN); 3409 3410 for (i = 0; i < n; ++i) 3411 { 3412 const expressionS *exp = &insn->tok[i]; 3413 3414 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3415 continue; 3416 3417 switch (exp->X_op) 3418 { 3419 case O_register: 3420 case O_constant: 3421 if (xg_check_operand (exp->X_add_number, insn->opcode, i)) 3422 return false; 3423 break; 3424 3425 case O_lo16: 3426 case O_hi16: 3427 /* Check for the worst case. */ 3428 if (xg_check_operand (0xffff, insn->opcode, i)) 3429 return false; 3430 break; 3431 3432 case O_symbol: 3433 /* We only allow symbols for PC-relative references. 3434 If pc_frag == 0, then we don't have frag locations yet. */ 3435 if (pc_frag == 0 3436 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) 3437 return false; 3438 3439 /* If it is a weak symbol or a symbol in a different section, 3440 it cannot be known to fit at assembly time. */ 3441 if (S_IS_WEAK (exp->X_add_symbol) 3442 || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) 3443 { 3444 /* For a direct call with --no-longcalls, be optimistic and 3445 assume it will be in range. If the symbol is weak and 3446 undefined, it may remain undefined at link-time, in which 3447 case it will have a zero value and almost certainly be out 3448 of range for a direct call; thus, relax for undefined weak 3449 symbols even if longcalls is not enabled. */ 3450 if (is_direct_call_opcode (insn->opcode) 3451 && ! pc_frag->tc_frag_data.use_longcalls 3452 && (! S_IS_WEAK (exp->X_add_symbol) 3453 || S_IS_DEFINED (exp->X_add_symbol))) 3454 return true; 3455 3456 return false; 3457 } 3458 3459 symbolP = exp->X_add_symbol; 3460 sym_frag = symbol_get_frag (symbolP); 3461 target = S_GET_VALUE (symbolP) + exp->X_add_number; 3462 pc = pc_frag->fr_address + pc_offset; 3463 3464 /* If frag has yet to be reached on this pass, assume it 3465 will move by STRETCH just as we did. If this is not so, 3466 it will be because some frag between grows, and that will 3467 force another pass. Beware zero-length frags. There 3468 should be a faster way to do this. */ 3469 3470 if (stretch != 0 3471 && sym_frag->relax_marker != pc_frag->relax_marker 3472 && S_GET_SEGMENT (symbolP) == pc_seg) 3473 { 3474 target += stretch; 3475 } 3476 3477 new_offset = target; 3478 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); 3479 if (xg_check_operand (new_offset, insn->opcode, i)) 3480 return false; 3481 break; 3482 3483 default: 3484 /* The symbol should have a fixup associated with it. */ 3485 return false; 3486 } 3487 } 3488 3489 return true; 3490} 3491 3492 3493/* Return TRUE on success. */ 3494 3495static bool 3496xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) 3497{ 3498 BuildOp *op; 3499 symbolS *sym; 3500 3501 tinsn_init (targ); 3502 targ->debug_line = insn->debug_line; 3503 targ->loc_directive_seen = insn->loc_directive_seen; 3504 switch (bi->typ) 3505 { 3506 case INSTR_INSTR: 3507 op = bi->ops; 3508 targ->opcode = bi->opcode; 3509 targ->insn_type = ITYPE_INSN; 3510 targ->is_specific_opcode = false; 3511 3512 for (; op != NULL; op = op->next) 3513 { 3514 int op_num = op->op_num; 3515 int op_data = op->op_data; 3516 3517 gas_assert (op->op_num < MAX_INSN_ARGS); 3518 3519 if (targ->ntok <= op_num) 3520 targ->ntok = op_num + 1; 3521 3522 switch (op->typ) 3523 { 3524 case OP_CONSTANT: 3525 set_expr_const (&targ->tok[op_num], op_data); 3526 break; 3527 case OP_OPERAND: 3528 gas_assert (op_data < insn->ntok); 3529 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3530 break; 3531 case OP_FREEREG: 3532 if (insn->extra_arg.X_op != O_register) 3533 return false; 3534 copy_expr (&targ->tok[op_num], &insn->extra_arg); 3535 break; 3536 case OP_LITERAL: 3537 sym = get_special_literal_symbol (); 3538 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3539 if (insn->tok[op_data].X_op == O_tlsfunc 3540 || insn->tok[op_data].X_op == O_tlsarg) 3541 copy_expr (&targ->extra_arg, &insn->tok[op_data]); 3542 break; 3543 case OP_LABEL: 3544 sym = get_special_label_symbol (); 3545 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3546 break; 3547 case OP_OPERAND_HI16U: 3548 case OP_OPERAND_LOW16U: 3549 gas_assert (op_data < insn->ntok); 3550 if (expr_is_const (&insn->tok[op_data])) 3551 { 3552 long val; 3553 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3554 val = xg_apply_userdef_op_fn (op->typ, 3555 targ->tok[op_num]. 3556 X_add_number); 3557 targ->tok[op_num].X_add_number = val; 3558 } 3559 else 3560 { 3561 /* For const16 we can create relocations for these. */ 3562 if (targ->opcode == XTENSA_UNDEFINED 3563 || (targ->opcode != xtensa_const16_opcode)) 3564 return false; 3565 gas_assert (op_data < insn->ntok); 3566 /* Need to build a O_lo16 or O_hi16. */ 3567 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3568 if (targ->tok[op_num].X_op == O_symbol) 3569 { 3570 if (op->typ == OP_OPERAND_HI16U) 3571 targ->tok[op_num].X_op = O_hi16; 3572 else if (op->typ == OP_OPERAND_LOW16U) 3573 targ->tok[op_num].X_op = O_lo16; 3574 else 3575 return false; 3576 } 3577 } 3578 break; 3579 default: 3580 /* currently handles: 3581 OP_OPERAND_LOW8 3582 OP_OPERAND_HI24S 3583 OP_OPERAND_F32MINUS */ 3584 if (xg_has_userdef_op_fn (op->typ)) 3585 { 3586 gas_assert (op_data < insn->ntok); 3587 if (expr_is_const (&insn->tok[op_data])) 3588 { 3589 long val; 3590 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3591 val = xg_apply_userdef_op_fn (op->typ, 3592 targ->tok[op_num]. 3593 X_add_number); 3594 targ->tok[op_num].X_add_number = val; 3595 } 3596 else 3597 return false; /* We cannot use a relocation for this. */ 3598 break; 3599 } 3600 gas_assert (0); 3601 break; 3602 } 3603 } 3604 break; 3605 3606 case INSTR_LITERAL_DEF: 3607 op = bi->ops; 3608 targ->opcode = XTENSA_UNDEFINED; 3609 targ->insn_type = ITYPE_LITERAL; 3610 targ->is_specific_opcode = false; 3611 for (; op != NULL; op = op->next) 3612 { 3613 int op_num = op->op_num; 3614 int op_data = op->op_data; 3615 gas_assert (op->op_num < MAX_INSN_ARGS); 3616 3617 if (targ->ntok <= op_num) 3618 targ->ntok = op_num + 1; 3619 3620 switch (op->typ) 3621 { 3622 case OP_OPERAND: 3623 gas_assert (op_data < insn->ntok); 3624 /* We can only pass resolvable literals through. */ 3625 if (!xg_valid_literal_expression (&insn->tok[op_data])) 3626 return false; 3627 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3628 break; 3629 case OP_LITERAL: 3630 case OP_CONSTANT: 3631 case OP_LABEL: 3632 default: 3633 gas_assert (0); 3634 break; 3635 } 3636 } 3637 break; 3638 3639 case INSTR_LABEL_DEF: 3640 op = bi->ops; 3641 targ->opcode = XTENSA_UNDEFINED; 3642 targ->insn_type = ITYPE_LABEL; 3643 targ->is_specific_opcode = false; 3644 /* Literal with no ops is a label? */ 3645 gas_assert (op == NULL); 3646 break; 3647 3648 default: 3649 gas_assert (0); 3650 } 3651 3652 return true; 3653} 3654 3655 3656/* Return TRUE on success. */ 3657 3658static bool 3659xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) 3660{ 3661 for (; bi != NULL; bi = bi->next) 3662 { 3663 TInsn *next_insn = istack_push_space (istack); 3664 3665 if (!xg_build_to_insn (next_insn, insn, bi)) 3666 return false; 3667 } 3668 return true; 3669} 3670 3671 3672/* Return TRUE on valid expansion. */ 3673 3674static bool 3675xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) 3676{ 3677 int stack_size = istack->ninsn; 3678 int steps_taken = 0; 3679 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3680 TransitionList *l; 3681 3682 gas_assert (insn->insn_type == ITYPE_INSN); 3683 gas_assert (insn->opcode < table->num_opcodes); 3684 3685 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3686 { 3687 TransitionRule *rule = l->rule; 3688 3689 if (xg_instruction_matches_rule (insn, rule)) 3690 { 3691 if (lateral_steps == steps_taken) 3692 { 3693 int i; 3694 3695 /* This is it. Expand the rule to the stack. */ 3696 if (!xg_build_to_stack (istack, insn, rule->to_instr)) 3697 return false; 3698 3699 /* Check to see if it fits. */ 3700 for (i = stack_size; i < istack->ninsn; i++) 3701 { 3702 TInsn *tinsn = &istack->insn[i]; 3703 3704 if (tinsn->insn_type == ITYPE_INSN 3705 && !tinsn_has_symbolic_operands (tinsn) 3706 && !xg_immeds_fit (tinsn)) 3707 { 3708 istack->ninsn = stack_size; 3709 return false; 3710 } 3711 } 3712 return true; 3713 } 3714 steps_taken++; 3715 } 3716 } 3717 return false; 3718} 3719 3720 3721/* Relax the assembly instruction at least "min_steps". 3722 Return the number of steps taken. 3723 3724 For relaxation to correctly terminate, every relaxation chain must 3725 terminate in one of two ways: 3726 3727 1. If the chain from one instruction to the next consists entirely of 3728 single instructions, then the chain *must* handle all possible 3729 immediates without failing. It must not ever fail because an 3730 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation 3731 chain is one example. L32R loads 32 bits, and there cannot be an 3732 immediate larger than 32 bits, so it satisfies this condition. 3733 Single instruction relaxation chains are as defined by 3734 xg_is_single_relaxable_instruction. 3735 3736 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., 3737 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J 3738 3739 Strictly speaking, in most cases you can violate condition 1 and be OK 3740 -- in particular when the last two instructions have the same single 3741 size. But nevertheless, you should guarantee the above two conditions. 3742 3743 We could fix this so that single-instruction expansions correctly 3744 terminate when they can't handle the range, but the error messages are 3745 worse, and it actually turns out that in every case but one (18-bit wide 3746 branches), you need a multi-instruction expansion to get the full range 3747 anyway. And because 18-bit branches are handled identically to 15-bit 3748 branches, there isn't any point in changing it. */ 3749 3750static int 3751xg_assembly_relax (IStack *istack, 3752 TInsn *insn, 3753 segT pc_seg, 3754 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ 3755 offsetT pc_offset, /* offset in fragment */ 3756 int min_steps, /* minimum conversion steps */ 3757 long stretch) /* number of bytes stretched so far */ 3758{ 3759 int steps_taken = 0; 3760 3761 /* Some of its immeds don't fit. Try to build a relaxed version. 3762 This may go through a couple of stages of single instruction 3763 transformations before we get there. */ 3764 3765 TInsn single_target; 3766 TInsn current_insn; 3767 int lateral_steps = 0; 3768 int istack_size = istack->ninsn; 3769 3770 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) 3771 && steps_taken >= min_steps) 3772 { 3773 istack_push (istack, insn); 3774 return steps_taken; 3775 } 3776 current_insn = *insn; 3777 3778 /* Walk through all of the single instruction expansions. */ 3779 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, false)) 3780 { 3781 steps_taken++; 3782 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, 3783 stretch)) 3784 { 3785 if (steps_taken >= min_steps) 3786 { 3787 istack_push (istack, &single_target); 3788 return steps_taken; 3789 } 3790 } 3791 current_insn = single_target; 3792 } 3793 3794 /* Now check for a multi-instruction expansion. */ 3795 while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) 3796 { 3797 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, 3798 stretch)) 3799 { 3800 if (steps_taken >= min_steps) 3801 { 3802 istack_push (istack, ¤t_insn); 3803 return steps_taken; 3804 } 3805 } 3806 steps_taken++; 3807 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) 3808 { 3809 if (steps_taken >= min_steps) 3810 return steps_taken; 3811 } 3812 lateral_steps++; 3813 istack->ninsn = istack_size; 3814 } 3815 3816 /* It's not going to work -- use the original. */ 3817 istack_push (istack, insn); 3818 return steps_taken; 3819} 3820 3821 3822static void 3823xg_finish_frag (char *last_insn, 3824 enum xtensa_relax_statesE frag_state, 3825 enum xtensa_relax_statesE slot0_state, 3826 int max_growth, 3827 bool is_insn) 3828{ 3829 /* Finish off this fragment so that it has at LEAST the desired 3830 max_growth. If it doesn't fit in this fragment, close this one 3831 and start a new one. In either case, return a pointer to the 3832 beginning of the growth area. */ 3833 3834 fragS *old_frag; 3835 3836 frag_grow (max_growth); 3837 old_frag = frag_now; 3838 3839 frag_now->fr_opcode = last_insn; 3840 if (is_insn) 3841 frag_now->tc_frag_data.is_insn = true; 3842 3843 frag_var (rs_machine_dependent, max_growth, max_growth, 3844 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); 3845 3846 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; 3847 xtensa_set_frag_assembly_state (frag_now); 3848 3849 /* Just to make sure that we did not split it up. */ 3850 gas_assert (old_frag->fr_next == frag_now); 3851} 3852 3853 3854/* Return TRUE if the target frag is one of the next non-empty frags. */ 3855 3856static bool 3857is_next_frag_target (const fragS *fragP, const fragS *target) 3858{ 3859 if (fragP == NULL) 3860 return false; 3861 3862 for (; fragP; fragP = fragP->fr_next) 3863 { 3864 if (fragP == target) 3865 return true; 3866 if (fragP->fr_fix != 0) 3867 return false; 3868 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) 3869 return false; 3870 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) 3871 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) 3872 return false; 3873 if (fragP->fr_type == rs_space) 3874 return false; 3875 } 3876 return false; 3877} 3878 3879 3880static bool 3881is_branch_jmp_to_next (TInsn *insn, fragS *fragP) 3882{ 3883 xtensa_isa isa = xtensa_default_isa; 3884 int i; 3885 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3886 int target_op = -1; 3887 symbolS *sym; 3888 fragS *target_frag; 3889 3890 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 3891 && xtensa_opcode_is_jump (isa, insn->opcode) != 1) 3892 return false; 3893 3894 for (i = 0; i < num_ops; i++) 3895 { 3896 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) 3897 { 3898 target_op = i; 3899 break; 3900 } 3901 } 3902 if (target_op == -1) 3903 return false; 3904 3905 if (insn->ntok <= target_op) 3906 return false; 3907 3908 if (insn->tok[target_op].X_op != O_symbol) 3909 return false; 3910 3911 sym = insn->tok[target_op].X_add_symbol; 3912 if (sym == NULL) 3913 return false; 3914 3915 if (insn->tok[target_op].X_add_number != 0) 3916 return false; 3917 3918 target_frag = symbol_get_frag (sym); 3919 if (target_frag == NULL) 3920 return false; 3921 3922 if (is_next_frag_target (fragP->fr_next, target_frag) 3923 && S_GET_VALUE (sym) == target_frag->fr_address) 3924 return true; 3925 3926 return false; 3927} 3928 3929 3930static void 3931xg_add_branch_and_loop_targets (TInsn *insn) 3932{ 3933 xtensa_isa isa = xtensa_default_isa; 3934 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3935 3936 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3937 { 3938 int i = 1; 3939 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3940 && insn->tok[i].X_op == O_symbol) 3941 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = true; 3942 return; 3943 } 3944 3945 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 3946 || xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3947 { 3948 int i; 3949 3950 for (i = 0; i < insn->ntok && i < num_ops; i++) 3951 { 3952 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3953 && insn->tok[i].X_op == O_symbol) 3954 { 3955 symbolS *sym = insn->tok[i].X_add_symbol; 3956 symbol_get_tc (sym)->is_branch_target = true; 3957 if (S_IS_DEFINED (sym)) 3958 symbol_get_frag (sym)->tc_frag_data.is_branch_target = true; 3959 } 3960 } 3961 } 3962} 3963 3964 3965/* Return FALSE if no error. */ 3966 3967static bool 3968xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) 3969{ 3970 int num_ops = 0; 3971 BuildOp *b_op; 3972 3973 switch (instr_spec->typ) 3974 { 3975 case INSTR_INSTR: 3976 new_insn->insn_type = ITYPE_INSN; 3977 new_insn->opcode = instr_spec->opcode; 3978 break; 3979 case INSTR_LITERAL_DEF: 3980 new_insn->insn_type = ITYPE_LITERAL; 3981 new_insn->opcode = XTENSA_UNDEFINED; 3982 break; 3983 case INSTR_LABEL_DEF: 3984 abort (); 3985 } 3986 new_insn->is_specific_opcode = false; 3987 new_insn->debug_line = old_insn->debug_line; 3988 new_insn->loc_directive_seen = old_insn->loc_directive_seen; 3989 3990 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) 3991 { 3992 expressionS *exp; 3993 const expressionS *src_exp; 3994 3995 num_ops++; 3996 switch (b_op->typ) 3997 { 3998 case OP_CONSTANT: 3999 /* The expression must be the constant. */ 4000 gas_assert (b_op->op_num < MAX_INSN_ARGS); 4001 exp = &new_insn->tok[b_op->op_num]; 4002 set_expr_const (exp, b_op->op_data); 4003 break; 4004 4005 case OP_OPERAND: 4006 gas_assert (b_op->op_num < MAX_INSN_ARGS); 4007 gas_assert (b_op->op_data < (unsigned) old_insn->ntok); 4008 src_exp = &old_insn->tok[b_op->op_data]; 4009 exp = &new_insn->tok[b_op->op_num]; 4010 copy_expr (exp, src_exp); 4011 break; 4012 4013 case OP_LITERAL: 4014 case OP_LABEL: 4015 as_bad (_("can't handle generation of literal/labels yet")); 4016 gas_assert (0); 4017 4018 default: 4019 as_bad (_("can't handle undefined OP TYPE")); 4020 gas_assert (0); 4021 } 4022 } 4023 4024 new_insn->ntok = num_ops; 4025 return false; 4026} 4027 4028 4029/* Return TRUE if it was simplified. */ 4030 4031static bool 4032xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) 4033{ 4034 TransitionRule *rule; 4035 BuildInstr *insn_spec; 4036 4037 if (old_insn->is_specific_opcode || !density_supported) 4038 return false; 4039 4040 rule = xg_instruction_match (old_insn); 4041 if (rule == NULL) 4042 return false; 4043 4044 insn_spec = rule->to_instr; 4045 /* There should only be one. */ 4046 gas_assert (insn_spec != NULL); 4047 gas_assert (insn_spec->next == NULL); 4048 if (insn_spec->next != NULL) 4049 return false; 4050 4051 xg_build_token_insn (insn_spec, old_insn, new_insn); 4052 4053 return true; 4054} 4055 4056 4057/* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> 4058 l32i.n. (2) Check the number of operands. (3) Place the instruction 4059 tokens into the stack or relax it and place multiple 4060 instructions/literals onto the stack. Return FALSE if no error. */ 4061 4062static bool 4063xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) 4064{ 4065 int noperands; 4066 TInsn new_insn; 4067 bool do_expand; 4068 4069 tinsn_init (&new_insn); 4070 4071 /* Narrow it if we can. xg_simplify_insn now does all the 4072 appropriate checking (e.g., for the density option). */ 4073 if (xg_simplify_insn (orig_insn, &new_insn)) 4074 orig_insn = &new_insn; 4075 4076 noperands = xtensa_opcode_num_operands (xtensa_default_isa, 4077 orig_insn->opcode); 4078 if (orig_insn->ntok < noperands) 4079 { 4080 as_bad (ngettext ("found %d operand for '%s': Expected %d", 4081 "found %d operands for '%s': Expected %d", 4082 orig_insn->ntok), 4083 orig_insn->ntok, 4084 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 4085 noperands); 4086 return true; 4087 } 4088 if (orig_insn->ntok > noperands) 4089 as_warn (ngettext ("found %d operand for '%s': Expected %d", 4090 "found %d operands for '%s': Expected %d", 4091 orig_insn->ntok), 4092 orig_insn->ntok, 4093 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 4094 noperands); 4095 4096 /* If there are not enough operands, we will assert above. If there 4097 are too many, just cut out the extras here. */ 4098 orig_insn->ntok = noperands; 4099 4100 if (tinsn_has_invalid_symbolic_operands (orig_insn)) 4101 return true; 4102 4103 /* Special case for extui opcode which has constraints not handled 4104 by the ordinary operand encoding checks. The number of operands 4105 and related syntax issues have already been checked. */ 4106 if (orig_insn->opcode == xtensa_extui_opcode) 4107 { 4108 int shiftimm = orig_insn->tok[2].X_add_number; 4109 int maskimm = orig_insn->tok[3].X_add_number; 4110 if (shiftimm + maskimm > 32) 4111 { 4112 as_bad (_("immediate operands sum to greater than 32")); 4113 return true; 4114 } 4115 } 4116 4117 /* If the instruction will definitely need to be relaxed, it is better 4118 to expand it now for better scheduling. Decide whether to expand 4119 now.... */ 4120 do_expand = (!orig_insn->is_specific_opcode && use_transform ()); 4121 4122 /* Calls should be expanded to longcalls only in the backend relaxation 4123 so that the assembly scheduler will keep the L32R/CALLX instructions 4124 adjacent. */ 4125 if (is_direct_call_opcode (orig_insn->opcode)) 4126 do_expand = false; 4127 4128 if (tinsn_has_symbolic_operands (orig_insn)) 4129 { 4130 /* The values of symbolic operands are not known yet, so only expand 4131 now if an operand is "complex" (e.g., difference of symbols) and 4132 will have to be stored as a literal regardless of the value. */ 4133 if (!tinsn_has_complex_operands (orig_insn)) 4134 do_expand = false; 4135 } 4136 else if (xg_immeds_fit (orig_insn)) 4137 do_expand = false; 4138 4139 if (do_expand) 4140 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); 4141 else 4142 istack_push (istack, orig_insn); 4143 4144 return false; 4145} 4146 4147 4148/* Return TRUE if the section flags are marked linkonce 4149 or the name is .gnu.linkonce.*. */ 4150 4151static int linkonce_len = sizeof (".gnu.linkonce.") - 1; 4152 4153static bool 4154get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) 4155{ 4156 flagword flags, link_once_flags; 4157 4158 flags = bfd_section_flags (sec); 4159 link_once_flags = (flags & SEC_LINK_ONCE); 4160 4161 /* Flags might not be set yet. */ 4162 if (!link_once_flags 4163 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) 4164 link_once_flags = SEC_LINK_ONCE; 4165 4166 return (link_once_flags != 0); 4167} 4168 4169 4170static void 4171xtensa_add_literal_sym (symbolS *sym) 4172{ 4173 sym_list *l; 4174 4175 l = XNEW (sym_list); 4176 l->sym = sym; 4177 l->next = literal_syms; 4178 literal_syms = l; 4179} 4180 4181 4182static symbolS * 4183xtensa_create_literal_symbol (segT sec, fragS *frag) 4184{ 4185 static int lit_num = 0; 4186 static char name[256]; 4187 symbolS *symbolP; 4188 4189 sprintf (name, ".L_lit_sym%d", lit_num); 4190 4191 /* Create a local symbol. If it is in a linkonce section, we have to 4192 be careful to make sure that if it is used in a relocation that the 4193 symbol will be in the output file. */ 4194 if (get_is_linkonce_section (stdoutput, sec)) 4195 { 4196 symbolP = symbol_new (name, sec, frag, 0); 4197 S_CLEAR_EXTERNAL (symbolP); 4198 /* symbolP->local = 1; */ 4199 } 4200 else 4201 symbolP = symbol_new (name, sec, frag, 0); 4202 4203 xtensa_add_literal_sym (symbolP); 4204 4205 lit_num++; 4206 return symbolP; 4207} 4208 4209 4210/* Currently all literals that are generated here are 32-bit L32R targets. */ 4211 4212static symbolS * 4213xg_assemble_literal (/* const */ TInsn *insn) 4214{ 4215 emit_state state; 4216 symbolS *lit_sym = NULL; 4217 bfd_reloc_code_real_type reloc; 4218 bool pcrel = false; 4219 char *p; 4220 4221 /* size = 4 for L32R. It could easily be larger when we move to 4222 larger constants. Add a parameter later. */ 4223 offsetT litsize = 4; 4224 offsetT litalign = 2; /* 2^2 = 4 */ 4225 expressionS saved_loc; 4226 expressionS * emit_val; 4227 4228 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); 4229 4230 gas_assert (insn->insn_type == ITYPE_LITERAL); 4231 gas_assert (insn->ntok == 1); /* must be only one token here */ 4232 4233 xtensa_switch_to_literal_fragment (&state); 4234 4235 emit_val = &insn->tok[0]; 4236 if (emit_val->X_op == O_big) 4237 { 4238 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; 4239 if (size > litsize) 4240 { 4241 /* This happens when someone writes a "movi a2, big_number". */ 4242 as_bad_where (frag_now->fr_file, frag_now->fr_line, 4243 _("invalid immediate")); 4244 xtensa_restore_emit_state (&state); 4245 return NULL; 4246 } 4247 } 4248 4249 /* Force a 4-byte align here. Note that this opens a new frag, so all 4250 literals done with this function have a frag to themselves. That's 4251 important for the way text section literals work. */ 4252 frag_align (litalign, 0, 0); 4253 record_alignment (now_seg, litalign); 4254 4255 switch (emit_val->X_op) 4256 { 4257 case O_pcrel: 4258 pcrel = true; 4259 /* fall through */ 4260 case O_pltrel: 4261 case O_tlsfunc: 4262 case O_tlsarg: 4263 case O_tpoff: 4264 case O_dtpoff: 4265 p = frag_more (litsize); 4266 xtensa_set_frag_assembly_state (frag_now); 4267 reloc = map_operator_to_reloc (emit_val->X_op, true); 4268 if (emit_val->X_add_symbol) 4269 emit_val->X_op = O_symbol; 4270 else 4271 emit_val->X_op = O_constant; 4272 fix_new_exp (frag_now, p - frag_now->fr_literal, 4273 litsize, emit_val, pcrel, reloc); 4274 break; 4275 4276 default: 4277 emit_expr (emit_val, litsize); 4278 break; 4279 } 4280 4281 gas_assert (frag_now->tc_frag_data.literal_frag == NULL); 4282 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4283 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4284 lit_sym = frag_now->fr_symbol; 4285 4286 /* Go back. */ 4287 xtensa_restore_emit_state (&state); 4288 return lit_sym; 4289} 4290 4291 4292static void 4293xg_assemble_literal_space (/* const */ int size, int slot) 4294{ 4295 emit_state state; 4296 /* We might have to do something about this alignment. It only 4297 takes effect if something is placed here. */ 4298 offsetT litalign = 2; /* 2^2 = 4 */ 4299 fragS *lit_saved_frag; 4300 4301 gas_assert (size % 4 == 0); 4302 4303 xtensa_switch_to_literal_fragment (&state); 4304 4305 /* Force a 4-byte align here. */ 4306 frag_align (litalign, 0, 0); 4307 record_alignment (now_seg, litalign); 4308 4309 frag_grow (size); 4310 4311 lit_saved_frag = frag_now; 4312 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4313 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4314 xg_finish_frag (0, RELAX_LITERAL, 0, size, false); 4315 4316 /* Go back. */ 4317 xtensa_restore_emit_state (&state); 4318 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; 4319} 4320 4321 4322/* Put in a fixup record based on the opcode. 4323 Return TRUE on success. */ 4324 4325static bool 4326xg_add_opcode_fix (TInsn *tinsn, 4327 int opnum, 4328 xtensa_format fmt, 4329 int slot, 4330 expressionS *exp, 4331 fragS *fragP, 4332 offsetT offset) 4333{ 4334 xtensa_opcode opcode = tinsn->opcode; 4335 bfd_reloc_code_real_type reloc; 4336 reloc_howto_type *howto; 4337 int fmt_length; 4338 fixS *the_fix; 4339 4340 reloc = BFD_RELOC_NONE; 4341 4342 /* First try the special cases for "alternate" relocs. */ 4343 if (opcode == xtensa_l32r_opcode) 4344 { 4345 if (fragP->tc_frag_data.use_absolute_literals) 4346 reloc = encode_alt_reloc (slot); 4347 } 4348 else if (opcode == xtensa_const16_opcode) 4349 { 4350 if (exp->X_op == O_lo16) 4351 { 4352 reloc = encode_reloc (slot); 4353 exp->X_op = O_symbol; 4354 } 4355 else if (exp->X_op == O_hi16) 4356 { 4357 reloc = encode_alt_reloc (slot); 4358 exp->X_op = O_symbol; 4359 } 4360 } 4361 4362 if (opnum != get_relaxable_immed (opcode)) 4363 { 4364 as_bad (_("invalid relocation for operand %i of '%s'"), 4365 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4366 return false; 4367 } 4368 4369 /* Handle erroneous "@h" and "@l" expressions here before they propagate 4370 into the symbol table where the generic portions of the assembler 4371 won't know what to do with them. */ 4372 if (exp->X_op == O_lo16 || exp->X_op == O_hi16) 4373 { 4374 as_bad (_("invalid expression for operand %i of '%s'"), 4375 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4376 return false; 4377 } 4378 4379 /* Next try the generic relocs. */ 4380 if (reloc == BFD_RELOC_NONE) 4381 reloc = encode_reloc (slot); 4382 if (reloc == BFD_RELOC_NONE) 4383 { 4384 as_bad (_("invalid relocation in instruction slot %i"), slot); 4385 return false; 4386 } 4387 4388 howto = bfd_reloc_type_lookup (stdoutput, reloc); 4389 if (!howto) 4390 { 4391 as_bad (_("undefined symbol for opcode \"%s\""), 4392 xtensa_opcode_name (xtensa_default_isa, opcode)); 4393 return false; 4394 } 4395 4396 fmt_length = xtensa_format_length (xtensa_default_isa, fmt); 4397 the_fix = fix_new_exp (fragP, offset, fmt_length, exp, 4398 howto->pc_relative, reloc); 4399 the_fix->fx_no_overflow = 1; 4400 the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; 4401 the_fix->tc_fix_data.X_add_number = exp->X_add_number; 4402 the_fix->tc_fix_data.slot = slot; 4403 4404 return true; 4405} 4406 4407 4408static bool 4409xg_emit_insn_to_buf (TInsn *tinsn, 4410 char *buf, 4411 fragS *fragP, 4412 offsetT offset, 4413 bool build_fix) 4414{ 4415 static xtensa_insnbuf insnbuf = NULL; 4416 bool has_symbolic_immed = false; 4417 bool ok = true; 4418 4419 if (!insnbuf) 4420 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4421 4422 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); 4423 if (has_symbolic_immed && build_fix) 4424 { 4425 /* Add a fixup. */ 4426 xtensa_format fmt = xg_get_single_format (tinsn->opcode); 4427 int slot = xg_get_single_slot (tinsn->opcode); 4428 int opnum = get_relaxable_immed (tinsn->opcode); 4429 expressionS *exp = &tinsn->tok[opnum]; 4430 4431 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) 4432 ok = false; 4433 } 4434 fragP->tc_frag_data.is_insn = true; 4435 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4436 (unsigned char *) buf, 0); 4437 return ok; 4438} 4439 4440 4441static void 4442xg_resolve_literals (TInsn *insn, symbolS *lit_sym) 4443{ 4444 symbolS *sym = get_special_literal_symbol (); 4445 int i; 4446 if (lit_sym == 0) 4447 return; 4448 gas_assert (insn->insn_type == ITYPE_INSN); 4449 for (i = 0; i < insn->ntok; i++) 4450 if (insn->tok[i].X_add_symbol == sym) 4451 insn->tok[i].X_add_symbol = lit_sym; 4452 4453} 4454 4455 4456static void 4457xg_resolve_labels (TInsn *insn, symbolS *label_sym) 4458{ 4459 symbolS *sym = get_special_label_symbol (); 4460 int i; 4461 for (i = 0; i < insn->ntok; i++) 4462 if (insn->tok[i].X_add_symbol == sym) 4463 insn->tok[i].X_add_symbol = label_sym; 4464 4465} 4466 4467 4468/* Return TRUE if the instruction can write to the specified 4469 integer register. */ 4470 4471static bool 4472is_register_writer (const TInsn *insn, const char *regset, int regnum) 4473{ 4474 int i; 4475 int num_ops; 4476 xtensa_isa isa = xtensa_default_isa; 4477 4478 num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 4479 4480 for (i = 0; i < num_ops; i++) 4481 { 4482 char inout; 4483 inout = xtensa_operand_inout (isa, insn->opcode, i); 4484 if ((inout == 'o' || inout == 'm') 4485 && xtensa_operand_is_register (isa, insn->opcode, i) == 1) 4486 { 4487 xtensa_regfile opnd_rf = 4488 xtensa_operand_regfile (isa, insn->opcode, i); 4489 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) 4490 { 4491 if ((insn->tok[i].X_op == O_register) 4492 && (insn->tok[i].X_add_number == regnum)) 4493 return true; 4494 } 4495 } 4496 } 4497 return false; 4498} 4499 4500 4501static bool 4502is_bad_loopend_opcode (const TInsn *tinsn) 4503{ 4504 xtensa_opcode opcode = tinsn->opcode; 4505 4506 if (opcode == XTENSA_UNDEFINED) 4507 return false; 4508 4509 if (opcode == xtensa_call0_opcode 4510 || opcode == xtensa_callx0_opcode 4511 || opcode == xtensa_call4_opcode 4512 || opcode == xtensa_callx4_opcode 4513 || opcode == xtensa_call8_opcode 4514 || opcode == xtensa_callx8_opcode 4515 || opcode == xtensa_call12_opcode 4516 || opcode == xtensa_callx12_opcode 4517 || opcode == xtensa_isync_opcode 4518 || opcode == xtensa_ret_opcode 4519 || opcode == xtensa_ret_n_opcode 4520 || opcode == xtensa_retw_opcode 4521 || opcode == xtensa_retw_n_opcode 4522 || opcode == xtensa_waiti_opcode 4523 || opcode == xtensa_rsr_lcount_opcode) 4524 return true; 4525 4526 return false; 4527} 4528 4529 4530/* Labels that begin with ".Ln" or ".LM" are unaligned. 4531 This allows the debugger to add unaligned labels. 4532 Also, the assembler generates stabs labels that need 4533 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ 4534 4535static bool 4536is_unaligned_label (symbolS *sym) 4537{ 4538 const char *name = S_GET_NAME (sym); 4539 static size_t fake_size = 0; 4540 4541 if (name 4542 && name[0] == '.' 4543 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) 4544 return true; 4545 4546 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ 4547 if (fake_size == 0) 4548 fake_size = strlen (FAKE_LABEL_NAME); 4549 4550 if (name 4551 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 4552 && (name[fake_size] == 'F' 4553 || name[fake_size] == 'L' 4554 || (name[fake_size] == 'e' 4555 && startswith (name + fake_size, "endfunc")))) 4556 return true; 4557 4558 return false; 4559} 4560 4561 4562static fragS * 4563next_non_empty_frag (const fragS *fragP) 4564{ 4565 fragS *next_fragP = fragP->fr_next; 4566 4567 /* Sometimes an empty will end up here due storage allocation issues. 4568 So we have to skip until we find something legit. */ 4569 while (next_fragP && next_fragP->fr_fix == 0) 4570 next_fragP = next_fragP->fr_next; 4571 4572 if (next_fragP == NULL || next_fragP->fr_fix == 0) 4573 return NULL; 4574 4575 return next_fragP; 4576} 4577 4578 4579static bool 4580next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) 4581{ 4582 xtensa_opcode out_opcode; 4583 const fragS *next_fragP = next_non_empty_frag (fragP); 4584 4585 if (next_fragP == NULL) 4586 return false; 4587 4588 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); 4589 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) 4590 { 4591 *opcode = out_opcode; 4592 return true; 4593 } 4594 return false; 4595} 4596 4597 4598static int 4599frag_format_size (const fragS *fragP) 4600{ 4601 static xtensa_insnbuf insnbuf = NULL; 4602 xtensa_isa isa = xtensa_default_isa; 4603 xtensa_format fmt; 4604 int fmt_size; 4605 4606 if (!insnbuf) 4607 insnbuf = xtensa_insnbuf_alloc (isa); 4608 4609 if (fragP == NULL) 4610 return XTENSA_UNDEFINED; 4611 4612 xtensa_insnbuf_from_chars (isa, insnbuf, 4613 (unsigned char *) fragP->fr_literal, 0); 4614 4615 fmt = xtensa_format_decode (isa, insnbuf); 4616 if (fmt == XTENSA_UNDEFINED) 4617 return XTENSA_UNDEFINED; 4618 fmt_size = xtensa_format_length (isa, fmt); 4619 4620 /* If the next format won't be changing due to relaxation, just 4621 return the length of the first format. */ 4622 if (fragP->fr_opcode != fragP->fr_literal) 4623 return fmt_size; 4624 4625 /* If during relaxation we have to pull an instruction out of a 4626 multi-slot instruction, we will return the more conservative 4627 number. This works because alignment on bigger instructions 4628 is more restrictive than alignment on smaller instructions. 4629 This is more conservative than we would like, but it happens 4630 infrequently. */ 4631 4632 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) 4633 return fmt_size; 4634 4635 /* If we aren't doing one of our own relaxations or it isn't 4636 slot-based, then the insn size won't change. */ 4637 if (fragP->fr_type != rs_machine_dependent) 4638 return fmt_size; 4639 if (fragP->fr_subtype != RELAX_SLOTS) 4640 return fmt_size; 4641 4642 /* If an instruction is about to grow, return the longer size. */ 4643 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 4644 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 4645 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) 4646 { 4647 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first 4648 instruction in the relaxed version is of length 3. (The case 4649 where we have to pull the instruction out of a FLIX bundle 4650 is handled conservatively above.) However, frags with opcodes 4651 that are expanding to wide branches end up having formats that 4652 are not determinable by the RELAX_IMMED_STEPX enumeration, and 4653 we can't tell directly what format the relaxer picked. This 4654 is a wart in the design of the relaxer that should someday be 4655 fixed, but would require major changes, or at least should 4656 be accompanied by major changes to make use of that data. 4657 4658 In any event, we can tell that we are expanding from a single-slot 4659 format to a wider one with the logic below. */ 4660 4661 int i; 4662 int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; 4663 4664 for (i = 0; i < xtensa_isa_num_formats (isa); i++) 4665 { 4666 if (relaxed_size == xtensa_format_length (isa, i)) 4667 return relaxed_size; 4668 } 4669 4670 return 3; 4671 } 4672 4673 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 4674 return 2 + fragP->tc_frag_data.text_expansion[0]; 4675 4676 return fmt_size; 4677} 4678 4679 4680static int 4681next_frag_format_size (const fragS *fragP) 4682{ 4683 const fragS *next_fragP = next_non_empty_frag (fragP); 4684 return frag_format_size (next_fragP); 4685} 4686 4687 4688/* In early Xtensa Processors, for reasons that are unclear, the ISA 4689 required two-byte instructions to be treated as three-byte instructions 4690 for loop instruction alignment. This restriction was removed beginning 4691 with Xtensa LX. Now the only requirement on loop instruction alignment 4692 is that the first instruction of the loop must appear at an address that 4693 does not cross a fetch boundary. */ 4694 4695static int 4696get_loop_align_size (int insn_size) 4697{ 4698 if (insn_size == XTENSA_UNDEFINED) 4699 return xtensa_fetch_width; 4700 4701 if (enforce_three_byte_loop_align && insn_size == 2) 4702 return 3; 4703 4704 return insn_size; 4705} 4706 4707 4708/* If the next legit fragment is an end-of-loop marker, 4709 switch its state so it will instantiate a NOP. */ 4710 4711static void 4712update_next_frag_state (fragS *fragP) 4713{ 4714 fragS *next_fragP = fragP->fr_next; 4715 fragS *new_target = NULL; 4716 4717 if (align_targets) 4718 { 4719 /* We are guaranteed there will be one of these... */ 4720 while (!(next_fragP->fr_type == rs_machine_dependent 4721 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4722 || next_fragP->fr_subtype == RELAX_UNREACHABLE))) 4723 next_fragP = next_fragP->fr_next; 4724 4725 gas_assert (next_fragP->fr_type == rs_machine_dependent 4726 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4727 || next_fragP->fr_subtype == RELAX_UNREACHABLE)); 4728 4729 /* ...and one of these. */ 4730 new_target = next_fragP->fr_next; 4731 while (!(new_target->fr_type == rs_machine_dependent 4732 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4733 || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) 4734 new_target = new_target->fr_next; 4735 4736 gas_assert (new_target->fr_type == rs_machine_dependent 4737 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4738 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); 4739 } 4740 4741 while (next_fragP && next_fragP->fr_fix == 0) 4742 { 4743 if (next_fragP->fr_type == rs_machine_dependent 4744 && next_fragP->fr_subtype == RELAX_LOOP_END) 4745 { 4746 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; 4747 return; 4748 } 4749 4750 next_fragP = next_fragP->fr_next; 4751 } 4752} 4753 4754 4755static bool 4756next_frag_is_branch_target (const fragS *fragP) 4757{ 4758 /* Sometimes an empty will end up here due to storage allocation issues, 4759 so we have to skip until we find something legit. */ 4760 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4761 { 4762 if (fragP->tc_frag_data.is_branch_target) 4763 return true; 4764 if (fragP->fr_fix != 0) 4765 break; 4766 } 4767 return false; 4768} 4769 4770 4771static bool 4772next_frag_is_loop_target (const fragS *fragP) 4773{ 4774 /* Sometimes an empty will end up here due storage allocation issues. 4775 So we have to skip until we find something legit. */ 4776 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4777 { 4778 if (fragP->tc_frag_data.is_loop_target) 4779 return true; 4780 if (fragP->fr_fix != 0) 4781 break; 4782 } 4783 return false; 4784} 4785 4786 4787/* As specified in the relaxation table, when a loop instruction is 4788 relaxed, there are 24 bytes between the loop instruction itself and 4789 the first instruction in the loop. */ 4790 4791#define RELAXED_LOOP_INSN_BYTES 24 4792 4793static addressT 4794next_frag_pre_opcode_bytes (const fragS *fragp) 4795{ 4796 const fragS *next_fragp = fragp->fr_next; 4797 xtensa_opcode next_opcode; 4798 4799 if (!next_frag_opcode_is_loop (fragp, &next_opcode)) 4800 return 0; 4801 4802 /* Sometimes an empty will end up here due to storage allocation issues, 4803 so we have to skip until we find something legit. */ 4804 while (next_fragp->fr_fix == 0) 4805 next_fragp = next_fragp->fr_next; 4806 4807 if (next_fragp->fr_type != rs_machine_dependent) 4808 return 0; 4809 4810 /* There is some implicit knowledge encoded in here. 4811 The LOOP instructions that are NOT RELAX_IMMED have 4812 been relaxed. Note that we can assume that the LOOP 4813 instruction is in slot 0 because loops aren't bundleable. */ 4814 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) 4815 return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; 4816 4817 return 0; 4818} 4819 4820 4821/* Mark a location where we can later insert literal frags. Update 4822 the section's literal_pool_loc, so subsequent literals can be 4823 placed nearest to their use. */ 4824 4825static void 4826xtensa_mark_literal_pool_location (void) 4827{ 4828 /* Any labels pointing to the current location need 4829 to be adjusted to after the literal pool. */ 4830 fragS *pool_location; 4831 4832 if (use_literal_section) 4833 return; 4834 4835 /* We stash info in these frags so we can later move the literal's 4836 fixes into this frchain's fix list. */ 4837 pool_location = frag_now; 4838 frag_now->tc_frag_data.lit_frchain = frchain_now; 4839 frag_now->tc_frag_data.literal_frag = frag_now; 4840 /* Just record this frag. */ 4841 xtensa_maybe_create_literal_pool_frag (false, false); 4842 frag_variant (rs_machine_dependent, 0, 0, 4843 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); 4844 xtensa_set_frag_assembly_state (frag_now); 4845 frag_now->tc_frag_data.lit_seg = now_seg; 4846 frag_variant (rs_machine_dependent, 0, 0, 4847 RELAX_LITERAL_POOL_END, NULL, 0, NULL); 4848 xtensa_set_frag_assembly_state (frag_now); 4849 4850 set_literal_pool_location (now_seg, pool_location); 4851} 4852 4853 4854/* Build a nop of the correct size into tinsn. */ 4855 4856static void 4857build_nop (TInsn *tinsn, int size) 4858{ 4859 tinsn_init (tinsn); 4860 switch (size) 4861 { 4862 case 2: 4863 tinsn->opcode = xtensa_nop_n_opcode; 4864 tinsn->ntok = 0; 4865 if (tinsn->opcode == XTENSA_UNDEFINED) 4866 as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); 4867 break; 4868 4869 case 3: 4870 if (xtensa_nop_opcode == XTENSA_UNDEFINED) 4871 { 4872 tinsn->opcode = xtensa_or_opcode; 4873 set_expr_const (&tinsn->tok[0], 1); 4874 set_expr_const (&tinsn->tok[1], 1); 4875 set_expr_const (&tinsn->tok[2], 1); 4876 tinsn->ntok = 3; 4877 } 4878 else 4879 tinsn->opcode = xtensa_nop_opcode; 4880 4881 gas_assert (tinsn->opcode != XTENSA_UNDEFINED); 4882 } 4883} 4884 4885 4886/* Assemble a NOP of the requested size in the buffer. User must have 4887 allocated "buf" with at least "size" bytes. */ 4888 4889static void 4890assemble_nop (int size, char *buf) 4891{ 4892 static xtensa_insnbuf insnbuf = NULL; 4893 TInsn tinsn; 4894 4895 build_nop (&tinsn, size); 4896 4897 if (!insnbuf) 4898 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4899 4900 tinsn_to_insnbuf (&tinsn, insnbuf); 4901 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4902 (unsigned char *) buf, 0); 4903} 4904 4905 4906/* Return the number of bytes for the offset of the expanded loop 4907 instruction. This should be incorporated into the relaxation 4908 specification but is hard-coded here. This is used to auto-align 4909 the loop instruction. It is invalid to call this function if the 4910 configuration does not have loops or if the opcode is not a loop 4911 opcode. */ 4912 4913static addressT 4914get_expanded_loop_offset (xtensa_opcode opcode) 4915{ 4916 /* This is the OFFSET of the loop instruction in the expanded loop. 4917 This MUST correspond directly to the specification of the loop 4918 expansion. It will be validated on fragment conversion. */ 4919 gas_assert (opcode != XTENSA_UNDEFINED); 4920 if (opcode == xtensa_loop_opcode) 4921 return 0; 4922 if (opcode == xtensa_loopnez_opcode) 4923 return 3; 4924 if (opcode == xtensa_loopgtz_opcode) 4925 return 6; 4926 as_fatal (_("get_expanded_loop_offset: invalid opcode")); 4927 return 0; 4928} 4929 4930 4931static fragS * 4932get_literal_pool_location (segT seg) 4933{ 4934 if (auto_litpools) 4935 { 4936 struct litpool_seg *lps = litpool_seg_list.next; 4937 struct litpool_frag *lpf; 4938 for ( ; lps && lps->seg->id != seg->id; lps = lps->next) 4939 ; 4940 if (lps) 4941 { 4942 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) 4943 { /* Skip "candidates" for now. */ 4944 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && 4945 lpf->priority == 1) 4946 return lpf->fragP; 4947 } 4948 /* Must convert a lower-priority pool. */ 4949 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) 4950 { 4951 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN) 4952 return lpf->fragP; 4953 } 4954 /* Still no match -- try for a low priority pool. */ 4955 for (lpf = lps->frag_list.prev; lpf->fragP; lpf = lpf->prev) 4956 { 4957 if (lpf->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) 4958 return lpf->fragP; 4959 } 4960 } 4961 } 4962 return seg_info (seg)->tc_segment_info_data.literal_pool_loc; 4963} 4964 4965 4966static void 4967set_literal_pool_location (segT seg, fragS *literal_pool_loc) 4968{ 4969 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; 4970} 4971 4972 4973/* Set frag assembly state should be called when a new frag is 4974 opened and after a frag has been closed. */ 4975 4976static void 4977xtensa_set_frag_assembly_state (fragS *fragP) 4978{ 4979 if (!density_supported) 4980 fragP->tc_frag_data.is_no_density = true; 4981 4982 /* This function is called from subsegs_finish, which is called 4983 after xtensa_end, so we can't use "use_transform" or 4984 "use_schedule" here. */ 4985 if (!directive_state[directive_transform]) 4986 fragP->tc_frag_data.is_no_transform = true; 4987 if (directive_state[directive_longcalls]) 4988 fragP->tc_frag_data.use_longcalls = true; 4989 fragP->tc_frag_data.use_absolute_literals = 4990 directive_state[directive_absolute_literals]; 4991 fragP->tc_frag_data.is_assembly_state_set = true; 4992} 4993 4994 4995static bool 4996relaxable_section (asection *sec) 4997{ 4998 return ((sec->flags & SEC_DEBUGGING) == 0 4999 && strcmp (sec->name, ".eh_frame") != 0); 5000} 5001 5002 5003static void 5004xtensa_mark_frags_for_org (void) 5005{ 5006 segT *seclist; 5007 5008 /* Walk over each fragment of all of the current segments. If we find 5009 a .org frag in any of the segments, mark all frags prior to it as 5010 "no transform", which will prevent linker optimizations from messing 5011 up the .org distance. This should be done after 5012 xtensa_find_unmarked_state_frags, because we don't want to worry here 5013 about that function trashing the data we save here. */ 5014 5015 for (seclist = &stdoutput->sections; 5016 seclist && *seclist; 5017 seclist = &(*seclist)->next) 5018 { 5019 segT sec = *seclist; 5020 segment_info_type *seginfo; 5021 fragS *fragP; 5022 flagword flags; 5023 flags = bfd_section_flags (sec); 5024 if (flags & SEC_DEBUGGING) 5025 continue; 5026 if (!(flags & SEC_ALLOC)) 5027 continue; 5028 5029 seginfo = seg_info (sec); 5030 if (seginfo && seginfo->frchainP) 5031 { 5032 fragS *last_fragP = seginfo->frchainP->frch_root; 5033 for (fragP = seginfo->frchainP->frch_root; fragP; 5034 fragP = fragP->fr_next) 5035 { 5036 /* cvt_frag_to_fill has changed the fr_type of org frags to 5037 rs_fill, so use the value as cached in rs_subtype here. */ 5038 if (fragP->fr_subtype == RELAX_ORG) 5039 { 5040 while (last_fragP != fragP->fr_next) 5041 { 5042 last_fragP->tc_frag_data.is_no_transform = true; 5043 last_fragP = last_fragP->fr_next; 5044 } 5045 } 5046 } 5047 } 5048 } 5049} 5050 5051 5052static void 5053xtensa_find_unmarked_state_frags (void) 5054{ 5055 segT *seclist; 5056 5057 /* Walk over each fragment of all of the current segments. For each 5058 unmarked fragment, mark it with the same info as the previous 5059 fragment. */ 5060 for (seclist = &stdoutput->sections; 5061 seclist && *seclist; 5062 seclist = &(*seclist)->next) 5063 { 5064 segT sec = *seclist; 5065 segment_info_type *seginfo; 5066 fragS *fragP; 5067 flagword flags; 5068 flags = bfd_section_flags (sec); 5069 if (flags & SEC_DEBUGGING) 5070 continue; 5071 if (!(flags & SEC_ALLOC)) 5072 continue; 5073 5074 seginfo = seg_info (sec); 5075 if (seginfo && seginfo->frchainP) 5076 { 5077 fragS *last_fragP = 0; 5078 for (fragP = seginfo->frchainP->frch_root; fragP; 5079 fragP = fragP->fr_next) 5080 { 5081 if (fragP->fr_fix != 0 5082 && !fragP->tc_frag_data.is_assembly_state_set) 5083 { 5084 if (last_fragP == 0) 5085 { 5086 as_warn_where (fragP->fr_file, fragP->fr_line, 5087 _("assembly state not set for first frag in section %s"), 5088 sec->name); 5089 } 5090 else 5091 { 5092 fragP->tc_frag_data.is_assembly_state_set = true; 5093 fragP->tc_frag_data.is_no_density = 5094 last_fragP->tc_frag_data.is_no_density; 5095 fragP->tc_frag_data.is_no_transform = 5096 last_fragP->tc_frag_data.is_no_transform; 5097 fragP->tc_frag_data.use_longcalls = 5098 last_fragP->tc_frag_data.use_longcalls; 5099 fragP->tc_frag_data.use_absolute_literals = 5100 last_fragP->tc_frag_data.use_absolute_literals; 5101 } 5102 } 5103 if (fragP->tc_frag_data.is_assembly_state_set) 5104 last_fragP = fragP; 5105 } 5106 } 5107 } 5108} 5109 5110 5111static void 5112xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, 5113 asection *sec, 5114 void *unused ATTRIBUTE_UNUSED) 5115{ 5116 flagword flags = bfd_section_flags (sec); 5117 segment_info_type *seginfo = seg_info (sec); 5118 fragS *frag = seginfo->frchainP->frch_root; 5119 5120 if (flags & SEC_CODE) 5121 { 5122 xtensa_isa isa = xtensa_default_isa; 5123 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 5124 while (frag != NULL) 5125 { 5126 if (frag->tc_frag_data.is_branch_target) 5127 { 5128 int op_size; 5129 addressT branch_align, frag_addr; 5130 xtensa_format fmt; 5131 5132 xtensa_insnbuf_from_chars 5133 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 5134 fmt = xtensa_format_decode (isa, insnbuf); 5135 op_size = xtensa_format_length (isa, fmt); 5136 branch_align = 1 << branch_align_power (sec); 5137 frag_addr = frag->fr_address % branch_align; 5138 if (frag_addr + op_size > branch_align) 5139 as_warn_where (frag->fr_file, frag->fr_line, 5140 _("unaligned branch target: %d bytes at 0x%lx"), 5141 op_size, (long) frag->fr_address); 5142 } 5143 frag = frag->fr_next; 5144 } 5145 xtensa_insnbuf_free (isa, insnbuf); 5146 } 5147} 5148 5149 5150static void 5151xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, 5152 asection *sec, 5153 void *unused ATTRIBUTE_UNUSED) 5154{ 5155 flagword flags = bfd_section_flags (sec); 5156 segment_info_type *seginfo = seg_info (sec); 5157 fragS *frag = seginfo->frchainP->frch_root; 5158 xtensa_isa isa = xtensa_default_isa; 5159 5160 if (flags & SEC_CODE) 5161 { 5162 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 5163 while (frag != NULL) 5164 { 5165 if (frag->tc_frag_data.is_first_loop_insn) 5166 { 5167 int op_size; 5168 addressT frag_addr; 5169 xtensa_format fmt; 5170 5171 if (frag->fr_fix == 0) 5172 frag = next_non_empty_frag (frag); 5173 5174 if (frag) 5175 { 5176 xtensa_insnbuf_from_chars 5177 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 5178 fmt = xtensa_format_decode (isa, insnbuf); 5179 op_size = xtensa_format_length (isa, fmt); 5180 frag_addr = frag->fr_address % xtensa_fetch_width; 5181 5182 if (frag_addr + op_size > xtensa_fetch_width) 5183 as_warn_where (frag->fr_file, frag->fr_line, 5184 _("unaligned loop: %d bytes at 0x%lx"), 5185 op_size, (long) frag->fr_address); 5186 } 5187 } 5188 frag = frag->fr_next; 5189 } 5190 xtensa_insnbuf_free (isa, insnbuf); 5191 } 5192} 5193 5194 5195static int 5196xg_apply_fix_value (fixS *fixP, valueT val) 5197{ 5198 xtensa_isa isa = xtensa_default_isa; 5199 static xtensa_insnbuf insnbuf = NULL; 5200 static xtensa_insnbuf slotbuf = NULL; 5201 xtensa_format fmt; 5202 int slot; 5203 bool alt_reloc; 5204 xtensa_opcode opcode; 5205 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5206 5207 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) 5208 || alt_reloc) 5209 as_fatal (_("unexpected fix")); 5210 5211 if (!insnbuf) 5212 { 5213 insnbuf = xtensa_insnbuf_alloc (isa); 5214 slotbuf = xtensa_insnbuf_alloc (isa); 5215 } 5216 5217 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5218 fmt = xtensa_format_decode (isa, insnbuf); 5219 if (fmt == XTENSA_UNDEFINED) 5220 as_fatal (_("undecodable fix")); 5221 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5222 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5223 if (opcode == XTENSA_UNDEFINED) 5224 as_fatal (_("undecodable fix")); 5225 5226 /* CONST16 immediates are not PC-relative, despite the fact that we 5227 reuse the normal PC-relative operand relocations for the low part 5228 of a CONST16 operand. */ 5229 if (opcode == xtensa_const16_opcode) 5230 return 0; 5231 5232 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, 5233 get_relaxable_immed (opcode), val, 5234 fixP->fx_file, fixP->fx_line); 5235 5236 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); 5237 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5238 5239 return 1; 5240} 5241 5242 5243/* External Functions and Other GAS Hooks. */ 5244 5245const char * 5246xtensa_target_format (void) 5247{ 5248 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); 5249} 5250 5251 5252void 5253xtensa_file_arch_init (bfd *abfd) 5254{ 5255 bfd_set_private_flags (abfd, 0x100 | 0x200); 5256} 5257 5258 5259void 5260md_number_to_chars (char *buf, valueT val, int n) 5261{ 5262 if (target_big_endian) 5263 number_to_chars_bigendian (buf, val, n); 5264 else 5265 number_to_chars_littleendian (buf, val, n); 5266} 5267 5268static void 5269xg_init_global_config (void) 5270{ 5271 target_big_endian = XCHAL_HAVE_BE; 5272 5273 density_supported = XCHAL_HAVE_DENSITY; 5274 absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; 5275 xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; 5276 5277 directive_state[directive_density] = XCHAL_HAVE_DENSITY; 5278 directive_state[directive_absolute_literals] = XSHAL_USE_ABSOLUTE_LITERALS; 5279 5280 microarch_earliest = XTENSA_MARCH_EARLIEST; 5281} 5282 5283void 5284xtensa_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) 5285{ 5286 xg_init_global_config (); 5287} 5288 5289/* This function is called once, at assembler startup time. It should 5290 set up all the tables, etc. that the MD part of the assembler will 5291 need. */ 5292 5293void 5294md_begin (void) 5295{ 5296 segT current_section = now_seg; 5297 int current_subsec = now_subseg; 5298 xtensa_isa isa; 5299 int i; 5300 5301 xtensa_default_isa = xtensa_isa_init (0, 0); 5302 isa = xtensa_default_isa; 5303 5304 linkrelax = opt_linkrelax; 5305 5306 /* Set up the literal sections. */ 5307 memset (&default_lit_sections, 0, sizeof (default_lit_sections)); 5308 5309 subseg_set (current_section, current_subsec); 5310 5311 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); 5312 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); 5313 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); 5314 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); 5315 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); 5316 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); 5317 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); 5318 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); 5319 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); 5320 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); 5321 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); 5322 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); 5323 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); 5324 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); 5325 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); 5326 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); 5327 xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); 5328 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); 5329 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); 5330 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); 5331 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); 5332 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); 5333 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); 5334 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); 5335 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); 5336 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); 5337 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); 5338 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); 5339 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); 5340 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); 5341 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); 5342 5343 for (i = 0; i < xtensa_isa_num_formats (isa); i++) 5344 { 5345 int format_slots = xtensa_format_num_slots (isa, i); 5346 if (format_slots > config_max_slots) 5347 config_max_slots = format_slots; 5348 } 5349 5350 xg_init_vinsn (&cur_vinsn); 5351 5352 xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); 5353 5354 init_op_placement_info_table (); 5355 5356 /* Set up the assembly state. */ 5357 if (!frag_now->tc_frag_data.is_assembly_state_set) 5358 xtensa_set_frag_assembly_state (frag_now); 5359 5360 if (!use_literal_section) 5361 xtensa_mark_literal_pool_location (); 5362} 5363 5364 5365/* TC_INIT_FIX_DATA hook */ 5366 5367void 5368xtensa_init_fix_data (fixS *x) 5369{ 5370 x->tc_fix_data.slot = 0; 5371 x->tc_fix_data.X_add_symbol = NULL; 5372 x->tc_fix_data.X_add_number = 0; 5373} 5374 5375 5376/* tc_frob_label hook */ 5377 5378void 5379xtensa_frob_label (symbolS *sym) 5380{ 5381 float freq; 5382 5383 if (cur_vinsn.inside_bundle) 5384 { 5385 as_bad (_("labels are not valid inside bundles")); 5386 return; 5387 } 5388 5389 freq = get_subseg_target_freq (now_seg, now_subseg); 5390 5391 /* Since the label was already attached to a frag associated with the 5392 previous basic block, it now needs to be reset to the current frag. */ 5393 symbol_set_frag (sym, frag_now); 5394 S_SET_VALUE (sym, (valueT) frag_now_fix ()); 5395 5396 if (generating_literals) 5397 xtensa_add_literal_sym (sym); 5398 else 5399 xtensa_add_insn_label (sym); 5400 5401 if (symbol_get_tc (sym)->is_loop_target) 5402 { 5403 if ((get_last_insn_flags (now_seg, now_subseg) 5404 & FLAG_IS_BAD_LOOPEND) != 0) 5405 as_bad (_("invalid last instruction for a zero-overhead loop")); 5406 5407 xtensa_set_frag_assembly_state (frag_now); 5408 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, 5409 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5410 5411 xtensa_set_frag_assembly_state (frag_now); 5412 xtensa_move_labels (frag_now, 0); 5413 } 5414 5415 /* No target aligning in the absolute section. */ 5416 if (now_seg != absolute_section 5417 && !is_unaligned_label (sym) 5418 && !generating_literals) 5419 { 5420 xtensa_set_frag_assembly_state (frag_now); 5421 5422 if (do_align_targets ()) 5423 frag_var (rs_machine_dependent, 0, (int) freq, 5424 RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, 5425 frag_now->fr_offset, NULL); 5426 else 5427 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 5428 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5429 xtensa_set_frag_assembly_state (frag_now); 5430 xtensa_move_labels (frag_now, 0); 5431 } 5432 5433 /* We need to mark the following properties even if we aren't aligning. */ 5434 5435 /* If the label is already known to be a branch target, i.e., a 5436 forward branch, mark the frag accordingly. Backward branches 5437 are handled by xg_add_branch_and_loop_targets. */ 5438 if (symbol_get_tc (sym)->is_branch_target) 5439 symbol_get_frag (sym)->tc_frag_data.is_branch_target = true; 5440 5441 /* Loops only go forward, so they can be identified here. */ 5442 if (symbol_get_tc (sym)->is_loop_target) 5443 symbol_get_frag (sym)->tc_frag_data.is_loop_target = true; 5444 5445 dwarf2_emit_label (sym); 5446} 5447 5448 5449/* tc_unrecognized_line hook */ 5450 5451int 5452xtensa_unrecognized_line (int ch) 5453{ 5454 switch (ch) 5455 { 5456 case '{' : 5457 if (cur_vinsn.inside_bundle == 0) 5458 { 5459 /* PR8110: Cannot emit line number info inside a FLIX bundle 5460 when using --gstabs. Temporarily disable debug info. */ 5461 generate_lineno_debug (); 5462 if (debug_type == DEBUG_STABS) 5463 { 5464 xt_saved_debug_type = debug_type; 5465 debug_type = DEBUG_NONE; 5466 } 5467 5468 cur_vinsn.inside_bundle = 1; 5469 } 5470 else 5471 { 5472 as_bad (_("extra opening brace")); 5473 return 0; 5474 } 5475 break; 5476 5477 case '}' : 5478 if (cur_vinsn.inside_bundle) 5479 finish_vinsn (&cur_vinsn); 5480 else 5481 { 5482 as_bad (_("extra closing brace")); 5483 return 0; 5484 } 5485 break; 5486 default: 5487 as_bad (_("syntax error")); 5488 return 0; 5489 } 5490 return 1; 5491} 5492 5493 5494/* md_flush_pending_output hook */ 5495 5496void 5497xtensa_flush_pending_output (void) 5498{ 5499 /* This line fixes a bug where automatically generated gstabs info 5500 separates a function label from its entry instruction, ending up 5501 with the literal position between the function label and the entry 5502 instruction and crashing code. It only happens with --gstabs and 5503 --text-section-literals, and when several other obscure relaxation 5504 conditions are met. */ 5505 if (outputting_stabs_line_debug) 5506 return; 5507 5508 if (cur_vinsn.inside_bundle) 5509 as_bad (_("missing closing brace")); 5510 5511 /* If there is a non-zero instruction fragment, close it. */ 5512 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) 5513 { 5514 frag_wane (frag_now); 5515 frag_new (0); 5516 xtensa_set_frag_assembly_state (frag_now); 5517 } 5518 frag_now->tc_frag_data.is_insn = false; 5519 5520 xtensa_clear_insn_labels (); 5521} 5522 5523 5524/* We had an error while parsing an instruction. The string might look 5525 like this: "insn arg1, arg2 }". If so, we need to see the closing 5526 brace and reset some fields. Otherwise, the vinsn never gets closed 5527 and the num_slots field will grow past the end of the array of slots, 5528 and bad things happen. */ 5529 5530static void 5531error_reset_cur_vinsn (void) 5532{ 5533 if (cur_vinsn.inside_bundle) 5534 { 5535 if (*input_line_pointer == '}' 5536 || *(input_line_pointer - 1) == '}' 5537 || *(input_line_pointer - 2) == '}') 5538 xg_clear_vinsn (&cur_vinsn); 5539 } 5540} 5541 5542 5543void 5544md_assemble (char *str) 5545{ 5546 xtensa_isa isa = xtensa_default_isa; 5547 char *opname; 5548 unsigned opnamelen; 5549 bool has_underbar = false; 5550 char *arg_strings[MAX_INSN_ARGS]; 5551 int num_args; 5552 TInsn orig_insn; /* Original instruction from the input. */ 5553 5554 tinsn_init (&orig_insn); 5555 5556 /* Split off the opcode. */ 5557 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); 5558 opname = xstrndup (str, opnamelen); 5559 5560 num_args = tokenize_arguments (arg_strings, str + opnamelen); 5561 if (num_args == -1) 5562 { 5563 as_bad (_("syntax error")); 5564 return; 5565 } 5566 5567 if (xg_translate_idioms (&opname, &num_args, arg_strings)) 5568 return; 5569 5570 /* Check for an underbar prefix. */ 5571 if (*opname == '_') 5572 { 5573 has_underbar = true; 5574 opname += 1; 5575 } 5576 5577 orig_insn.insn_type = ITYPE_INSN; 5578 orig_insn.ntok = 0; 5579 orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); 5580 orig_insn.opcode = xtensa_opcode_lookup (isa, opname); 5581 5582 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its 5583 extra argument and set the opcode to "CALLXn". */ 5584 if (orig_insn.opcode == XTENSA_UNDEFINED 5585 && strncasecmp (opname, "callx", 5) == 0) 5586 { 5587 unsigned long window_size; 5588 char *suffix; 5589 5590 window_size = strtoul (opname + 5, &suffix, 10); 5591 if (suffix != opname + 5 5592 && (window_size == 0 5593 || window_size == 4 5594 || window_size == 8 5595 || window_size == 12) 5596 && strcasecmp (suffix, ".tls") == 0) 5597 { 5598 switch (window_size) 5599 { 5600 case 0: orig_insn.opcode = xtensa_callx0_opcode; break; 5601 case 4: orig_insn.opcode = xtensa_callx4_opcode; break; 5602 case 8: orig_insn.opcode = xtensa_callx8_opcode; break; 5603 case 12: orig_insn.opcode = xtensa_callx12_opcode; break; 5604 } 5605 5606 if (num_args != 2) 5607 as_bad (_("wrong number of operands for '%s'"), opname); 5608 else 5609 { 5610 bfd_reloc_code_real_type reloc; 5611 char *old_input_line_pointer; 5612 expressionS *tok = &orig_insn.extra_arg; 5613 5614 old_input_line_pointer = input_line_pointer; 5615 input_line_pointer = arg_strings[num_args - 1]; 5616 5617 expression (tok); 5618 if (tok->X_op == O_symbol 5619 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 5620 == BFD_RELOC_XTENSA_TLS_CALL)) 5621 tok->X_op = map_suffix_reloc_to_operator (reloc); 5622 else 5623 as_bad (_("bad relocation expression for '%s'"), opname); 5624 5625 input_line_pointer = old_input_line_pointer; 5626 num_args -= 1; 5627 } 5628 } 5629 } 5630 5631 /* Special case: Check for "j.l" pseudo op. */ 5632 if (orig_insn.opcode == XTENSA_UNDEFINED 5633 && strncasecmp (opname, "j.l", 3) == 0) 5634 { 5635 if (num_args != 2) 5636 as_bad (_("wrong number of operands for '%s'"), opname); 5637 else 5638 { 5639 char *old_input_line_pointer; 5640 expressionS *tok = &orig_insn.extra_arg; 5641 5642 old_input_line_pointer = input_line_pointer; 5643 input_line_pointer = arg_strings[num_args - 1]; 5644 5645 expression_maybe_register (xtensa_jx_opcode, 0, tok); 5646 input_line_pointer = old_input_line_pointer; 5647 5648 num_args -= 1; 5649 orig_insn.opcode = xtensa_j_opcode; 5650 } 5651 } 5652 5653 if (orig_insn.opcode == XTENSA_UNDEFINED) 5654 { 5655 xtensa_format fmt = xtensa_format_lookup (isa, opname); 5656 if (fmt == XTENSA_UNDEFINED) 5657 { 5658 as_bad (_("unknown opcode or format name '%s'"), opname); 5659 error_reset_cur_vinsn (); 5660 return; 5661 } 5662 if (!cur_vinsn.inside_bundle) 5663 { 5664 as_bad (_("format names only valid inside bundles")); 5665 error_reset_cur_vinsn (); 5666 return; 5667 } 5668 if (cur_vinsn.format != XTENSA_UNDEFINED) 5669 as_warn (_("multiple formats specified for one bundle; using '%s'"), 5670 opname); 5671 cur_vinsn.format = fmt; 5672 free (has_underbar ? opname - 1 : opname); 5673 error_reset_cur_vinsn (); 5674 return; 5675 } 5676 5677 /* Parse the arguments. */ 5678 if (parse_arguments (&orig_insn, num_args, arg_strings)) 5679 { 5680 as_bad (_("syntax error")); 5681 error_reset_cur_vinsn (); 5682 return; 5683 } 5684 5685 /* Free the opcode and argument strings, now that they've been parsed. */ 5686 free (has_underbar ? opname - 1 : opname); 5687 opname = 0; 5688 while (num_args-- > 0) 5689 free (arg_strings[num_args]); 5690 5691 /* Get expressions for invisible operands. */ 5692 if (get_invisible_operands (&orig_insn)) 5693 { 5694 error_reset_cur_vinsn (); 5695 return; 5696 } 5697 5698 /* Check for the right number and type of arguments. */ 5699 if (tinsn_check_arguments (&orig_insn)) 5700 { 5701 error_reset_cur_vinsn (); 5702 return; 5703 } 5704 5705 /* Record the line number for each TInsn, because a FLIX bundle may be 5706 spread across multiple input lines and individual instructions may be 5707 moved around in some cases. */ 5708 orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; 5709 dwarf2_where (&orig_insn.debug_line); 5710 dwarf2_consume_line_info (); 5711 5712 xg_add_branch_and_loop_targets (&orig_insn); 5713 5714 /* Check that immediate value for ENTRY is >= 16. */ 5715 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) 5716 { 5717 expressionS *exp = &orig_insn.tok[2]; 5718 if (exp->X_op == O_constant && exp->X_add_number < 16) 5719 as_warn (_("entry instruction with stack decrement < 16")); 5720 } 5721 5722 /* Finish it off: 5723 assemble_tokens (opcode, tok, ntok); 5724 expand the tokens from the orig_insn into the 5725 stack of instructions that will not expand 5726 unless required at relaxation time. */ 5727 5728 if (!cur_vinsn.inside_bundle) 5729 emit_single_op (&orig_insn); 5730 else /* We are inside a bundle. */ 5731 { 5732 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; 5733 cur_vinsn.num_slots++; 5734 if (*input_line_pointer == '}' 5735 || *(input_line_pointer - 1) == '}' 5736 || *(input_line_pointer - 2) == '}') 5737 finish_vinsn (&cur_vinsn); 5738 } 5739 5740 /* We've just emitted a new instruction so clear the list of labels. */ 5741 xtensa_clear_insn_labels (); 5742 5743 xtensa_check_frag_count (); 5744} 5745 5746 5747/* HANDLE_ALIGN hook */ 5748 5749/* For a .align directive, we mark the previous block with the alignment 5750 information. This will be placed in the object file in the 5751 property section corresponding to this section. */ 5752 5753void 5754xtensa_handle_align (fragS *fragP) 5755{ 5756 if (linkrelax 5757 && ! fragP->tc_frag_data.is_literal 5758 && (fragP->fr_type == rs_align 5759 || fragP->fr_type == rs_align_code) 5760 && fragP->fr_offset > 0 5761 && now_seg != bss_section) 5762 { 5763 fragP->tc_frag_data.is_align = true; 5764 fragP->tc_frag_data.alignment = fragP->fr_offset; 5765 } 5766 5767 if (fragP->fr_type == rs_align_test) 5768 { 5769 int count; 5770 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 5771 if (count != 0) 5772 as_bad_where (fragP->fr_file, fragP->fr_line, 5773 _("unaligned entry instruction")); 5774 } 5775 5776 if (linkrelax && fragP->fr_type == rs_org) 5777 fragP->fr_subtype = RELAX_ORG; 5778} 5779 5780 5781/* TC_FRAG_INIT hook */ 5782 5783void 5784xtensa_frag_init (fragS *frag) 5785{ 5786 xtensa_set_frag_assembly_state (frag); 5787} 5788 5789 5790symbolS * 5791md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 5792{ 5793 return NULL; 5794} 5795 5796 5797/* Round up a section size to the appropriate boundary. */ 5798 5799valueT 5800md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 5801{ 5802 return size; /* Byte alignment is fine. */ 5803} 5804 5805 5806long 5807md_pcrel_from (fixS *fixP) 5808{ 5809 char *insn_p; 5810 static xtensa_insnbuf insnbuf = NULL; 5811 static xtensa_insnbuf slotbuf = NULL; 5812 int opnum; 5813 uint32 opnd_value; 5814 xtensa_opcode opcode; 5815 xtensa_format fmt; 5816 int slot; 5817 xtensa_isa isa = xtensa_default_isa; 5818 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 5819 bool alt_reloc; 5820 5821 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) 5822 return 0; 5823 5824 if (fixP->fx_r_type == BFD_RELOC_32_PCREL) 5825 return addr; 5826 5827 if (!insnbuf) 5828 { 5829 insnbuf = xtensa_insnbuf_alloc (isa); 5830 slotbuf = xtensa_insnbuf_alloc (isa); 5831 } 5832 5833 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; 5834 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); 5835 fmt = xtensa_format_decode (isa, insnbuf); 5836 5837 if (fmt == XTENSA_UNDEFINED) 5838 as_fatal (_("bad instruction format")); 5839 5840 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) 5841 as_fatal (_("invalid relocation")); 5842 5843 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5844 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5845 5846 /* Check for "alternate" relocations (operand not specified). None 5847 of the current uses for these are really PC-relative. */ 5848 if (alt_reloc || opcode == xtensa_const16_opcode) 5849 { 5850 if (opcode != xtensa_l32r_opcode 5851 && opcode != xtensa_const16_opcode) 5852 as_fatal (_("invalid relocation for '%s' instruction"), 5853 xtensa_opcode_name (isa, opcode)); 5854 return 0; 5855 } 5856 5857 opnum = get_relaxable_immed (opcode); 5858 opnd_value = 0; 5859 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 5860 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) 5861 { 5862 as_bad_where (fixP->fx_file, 5863 fixP->fx_line, 5864 _("invalid relocation for operand %d of '%s'"), 5865 opnum, xtensa_opcode_name (isa, opcode)); 5866 return 0; 5867 } 5868 return 0 - opnd_value; 5869} 5870 5871 5872/* TC_FORCE_RELOCATION hook */ 5873 5874int 5875xtensa_force_relocation (fixS *fix) 5876{ 5877 switch (fix->fx_r_type) 5878 { 5879 case BFD_RELOC_XTENSA_ASM_EXPAND: 5880 case BFD_RELOC_XTENSA_SLOT0_ALT: 5881 case BFD_RELOC_XTENSA_SLOT1_ALT: 5882 case BFD_RELOC_XTENSA_SLOT2_ALT: 5883 case BFD_RELOC_XTENSA_SLOT3_ALT: 5884 case BFD_RELOC_XTENSA_SLOT4_ALT: 5885 case BFD_RELOC_XTENSA_SLOT5_ALT: 5886 case BFD_RELOC_XTENSA_SLOT6_ALT: 5887 case BFD_RELOC_XTENSA_SLOT7_ALT: 5888 case BFD_RELOC_XTENSA_SLOT8_ALT: 5889 case BFD_RELOC_XTENSA_SLOT9_ALT: 5890 case BFD_RELOC_XTENSA_SLOT10_ALT: 5891 case BFD_RELOC_XTENSA_SLOT11_ALT: 5892 case BFD_RELOC_XTENSA_SLOT12_ALT: 5893 case BFD_RELOC_XTENSA_SLOT13_ALT: 5894 case BFD_RELOC_XTENSA_SLOT14_ALT: 5895 return 1; 5896 default: 5897 break; 5898 } 5899 5900 if (linkrelax && fix->fx_addsy 5901 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) 5902 return 1; 5903 5904 return generic_force_reloc (fix); 5905} 5906 5907 5908/* TC_VALIDATE_FIX_SUB hook */ 5909 5910int 5911xtensa_validate_fix_sub (fixS *fix) 5912{ 5913 segT add_symbol_segment, sub_symbol_segment; 5914 5915 /* The difference of two symbols should be resolved by the assembler when 5916 linkrelax is not set. If the linker may relax the section containing 5917 the symbols, then an Xtensa DIFF relocation must be generated so that 5918 the linker knows to adjust the difference value. */ 5919 if (!linkrelax || fix->fx_addsy == NULL) 5920 return 0; 5921 5922 /* Make sure both symbols are in the same segment, and that segment is 5923 "normal" and relaxable. If the segment is not "normal", then the 5924 fix is not valid. If the segment is not "relaxable", then the fix 5925 should have been handled earlier. */ 5926 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); 5927 if (! SEG_NORMAL (add_symbol_segment) || 5928 ! relaxable_section (add_symbol_segment)) 5929 return 0; 5930 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); 5931 return (sub_symbol_segment == add_symbol_segment); 5932} 5933 5934 5935/* NO_PSEUDO_DOT hook */ 5936 5937/* This function has nothing to do with pseudo dots, but this is the 5938 nearest macro to where the check needs to take place. FIXME: This 5939 seems wrong. */ 5940 5941bool 5942xtensa_check_inside_bundle (void) 5943{ 5944 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') 5945 as_bad (_("directives are not valid inside bundles")); 5946 5947 /* This function must always return FALSE because it is called via a 5948 macro that has nothing to do with bundling. */ 5949 return false; 5950} 5951 5952 5953/* md_elf_section_change_hook */ 5954 5955void 5956xtensa_elf_section_change_hook (void) 5957{ 5958 /* Set up the assembly state. */ 5959 if (!frag_now->tc_frag_data.is_assembly_state_set) 5960 xtensa_set_frag_assembly_state (frag_now); 5961 5962 if (!use_literal_section 5963 && seg_info (now_seg)->tc_segment_info_data.literal_pool_loc == NULL 5964 && !xtensa_is_init_fini (now_seg)) 5965 xtensa_mark_literal_pool_location (); 5966} 5967 5968 5969/* tc_fix_adjustable hook */ 5970 5971bool 5972xtensa_fix_adjustable (fixS *fixP) 5973{ 5974 /* We need the symbol name for the VTABLE entries. */ 5975 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 5976 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5977 return 0; 5978 5979 return 1; 5980} 5981 5982 5983/* tc_symbol_new_hook */ 5984 5985symbolS *expr_symbols = NULL; 5986 5987void 5988xtensa_symbol_new_hook (symbolS *sym) 5989{ 5990 if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) 5991 { 5992 symbol_get_tc (sym)->next_expr_symbol = expr_symbols; 5993 expr_symbols = sym; 5994 } 5995} 5996 5997 5998void 5999md_apply_fix (fixS *fixP, valueT *valP, segT seg) 6000{ 6001 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 6002 valueT val = 0; 6003 6004 /* Subtracted symbols are only allowed for a few relocation types, and 6005 unless linkrelax is enabled, they should not make it to this point. */ 6006 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 6007 || fixP->fx_r_type == BFD_RELOC_16 6008 || fixP->fx_r_type == BFD_RELOC_8))) 6009 as_bad_subtract (fixP); 6010 6011 switch (fixP->fx_r_type) 6012 { 6013 case BFD_RELOC_32_PCREL: 6014 case BFD_RELOC_32: 6015 case BFD_RELOC_16: 6016 case BFD_RELOC_8: 6017 if (fixP->fx_subsy) 6018 { 6019 bool neg = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 6020 < S_GET_VALUE (fixP->fx_subsy)); 6021 6022 switch (fixP->fx_r_type) 6023 { 6024 case BFD_RELOC_8: 6025 fixP->fx_r_type = neg 6026 ? BFD_RELOC_XTENSA_NDIFF8 : BFD_RELOC_XTENSA_PDIFF8; 6027 fixP->fx_signed = 0; 6028 break; 6029 case BFD_RELOC_16: 6030 fixP->fx_r_type = neg 6031 ? BFD_RELOC_XTENSA_NDIFF16 : BFD_RELOC_XTENSA_PDIFF16; 6032 fixP->fx_signed = 0; 6033 break; 6034 case BFD_RELOC_32: 6035 fixP->fx_r_type = neg 6036 ? BFD_RELOC_XTENSA_NDIFF32 : BFD_RELOC_XTENSA_PDIFF32; 6037 fixP->fx_signed = 0; 6038 break; 6039 default: 6040 break; 6041 } 6042 6043 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 6044 - S_GET_VALUE (fixP->fx_subsy)); 6045 6046 /* The difference value gets written out, and the DIFF reloc 6047 identifies the address of the subtracted symbol (i.e., the one 6048 with the lowest address). */ 6049 *valP = val; 6050 fixP->fx_offset -= val; 6051 fixP->fx_subsy = NULL; 6052 } 6053 else if (! fixP->fx_addsy) 6054 { 6055 val = *valP; 6056 fixP->fx_done = 1; 6057 } 6058 else if (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section) 6059 { 6060 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; 6061 *valP = val; 6062 fixP->fx_done = 1; 6063 } 6064 /* fall through */ 6065 6066 case BFD_RELOC_XTENSA_PLT: 6067 md_number_to_chars (fixpos, val, fixP->fx_size); 6068 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 6069 break; 6070 6071 case BFD_RELOC_XTENSA_TLSDESC_FN: 6072 case BFD_RELOC_XTENSA_TLSDESC_ARG: 6073 case BFD_RELOC_XTENSA_TLS_TPOFF: 6074 case BFD_RELOC_XTENSA_TLS_DTPOFF: 6075 S_SET_THREAD_LOCAL (fixP->fx_addsy); 6076 md_number_to_chars (fixpos, 0, fixP->fx_size); 6077 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 6078 break; 6079 6080 case BFD_RELOC_XTENSA_SLOT0_OP: 6081 case BFD_RELOC_XTENSA_SLOT1_OP: 6082 case BFD_RELOC_XTENSA_SLOT2_OP: 6083 case BFD_RELOC_XTENSA_SLOT3_OP: 6084 case BFD_RELOC_XTENSA_SLOT4_OP: 6085 case BFD_RELOC_XTENSA_SLOT5_OP: 6086 case BFD_RELOC_XTENSA_SLOT6_OP: 6087 case BFD_RELOC_XTENSA_SLOT7_OP: 6088 case BFD_RELOC_XTENSA_SLOT8_OP: 6089 case BFD_RELOC_XTENSA_SLOT9_OP: 6090 case BFD_RELOC_XTENSA_SLOT10_OP: 6091 case BFD_RELOC_XTENSA_SLOT11_OP: 6092 case BFD_RELOC_XTENSA_SLOT12_OP: 6093 case BFD_RELOC_XTENSA_SLOT13_OP: 6094 case BFD_RELOC_XTENSA_SLOT14_OP: 6095 if (linkrelax) 6096 { 6097 /* Write the tentative value of a PC-relative relocation to a 6098 local symbol into the instruction. The value will be ignored 6099 by the linker, and it makes the object file disassembly 6100 readable when all branch targets are encoded in relocations. */ 6101 6102 gas_assert (fixP->fx_addsy); 6103 if (S_GET_SEGMENT (fixP->fx_addsy) == seg 6104 && !S_FORCE_RELOC (fixP->fx_addsy, 1)) 6105 { 6106 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 6107 - md_pcrel_from (fixP)); 6108 (void) xg_apply_fix_value (fixP, val); 6109 } 6110 } 6111 else if (! fixP->fx_addsy) 6112 { 6113 val = *valP; 6114 if (xg_apply_fix_value (fixP, val)) 6115 fixP->fx_done = 1; 6116 } 6117 break; 6118 6119 case BFD_RELOC_XTENSA_ASM_EXPAND: 6120 case BFD_RELOC_XTENSA_TLS_FUNC: 6121 case BFD_RELOC_XTENSA_TLS_ARG: 6122 case BFD_RELOC_XTENSA_TLS_CALL: 6123 case BFD_RELOC_XTENSA_SLOT0_ALT: 6124 case BFD_RELOC_XTENSA_SLOT1_ALT: 6125 case BFD_RELOC_XTENSA_SLOT2_ALT: 6126 case BFD_RELOC_XTENSA_SLOT3_ALT: 6127 case BFD_RELOC_XTENSA_SLOT4_ALT: 6128 case BFD_RELOC_XTENSA_SLOT5_ALT: 6129 case BFD_RELOC_XTENSA_SLOT6_ALT: 6130 case BFD_RELOC_XTENSA_SLOT7_ALT: 6131 case BFD_RELOC_XTENSA_SLOT8_ALT: 6132 case BFD_RELOC_XTENSA_SLOT9_ALT: 6133 case BFD_RELOC_XTENSA_SLOT10_ALT: 6134 case BFD_RELOC_XTENSA_SLOT11_ALT: 6135 case BFD_RELOC_XTENSA_SLOT12_ALT: 6136 case BFD_RELOC_XTENSA_SLOT13_ALT: 6137 case BFD_RELOC_XTENSA_SLOT14_ALT: 6138 /* These all need to be resolved at link-time. Do nothing now. */ 6139 break; 6140 6141 case BFD_RELOC_VTABLE_INHERIT: 6142 case BFD_RELOC_VTABLE_ENTRY: 6143 fixP->fx_done = 0; 6144 break; 6145 6146 default: 6147 as_bad (_("unhandled local relocation fix %s"), 6148 bfd_get_reloc_code_name (fixP->fx_r_type)); 6149 } 6150} 6151 6152 6153const char * 6154md_atof (int type, char *litP, int *sizeP) 6155{ 6156 return ieee_md_atof (type, litP, sizeP, target_big_endian); 6157} 6158 6159 6160int 6161md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) 6162{ 6163 return total_frag_text_expansion (fragP); 6164} 6165 6166 6167/* Translate internal representation of relocation info to BFD target 6168 format. */ 6169 6170arelent * 6171tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 6172{ 6173 arelent *reloc; 6174 6175 reloc = XNEW (arelent); 6176 reloc->sym_ptr_ptr = XNEW (asymbol *); 6177 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 6178 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 6179 6180 /* Make sure none of our internal relocations make it this far. 6181 They'd better have been fully resolved by this point. */ 6182 gas_assert ((int) fixp->fx_r_type > 0); 6183 6184 reloc->addend = fixp->fx_offset; 6185 6186 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 6187 if (reloc->howto == NULL) 6188 { 6189 as_bad_where (fixp->fx_file, fixp->fx_line, 6190 _("cannot represent `%s' relocation in object file"), 6191 bfd_get_reloc_code_name (fixp->fx_r_type)); 6192 free (reloc->sym_ptr_ptr); 6193 free (reloc); 6194 return NULL; 6195 } 6196 6197 if (!fixp->fx_pcrel != !reloc->howto->pc_relative) 6198 as_fatal (_("internal error; cannot generate `%s' relocation"), 6199 bfd_get_reloc_code_name (fixp->fx_r_type)); 6200 6201 return reloc; 6202} 6203 6204 6205/* Checks for resource conflicts between instructions. */ 6206 6207/* The func unit stuff could be implemented as bit-vectors rather 6208 than the iterative approach here. If it ends up being too 6209 slow, we will switch it. */ 6210 6211resource_table * 6212new_resource_table (void *data, 6213 int cycles, 6214 int nu, 6215 unit_num_copies_func uncf, 6216 opcode_num_units_func onuf, 6217 opcode_funcUnit_use_unit_func ouuf, 6218 opcode_funcUnit_use_stage_func ousf) 6219{ 6220 int i; 6221 resource_table *rt = XNEW (resource_table); 6222 rt->data = data; 6223 rt->cycles = cycles; 6224 rt->allocated_cycles = cycles; 6225 rt->num_units = nu; 6226 rt->unit_num_copies = uncf; 6227 rt->opcode_num_units = onuf; 6228 rt->opcode_unit_use = ouuf; 6229 rt->opcode_unit_stage = ousf; 6230 6231 rt->units = XCNEWVEC (unsigned char *, cycles); 6232 for (i = 0; i < cycles; i++) 6233 rt->units[i] = XCNEWVEC (unsigned char, nu); 6234 6235 return rt; 6236} 6237 6238 6239void 6240clear_resource_table (resource_table *rt) 6241{ 6242 int i, j; 6243 for (i = 0; i < rt->allocated_cycles; i++) 6244 for (j = 0; j < rt->num_units; j++) 6245 rt->units[i][j] = 0; 6246} 6247 6248 6249/* We never shrink it, just fake it into thinking so. */ 6250 6251void 6252resize_resource_table (resource_table *rt, int cycles) 6253{ 6254 int i, old_cycles; 6255 6256 rt->cycles = cycles; 6257 if (cycles <= rt->allocated_cycles) 6258 return; 6259 6260 old_cycles = rt->allocated_cycles; 6261 rt->allocated_cycles = cycles; 6262 6263 rt->units = XRESIZEVEC (unsigned char *, rt->units, rt->allocated_cycles); 6264 for (i = 0; i < old_cycles; i++) 6265 rt->units[i] = XRESIZEVEC (unsigned char, rt->units[i], rt->num_units); 6266 for (i = old_cycles; i < cycles; i++) 6267 rt->units[i] = XCNEWVEC (unsigned char, rt->num_units); 6268} 6269 6270 6271bool 6272resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) 6273{ 6274 int i; 6275 int uses = (rt->opcode_num_units) (rt->data, opcode); 6276 6277 for (i = 0; i < uses; i++) 6278 { 6279 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6280 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6281 int copies_in_use = rt->units[stage + cycle][unit]; 6282 int copies = (rt->unit_num_copies) (rt->data, unit); 6283 if (copies_in_use >= copies) 6284 return false; 6285 } 6286 return true; 6287} 6288 6289 6290void 6291reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6292{ 6293 int i; 6294 int uses = (rt->opcode_num_units) (rt->data, opcode); 6295 6296 for (i = 0; i < uses; i++) 6297 { 6298 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6299 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6300 /* Note that this allows resources to be oversubscribed. That's 6301 essential to the way the optional scheduler works. 6302 resources_available reports when a resource is over-subscribed, 6303 so it's easy to tell. */ 6304 rt->units[stage + cycle][unit]++; 6305 } 6306} 6307 6308 6309void 6310release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6311{ 6312 int i; 6313 int uses = (rt->opcode_num_units) (rt->data, opcode); 6314 6315 for (i = 0; i < uses; i++) 6316 { 6317 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6318 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6319 gas_assert (rt->units[stage + cycle][unit] > 0); 6320 rt->units[stage + cycle][unit]--; 6321 } 6322} 6323 6324 6325/* Wrapper functions make parameterized resource reservation 6326 more convenient. */ 6327 6328int 6329opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) 6330{ 6331 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6332 return use->unit; 6333} 6334 6335 6336int 6337opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) 6338{ 6339 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6340 return use->stage; 6341} 6342 6343 6344/* Note that this function does not check issue constraints, but 6345 solely whether the hardware is available to execute the given 6346 instructions together. It also doesn't check if the tinsns 6347 write the same state, or access the same tieports. That is 6348 checked by check_t1_t2_reads_and_writes. */ 6349 6350static bool 6351resources_conflict (vliw_insn *vinsn) 6352{ 6353 int i; 6354 static resource_table *rt = NULL; 6355 6356 /* This is the most common case by far. Optimize it. */ 6357 if (vinsn->num_slots == 1) 6358 return false; 6359 6360 if (rt == NULL) 6361 { 6362 xtensa_isa isa = xtensa_default_isa; 6363 rt = new_resource_table 6364 (isa, xtensa_num_pipe_stages, 6365 xtensa_isa_num_funcUnits (isa), 6366 (unit_num_copies_func) xtensa_funcUnit_num_copies, 6367 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, 6368 opcode_funcUnit_use_unit, 6369 opcode_funcUnit_use_stage); 6370 } 6371 6372 clear_resource_table (rt); 6373 6374 for (i = 0; i < vinsn->num_slots; i++) 6375 { 6376 if (!resources_available (rt, vinsn->slots[i].opcode, 0)) 6377 return true; 6378 reserve_resources (rt, vinsn->slots[i].opcode, 0); 6379 } 6380 6381 return false; 6382} 6383 6384 6385/* finish_vinsn, emit_single_op and helper functions. */ 6386 6387static bool find_vinsn_conflicts (vliw_insn *); 6388static xtensa_format xg_find_narrowest_format (vliw_insn *); 6389static void xg_assemble_vliw_tokens (vliw_insn *); 6390 6391 6392/* We have reached the end of a bundle; emit into the frag. */ 6393 6394static void 6395finish_vinsn (vliw_insn *vinsn) 6396{ 6397 IStack slotstack; 6398 int i; 6399 int slots; 6400 6401 if (find_vinsn_conflicts (vinsn)) 6402 { 6403 xg_clear_vinsn (vinsn); 6404 return; 6405 } 6406 6407 /* First, find a format that works. */ 6408 if (vinsn->format == XTENSA_UNDEFINED) 6409 vinsn->format = xg_find_narrowest_format (vinsn); 6410 6411 slots = xtensa_format_num_slots (xtensa_default_isa, vinsn->format); 6412 if (slots > 1 6413 && produce_flix == FLIX_NONE) 6414 { 6415 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); 6416 xg_clear_vinsn (vinsn); 6417 return; 6418 } 6419 6420 if (vinsn->format == XTENSA_UNDEFINED) 6421 { 6422 as_bad (_("couldn't find a valid instruction format")); 6423 fprintf (stderr, _(" ops were: ")); 6424 for (i = 0; i < vinsn->num_slots; i++) 6425 fprintf (stderr, _(" %s;"), 6426 xtensa_opcode_name (xtensa_default_isa, 6427 vinsn->slots[i].opcode)); 6428 fprintf (stderr, _("\n")); 6429 xg_clear_vinsn (vinsn); 6430 return; 6431 } 6432 6433 if (vinsn->num_slots != slots) 6434 { 6435 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"), 6436 xtensa_format_name (xtensa_default_isa, vinsn->format), 6437 slots, vinsn->num_slots); 6438 xg_clear_vinsn (vinsn); 6439 return; 6440 } 6441 6442 if (resources_conflict (vinsn)) 6443 { 6444 as_bad (_("illegal resource usage in bundle")); 6445 fprintf (stderr, " ops were: "); 6446 for (i = 0; i < vinsn->num_slots; i++) 6447 fprintf (stderr, " %s;", 6448 xtensa_opcode_name (xtensa_default_isa, 6449 vinsn->slots[i].opcode)); 6450 fprintf (stderr, "\n"); 6451 xg_clear_vinsn (vinsn); 6452 return; 6453 } 6454 6455 for (i = 0; i < vinsn->num_slots; i++) 6456 { 6457 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) 6458 { 6459 symbolS *lit_sym = NULL; 6460 int j; 6461 bool e = false; 6462 bool saved_density = density_supported; 6463 6464 /* We don't want to narrow ops inside multi-slot bundles. */ 6465 if (vinsn->num_slots > 1) 6466 density_supported = false; 6467 6468 istack_init (&slotstack); 6469 if (vinsn->slots[i].opcode == xtensa_nop_opcode) 6470 { 6471 vinsn->slots[i].opcode = 6472 xtensa_format_slot_nop_opcode (xtensa_default_isa, 6473 vinsn->format, i); 6474 vinsn->slots[i].ntok = 0; 6475 } 6476 6477 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) 6478 { 6479 e = true; 6480 continue; 6481 } 6482 6483 density_supported = saved_density; 6484 6485 if (e) 6486 { 6487 xg_clear_vinsn (vinsn); 6488 return; 6489 } 6490 6491 for (j = 0; j < slotstack.ninsn; j++) 6492 { 6493 TInsn *insn = &slotstack.insn[j]; 6494 if (insn->insn_type == ITYPE_LITERAL) 6495 { 6496 gas_assert (lit_sym == NULL); 6497 lit_sym = xg_assemble_literal (insn); 6498 } 6499 else 6500 { 6501 gas_assert (insn->insn_type == ITYPE_INSN); 6502 if (lit_sym) 6503 xg_resolve_literals (insn, lit_sym); 6504 if (j != slotstack.ninsn - 1) 6505 emit_single_op (insn); 6506 } 6507 } 6508 6509 if (vinsn->num_slots > 1) 6510 { 6511 if (opcode_fits_format_slot 6512 (slotstack.insn[slotstack.ninsn - 1].opcode, 6513 vinsn->format, i)) 6514 { 6515 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; 6516 } 6517 else 6518 { 6519 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); 6520 if (vinsn->format == XTENSA_UNDEFINED) 6521 vinsn->slots[i].opcode = xtensa_nop_opcode; 6522 else 6523 vinsn->slots[i].opcode 6524 = xtensa_format_slot_nop_opcode (xtensa_default_isa, 6525 vinsn->format, i); 6526 6527 vinsn->slots[i].ntok = 0; 6528 } 6529 } 6530 else 6531 { 6532 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; 6533 vinsn->format = XTENSA_UNDEFINED; 6534 } 6535 } 6536 } 6537 6538 /* Now check resource conflicts on the modified bundle. */ 6539 if (resources_conflict (vinsn)) 6540 { 6541 as_bad (_("illegal resource usage in bundle")); 6542 fprintf (stderr, " ops were: "); 6543 for (i = 0; i < vinsn->num_slots; i++) 6544 fprintf (stderr, " %s;", 6545 xtensa_opcode_name (xtensa_default_isa, 6546 vinsn->slots[i].opcode)); 6547 fprintf (stderr, "\n"); 6548 xg_clear_vinsn (vinsn); 6549 return; 6550 } 6551 6552 /* First, find a format that works. */ 6553 if (vinsn->format == XTENSA_UNDEFINED) 6554 vinsn->format = xg_find_narrowest_format (vinsn); 6555 6556 xg_assemble_vliw_tokens (vinsn); 6557 6558 xg_clear_vinsn (vinsn); 6559 6560 xtensa_check_frag_count (); 6561} 6562 6563 6564/* Given an vliw instruction, what conflicts are there in register 6565 usage and in writes to states and queues? 6566 6567 This function does two things: 6568 1. Reports an error when a vinsn contains illegal combinations 6569 of writes to registers states or queues. 6570 2. Marks individual tinsns as not relaxable if the combination 6571 contains antidependencies. 6572 6573 Job 2 handles things like swap semantics in instructions that need 6574 to be relaxed. For example, 6575 6576 addi a0, a1, 100000 6577 6578 normally would be relaxed to 6579 6580 l32r a0, some_label 6581 add a0, a1, a0 6582 6583 _but_, if the above instruction is bundled with an a0 reader, e.g., 6584 6585 { addi a0, a1, 10000 ; add a2, a0, a4 ; } 6586 6587 then we can't relax it into 6588 6589 l32r a0, some_label 6590 { add a0, a1, a0 ; add a2, a0, a4 ; } 6591 6592 because the value of a0 is trashed before the second add can read it. */ 6593 6594static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); 6595 6596static bool 6597find_vinsn_conflicts (vliw_insn *vinsn) 6598{ 6599 int i, j; 6600 int branches = 0; 6601 xtensa_isa isa = xtensa_default_isa; 6602 6603 gas_assert (!past_xtensa_end); 6604 6605 for (i = 0 ; i < vinsn->num_slots; i++) 6606 { 6607 TInsn *op1 = &vinsn->slots[i]; 6608 if (op1->is_specific_opcode) 6609 op1->keep_wide = true; 6610 else 6611 op1->keep_wide = false; 6612 } 6613 6614 for (i = 0 ; i < vinsn->num_slots; i++) 6615 { 6616 TInsn *op1 = &vinsn->slots[i]; 6617 6618 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) 6619 branches++; 6620 6621 for (j = 0; j < vinsn->num_slots; j++) 6622 { 6623 if (i != j) 6624 { 6625 TInsn *op2 = &vinsn->slots[j]; 6626 char conflict_type = check_t1_t2_reads_and_writes (op1, op2); 6627 switch (conflict_type) 6628 { 6629 case 'c': 6630 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), 6631 xtensa_opcode_name (isa, op1->opcode), i, 6632 xtensa_opcode_name (isa, op2->opcode), j); 6633 return true; 6634 case 'd': 6635 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), 6636 xtensa_opcode_name (isa, op1->opcode), i, 6637 xtensa_opcode_name (isa, op2->opcode), j); 6638 return true; 6639 case 'e': 6640 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), 6641 xtensa_opcode_name (isa, op1->opcode), i, 6642 xtensa_opcode_name (isa, op2->opcode), j); 6643 return true; 6644 case 'f': 6645 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), 6646 xtensa_opcode_name (isa, op1->opcode), i, 6647 xtensa_opcode_name (isa, op2->opcode), j); 6648 return true; 6649 default: 6650 /* Everything is OK. */ 6651 break; 6652 } 6653 op2->is_specific_opcode = (op2->is_specific_opcode 6654 || conflict_type == 'a'); 6655 } 6656 } 6657 } 6658 6659 if (branches > 1) 6660 { 6661 as_bad (_("multiple branches or jumps in the same bundle")); 6662 return true; 6663 } 6664 6665 return false; 6666} 6667 6668 6669/* Check how the state used by t1 and t2 relate. 6670 Cases found are: 6671 6672 case A: t1 reads a register t2 writes (an antidependency within a bundle) 6673 case B: no relationship between what is read and written (both could 6674 read the same reg though) 6675 case C: t1 writes a register t2 writes (a register conflict within a 6676 bundle) 6677 case D: t1 writes a state that t2 also writes 6678 case E: t1 writes a tie queue that t2 also writes 6679 case F: two volatile queue accesses 6680*/ 6681 6682static char 6683check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) 6684{ 6685 xtensa_isa isa = xtensa_default_isa; 6686 xtensa_regfile t1_regfile, t2_regfile; 6687 int t1_reg, t2_reg; 6688 int t1_base_reg, t1_last_reg; 6689 int t2_base_reg, t2_last_reg; 6690 char t1_inout, t2_inout; 6691 int i, j; 6692 char conflict = 'b'; 6693 int t1_states; 6694 int t2_states; 6695 int t1_interfaces; 6696 int t2_interfaces; 6697 bool t1_volatile = false; 6698 bool t2_volatile = false; 6699 6700 /* Check registers. */ 6701 for (j = 0; j < t2->ntok; j++) 6702 { 6703 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) 6704 continue; 6705 6706 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); 6707 t2_base_reg = t2->tok[j].X_add_number; 6708 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); 6709 6710 for (i = 0; i < t1->ntok; i++) 6711 { 6712 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) 6713 continue; 6714 6715 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); 6716 6717 if (t1_regfile != t2_regfile) 6718 continue; 6719 6720 t1_inout = xtensa_operand_inout (isa, t1->opcode, i); 6721 t2_inout = xtensa_operand_inout (isa, t2->opcode, j); 6722 6723 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 6724 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) 6725 { 6726 if (t1_inout == 'm' || t1_inout == 'o' 6727 || t2_inout == 'm' || t2_inout == 'o') 6728 { 6729 conflict = 'a'; 6730 continue; 6731 } 6732 } 6733 6734 t1_base_reg = t1->tok[i].X_add_number; 6735 t1_last_reg = (t1_base_reg 6736 + xtensa_operand_num_regs (isa, t1->opcode, i)); 6737 6738 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 6739 { 6740 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 6741 { 6742 if (t1_reg != t2_reg) 6743 continue; 6744 6745 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6746 { 6747 conflict = 'a'; 6748 continue; 6749 } 6750 6751 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6752 { 6753 conflict = 'a'; 6754 continue; 6755 } 6756 6757 if (t1_inout != 'i' && t2_inout != 'i') 6758 return 'c'; 6759 } 6760 } 6761 } 6762 } 6763 6764 /* Check states. */ 6765 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); 6766 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); 6767 for (j = 0; j < t2_states; j++) 6768 { 6769 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); 6770 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); 6771 for (i = 0; i < t1_states; i++) 6772 { 6773 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); 6774 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); 6775 if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) 6776 continue; 6777 6778 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6779 { 6780 conflict = 'a'; 6781 continue; 6782 } 6783 6784 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6785 { 6786 conflict = 'a'; 6787 continue; 6788 } 6789 6790 if (t1_inout != 'i' && t2_inout != 'i') 6791 return 'd'; 6792 } 6793 } 6794 6795 /* Check tieports. */ 6796 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); 6797 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); 6798 for (j = 0; j < t2_interfaces; j++) 6799 { 6800 xtensa_interface t2_int 6801 = xtensa_interfaceOperand_interface (isa, t2->opcode, j); 6802 int t2_class = xtensa_interface_class_id (isa, t2_int); 6803 6804 t2_inout = xtensa_interface_inout (isa, t2_int); 6805 if (xtensa_interface_has_side_effect (isa, t2_int) == 1) 6806 t2_volatile = true; 6807 6808 for (i = 0; i < t1_interfaces; i++) 6809 { 6810 xtensa_interface t1_int 6811 = xtensa_interfaceOperand_interface (isa, t1->opcode, j); 6812 int t1_class = xtensa_interface_class_id (isa, t1_int); 6813 6814 t1_inout = xtensa_interface_inout (isa, t1_int); 6815 if (xtensa_interface_has_side_effect (isa, t1_int) == 1) 6816 t1_volatile = true; 6817 6818 if (t1_volatile && t2_volatile && (t1_class == t2_class)) 6819 return 'f'; 6820 6821 if (t1_int != t2_int) 6822 continue; 6823 6824 if (t2_inout == 'i' && t1_inout == 'o') 6825 { 6826 conflict = 'a'; 6827 continue; 6828 } 6829 6830 if (t1_inout == 'i' && t2_inout == 'o') 6831 { 6832 conflict = 'a'; 6833 continue; 6834 } 6835 6836 if (t1_inout != 'i' && t2_inout != 'i') 6837 return 'e'; 6838 } 6839 } 6840 6841 return conflict; 6842} 6843 6844 6845static xtensa_format 6846xg_find_narrowest_format (vliw_insn *vinsn) 6847{ 6848 /* Right now we assume that the ops within the vinsn are properly 6849 ordered for the slots that the programmer wanted them in. In 6850 other words, we don't rearrange the ops in hopes of finding a 6851 better format. The scheduler handles that. */ 6852 6853 xtensa_isa isa = xtensa_default_isa; 6854 xtensa_format format; 6855 xtensa_opcode nop_opcode = xtensa_nop_opcode; 6856 6857 if (vinsn->num_slots == 1) 6858 return xg_get_single_format (vinsn->slots[0].opcode); 6859 6860 for (format = 0; format < xtensa_isa_num_formats (isa); format++) 6861 { 6862 vliw_insn v_copy; 6863 xg_copy_vinsn (&v_copy, vinsn); 6864 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) 6865 { 6866 int slot; 6867 int fit = 0; 6868 for (slot = 0; slot < v_copy.num_slots; slot++) 6869 { 6870 if (v_copy.slots[slot].opcode == nop_opcode) 6871 { 6872 v_copy.slots[slot].opcode = 6873 xtensa_format_slot_nop_opcode (isa, format, slot); 6874 v_copy.slots[slot].ntok = 0; 6875 } 6876 6877 if (opcode_fits_format_slot (v_copy.slots[slot].opcode, 6878 format, slot)) 6879 fit++; 6880 else if (v_copy.num_slots > 1) 6881 { 6882 TInsn widened; 6883 /* Try the widened version. */ 6884 if (!v_copy.slots[slot].keep_wide 6885 && !v_copy.slots[slot].is_specific_opcode 6886 && xg_is_single_relaxable_insn (&v_copy.slots[slot], 6887 &widened, true) 6888 && opcode_fits_format_slot (widened.opcode, 6889 format, slot)) 6890 { 6891 v_copy.slots[slot] = widened; 6892 fit++; 6893 } 6894 } 6895 } 6896 if (fit == v_copy.num_slots) 6897 { 6898 xg_copy_vinsn (vinsn, &v_copy); 6899 xtensa_format_encode (isa, format, vinsn->insnbuf); 6900 vinsn->format = format; 6901 break; 6902 } 6903 } 6904 } 6905 6906 if (format == xtensa_isa_num_formats (isa)) 6907 return XTENSA_UNDEFINED; 6908 6909 return format; 6910} 6911 6912 6913/* Return the additional space needed in a frag 6914 for possible relaxations of any ops in a VLIW insn. 6915 Also fill out the relaxations that might be required of 6916 each tinsn in the vinsn. */ 6917 6918static int 6919relaxation_requirements (vliw_insn *vinsn, bool *pfinish_frag) 6920{ 6921 bool finish_frag = false; 6922 int extra_space = 0; 6923 int slot; 6924 6925 for (slot = 0; slot < vinsn->num_slots; slot++) 6926 { 6927 TInsn *tinsn = &vinsn->slots[slot]; 6928 if (!tinsn_has_symbolic_operands (tinsn)) 6929 { 6930 /* A narrow instruction could be widened later to help 6931 alignment issues. */ 6932 if (xg_is_single_relaxable_insn (tinsn, 0, true) 6933 && !tinsn->is_specific_opcode 6934 && vinsn->num_slots == 1) 6935 { 6936 /* Difference in bytes between narrow and wide insns... */ 6937 extra_space += 1; 6938 tinsn->subtype = RELAX_NARROW; 6939 } 6940 } 6941 else 6942 { 6943 if (workaround_b_j_loop_end 6944 && tinsn->opcode == xtensa_jx_opcode 6945 && use_transform ()) 6946 { 6947 /* Add 2 of these. */ 6948 extra_space += 3; /* for the nop size */ 6949 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; 6950 } 6951 6952 /* Need to assemble it with space for the relocation. */ 6953 if (xg_is_relaxable_insn (tinsn, 0) 6954 && !tinsn->is_specific_opcode) 6955 { 6956 int max_size = xg_get_max_insn_widen_size (tinsn->opcode); 6957 int max_literal_size = 6958 xg_get_max_insn_widen_literal_size (tinsn->opcode); 6959 6960 tinsn->literal_space = max_literal_size; 6961 6962 tinsn->subtype = RELAX_IMMED; 6963 extra_space += max_size; 6964 } 6965 else 6966 { 6967 /* A fix record will be added for this instruction prior 6968 to relaxation, so make it end the frag. */ 6969 finish_frag = true; 6970 } 6971 } 6972 } 6973 *pfinish_frag = finish_frag; 6974 return extra_space; 6975} 6976 6977 6978static void 6979bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) 6980{ 6981 xtensa_isa isa = xtensa_default_isa; 6982 int slot, chosen_slot; 6983 6984 vinsn->format = xg_get_single_format (tinsn->opcode); 6985 gas_assert (vinsn->format != XTENSA_UNDEFINED); 6986 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); 6987 6988 chosen_slot = xg_get_single_slot (tinsn->opcode); 6989 for (slot = 0; slot < vinsn->num_slots; slot++) 6990 { 6991 if (slot == chosen_slot) 6992 vinsn->slots[slot] = *tinsn; 6993 else 6994 { 6995 vinsn->slots[slot].opcode = 6996 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); 6997 vinsn->slots[slot].ntok = 0; 6998 vinsn->slots[slot].insn_type = ITYPE_INSN; 6999 } 7000 } 7001} 7002 7003 7004static bool 7005emit_single_op (TInsn *orig_insn) 7006{ 7007 int i; 7008 IStack istack; /* put instructions into here */ 7009 symbolS *lit_sym = NULL; 7010 symbolS *label_sym = NULL; 7011 7012 istack_init (&istack); 7013 7014 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. 7015 Because the scheduling and bundling characteristics of movi and 7016 l32r or const16 are so different, we can do much better if we relax 7017 it prior to scheduling and bundling, rather than after. */ 7018 if ((orig_insn->opcode == xtensa_movi_opcode 7019 || orig_insn->opcode == xtensa_movi_n_opcode) 7020 && !cur_vinsn.inside_bundle 7021 && (orig_insn->tok[1].X_op == O_symbol 7022 || orig_insn->tok[1].X_op == O_pltrel 7023 || orig_insn->tok[1].X_op == O_tlsfunc 7024 || orig_insn->tok[1].X_op == O_tlsarg 7025 || orig_insn->tok[1].X_op == O_tpoff 7026 || orig_insn->tok[1].X_op == O_dtpoff) 7027 && !orig_insn->is_specific_opcode && use_transform ()) 7028 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); 7029 else 7030 if (xg_expand_assembly_insn (&istack, orig_insn)) 7031 return true; 7032 7033 for (i = 0; i < istack.ninsn; i++) 7034 { 7035 TInsn *insn = &istack.insn[i]; 7036 switch (insn->insn_type) 7037 { 7038 case ITYPE_LITERAL: 7039 gas_assert (lit_sym == NULL); 7040 lit_sym = xg_assemble_literal (insn); 7041 break; 7042 case ITYPE_LABEL: 7043 { 7044 static int relaxed_sym_idx = 0; 7045 char *label = XNEWVEC (char, strlen (FAKE_LABEL_NAME) + 12); 7046 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); 7047 colon (label); 7048 gas_assert (label_sym == NULL); 7049 label_sym = symbol_find_or_make (label); 7050 gas_assert (label_sym); 7051 free (label); 7052 } 7053 break; 7054 case ITYPE_INSN: 7055 { 7056 vliw_insn v; 7057 if (lit_sym) 7058 xg_resolve_literals (insn, lit_sym); 7059 if (label_sym) 7060 xg_resolve_labels (insn, label_sym); 7061 xg_init_vinsn (&v); 7062 bundle_tinsn (insn, &v); 7063 finish_vinsn (&v); 7064 xg_free_vinsn (&v); 7065 } 7066 break; 7067 default: 7068 gas_assert (0); 7069 break; 7070 } 7071 } 7072 return false; 7073} 7074 7075 7076static int 7077total_frag_text_expansion (fragS *fragP) 7078{ 7079 int slot; 7080 int total_expansion = 0; 7081 7082 for (slot = 0; slot < config_max_slots; slot++) 7083 total_expansion += fragP->tc_frag_data.text_expansion[slot]; 7084 7085 return total_expansion; 7086} 7087 7088 7089/* Emit a vliw instruction to the current fragment. */ 7090 7091static void 7092xg_assemble_vliw_tokens (vliw_insn *vinsn) 7093{ 7094 bool finish_frag; 7095 bool is_jump = false; 7096 bool is_branch = false; 7097 xtensa_isa isa = xtensa_default_isa; 7098 int insn_size; 7099 int extra_space; 7100 char *f = NULL; 7101 int slot; 7102 struct dwarf2_line_info debug_line; 7103 bool loc_directive_seen = false; 7104 TInsn *tinsn; 7105 7106 memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); 7107 7108 if (generating_literals) 7109 { 7110 static int reported = 0; 7111 if (reported < 4) 7112 as_bad_where (frag_now->fr_file, frag_now->fr_line, 7113 _("cannot assemble into a literal fragment")); 7114 if (reported == 3) 7115 as_bad (_("...")); 7116 reported++; 7117 return; 7118 } 7119 7120 if (frag_now_fix () != 0 7121 && (! frag_now->tc_frag_data.is_insn 7122 || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7123 || (!use_transform ()) != frag_now->tc_frag_data.is_no_transform 7124 || (directive_state[directive_longcalls] 7125 != frag_now->tc_frag_data.use_longcalls) 7126 || (directive_state[directive_absolute_literals] 7127 != frag_now->tc_frag_data.use_absolute_literals))) 7128 { 7129 frag_wane (frag_now); 7130 frag_new (0); 7131 xtensa_set_frag_assembly_state (frag_now); 7132 } 7133 7134 if (workaround_a0_b_retw 7135 && vinsn->num_slots == 1 7136 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 7137 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 7138 && use_transform ()) 7139 { 7140 has_a0_b_retw = true; 7141 7142 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. 7143 After the first assembly pass we will check all of them and 7144 add a nop if needed. */ 7145 frag_now->tc_frag_data.is_insn = true; 7146 frag_var (rs_machine_dependent, 4, 4, 7147 RELAX_ADD_NOP_IF_A0_B_RETW, 7148 frag_now->fr_symbol, 7149 frag_now->fr_offset, 7150 NULL); 7151 xtensa_set_frag_assembly_state (frag_now); 7152 frag_now->tc_frag_data.is_insn = true; 7153 frag_var (rs_machine_dependent, 4, 4, 7154 RELAX_ADD_NOP_IF_A0_B_RETW, 7155 frag_now->fr_symbol, 7156 frag_now->fr_offset, 7157 NULL); 7158 xtensa_set_frag_assembly_state (frag_now); 7159 } 7160 7161 for (slot = 0; slot < vinsn->num_slots; slot++) 7162 { 7163 tinsn = &vinsn->slots[slot]; 7164 7165 /* See if the instruction implies an aligned section. */ 7166 if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) 7167 record_alignment (now_seg, 2); 7168 7169 /* Determine the best line number for debug info. */ 7170 if ((tinsn->loc_directive_seen || !loc_directive_seen) 7171 && (tinsn->debug_line.filenum != debug_line.filenum 7172 || tinsn->debug_line.line < debug_line.line 7173 || tinsn->debug_line.column < debug_line.column)) 7174 debug_line = tinsn->debug_line; 7175 if (tinsn->loc_directive_seen) 7176 loc_directive_seen = true; 7177 } 7178 7179 /* Special cases for instructions that force an alignment... */ 7180 /* None of these opcodes are bundle-able. */ 7181 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) 7182 { 7183 int max_fill; 7184 7185 /* Remember the symbol that marks the end of the loop in the frag 7186 that marks the start of the loop. This way we can easily find 7187 the end of the loop at the beginning, without adding special code 7188 to mark the loop instructions themselves. */ 7189 symbolS *target_sym = NULL; 7190 if (vinsn->slots[0].tok[1].X_op == O_symbol) 7191 target_sym = vinsn->slots[0].tok[1].X_add_symbol; 7192 7193 xtensa_set_frag_assembly_state (frag_now); 7194 frag_now->tc_frag_data.is_insn = true; 7195 7196 max_fill = get_text_align_max_fill_size 7197 (get_text_align_power (xtensa_fetch_width), 7198 true, frag_now->tc_frag_data.is_no_density); 7199 7200 if (use_transform ()) 7201 frag_var (rs_machine_dependent, max_fill, max_fill, 7202 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 7203 else 7204 frag_var (rs_machine_dependent, 0, 0, 7205 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 7206 xtensa_set_frag_assembly_state (frag_now); 7207 } 7208 7209 if (vinsn->slots[0].opcode == xtensa_entry_opcode 7210 && !vinsn->slots[0].is_specific_opcode) 7211 { 7212 xtensa_mark_literal_pool_location (); 7213 xtensa_move_labels (frag_now, 0); 7214 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); 7215 } 7216 7217 if (vinsn->num_slots == 1) 7218 { 7219 if (workaround_a0_b_retw && use_transform ()) 7220 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, 7221 is_register_writer (&vinsn->slots[0], "a", 0)); 7222 7223 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, 7224 is_bad_loopend_opcode (&vinsn->slots[0])); 7225 } 7226 else 7227 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, false); 7228 7229 insn_size = xtensa_format_length (isa, vinsn->format); 7230 7231 extra_space = relaxation_requirements (vinsn, &finish_frag); 7232 7233 /* vinsn_to_insnbuf will produce the error. */ 7234 if (vinsn->format != XTENSA_UNDEFINED) 7235 { 7236 f = frag_more (insn_size + extra_space); 7237 xtensa_set_frag_assembly_state (frag_now); 7238 frag_now->tc_frag_data.is_insn = true; 7239 } 7240 7241 vinsn_to_insnbuf (vinsn, f, frag_now, false); 7242 if (vinsn->format == XTENSA_UNDEFINED) 7243 return; 7244 7245 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); 7246 7247 if (debug_type == DEBUG_DWARF2 || loc_directive_seen) 7248 dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), 7249 &debug_line); 7250 7251 for (slot = 0; slot < vinsn->num_slots; slot++) 7252 { 7253 tinsn = &vinsn->slots[slot]; 7254 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; 7255 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; 7256 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; 7257 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; 7258 if (tinsn->opcode == xtensa_l32r_opcode) 7259 frag_now->tc_frag_data.literal_frags[slot] 7260 = symbol_get_frag (tinsn->tok[1].X_add_symbol); 7261 if (tinsn->literal_space != 0) 7262 xg_assemble_literal_space (tinsn->literal_space, slot); 7263 frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; 7264 7265 if (tinsn->subtype == RELAX_NARROW) 7266 gas_assert (vinsn->num_slots == 1); 7267 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) 7268 is_jump = true; 7269 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) 7270 is_branch = true; 7271 7272 if (tinsn->subtype || tinsn->symbol || tinsn->offset 7273 || tinsn->literal_frag || is_jump || is_branch) 7274 finish_frag = true; 7275 } 7276 7277 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7278 frag_now->tc_frag_data.is_specific_opcode = true; 7279 7280 if (finish_frag) 7281 { 7282 frag_variant (rs_machine_dependent, 7283 extra_space, extra_space, RELAX_SLOTS, 7284 frag_now->fr_symbol, frag_now->fr_offset, f); 7285 xtensa_set_frag_assembly_state (frag_now); 7286 } 7287 7288 /* Special cases for loops: 7289 close_loop_end should be inserted AFTER short_loop. 7290 Make sure that CLOSE loops are processed BEFORE short_loops 7291 when converting them. */ 7292 7293 /* "short_loop": Add a NOP if the loop is < 4 bytes. */ 7294 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 7295 && !vinsn->slots[0].is_specific_opcode) 7296 { 7297 if (workaround_short_loop && use_transform ()) 7298 { 7299 maybe_has_short_loop = true; 7300 frag_now->tc_frag_data.is_insn = true; 7301 frag_var (rs_machine_dependent, 4, 4, 7302 RELAX_ADD_NOP_IF_SHORT_LOOP, 7303 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7304 frag_now->tc_frag_data.is_insn = true; 7305 frag_var (rs_machine_dependent, 4, 4, 7306 RELAX_ADD_NOP_IF_SHORT_LOOP, 7307 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7308 } 7309 7310 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a 7311 loop at least 12 bytes away from another loop's end. */ 7312 if (workaround_close_loop_end && use_transform ()) 7313 { 7314 maybe_has_close_loop_end = true; 7315 frag_now->tc_frag_data.is_insn = true; 7316 frag_var (rs_machine_dependent, 12, 12, 7317 RELAX_ADD_NOP_IF_CLOSE_LOOP_END, 7318 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7319 } 7320 } 7321 7322 if (use_transform ()) 7323 { 7324 if (is_jump) 7325 { 7326 gas_assert (finish_frag); 7327 frag_var (rs_machine_dependent, 7328 xtensa_fetch_width, xtensa_fetch_width, 7329 RELAX_UNREACHABLE, 7330 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7331 xtensa_set_frag_assembly_state (frag_now); 7332 xtensa_maybe_create_trampoline_frag (); 7333 /* Always create one here. */ 7334 xtensa_maybe_create_literal_pool_frag (true, false); 7335 } 7336 else if (is_branch && do_align_targets ()) 7337 { 7338 gas_assert (finish_frag); 7339 frag_var (rs_machine_dependent, 7340 xtensa_fetch_width, xtensa_fetch_width, 7341 RELAX_MAYBE_UNREACHABLE, 7342 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7343 xtensa_set_frag_assembly_state (frag_now); 7344 frag_var (rs_machine_dependent, 7345 0, 0, 7346 RELAX_MAYBE_DESIRE_ALIGN, 7347 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7348 xtensa_set_frag_assembly_state (frag_now); 7349 } 7350 } 7351 7352 /* Now, if the original opcode was a call... */ 7353 if (do_align_targets () 7354 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) 7355 { 7356 float freq = get_subseg_total_freq (now_seg, now_subseg); 7357 frag_now->tc_frag_data.is_insn = true; 7358 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, 7359 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7360 xtensa_set_frag_assembly_state (frag_now); 7361 } 7362 7363 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7364 { 7365 frag_wane (frag_now); 7366 frag_new (0); 7367 xtensa_set_frag_assembly_state (frag_now); 7368 } 7369} 7370 7371 7372/* xtensa_end and helper functions. */ 7373 7374static void xtensa_cleanup_align_frags (void); 7375static void xtensa_fix_target_frags (void); 7376static void xtensa_mark_narrow_branches (void); 7377static void xtensa_mark_zcl_first_insns (void); 7378static void xtensa_mark_difference_of_two_symbols (void); 7379static void xtensa_fix_a0_b_retw_frags (void); 7380static void xtensa_fix_b_j_loop_end_frags (void); 7381static void xtensa_fix_close_loop_end_frags (void); 7382static void xtensa_fix_short_loop_frags (void); 7383static void xtensa_sanity_check (void); 7384static void xtensa_add_config_info (void); 7385 7386void 7387xtensa_end (void) 7388{ 7389 directive_balance (); 7390 xtensa_flush_pending_output (); 7391 7392 past_xtensa_end = true; 7393 7394 xtensa_move_literals (); 7395 7396 xtensa_reorder_segments (); 7397 xtensa_cleanup_align_frags (); 7398 xtensa_fix_target_frags (); 7399 if (workaround_a0_b_retw && has_a0_b_retw) 7400 xtensa_fix_a0_b_retw_frags (); 7401 if (workaround_b_j_loop_end) 7402 xtensa_fix_b_j_loop_end_frags (); 7403 7404 /* "close_loop_end" should be processed BEFORE "short_loop". */ 7405 if (workaround_close_loop_end && maybe_has_close_loop_end) 7406 xtensa_fix_close_loop_end_frags (); 7407 7408 if (workaround_short_loop && maybe_has_short_loop) 7409 xtensa_fix_short_loop_frags (); 7410 if (align_targets) 7411 xtensa_mark_narrow_branches (); 7412 xtensa_mark_zcl_first_insns (); 7413 7414 xtensa_sanity_check (); 7415 7416 xtensa_add_config_info (); 7417 7418 xtensa_check_frag_count (); 7419} 7420 7421struct trampoline_chain_entry 7422{ 7423 symbolS *sym; 7424 addressT offset; 7425}; 7426 7427/* Trampoline chain for a given (sym, offset) pair is a sorted array 7428 of locations of trampoline jumps leading there. Jumps are represented 7429 as pairs (sym, offset): trampoline frag symbol and offset of the jump 7430 inside the frag. */ 7431struct trampoline_chain 7432{ 7433 struct trampoline_chain_entry target; 7434 struct trampoline_chain_entry *entry; 7435 size_t n_entries; 7436 size_t n_max; 7437 bool needs_sorting; 7438}; 7439 7440struct trampoline_chain_index 7441{ 7442 struct trampoline_chain *entry; 7443 size_t n_entries; 7444 size_t n_max; 7445 bool needs_sorting; 7446}; 7447 7448struct trampoline_index 7449{ 7450 fragS **entry; 7451 size_t n_entries; 7452 size_t n_max; 7453}; 7454 7455struct trampoline_seg 7456{ 7457 struct trampoline_seg *next; 7458 asection *seg; 7459 /* Trampolines ordered by their frag fr_address */ 7460 struct trampoline_index index; 7461 /* Known trampoline chains ordered by (sym, offset) pair */ 7462 struct trampoline_chain_index chain_index; 7463}; 7464 7465static struct trampoline_seg trampoline_seg_list; 7466#define J_RANGE (128 * 1024) 7467#define J_MARGIN 4096 7468 7469static int unreachable_count = 0; 7470 7471 7472static void 7473xtensa_maybe_create_trampoline_frag (void) 7474{ 7475 if (!use_trampolines) 7476 return; 7477 7478 /* We create an area for possible trampolines every 10 unreachable frags. 7479 These are preferred over the ones not preceded by an unreachable frag, 7480 because we don't have to jump around them. This function is called after 7481 each RELAX_UNREACHABLE frag is created. */ 7482 7483 if (++unreachable_count > 10) 7484 { 7485 xtensa_create_trampoline_frag (false); 7486 clear_frag_count (); 7487 unreachable_count = 0; 7488 } 7489} 7490 7491static void 7492xtensa_check_frag_count (void) 7493{ 7494 if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) 7495 return; 7496 7497 /* We create an area for possible trampolines every 8000 frags or so. This 7498 is an estimate based on the max range of a "j" insn (+/-128K) divided 7499 by a typical frag byte count (16), minus a few for safety. This function 7500 is called after each source line is processed. */ 7501 7502 if (get_frag_count () > 8000) 7503 { 7504 xtensa_create_trampoline_frag (true); 7505 clear_frag_count (); 7506 unreachable_count = 0; 7507 } 7508 7509 /* We create an area for a possible literal pool every N (default 5000) 7510 frags or so. */ 7511 xtensa_maybe_create_literal_pool_frag (true, true); 7512} 7513 7514static xtensa_insnbuf trampoline_buf = NULL; 7515static xtensa_insnbuf trampoline_slotbuf = NULL; 7516 7517static xtensa_insnbuf litpool_buf = NULL; 7518static xtensa_insnbuf litpool_slotbuf = NULL; 7519 7520#define TRAMPOLINE_FRAG_SIZE 3000 7521 7522static struct trampoline_seg * 7523find_trampoline_seg (asection *seg) 7524{ 7525 struct trampoline_seg *ts = trampoline_seg_list.next; 7526 static struct trampoline_seg *mr; 7527 7528 if (mr && mr->seg == seg) 7529 return mr; 7530 7531 for ( ; ts; ts = ts->next) 7532 { 7533 if (ts->seg == seg) 7534 { 7535 mr = ts; 7536 return ts; 7537 } 7538 } 7539 7540 return NULL; 7541} 7542 7543static size_t xg_find_trampoline (const struct trampoline_index *idx, 7544 addressT addr) 7545{ 7546 size_t a = 0; 7547 size_t b = idx->n_entries; 7548 7549 while (b - a > 1) 7550 { 7551 size_t c = (a + b) / 2; 7552 7553 if (idx->entry[c]->fr_address <= addr) 7554 a = c; 7555 else 7556 b = c; 7557 } 7558 return a; 7559} 7560 7561static void xg_add_trampoline_to_index (struct trampoline_index *idx, 7562 fragS *fragP) 7563{ 7564 if (idx->n_entries == idx->n_max) 7565 { 7566 idx->n_max = (idx->n_entries + 1) * 2; 7567 idx->entry = xrealloc (idx->entry, 7568 sizeof (*idx->entry) * idx->n_max); 7569 } 7570 idx->entry[idx->n_entries] = fragP; 7571 ++idx->n_entries; 7572} 7573 7574static void xg_remove_trampoline_from_index (struct trampoline_index *idx, 7575 size_t i) 7576{ 7577 gas_assert (i < idx->n_entries); 7578 memmove (idx->entry + i, idx->entry + i + 1, 7579 (idx->n_entries - i - 1) * sizeof (*idx->entry)); 7580 --idx->n_entries; 7581} 7582 7583static void xg_add_trampoline_to_seg (struct trampoline_seg *ts, 7584 fragS *fragP) 7585{ 7586 xg_add_trampoline_to_index (&ts->index, fragP); 7587} 7588 7589static void 7590xtensa_create_trampoline_frag (bool needs_jump_around) 7591{ 7592 /* Emit a frag where we can place intermediate jump instructions, 7593 in case we need to jump farther than 128K bytes. 7594 Each jump instruction takes three bytes. 7595 We allocate enough for 1000 trampolines in each frag. 7596 If that's not enough, oh well. */ 7597 7598 struct trampoline_seg *ts = find_trampoline_seg (now_seg); 7599 char *varP; 7600 fragS *fragP; 7601 int size = TRAMPOLINE_FRAG_SIZE; 7602 7603 if (ts == NULL) 7604 { 7605 ts = XCNEW(struct trampoline_seg); 7606 ts->next = trampoline_seg_list.next; 7607 trampoline_seg_list.next = ts; 7608 ts->seg = now_seg; 7609 } 7610 7611 frag_wane (frag_now); 7612 frag_new (0); 7613 xtensa_set_frag_assembly_state (frag_now); 7614 varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); 7615 fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); 7616 if (trampoline_buf == NULL) 7617 { 7618 trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); 7619 trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 7620 } 7621 fragP->tc_frag_data.needs_jump_around = needs_jump_around; 7622 xg_add_trampoline_to_seg (ts, fragP); 7623} 7624 7625static bool xg_is_trampoline_frag_full (const fragS *fragP) 7626{ 7627 return fragP->fr_var < 3; 7628} 7629 7630static int xg_order_trampoline_chain_entry (const void *a, const void *b) 7631{ 7632 const struct trampoline_chain_entry *pa = a; 7633 const struct trampoline_chain_entry *pb = b; 7634 7635 if (pa->sym != pb->sym) 7636 { 7637 valueT aval = S_GET_VALUE (pa->sym); 7638 valueT bval = S_GET_VALUE (pb->sym); 7639 7640 if (aval != bval) 7641 return aval < bval ? -1 : 1; 7642 } 7643 if (pa->offset != pb->offset) 7644 return pa->offset < pb->offset ? -1 : 1; 7645 return 0; 7646} 7647 7648static void xg_sort_trampoline_chain (struct trampoline_chain *tc) 7649{ 7650 qsort (tc->entry, tc->n_entries, sizeof (*tc->entry), 7651 xg_order_trampoline_chain_entry); 7652 tc->needs_sorting = false; 7653} 7654 7655/* Find entry index in the given chain with maximal address <= source. */ 7656static size_t xg_find_chain_entry (struct trampoline_chain *tc, 7657 addressT source) 7658{ 7659 size_t a = 0; 7660 size_t b = tc->n_entries; 7661 7662 if (tc->needs_sorting) 7663 xg_sort_trampoline_chain (tc); 7664 7665 while (b - a > 1) 7666 { 7667 size_t c = (a + b) / 2; 7668 struct trampoline_chain_entry *e = tc->entry + c; 7669 7670 if (S_GET_VALUE(e->sym) + e->offset <= source) 7671 a = c; 7672 else 7673 b = c; 7674 } 7675 return a; 7676} 7677 7678/* Find the best jump target for the source in the given trampoline chain. 7679 The best jump target is the one that results in the shortest path to the 7680 final target, it's the location of the jump closest to the final target, 7681 but within the J_RANGE - J_MARGIN from the source. */ 7682static struct trampoline_chain_entry * 7683xg_get_best_chain_entry (struct trampoline_chain *tc, addressT source) 7684{ 7685 addressT target = S_GET_VALUE(tc->target.sym) + tc->target.offset; 7686 size_t i = xg_find_chain_entry (tc, source); 7687 struct trampoline_chain_entry *e = tc->entry + i; 7688 int step = target < source ? -1 : 1; 7689 addressT chained_target; 7690 offsetT off; 7691 7692 if (target > source && 7693 S_GET_VALUE(e->sym) + e->offset <= source && 7694 i + 1 < tc->n_entries) 7695 ++i; 7696 7697 while (i + step < tc->n_entries) 7698 { 7699 struct trampoline_chain_entry *next = tc->entry + i + step; 7700 7701 chained_target = S_GET_VALUE(next->sym) + next->offset; 7702 off = source - chained_target; 7703 7704 if (labs (off) >= J_RANGE - J_MARGIN) 7705 break; 7706 7707 i += step; 7708 } 7709 7710 e = tc->entry + i; 7711 chained_target = S_GET_VALUE(e->sym) + e->offset; 7712 off = source - chained_target; 7713 7714 if (labs (off) < J_MARGIN || 7715 labs (off) >= J_RANGE - J_MARGIN) 7716 return &tc->target; 7717 return tc->entry + i; 7718} 7719 7720static int xg_order_trampoline_chain (const void *a, const void *b) 7721{ 7722 const struct trampoline_chain *_pa = a; 7723 const struct trampoline_chain *_pb = b; 7724 const struct trampoline_chain_entry *pa = &_pa->target; 7725 const struct trampoline_chain_entry *pb = &_pb->target; 7726 symbolS *s1 = pa->sym; 7727 symbolS *s2 = pb->sym; 7728 7729 if (s1 != s2) 7730 { 7731 symbolS *tmp = symbol_symbolS (s1); 7732 if (tmp) 7733 s1 = tmp; 7734 7735 tmp = symbol_symbolS (s2); 7736 if (tmp) 7737 s2 = tmp; 7738 7739 if (s1 != s2) 7740 return s1 < s2 ? -1 : 1; 7741 } 7742 7743 if (pa->offset != pb->offset) 7744 return pa->offset < pb->offset ? -1 : 1; 7745 return 0; 7746} 7747 7748static struct trampoline_chain * 7749xg_get_trampoline_chain (struct trampoline_seg *ts, 7750 symbolS *sym, 7751 addressT offset) 7752{ 7753 struct trampoline_chain_index *idx = &ts->chain_index; 7754 struct trampoline_chain c; 7755 7756 if (idx->n_entries == 0) 7757 return NULL; 7758 7759 if (idx->needs_sorting) 7760 { 7761 qsort (idx->entry, idx->n_entries, sizeof (*idx->entry), 7762 xg_order_trampoline_chain); 7763 idx->needs_sorting = false; 7764 } 7765 c.target.sym = sym; 7766 c.target.offset = offset; 7767 return bsearch (&c, idx->entry, idx->n_entries, 7768 sizeof (struct trampoline_chain), 7769 xg_order_trampoline_chain); 7770} 7771 7772/* Find trampoline chain in the given trampoline segment that is going 7773 to the *sym + *offset. If found, replace *sym and *offset with the 7774 best jump target in that chain. */ 7775static struct trampoline_chain * 7776xg_find_best_eq_target (struct trampoline_seg *ts, 7777 addressT source, symbolS **sym, 7778 addressT *offset) 7779{ 7780 struct trampoline_chain *tc = xg_get_trampoline_chain (ts, *sym, *offset); 7781 7782 if (tc) 7783 { 7784 struct trampoline_chain_entry *e = xg_get_best_chain_entry (tc, source); 7785 7786 *sym = e->sym; 7787 *offset = e->offset; 7788 } 7789 return tc; 7790} 7791 7792static void xg_add_location_to_chain (struct trampoline_chain *tc, 7793 symbolS *sym, addressT offset) 7794{ 7795 struct trampoline_chain_entry *e; 7796 7797 if (tc->n_entries == tc->n_max) 7798 { 7799 tc->n_max = (tc->n_max + 1) * 2; 7800 tc->entry = xrealloc (tc->entry, sizeof (*tc->entry) * tc->n_max); 7801 } 7802 e = tc->entry + tc->n_entries; 7803 e->sym = sym; 7804 e->offset = offset; 7805 ++tc->n_entries; 7806 tc->needs_sorting = true; 7807} 7808 7809static struct trampoline_chain * 7810xg_create_trampoline_chain (struct trampoline_seg *ts, 7811 symbolS *sym, addressT offset) 7812{ 7813 struct trampoline_chain_index *idx = &ts->chain_index; 7814 struct trampoline_chain *tc; 7815 7816 if (idx->n_entries == idx->n_max) 7817 { 7818 idx->n_max = (idx->n_max + 1) * 2; 7819 idx->entry = xrealloc (idx->entry, 7820 sizeof (*idx->entry) * idx->n_max); 7821 } 7822 7823 tc = idx->entry + idx->n_entries; 7824 tc->target.sym = sym; 7825 tc->target.offset = offset; 7826 tc->entry = NULL; 7827 tc->n_entries = 0; 7828 tc->n_max = 0; 7829 xg_add_location_to_chain (tc, sym, offset); 7830 7831 ++idx->n_entries; 7832 idx->needs_sorting = true; 7833 7834 return tc; 7835} 7836 7837void dump_trampolines (void); 7838 7839void 7840dump_trampolines (void) 7841{ 7842 struct trampoline_seg *ts = trampoline_seg_list.next; 7843 7844 for ( ; ts; ts = ts->next) 7845 { 7846 size_t i; 7847 asection *seg = ts->seg; 7848 7849 if (seg == NULL) 7850 continue; 7851 fprintf(stderr, "SECTION %s\n", seg->name); 7852 7853 for (i = 0; i < ts->index.n_entries; ++i) 7854 { 7855 fragS *tf = ts->index.entry[i]; 7856 7857 fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", 7858 (int)tf->fr_address, (int)tf->fr_fix, 7859 tf->tc_frag_data.needs_jump_around ? "T" : "F"); 7860 } 7861 } 7862} 7863 7864static void dump_litpools (void) __attribute__ ((unused)); 7865 7866static void 7867dump_litpools (void) 7868{ 7869 struct litpool_seg *lps = litpool_seg_list.next; 7870 struct litpool_frag *lpf; 7871 7872 for ( ; lps ; lps = lps->next ) 7873 { 7874 printf("litpool seg %s\n", lps->seg->name); 7875 for ( lpf = lps->frag_list.next; lpf->fragP; lpf = lpf->next ) 7876 { 7877 fragS *litfrag = lpf->fragP->fr_next; 7878 int count = 0; 7879 while (litfrag && litfrag->fr_subtype != RELAX_LITERAL_POOL_END) 7880 { 7881 if (litfrag->fr_fix == 4) 7882 count++; 7883 litfrag = litfrag->fr_next; 7884 } 7885 printf(" %ld <%d:%d> (%d) [%d]: ", 7886 lpf->addr, lpf->priority, lpf->original_priority, 7887 lpf->fragP->fr_line, count); 7888 /* dump_frag(lpf->fragP); */ 7889 } 7890 } 7891} 7892 7893static void 7894xtensa_maybe_create_literal_pool_frag (bool create, bool only_if_needed) 7895{ 7896 struct litpool_seg *lps = litpool_seg_list.next; 7897 fragS *fragP; 7898 struct litpool_frag *lpf; 7899 bool needed = false; 7900 7901 if (use_literal_section || !auto_litpools) 7902 return; 7903 7904 for ( ; lps ; lps = lps->next ) 7905 { 7906 if (lps->seg == now_seg) 7907 break; 7908 } 7909 7910 if (lps == NULL) 7911 { 7912 lps = XCNEW (struct litpool_seg); 7913 lps->next = litpool_seg_list.next; 7914 litpool_seg_list.next = lps; 7915 lps->seg = now_seg; 7916 lps->frag_list.next = &lps->frag_list; 7917 lps->frag_list.prev = &lps->frag_list; 7918 /* Put candidate literal pool at the beginning of every section, 7919 so that even when section starts with literal load there's a 7920 literal pool available. */ 7921 lps->frag_count = auto_litpool_limit; 7922 } 7923 7924 lps->frag_count++; 7925 7926 if (create) 7927 { 7928 if (only_if_needed) 7929 { 7930 if (past_xtensa_end || !use_transform() || 7931 frag_now->tc_frag_data.is_no_transform) 7932 { 7933 return; 7934 } 7935 if (auto_litpool_limit <= 0) 7936 { 7937 /* Don't create a litpool based only on frag count. */ 7938 return; 7939 } 7940 else if (lps->frag_count > auto_litpool_limit) 7941 { 7942 needed = true; 7943 } 7944 else 7945 { 7946 return; 7947 } 7948 } 7949 else 7950 { 7951 needed = true; 7952 } 7953 } 7954 7955 if (needed) 7956 { 7957 int size = (only_if_needed) ? 3 : 0; /* Space for a "j" insn. */ 7958 /* Create a potential site for a literal pool. */ 7959 frag_wane (frag_now); 7960 frag_new (0); 7961 xtensa_set_frag_assembly_state (frag_now); 7962 fragP = frag_now; 7963 fragP->tc_frag_data.lit_frchain = frchain_now; 7964 fragP->tc_frag_data.literal_frag = fragP; 7965 frag_var (rs_machine_dependent, size, size, 7966 (only_if_needed) ? 7967 RELAX_LITERAL_POOL_CANDIDATE_BEGIN : 7968 RELAX_LITERAL_POOL_BEGIN, 7969 NULL, 0, NULL); 7970 frag_now->tc_frag_data.lit_seg = now_seg; 7971 frag_variant (rs_machine_dependent, 0, 0, 7972 RELAX_LITERAL_POOL_END, NULL, 0, NULL); 7973 xtensa_set_frag_assembly_state (frag_now); 7974 } 7975 else 7976 { 7977 /* RELAX_LITERAL_POOL_BEGIN frag is being created; 7978 just record it here. */ 7979 fragP = frag_now; 7980 } 7981 7982 lpf = XNEW (struct litpool_frag); 7983 /* Insert at tail of circular list. */ 7984 lpf->addr = 0; 7985 lps->frag_list.prev->next = lpf; 7986 lpf->next = &lps->frag_list; 7987 lpf->prev = lps->frag_list.prev; 7988 lps->frag_list.prev = lpf; 7989 lpf->fragP = fragP; 7990 lpf->priority = (needed) ? (only_if_needed) ? 3 : 2 : 1; 7991 lpf->original_priority = lpf->priority; 7992 lpf->literal_count = 0; 7993 7994 lps->frag_count = 0; 7995} 7996 7997static void 7998xtensa_cleanup_align_frags (void) 7999{ 8000 frchainS *frchP; 8001 asection *s; 8002 8003 for (s = stdoutput->sections; s; s = s->next) 8004 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8005 { 8006 fragS *fragP; 8007 /* Walk over all of the fragments in a subsection. */ 8008 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8009 { 8010 if ((fragP->fr_type == rs_align 8011 || fragP->fr_type == rs_align_code 8012 || (fragP->fr_type == rs_machine_dependent 8013 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN 8014 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) 8015 && fragP->fr_fix == 0) 8016 { 8017 fragS *next = fragP->fr_next; 8018 8019 while (next 8020 && next->fr_fix == 0 8021 && next->fr_type == rs_machine_dependent 8022 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 8023 { 8024 frag_wane (next); 8025 next = next->fr_next; 8026 } 8027 } 8028 /* If we don't widen branch targets, then they 8029 will be easier to align. */ 8030 if (fragP->tc_frag_data.is_branch_target 8031 && fragP->fr_opcode == fragP->fr_literal 8032 && fragP->fr_type == rs_machine_dependent 8033 && fragP->fr_subtype == RELAX_SLOTS 8034 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8035 frag_wane (fragP); 8036 if (fragP->fr_type == rs_machine_dependent 8037 && fragP->fr_subtype == RELAX_UNREACHABLE) 8038 fragP->tc_frag_data.is_unreachable = true; 8039 } 8040 } 8041} 8042 8043 8044/* Re-process all of the fragments looking to convert all of the 8045 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch 8046 target in the next fragment, convert this to RELAX_DESIRE_ALIGN. 8047 Otherwise, convert to a .fill 0. */ 8048 8049static void 8050xtensa_fix_target_frags (void) 8051{ 8052 frchainS *frchP; 8053 asection *s; 8054 8055 /* When this routine is called, all of the subsections are still intact 8056 so we walk over subsections instead of sections. */ 8057 for (s = stdoutput->sections; s; s = s->next) 8058 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8059 { 8060 fragS *fragP; 8061 8062 /* Walk over all of the fragments in a subsection. */ 8063 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8064 { 8065 if (fragP->fr_type == rs_machine_dependent 8066 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 8067 { 8068 if (next_frag_is_branch_target (fragP)) 8069 fragP->fr_subtype = RELAX_DESIRE_ALIGN; 8070 else 8071 frag_wane (fragP); 8072 } 8073 } 8074 } 8075} 8076 8077 8078static bool is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); 8079 8080static void 8081xtensa_mark_narrow_branches (void) 8082{ 8083 frchainS *frchP; 8084 asection *s; 8085 8086 for (s = stdoutput->sections; s; s = s->next) 8087 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8088 { 8089 fragS *fragP; 8090 /* Walk over all of the fragments in a subsection. */ 8091 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8092 { 8093 if (fragP->fr_type == rs_machine_dependent 8094 && fragP->fr_subtype == RELAX_SLOTS 8095 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 8096 { 8097 vliw_insn vinsn; 8098 8099 vinsn_from_chars (&vinsn, fragP->fr_opcode); 8100 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); 8101 8102 if (vinsn.num_slots == 1 8103 && xtensa_opcode_is_branch (xtensa_default_isa, 8104 vinsn.slots[0].opcode) == 1 8105 && xg_get_single_size (vinsn.slots[0].opcode) == 2 8106 && is_narrow_branch_guaranteed_in_range (fragP, 8107 &vinsn.slots[0])) 8108 { 8109 fragP->fr_subtype = RELAX_SLOTS; 8110 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; 8111 fragP->tc_frag_data.is_aligning_branch = 1; 8112 } 8113 } 8114 } 8115 } 8116} 8117 8118 8119/* A branch is typically widened only when its target is out of 8120 range. However, we would like to widen them to align a subsequent 8121 branch target when possible. 8122 8123 Because the branch relaxation code is so convoluted, the optimal solution 8124 (combining the two cases) is difficult to get right in all circumstances. 8125 We therefore go with an "almost as good" solution, where we only 8126 use for alignment narrow branches that definitely will not expand to a 8127 jump and a branch. These functions find and mark these cases. */ 8128 8129/* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded 8130 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. 8131 We start counting beginning with the frag after the 2-byte branch, so the 8132 maximum offset is (4 - 2) + 63 = 65. */ 8133#define MAX_IMMED6 65 8134 8135static offsetT unrelaxed_frag_max_size (fragS *); 8136 8137static bool 8138is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) 8139{ 8140 const expressionS *exp = &tinsn->tok[1]; 8141 symbolS *symbolP = exp->X_add_symbol; 8142 offsetT max_distance = exp->X_add_number; 8143 fragS *target_frag; 8144 8145 if (exp->X_op != O_symbol) 8146 return false; 8147 8148 target_frag = symbol_get_frag (symbolP); 8149 8150 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); 8151 if (is_branch_jmp_to_next (tinsn, fragP)) 8152 return false; 8153 8154 /* The branch doesn't branch over it's own frag, 8155 but over the subsequent ones. */ 8156 fragP = fragP->fr_next; 8157 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) 8158 { 8159 max_distance += unrelaxed_frag_max_size (fragP); 8160 fragP = fragP->fr_next; 8161 } 8162 if (max_distance <= MAX_IMMED6 && fragP == target_frag) 8163 return true; 8164 return false; 8165} 8166 8167 8168static void 8169xtensa_mark_zcl_first_insns (void) 8170{ 8171 frchainS *frchP; 8172 asection *s; 8173 8174 for (s = stdoutput->sections; s; s = s->next) 8175 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8176 { 8177 fragS *fragP; 8178 /* Walk over all of the fragments in a subsection. */ 8179 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8180 { 8181 if (fragP->fr_type == rs_machine_dependent 8182 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 8183 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 8184 { 8185 /* Find the loop frag. */ 8186 fragS *loop_frag = next_non_empty_frag (fragP); 8187 /* Find the first insn frag. */ 8188 fragS *targ_frag = next_non_empty_frag (loop_frag); 8189 8190 /* Handle a corner case that comes up in hardware 8191 diagnostics. The original assembly looks like this: 8192 8193 loop aX, LabelA 8194 <empty_frag>--not found by next_non_empty_frag 8195 loop aY, LabelB 8196 8197 Depending on the start address, the assembler may or 8198 may not change it to look something like this: 8199 8200 loop aX, LabelA 8201 nop--frag isn't empty anymore 8202 loop aY, LabelB 8203 8204 So set up to check the alignment of the nop if it 8205 exists */ 8206 while (loop_frag != targ_frag) 8207 { 8208 if (loop_frag->fr_type == rs_machine_dependent 8209 && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 8210 || loop_frag->fr_subtype 8211 == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 8212 targ_frag = loop_frag; 8213 else 8214 loop_frag = loop_frag->fr_next; 8215 } 8216 8217 /* Of course, sometimes (mostly for toy test cases) a 8218 zero-cost loop instruction is the last in a section. */ 8219 if (targ_frag) 8220 { 8221 targ_frag->tc_frag_data.is_first_loop_insn = true; 8222 /* Do not widen a frag that is the first instruction of a 8223 zero-cost loop. It makes that loop harder to align. */ 8224 if (targ_frag->fr_type == rs_machine_dependent 8225 && targ_frag->fr_subtype == RELAX_SLOTS 8226 && (targ_frag->tc_frag_data.slot_subtypes[0] 8227 == RELAX_NARROW)) 8228 { 8229 if (targ_frag->tc_frag_data.is_aligning_branch) 8230 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 8231 else 8232 { 8233 frag_wane (targ_frag); 8234 targ_frag->tc_frag_data.slot_subtypes[0] = 0; 8235 } 8236 } 8237 } 8238 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) 8239 frag_wane (fragP); 8240 } 8241 } 8242 } 8243} 8244 8245 8246/* When a difference-of-symbols expression is encoded as a uleb128 or 8247 sleb128 value, the linker is unable to adjust that value to account for 8248 link-time relaxation. Mark all the code between such symbols so that 8249 its size cannot be changed by linker relaxation. */ 8250 8251static void 8252xtensa_mark_difference_of_two_symbols (void) 8253{ 8254 symbolS *expr_sym; 8255 8256 for (expr_sym = expr_symbols; expr_sym; 8257 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) 8258 { 8259 expressionS *exp = symbol_get_value_expression (expr_sym); 8260 8261 if (exp->X_op == O_subtract) 8262 { 8263 symbolS *left = exp->X_add_symbol; 8264 symbolS *right = exp->X_op_symbol; 8265 8266 /* Difference of two symbols not in the same section 8267 are handled with relocations in the linker. */ 8268 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) 8269 { 8270 fragS *start; 8271 fragS *end; 8272 fragS *walk; 8273 8274 if (symbol_get_frag (left)->fr_address 8275 <= symbol_get_frag (right)->fr_address) 8276 { 8277 start = symbol_get_frag (left); 8278 end = symbol_get_frag (right); 8279 } 8280 else 8281 { 8282 start = symbol_get_frag (right); 8283 end = symbol_get_frag (left); 8284 } 8285 8286 if (start->tc_frag_data.no_transform_end != NULL) 8287 walk = start->tc_frag_data.no_transform_end; 8288 else 8289 walk = start; 8290 do 8291 { 8292 walk->tc_frag_data.is_no_transform = 1; 8293 walk = walk->fr_next; 8294 } 8295 while (walk && walk->fr_address < end->fr_address); 8296 8297 start->tc_frag_data.no_transform_end = walk; 8298 } 8299 } 8300 } 8301} 8302 8303 8304/* Re-process all of the fragments looking to convert all of the 8305 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a 8306 conditional branch or a retw/retw.n, convert this frag to one that 8307 will generate a NOP. In any case close it off with a .fill 0. */ 8308 8309static bool next_instrs_are_b_retw (fragS *); 8310 8311static void 8312xtensa_fix_a0_b_retw_frags (void) 8313{ 8314 frchainS *frchP; 8315 asection *s; 8316 8317 /* When this routine is called, all of the subsections are still intact 8318 so we walk over subsections instead of sections. */ 8319 for (s = stdoutput->sections; s; s = s->next) 8320 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8321 { 8322 fragS *fragP; 8323 8324 /* Walk over all of the fragments in a subsection. */ 8325 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8326 { 8327 if (fragP->fr_type == rs_machine_dependent 8328 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) 8329 { 8330 if (next_instrs_are_b_retw (fragP)) 8331 { 8332 if (fragP->tc_frag_data.is_no_transform) 8333 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); 8334 else 8335 relax_frag_add_nop (fragP); 8336 } 8337 frag_wane (fragP); 8338 } 8339 } 8340 } 8341} 8342 8343 8344static bool 8345next_instrs_are_b_retw (fragS *fragP) 8346{ 8347 xtensa_opcode opcode; 8348 xtensa_format fmt; 8349 const fragS *next_fragP = next_non_empty_frag (fragP); 8350 static xtensa_insnbuf insnbuf = NULL; 8351 static xtensa_insnbuf slotbuf = NULL; 8352 xtensa_isa isa = xtensa_default_isa; 8353 unsigned int offset = 0; 8354 int slot; 8355 bool branch_seen = false; 8356 8357 if (!insnbuf) 8358 { 8359 insnbuf = xtensa_insnbuf_alloc (isa); 8360 slotbuf = xtensa_insnbuf_alloc (isa); 8361 } 8362 8363 if (next_fragP == NULL) 8364 return false; 8365 8366 /* Check for the conditional branch. */ 8367 xtensa_insnbuf_from_chars 8368 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 8369 fmt = xtensa_format_decode (isa, insnbuf); 8370 if (fmt == XTENSA_UNDEFINED) 8371 return false; 8372 8373 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 8374 { 8375 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 8376 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 8377 8378 branch_seen = (branch_seen 8379 || xtensa_opcode_is_branch (isa, opcode) == 1); 8380 } 8381 8382 if (!branch_seen) 8383 return false; 8384 8385 offset += xtensa_format_length (isa, fmt); 8386 if (offset == next_fragP->fr_fix) 8387 { 8388 next_fragP = next_non_empty_frag (next_fragP); 8389 offset = 0; 8390 } 8391 8392 if (next_fragP == NULL) 8393 return false; 8394 8395 /* Check for the retw/retw.n. */ 8396 xtensa_insnbuf_from_chars 8397 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 8398 fmt = xtensa_format_decode (isa, insnbuf); 8399 8400 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we 8401 have no problems. */ 8402 if (fmt == XTENSA_UNDEFINED 8403 || xtensa_format_num_slots (isa, fmt) != 1) 8404 return false; 8405 8406 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); 8407 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); 8408 8409 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) 8410 return true; 8411 8412 return false; 8413} 8414 8415 8416/* Re-process all of the fragments looking to convert all of the 8417 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a 8418 loop end label, convert this frag to one that will generate a NOP. 8419 In any case close it off with a .fill 0. */ 8420 8421static bool next_instr_is_loop_end (fragS *); 8422 8423static void 8424xtensa_fix_b_j_loop_end_frags (void) 8425{ 8426 frchainS *frchP; 8427 asection *s; 8428 8429 /* When this routine is called, all of the subsections are still intact 8430 so we walk over subsections instead of sections. */ 8431 for (s = stdoutput->sections; s; s = s->next) 8432 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8433 { 8434 fragS *fragP; 8435 8436 /* Walk over all of the fragments in a subsection. */ 8437 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8438 { 8439 if (fragP->fr_type == rs_machine_dependent 8440 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) 8441 { 8442 if (next_instr_is_loop_end (fragP)) 8443 { 8444 if (fragP->tc_frag_data.is_no_transform) 8445 as_bad (_("branching or jumping to a loop end may trigger hardware errata")); 8446 else 8447 relax_frag_add_nop (fragP); 8448 } 8449 frag_wane (fragP); 8450 } 8451 } 8452 } 8453} 8454 8455 8456static bool 8457next_instr_is_loop_end (fragS *fragP) 8458{ 8459 const fragS *next_fragP; 8460 8461 if (next_frag_is_loop_target (fragP)) 8462 return false; 8463 8464 next_fragP = next_non_empty_frag (fragP); 8465 if (next_fragP == NULL) 8466 return false; 8467 8468 if (!next_frag_is_loop_target (next_fragP)) 8469 return false; 8470 8471 /* If the size is >= 3 then there is more than one instruction here. 8472 The hardware bug will not fire. */ 8473 if (next_fragP->fr_fix > 3) 8474 return false; 8475 8476 return true; 8477} 8478 8479 8480/* Re-process all of the fragments looking to convert all of the 8481 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is 8482 not MY loop's loop end within 12 bytes, add enough nops here to 8483 make it at least 12 bytes away. In any case close it off with a 8484 .fill 0. */ 8485 8486static offsetT min_bytes_to_other_loop_end 8487 (fragS *, fragS *, offsetT); 8488 8489static void 8490xtensa_fix_close_loop_end_frags (void) 8491{ 8492 frchainS *frchP; 8493 asection *s; 8494 8495 /* When this routine is called, all of the subsections are still intact 8496 so we walk over subsections instead of sections. */ 8497 for (s = stdoutput->sections; s; s = s->next) 8498 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8499 { 8500 fragS *fragP; 8501 8502 fragS *current_target = NULL; 8503 8504 /* Walk over all of the fragments in a subsection. */ 8505 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8506 { 8507 if (fragP->fr_type == rs_machine_dependent 8508 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 8509 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 8510 current_target = symbol_get_frag (fragP->fr_symbol); 8511 8512 if (current_target 8513 && fragP->fr_type == rs_machine_dependent 8514 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) 8515 { 8516 offsetT min_bytes; 8517 int bytes_added = 0; 8518 8519#define REQUIRED_LOOP_DIVIDING_BYTES 12 8520 /* Max out at 12. */ 8521 min_bytes = min_bytes_to_other_loop_end 8522 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); 8523 8524 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) 8525 { 8526 if (fragP->tc_frag_data.is_no_transform) 8527 as_bad (_("loop end too close to another loop end may trigger hardware errata")); 8528 else 8529 { 8530 while (min_bytes + bytes_added 8531 < REQUIRED_LOOP_DIVIDING_BYTES) 8532 { 8533 int length = 3; 8534 8535 if (fragP->fr_var < length) 8536 as_fatal (_("fr_var %lu < length %d"), 8537 (long) fragP->fr_var, length); 8538 else 8539 { 8540 assemble_nop (length, 8541 fragP->fr_literal + fragP->fr_fix); 8542 fragP->fr_fix += length; 8543 fragP->fr_var -= length; 8544 } 8545 bytes_added += length; 8546 } 8547 } 8548 } 8549 frag_wane (fragP); 8550 } 8551 gas_assert (fragP->fr_type != rs_machine_dependent 8552 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); 8553 } 8554 } 8555} 8556 8557 8558static offsetT unrelaxed_frag_min_size (fragS *); 8559 8560static offsetT 8561min_bytes_to_other_loop_end (fragS *fragP, 8562 fragS *current_target, 8563 offsetT max_size) 8564{ 8565 offsetT offset = 0; 8566 fragS *current_fragP; 8567 8568 for (current_fragP = fragP; 8569 current_fragP; 8570 current_fragP = current_fragP->fr_next) 8571 { 8572 if (current_fragP->tc_frag_data.is_loop_target 8573 && current_fragP != current_target) 8574 return offset; 8575 8576 offset += unrelaxed_frag_min_size (current_fragP); 8577 8578 if (offset >= max_size) 8579 return max_size; 8580 } 8581 return max_size; 8582} 8583 8584 8585static offsetT 8586unrelaxed_frag_min_size (fragS *fragP) 8587{ 8588 offsetT size = fragP->fr_fix; 8589 8590 /* Add fill size. */ 8591 if (fragP->fr_type == rs_fill) 8592 size += fragP->fr_offset; 8593 8594 return size; 8595} 8596 8597 8598static offsetT 8599unrelaxed_frag_max_size (fragS *fragP) 8600{ 8601 offsetT size = fragP->fr_fix; 8602 switch (fragP->fr_type) 8603 { 8604 case 0: 8605 /* Empty frags created by the obstack allocation scheme 8606 end up with type 0. */ 8607 break; 8608 case rs_fill: 8609 case rs_org: 8610 case rs_space: 8611 size += fragP->fr_offset; 8612 break; 8613 case rs_align: 8614 case rs_align_code: 8615 case rs_align_test: 8616 case rs_leb128: 8617 case rs_cfa: 8618 case rs_dwarf2dbg: 8619 /* No further adjustments needed. */ 8620 break; 8621 case rs_machine_dependent: 8622 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) 8623 size += fragP->fr_var; 8624 break; 8625 default: 8626 /* We had darn well better know how big it is. */ 8627 gas_assert (0); 8628 break; 8629 } 8630 8631 return size; 8632} 8633 8634 8635/* Re-process all of the fragments looking to convert all 8636 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: 8637 8638 A) 8639 1) the instruction size count to the loop end label 8640 is too short (<= 2 instructions), 8641 2) loop has a jump or branch in it 8642 8643 or B) 8644 1) workaround_all_short_loops is TRUE 8645 2) The generating loop was a 'loopgtz' or 'loopnez' 8646 3) the instruction size count to the loop end label is too short 8647 (<= 2 instructions) 8648 then convert this frag (and maybe the next one) to generate a NOP. 8649 In any case close it off with a .fill 0. */ 8650 8651static int count_insns_to_loop_end (fragS *, bool, int); 8652static bool branch_before_loop_end (fragS *); 8653 8654static void 8655xtensa_fix_short_loop_frags (void) 8656{ 8657 frchainS *frchP; 8658 asection *s; 8659 8660 /* When this routine is called, all of the subsections are still intact 8661 so we walk over subsections instead of sections. */ 8662 for (s = stdoutput->sections; s; s = s->next) 8663 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8664 { 8665 fragS *fragP; 8666 xtensa_opcode current_opcode = XTENSA_UNDEFINED; 8667 8668 /* Walk over all of the fragments in a subsection. */ 8669 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8670 { 8671 if (fragP->fr_type == rs_machine_dependent 8672 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 8673 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 8674 { 8675 TInsn t_insn; 8676 fragS *loop_frag = next_non_empty_frag (fragP); 8677 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); 8678 current_opcode = t_insn.opcode; 8679 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, 8680 current_opcode) == 1); 8681 } 8682 8683 if (fragP->fr_type == rs_machine_dependent 8684 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 8685 { 8686 if (count_insns_to_loop_end (fragP->fr_next, true, 3) < 3 8687 && (branch_before_loop_end (fragP->fr_next) 8688 || (workaround_all_short_loops 8689 && current_opcode != XTENSA_UNDEFINED 8690 && current_opcode != xtensa_loop_opcode))) 8691 { 8692 if (fragP->tc_frag_data.is_no_transform) 8693 as_bad (_("loop containing less than three instructions may trigger hardware errata")); 8694 else 8695 relax_frag_add_nop (fragP); 8696 } 8697 frag_wane (fragP); 8698 } 8699 } 8700 } 8701} 8702 8703 8704static int unrelaxed_frag_min_insn_count (fragS *); 8705 8706static int 8707count_insns_to_loop_end (fragS *base_fragP, 8708 bool count_relax_add, 8709 int max_count) 8710{ 8711 fragS *fragP = NULL; 8712 int insn_count = 0; 8713 8714 fragP = base_fragP; 8715 8716 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) 8717 { 8718 insn_count += unrelaxed_frag_min_insn_count (fragP); 8719 if (insn_count >= max_count) 8720 return max_count; 8721 8722 if (count_relax_add) 8723 { 8724 if (fragP->fr_type == rs_machine_dependent 8725 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 8726 { 8727 /* In order to add the appropriate number of 8728 NOPs, we count an instruction for downstream 8729 occurrences. */ 8730 insn_count++; 8731 if (insn_count >= max_count) 8732 return max_count; 8733 } 8734 } 8735 } 8736 return insn_count; 8737} 8738 8739 8740static int 8741unrelaxed_frag_min_insn_count (fragS *fragP) 8742{ 8743 xtensa_isa isa = xtensa_default_isa; 8744 static xtensa_insnbuf insnbuf = NULL; 8745 int insn_count = 0; 8746 unsigned int offset = 0; 8747 8748 if (!fragP->tc_frag_data.is_insn) 8749 return insn_count; 8750 8751 if (!insnbuf) 8752 insnbuf = xtensa_insnbuf_alloc (isa); 8753 8754 /* Decode the fixed instructions. */ 8755 while (offset < fragP->fr_fix) 8756 { 8757 xtensa_format fmt; 8758 8759 xtensa_insnbuf_from_chars 8760 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 8761 fmt = xtensa_format_decode (isa, insnbuf); 8762 8763 if (fmt == XTENSA_UNDEFINED) 8764 { 8765 as_fatal (_("undecodable instruction in instruction frag")); 8766 return insn_count; 8767 } 8768 offset += xtensa_format_length (isa, fmt); 8769 insn_count++; 8770 } 8771 8772 return insn_count; 8773} 8774 8775 8776static bool unrelaxed_frag_has_b_j (fragS *); 8777 8778static bool 8779branch_before_loop_end (fragS *base_fragP) 8780{ 8781 fragS *fragP; 8782 8783 for (fragP = base_fragP; 8784 fragP && !fragP->tc_frag_data.is_loop_target; 8785 fragP = fragP->fr_next) 8786 { 8787 if (unrelaxed_frag_has_b_j (fragP)) 8788 return true; 8789 } 8790 return false; 8791} 8792 8793 8794static bool 8795unrelaxed_frag_has_b_j (fragS *fragP) 8796{ 8797 static xtensa_insnbuf insnbuf = NULL; 8798 xtensa_isa isa = xtensa_default_isa; 8799 unsigned int offset = 0; 8800 8801 if (!fragP->tc_frag_data.is_insn) 8802 return false; 8803 8804 if (!insnbuf) 8805 insnbuf = xtensa_insnbuf_alloc (isa); 8806 8807 /* Decode the fixed instructions. */ 8808 while (offset < fragP->fr_fix) 8809 { 8810 xtensa_format fmt; 8811 int slot; 8812 8813 xtensa_insnbuf_from_chars 8814 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 8815 fmt = xtensa_format_decode (isa, insnbuf); 8816 if (fmt == XTENSA_UNDEFINED) 8817 return false; 8818 8819 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 8820 { 8821 xtensa_opcode opcode = 8822 get_opcode_from_buf (fragP->fr_literal + offset, slot); 8823 if (xtensa_opcode_is_branch (isa, opcode) == 1 8824 || xtensa_opcode_is_jump (isa, opcode) == 1) 8825 return true; 8826 } 8827 offset += xtensa_format_length (isa, fmt); 8828 } 8829 return false; 8830} 8831 8832 8833/* Checks to be made after initial assembly but before relaxation. */ 8834 8835static bool is_empty_loop (const TInsn *, fragS *); 8836static bool is_local_forward_loop (const TInsn *, fragS *); 8837 8838static void 8839xtensa_sanity_check (void) 8840{ 8841 const char *file_name; 8842 unsigned line; 8843 frchainS *frchP; 8844 asection *s; 8845 8846 file_name = as_where (&line); 8847 for (s = stdoutput->sections; s; s = s->next) 8848 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8849 { 8850 fragS *fragP; 8851 8852 /* Walk over all of the fragments in a subsection. */ 8853 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8854 { 8855 if (fragP->fr_type == rs_machine_dependent 8856 && fragP->fr_subtype == RELAX_SLOTS 8857 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 8858 { 8859 static xtensa_insnbuf insnbuf = NULL; 8860 TInsn t_insn; 8861 8862 if (fragP->fr_opcode != NULL) 8863 { 8864 if (!insnbuf) 8865 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 8866 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); 8867 tinsn_immed_from_frag (&t_insn, fragP, 0); 8868 8869 if (xtensa_opcode_is_loop (xtensa_default_isa, 8870 t_insn.opcode) == 1) 8871 { 8872 if (is_empty_loop (&t_insn, fragP)) 8873 { 8874 new_logical_line (fragP->fr_file, fragP->fr_line); 8875 as_bad (_("invalid empty loop")); 8876 } 8877 if (!is_local_forward_loop (&t_insn, fragP)) 8878 { 8879 new_logical_line (fragP->fr_file, fragP->fr_line); 8880 as_bad (_("loop target does not follow " 8881 "loop instruction in section")); 8882 } 8883 } 8884 } 8885 } 8886 } 8887 } 8888 new_logical_line (file_name, line); 8889} 8890 8891 8892#define LOOP_IMMED_OPN 1 8893 8894/* Return TRUE if the loop target is the next non-zero fragment. */ 8895 8896static bool 8897is_empty_loop (const TInsn *insn, fragS *fragP) 8898{ 8899 const expressionS *exp; 8900 symbolS *symbolP; 8901 fragS *next_fragP; 8902 8903 if (insn->insn_type != ITYPE_INSN) 8904 return false; 8905 8906 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8907 return false; 8908 8909 if (insn->ntok <= LOOP_IMMED_OPN) 8910 return false; 8911 8912 exp = &insn->tok[LOOP_IMMED_OPN]; 8913 8914 if (exp->X_op != O_symbol) 8915 return false; 8916 8917 symbolP = exp->X_add_symbol; 8918 if (!symbolP) 8919 return false; 8920 8921 if (symbol_get_frag (symbolP) == NULL) 8922 return false; 8923 8924 if (S_GET_VALUE (symbolP) != 0) 8925 return false; 8926 8927 /* Walk through the zero-size fragments from this one. If we find 8928 the target fragment, then this is a zero-size loop. */ 8929 8930 for (next_fragP = fragP->fr_next; 8931 next_fragP != NULL; 8932 next_fragP = next_fragP->fr_next) 8933 { 8934 if (next_fragP == symbol_get_frag (symbolP)) 8935 return true; 8936 if (next_fragP->fr_fix != 0) 8937 return false; 8938 } 8939 return false; 8940} 8941 8942 8943static bool 8944is_local_forward_loop (const TInsn *insn, fragS *fragP) 8945{ 8946 const expressionS *exp; 8947 symbolS *symbolP; 8948 fragS *next_fragP; 8949 8950 if (insn->insn_type != ITYPE_INSN) 8951 return false; 8952 8953 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8954 return false; 8955 8956 if (insn->ntok <= LOOP_IMMED_OPN) 8957 return false; 8958 8959 exp = &insn->tok[LOOP_IMMED_OPN]; 8960 8961 if (exp->X_op != O_symbol) 8962 return false; 8963 8964 symbolP = exp->X_add_symbol; 8965 if (!symbolP) 8966 return false; 8967 8968 if (symbol_get_frag (symbolP) == NULL) 8969 return false; 8970 8971 /* Walk through fragments until we find the target. 8972 If we do not find the target, then this is an invalid loop. */ 8973 8974 for (next_fragP = fragP->fr_next; 8975 next_fragP != NULL; 8976 next_fragP = next_fragP->fr_next) 8977 { 8978 if (next_fragP == symbol_get_frag (symbolP)) 8979 return true; 8980 } 8981 8982 return false; 8983} 8984 8985#define XTINFO_NAME "Xtensa_Info" 8986#define XTINFO_NAMESZ 12 8987#define XTINFO_TYPE 1 8988 8989static void 8990xtensa_add_config_info (void) 8991{ 8992 asection *info_sec; 8993 char *data, *p; 8994 int sz; 8995 8996 info_sec = subseg_new (".xtensa.info", 0); 8997 bfd_set_section_flags (info_sec, SEC_HAS_CONTENTS | SEC_READONLY); 8998 8999 data = XNEWVEC (char, 100); 9000 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", 9001 XSHAL_USE_ABSOLUTE_LITERALS, xtensa_abi_choice ()); 9002 sz = strlen (data) + 1; 9003 9004 /* Add enough null terminators to pad to a word boundary. */ 9005 do 9006 data[sz++] = 0; 9007 while ((sz & 3) != 0); 9008 9009 /* Follow the standard note section layout: 9010 First write the length of the name string. */ 9011 p = frag_more (4); 9012 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); 9013 9014 /* Next comes the length of the "descriptor", i.e., the actual data. */ 9015 p = frag_more (4); 9016 md_number_to_chars (p, (valueT) sz, 4); 9017 9018 /* Write the note type. */ 9019 p = frag_more (4); 9020 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); 9021 9022 /* Write the name field. */ 9023 p = frag_more (XTINFO_NAMESZ); 9024 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); 9025 9026 /* Finally, write the descriptor. */ 9027 p = frag_more (sz); 9028 memcpy (p, data, sz); 9029 9030 free (data); 9031} 9032 9033 9034/* Alignment Functions. */ 9035 9036static int 9037get_text_align_power (unsigned target_size) 9038{ 9039 if (target_size <= 4) 9040 return 2; 9041 9042 if (target_size <= 8) 9043 return 3; 9044 9045 if (target_size <= 16) 9046 return 4; 9047 9048 if (target_size <= 32) 9049 return 5; 9050 9051 if (target_size <= 64) 9052 return 6; 9053 9054 if (target_size <= 128) 9055 return 7; 9056 9057 if (target_size <= 256) 9058 return 8; 9059 9060 if (target_size <= 512) 9061 return 9; 9062 9063 if (target_size <= 1024) 9064 return 10; 9065 9066 gas_assert (0); 9067 return 0; 9068} 9069 9070 9071static int 9072get_text_align_max_fill_size (int align_pow, 9073 bool use_nops, 9074 bool use_no_density) 9075{ 9076 if (!use_nops) 9077 return (1 << align_pow); 9078 if (use_no_density) 9079 return 3 * (1 << align_pow); 9080 9081 return 1 + (1 << align_pow); 9082} 9083 9084 9085/* Calculate the minimum bytes of fill needed at "address" to align a 9086 target instruction of size "target_size" so that it does not cross a 9087 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, 9088 the fill can be an arbitrary number of bytes. Otherwise, the space must 9089 be filled by NOP instructions. */ 9090 9091static int 9092get_text_align_fill_size (addressT address, 9093 int align_pow, 9094 int target_size, 9095 bool use_nops, 9096 bool use_no_density) 9097{ 9098 addressT alignment, fill, fill_limit, fill_step; 9099 bool skip_one = false; 9100 9101 alignment = (1 << align_pow); 9102 gas_assert (target_size > 0 && alignment >= (addressT) target_size); 9103 9104 if (!use_nops) 9105 { 9106 fill_limit = alignment; 9107 fill_step = 1; 9108 } 9109 else if (!use_no_density) 9110 { 9111 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ 9112 fill_limit = alignment * 2; 9113 fill_step = 1; 9114 skip_one = true; 9115 } 9116 else 9117 { 9118 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ 9119 fill_limit = alignment * 3; 9120 fill_step = 3; 9121 } 9122 9123 /* Try all fill sizes until finding one that works. */ 9124 for (fill = 0; fill < fill_limit; fill += fill_step) 9125 { 9126 if (skip_one && fill == 1) 9127 continue; 9128 if ((address + fill) >> align_pow 9129 == (address + fill + target_size - 1) >> align_pow) 9130 return fill; 9131 } 9132 gas_assert (0); 9133 return 0; 9134} 9135 9136 9137static int 9138branch_align_power (segT sec) 9139{ 9140 /* If the Xtensa processor has a fetch width of X, and 9141 the section is aligned to at least that boundary, then a branch 9142 target need only fit within that aligned block of memory to avoid 9143 a stall. Otherwise, try to fit branch targets within 4-byte 9144 aligned blocks (which may be insufficient, e.g., if the section 9145 has no alignment, but it's good enough). */ 9146 int fetch_align = get_text_align_power(xtensa_fetch_width); 9147 int sec_align = get_recorded_alignment (sec); 9148 9149 if (sec_align >= fetch_align) 9150 return fetch_align; 9151 9152 return 2; 9153} 9154 9155 9156/* This will assert if it is not possible. */ 9157 9158static int 9159get_text_align_nop_count (offsetT fill_size, bool use_no_density) 9160{ 9161 int count = 0; 9162 9163 if (use_no_density) 9164 { 9165 gas_assert (fill_size % 3 == 0); 9166 return (fill_size / 3); 9167 } 9168 9169 gas_assert (fill_size != 1); /* Bad argument. */ 9170 9171 while (fill_size > 1) 9172 { 9173 int insn_size = 3; 9174 if (fill_size == 2 || fill_size == 4) 9175 insn_size = 2; 9176 fill_size -= insn_size; 9177 count++; 9178 } 9179 gas_assert (fill_size != 1); /* Bad algorithm. */ 9180 return count; 9181} 9182 9183 9184static int 9185get_text_align_nth_nop_size (offsetT fill_size, 9186 int n, 9187 bool use_no_density) 9188{ 9189 int count = 0; 9190 9191 if (use_no_density) 9192 return 3; 9193 9194 gas_assert (fill_size != 1); /* Bad argument. */ 9195 9196 while (fill_size > 1) 9197 { 9198 int insn_size = 3; 9199 if (fill_size == 2 || fill_size == 4) 9200 insn_size = 2; 9201 fill_size -= insn_size; 9202 count++; 9203 if (n + 1 == count) 9204 return insn_size; 9205 } 9206 gas_assert (0); 9207 return 0; 9208} 9209 9210 9211/* For the given fragment, find the appropriate address 9212 for it to begin at if we are using NOPs to align it. */ 9213 9214static addressT 9215get_noop_aligned_address (fragS *fragP, addressT address) 9216{ 9217 /* The rule is: get next fragment's FIRST instruction. Find 9218 the smallest number of bytes that need to be added to 9219 ensure that the next fragment's FIRST instruction will fit 9220 in a single word. 9221 9222 E.G., 2 bytes : 0, 1, 2 mod 4 9223 3 bytes: 0, 1 mod 4 9224 9225 If the FIRST instruction MIGHT be relaxed, 9226 assume that it will become a 3-byte instruction. 9227 9228 Note again here that LOOP instructions are not bundleable, 9229 and this relaxation only applies to LOOP opcodes. */ 9230 9231 int fill_size = 0; 9232 int first_insn_size; 9233 int loop_insn_size; 9234 addressT pre_opcode_bytes; 9235 int align_power; 9236 fragS *first_insn; 9237 xtensa_opcode opcode; 9238 bool is_loop; 9239 9240 gas_assert (fragP->fr_type == rs_machine_dependent); 9241 gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); 9242 9243 /* Find the loop frag. */ 9244 first_insn = next_non_empty_frag (fragP); 9245 /* Now find the first insn frag. */ 9246 first_insn = next_non_empty_frag (first_insn); 9247 9248 is_loop = next_frag_opcode_is_loop (fragP, &opcode); 9249 gas_assert (is_loop); 9250 loop_insn_size = xg_get_single_size (opcode); 9251 9252 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); 9253 pre_opcode_bytes += loop_insn_size; 9254 9255 /* For loops, the alignment depends on the size of the 9256 instruction following the loop, not the LOOP instruction. */ 9257 9258 if (first_insn == NULL) 9259 first_insn_size = xtensa_fetch_width; 9260 else 9261 first_insn_size = get_loop_align_size (frag_format_size (first_insn)); 9262 9263 /* If it was 8, then we'll need a larger alignment for the section. */ 9264 align_power = get_text_align_power (first_insn_size); 9265 record_alignment (now_seg, align_power); 9266 9267 fill_size = get_text_align_fill_size 9268 (address + pre_opcode_bytes, align_power, first_insn_size, true, 9269 fragP->tc_frag_data.is_no_density); 9270 9271 return address + fill_size; 9272} 9273 9274 9275/* 3 mechanisms for relaxing an alignment: 9276 9277 Align to a power of 2. 9278 Align so the next fragment's instruction does not cross a word boundary. 9279 Align the current instruction so that if the next instruction 9280 were 3 bytes, it would not cross a word boundary. 9281 9282 We can align with: 9283 9284 zeros - This is easy; always insert zeros. 9285 nops - 3-byte and 2-byte instructions 9286 2 - 2-byte nop 9287 3 - 3-byte nop 9288 4 - 2 2-byte nops 9289 >=5 : 3-byte instruction + fn (n-3) 9290 widening - widen previous instructions. */ 9291 9292static offsetT 9293get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) 9294{ 9295 addressT target_address, loop_insn_offset; 9296 int target_size; 9297 xtensa_opcode loop_opcode; 9298 bool is_loop; 9299 int align_power; 9300 offsetT opt_diff; 9301 offsetT branch_align; 9302 fragS *loop_frag; 9303 9304 gas_assert (fragP->fr_type == rs_machine_dependent); 9305 switch (fragP->fr_subtype) 9306 { 9307 case RELAX_DESIRE_ALIGN: 9308 target_size = next_frag_format_size (fragP); 9309 if (target_size == XTENSA_UNDEFINED) 9310 target_size = 3; 9311 align_power = branch_align_power (now_seg); 9312 branch_align = 1 << align_power; 9313 /* Don't count on the section alignment being as large as the target. */ 9314 if (target_size > branch_align) 9315 target_size = branch_align; 9316 opt_diff = get_text_align_fill_size (address, align_power, 9317 target_size, false, false); 9318 9319 *max_diff = (opt_diff + branch_align 9320 - (target_size + ((address + opt_diff) % branch_align))); 9321 gas_assert (*max_diff >= opt_diff); 9322 return opt_diff; 9323 9324 case RELAX_ALIGN_NEXT_OPCODE: 9325 /* The next non-empty frag after this one holds the LOOP instruction 9326 that needs to be aligned. The required alignment depends on the 9327 size of the next non-empty frag after the loop frag, i.e., the 9328 first instruction in the loop. */ 9329 loop_frag = next_non_empty_frag (fragP); 9330 target_size = get_loop_align_size (next_frag_format_size (loop_frag)); 9331 loop_insn_offset = 0; 9332 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); 9333 gas_assert (is_loop); 9334 9335 /* If the loop has been expanded then the LOOP instruction 9336 could be at an offset from this fragment. */ 9337 if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) 9338 loop_insn_offset = get_expanded_loop_offset (loop_opcode); 9339 9340 /* In an ideal world, which is what we are shooting for here, 9341 we wouldn't need to use any NOPs immediately prior to the 9342 LOOP instruction. If this approach fails, relax_frag_loop_align 9343 will call get_noop_aligned_address. */ 9344 target_address = 9345 address + loop_insn_offset + xg_get_single_size (loop_opcode); 9346 align_power = get_text_align_power (target_size); 9347 opt_diff = get_text_align_fill_size (target_address, align_power, 9348 target_size, false, false); 9349 9350 *max_diff = xtensa_fetch_width 9351 - ((target_address + opt_diff) % xtensa_fetch_width) 9352 - target_size + opt_diff; 9353 gas_assert (*max_diff >= opt_diff); 9354 return opt_diff; 9355 9356 default: 9357 break; 9358 } 9359 gas_assert (0); 9360 return 0; 9361} 9362 9363 9364/* md_relax_frag Hook and Helper Functions. */ 9365 9366static long relax_frag_loop_align (fragS *, long); 9367static long relax_frag_for_align (fragS *, long); 9368static long relax_frag_immed 9369 (segT, fragS *, long, int, xtensa_format, int, int *, bool); 9370 9371/* Get projected address for the first fulcrum on a path from source to 9372 target. */ 9373static addressT xg_get_fulcrum (addressT source, addressT target) 9374{ 9375 offsetT delta = target - source; 9376 int n; 9377 9378 n = (labs (delta) + J_RANGE - J_MARGIN - 1) / (J_RANGE - J_MARGIN); 9379 return source + delta / n; 9380} 9381 9382/* Given trampoline index, source and target of a jump find the best 9383 candidate trampoline for the first fulcrum. The best trampoline is 9384 the one in the reach of "j' instruction from the source, closest to 9385 the projected fulcrum address, and preferrably w/o a jump around or 9386 with already initialized jump around. */ 9387static size_t xg_find_best_trampoline (struct trampoline_index *idx, 9388 addressT source, addressT target) 9389{ 9390 addressT fulcrum = xg_get_fulcrum (source, target); 9391 size_t dist = 0; 9392 size_t best = -1; 9393 size_t base_tr = xg_find_trampoline (idx, fulcrum); 9394 int checked = 1; 9395 9396 /* Check trampoline frags around the base_tr to find the best. */ 9397 for (dist = 0; checked; ++dist) 9398 { 9399 int i; 9400 size_t tr = base_tr - dist; 9401 9402 checked = 0; 9403 9404 /* Trampolines are checked in the following order: 9405 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */ 9406 for (i = 0; i < 2; ++i, tr = base_tr + dist + 1) 9407 if (tr < idx->n_entries) 9408 { 9409 fragS *trampoline_frag = idx->entry[tr]; 9410 offsetT off; 9411 9412 /* Don't check trampolines outside source - target interval. */ 9413 if ((trampoline_frag->fr_address < source && 9414 trampoline_frag->fr_address < target) || 9415 (trampoline_frag->fr_address > source && 9416 trampoline_frag->fr_address > target)) 9417 continue; 9418 9419 /* Don't choose trampoline that contains the source. */ 9420 if (source >= trampoline_frag->fr_address 9421 && source <= trampoline_frag->fr_address + 9422 trampoline_frag->fr_fix) 9423 continue; 9424 9425 off = trampoline_frag->fr_address - fulcrum; 9426 /* Stop if some trampoline is found and the search is more than 9427 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump 9428 around is nice, but it shouldn't have much overhead. */ 9429 if (best < idx->n_entries && labs (off) > J_RANGE / 4) 9430 return best; 9431 9432 off = trampoline_frag->fr_address - source; 9433 if (labs (off) < J_RANGE - J_MARGIN) 9434 { 9435 ++checked; 9436 /* Stop if a trampoline w/o jump around is found or initialized 9437 trampoline with jump around is found. */ 9438 if (!trampoline_frag->tc_frag_data.needs_jump_around || 9439 trampoline_frag->fr_fix) 9440 return tr; 9441 else if (best >= idx->n_entries) 9442 best = tr; 9443 } 9444 } 9445 } 9446 9447 if (best < idx->n_entries) 9448 return best; 9449 else 9450 as_fatal (_("cannot find suitable trampoline")); 9451} 9452 9453static fixS *xg_relax_fixup (struct trampoline_index *idx, fixS *fixP) 9454{ 9455 symbolS *s = fixP->fx_addsy; 9456 addressT source = fixP->fx_frag->fr_address; 9457 addressT target = S_GET_VALUE (s) + fixP->fx_offset; 9458 size_t tr = xg_find_best_trampoline (idx, source, target); 9459 fragS *trampoline_frag = idx->entry[tr]; 9460 fixS *newfixP; 9461 9462 init_trampoline_frag (trampoline_frag); 9463 newfixP = xg_append_jump (trampoline_frag, 9464 fixP->fx_addsy, fixP->fx_offset); 9465 9466 /* Adjust the fixup for the original "j" instruction to 9467 point to the newly added jump. */ 9468 fixP->fx_addsy = trampoline_frag->fr_symbol; 9469 fixP->fx_offset = trampoline_frag->fr_fix - 3; 9470 fixP->tc_fix_data.X_add_symbol = trampoline_frag->fr_symbol; 9471 fixP->tc_fix_data.X_add_number = trampoline_frag->fr_fix - 3; 9472 9473 trampoline_frag->tc_frag_data.relax_seen = false; 9474 9475 if (xg_is_trampoline_frag_full (trampoline_frag)) 9476 xg_remove_trampoline_from_index (idx, tr); 9477 9478 return newfixP; 9479} 9480 9481static bool xg_is_relaxable_fixup (fixS *fixP) 9482{ 9483 xtensa_isa isa = xtensa_default_isa; 9484 addressT addr = fixP->fx_frag->fr_address; 9485 addressT target; 9486 offsetT delta; 9487 symbolS *s = fixP->fx_addsy; 9488 int slot; 9489 xtensa_format fmt; 9490 xtensa_opcode opcode; 9491 9492 if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || 9493 fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) 9494 return false; 9495 9496 target = S_GET_VALUE (s) + fixP->fx_offset; 9497 delta = target - addr; 9498 9499 if (labs (delta) < J_RANGE - J_MARGIN) 9500 return false; 9501 9502 xtensa_insnbuf_from_chars (isa, trampoline_buf, 9503 (unsigned char *) fixP->fx_frag->fr_literal + 9504 fixP->fx_where, 0); 9505 fmt = xtensa_format_decode (isa, trampoline_buf); 9506 gas_assert (fmt != XTENSA_UNDEFINED); 9507 slot = fixP->tc_fix_data.slot; 9508 xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); 9509 opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); 9510 return opcode == xtensa_j_opcode; 9511} 9512 9513static void xg_relax_fixups (struct trampoline_seg *ts) 9514{ 9515 struct trampoline_index *idx = &ts->index; 9516 segment_info_type *seginfo = seg_info (now_seg); 9517 fixS *fx; 9518 9519 for (fx = seginfo->fix_root; fx; fx = fx->fx_next) 9520 { 9521 fixS *fixP = fx; 9522 struct trampoline_chain *tc = NULL; 9523 9524 if (xg_is_relaxable_fixup (fixP)) 9525 { 9526 tc = xg_find_best_eq_target (ts, fixP->fx_frag->fr_address, 9527 &fixP->fx_addsy, &fixP->fx_offset); 9528 if (!tc) 9529 tc = xg_create_trampoline_chain (ts, fixP->fx_addsy, 9530 fixP->fx_offset); 9531 gas_assert (tc); 9532 } 9533 9534 while (xg_is_relaxable_fixup (fixP)) 9535 { 9536 fixP = xg_relax_fixup (idx, fixP); 9537 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, 9538 fixP->fx_where); 9539 } 9540 } 9541} 9542 9543/* Given a trampoline frag relax all jumps that might want to use this 9544 trampoline. Only do real work once per relaxation cycle, when 9545 xg_relax_trampoline is called for the first trampoline in the now_seg. 9546 Don't use stretch, don't update new_stretch: place fulcrums with a 9547 slack to tolerate code movement. In the worst case if a jump between 9548 two trampolines wouldn't reach the next relaxation pass will fix it. */ 9549static void xg_relax_trampoline (fragS *fragP, long stretch ATTRIBUTE_UNUSED, 9550 long *new_stretch ATTRIBUTE_UNUSED) 9551{ 9552 struct trampoline_seg *ts = find_trampoline_seg (now_seg); 9553 9554 if (ts->index.n_entries && ts->index.entry[0] == fragP) 9555 xg_relax_fixups (ts); 9556} 9557 9558/* Return the number of bytes added to this fragment, given that the 9559 input has been stretched already by "stretch". */ 9560 9561long 9562xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) 9563{ 9564 xtensa_isa isa = xtensa_default_isa; 9565 int unreported = fragP->tc_frag_data.unreported_expansion; 9566 long new_stretch = 0; 9567 const char *file_name; 9568 unsigned line; 9569 int lit_size; 9570 static xtensa_insnbuf vbuf = NULL; 9571 int slot, num_slots; 9572 xtensa_format fmt; 9573 9574 file_name = as_where (&line); 9575 new_logical_line (fragP->fr_file, fragP->fr_line); 9576 9577 fragP->tc_frag_data.unreported_expansion = 0; 9578 9579 switch (fragP->fr_subtype) 9580 { 9581 case RELAX_ALIGN_NEXT_OPCODE: 9582 /* Always convert. */ 9583 if (fragP->tc_frag_data.relax_seen) 9584 new_stretch = relax_frag_loop_align (fragP, stretch); 9585 break; 9586 9587 case RELAX_LOOP_END: 9588 /* Do nothing. */ 9589 break; 9590 9591 case RELAX_LOOP_END_ADD_NOP: 9592 /* Add a NOP and switch to .fill 0. */ 9593 new_stretch = relax_frag_add_nop (fragP); 9594 frag_wane (fragP); 9595 break; 9596 9597 case RELAX_DESIRE_ALIGN: 9598 /* Do nothing. The narrowing before this frag will either align 9599 it or not. */ 9600 break; 9601 9602 case RELAX_LITERAL: 9603 case RELAX_LITERAL_FINAL: 9604 return 0; 9605 9606 case RELAX_LITERAL_NR: 9607 lit_size = 4; 9608 fragP->fr_subtype = RELAX_LITERAL_FINAL; 9609 gas_assert (unreported == lit_size); 9610 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); 9611 fragP->fr_var -= lit_size; 9612 fragP->fr_fix += lit_size; 9613 new_stretch = 4; 9614 break; 9615 9616 case RELAX_SLOTS: 9617 if (vbuf == NULL) 9618 vbuf = xtensa_insnbuf_alloc (isa); 9619 9620 xtensa_insnbuf_from_chars 9621 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); 9622 fmt = xtensa_format_decode (isa, vbuf); 9623 num_slots = xtensa_format_num_slots (isa, fmt); 9624 9625 for (slot = 0; slot < num_slots; slot++) 9626 { 9627 switch (fragP->tc_frag_data.slot_subtypes[slot]) 9628 { 9629 case RELAX_NARROW: 9630 if (fragP->tc_frag_data.relax_seen) 9631 new_stretch += relax_frag_for_align (fragP, stretch); 9632 break; 9633 9634 case RELAX_IMMED: 9635 case RELAX_IMMED_STEP1: 9636 case RELAX_IMMED_STEP2: 9637 case RELAX_IMMED_STEP3: 9638 /* Place the immediate. */ 9639 new_stretch += relax_frag_immed 9640 (now_seg, fragP, stretch, 9641 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 9642 fmt, slot, stretched_p, false); 9643 break; 9644 9645 default: 9646 /* This is OK; see the note in xg_assemble_vliw_tokens. */ 9647 break; 9648 } 9649 } 9650 break; 9651 9652 case RELAX_LITERAL_POOL_BEGIN: 9653 if (fragP->fr_var != 0) 9654 { 9655 /* We have a converted "candidate" literal pool; 9656 assemble a jump around it. */ 9657 TInsn insn; 9658 if (!litpool_slotbuf) 9659 { 9660 litpool_buf = xtensa_insnbuf_alloc (isa); 9661 litpool_slotbuf = xtensa_insnbuf_alloc (isa); 9662 } 9663 new_stretch += 3; 9664 fragP->tc_frag_data.relax_seen = false; /* Need another pass. */ 9665 fragP->tc_frag_data.is_insn = true; 9666 tinsn_init (&insn); 9667 insn.insn_type = ITYPE_INSN; 9668 insn.opcode = xtensa_j_opcode; 9669 insn.ntok = 1; 9670 set_expr_symbol_offset (&insn.tok[0], fragP->fr_symbol, 9671 fragP->fr_fix); 9672 fmt = xg_get_single_format (xtensa_j_opcode); 9673 tinsn_to_slotbuf (fmt, 0, &insn, litpool_slotbuf); 9674 xtensa_format_set_slot (isa, fmt, 0, litpool_buf, litpool_slotbuf); 9675 xtensa_insnbuf_to_chars (isa, litpool_buf, 9676 (unsigned char *)fragP->fr_literal + 9677 fragP->fr_fix, 3); 9678 fragP->fr_fix += 3; 9679 fragP->fr_var -= 3; 9680 /* Add a fix-up. */ 9681 fix_new (fragP, 0, 3, fragP->fr_symbol, 0, true, 9682 BFD_RELOC_XTENSA_SLOT0_OP); 9683 } 9684 break; 9685 9686 case RELAX_LITERAL_POOL_END: 9687 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN: 9688 case RELAX_MAYBE_UNREACHABLE: 9689 case RELAX_MAYBE_DESIRE_ALIGN: 9690 /* No relaxation required. */ 9691 break; 9692 9693 case RELAX_FILL_NOP: 9694 case RELAX_UNREACHABLE: 9695 if (fragP->tc_frag_data.relax_seen) 9696 new_stretch += relax_frag_for_align (fragP, stretch); 9697 break; 9698 9699 case RELAX_TRAMPOLINE: 9700 if (fragP->tc_frag_data.relax_seen) 9701 xg_relax_trampoline (fragP, stretch, &new_stretch); 9702 break; 9703 9704 default: 9705 as_bad (_("bad relaxation state")); 9706 } 9707 9708 /* Tell gas we need another relaxation pass. */ 9709 if (! fragP->tc_frag_data.relax_seen) 9710 { 9711 fragP->tc_frag_data.relax_seen = true; 9712 *stretched_p = 1; 9713 } 9714 9715 new_logical_line (file_name, line); 9716 return new_stretch; 9717} 9718 9719 9720static long 9721relax_frag_loop_align (fragS *fragP, long stretch) 9722{ 9723 addressT old_address, old_next_address, old_size; 9724 addressT new_address, new_next_address, new_size; 9725 addressT growth; 9726 9727 /* All the frags with relax_frag_for_alignment prior to this one in the 9728 section have been done, hopefully eliminating the need for a NOP here. 9729 But, this will put it in if necessary. */ 9730 9731 /* Calculate the old address of this fragment and the next fragment. */ 9732 old_address = fragP->fr_address - stretch; 9733 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + 9734 fragP->tc_frag_data.text_expansion[0]); 9735 old_size = old_next_address - old_address; 9736 9737 /* Calculate the new address of this fragment and the next fragment. */ 9738 new_address = fragP->fr_address; 9739 new_next_address = 9740 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); 9741 new_size = new_next_address - new_address; 9742 9743 growth = new_size - old_size; 9744 9745 /* Fix up the text_expansion field and return the new growth. */ 9746 fragP->tc_frag_data.text_expansion[0] += growth; 9747 return growth; 9748} 9749 9750 9751/* Add a NOP instruction. */ 9752 9753static long 9754relax_frag_add_nop (fragS *fragP) 9755{ 9756 char *nop_buf = fragP->fr_literal + fragP->fr_fix; 9757 int length = fragP->tc_frag_data.is_no_density ? 3 : 2; 9758 assemble_nop (length, nop_buf); 9759 fragP->tc_frag_data.is_insn = true; 9760 9761 if (fragP->fr_var < length) 9762 { 9763 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); 9764 return 0; 9765 } 9766 9767 fragP->fr_fix += length; 9768 fragP->fr_var -= length; 9769 return length; 9770} 9771 9772 9773static long future_alignment_required (fragS *, long); 9774 9775static long 9776relax_frag_for_align (fragS *fragP, long stretch) 9777{ 9778 /* Overview of the relaxation procedure for alignment: 9779 We can widen with NOPs or by widening instructions or by filling 9780 bytes after jump instructions. Find the opportune places and widen 9781 them if necessary. */ 9782 9783 long stretch_me; 9784 long diff; 9785 9786 gas_assert (fragP->fr_subtype == RELAX_FILL_NOP 9787 || fragP->fr_subtype == RELAX_UNREACHABLE 9788 || (fragP->fr_subtype == RELAX_SLOTS 9789 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); 9790 9791 stretch_me = future_alignment_required (fragP, stretch); 9792 diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; 9793 if (diff == 0) 9794 return 0; 9795 9796 if (diff < 0) 9797 { 9798 /* We expanded on a previous pass. Can we shrink now? */ 9799 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; 9800 if (shrink <= stretch && stretch > 0) 9801 { 9802 fragP->tc_frag_data.text_expansion[0] = stretch_me; 9803 return -shrink; 9804 } 9805 return 0; 9806 } 9807 9808 /* Below here, diff > 0. */ 9809 fragP->tc_frag_data.text_expansion[0] = stretch_me; 9810 9811 return diff; 9812} 9813 9814 9815/* Return the address of the next frag that should be aligned. 9816 9817 By "address" we mean the address it _would_ be at if there 9818 is no action taken to align it between here and the target frag. 9819 In other words, if no narrows and no fill nops are used between 9820 here and the frag to align, _even_if_ some of the frags we use 9821 to align targets have already expanded on a previous relaxation 9822 pass. 9823 9824 Also, count each frag that may be used to help align the target. 9825 9826 Return 0 if there are no frags left in the chain that need to be 9827 aligned. */ 9828 9829static addressT 9830find_address_of_next_align_frag (fragS **fragPP, 9831 int *wide_nops, 9832 int *narrow_nops, 9833 int *widens, 9834 bool *paddable) 9835{ 9836 fragS *fragP = *fragPP; 9837 addressT address = fragP->fr_address; 9838 9839 /* Do not reset the counts to 0. */ 9840 9841 while (fragP) 9842 { 9843 /* Limit this to a small search. */ 9844 if (*widens >= (int) xtensa_fetch_width) 9845 { 9846 *fragPP = fragP; 9847 return 0; 9848 } 9849 address += fragP->fr_fix; 9850 9851 if (fragP->fr_type == rs_fill) 9852 address += fragP->fr_offset * fragP->fr_var; 9853 else if (fragP->fr_type == rs_machine_dependent) 9854 { 9855 switch (fragP->fr_subtype) 9856 { 9857 case RELAX_UNREACHABLE: 9858 *paddable = true; 9859 break; 9860 9861 case RELAX_FILL_NOP: 9862 (*wide_nops)++; 9863 if (!fragP->tc_frag_data.is_no_density) 9864 (*narrow_nops)++; 9865 break; 9866 9867 case RELAX_SLOTS: 9868 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 9869 { 9870 (*widens)++; 9871 break; 9872 } 9873 address += total_frag_text_expansion (fragP); 9874 break; 9875 9876 case RELAX_IMMED: 9877 address += fragP->tc_frag_data.text_expansion[0]; 9878 break; 9879 9880 case RELAX_ALIGN_NEXT_OPCODE: 9881 case RELAX_DESIRE_ALIGN: 9882 *fragPP = fragP; 9883 return address; 9884 9885 case RELAX_MAYBE_UNREACHABLE: 9886 case RELAX_MAYBE_DESIRE_ALIGN: 9887 /* Do nothing. */ 9888 break; 9889 9890 default: 9891 /* Just punt if we don't know the type. */ 9892 *fragPP = fragP; 9893 return 0; 9894 } 9895 } 9896 else 9897 { 9898 /* Just punt if we don't know the type. */ 9899 *fragPP = fragP; 9900 return 0; 9901 } 9902 fragP = fragP->fr_next; 9903 } 9904 9905 *fragPP = fragP; 9906 return 0; 9907} 9908 9909 9910static long bytes_to_stretch (fragS *, int, int, int, int); 9911 9912static long 9913future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) 9914{ 9915 fragS *this_frag = fragP; 9916 long address; 9917 int num_widens = 0; 9918 int wide_nops = 0; 9919 int narrow_nops = 0; 9920 bool paddable = false; 9921 offsetT local_opt_diff; 9922 offsetT opt_diff; 9923 offsetT max_diff; 9924 int stretch_amount = 0; 9925 int local_stretch_amount; 9926 int global_stretch_amount; 9927 9928 address = find_address_of_next_align_frag 9929 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); 9930 9931 if (!address) 9932 { 9933 if (this_frag->tc_frag_data.is_aligning_branch) 9934 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 9935 else 9936 frag_wane (this_frag); 9937 } 9938 else 9939 { 9940 local_opt_diff = get_aligned_diff (fragP, address, &max_diff); 9941 opt_diff = local_opt_diff; 9942 gas_assert (opt_diff >= 0); 9943 gas_assert (max_diff >= opt_diff); 9944 if (max_diff == 0) 9945 return 0; 9946 9947 if (fragP) 9948 fragP = fragP->fr_next; 9949 9950 while (fragP && opt_diff < max_diff && address) 9951 { 9952 /* We only use these to determine if we can exit early 9953 because there will be plenty of ways to align future 9954 align frags. */ 9955 int glob_widens = 0; 9956 int dnn = 0; 9957 int dw = 0; 9958 bool glob_pad = 0; 9959 address = find_address_of_next_align_frag 9960 (&fragP, &glob_widens, &dnn, &dw, &glob_pad); 9961 /* If there is a padable portion, then skip. */ 9962 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) 9963 address = 0; 9964 9965 if (address) 9966 { 9967 offsetT next_m_diff; 9968 offsetT next_o_diff; 9969 9970 /* Downrange frags haven't had stretch added to them yet. */ 9971 address += stretch; 9972 9973 /* The address also includes any text expansion from this 9974 frag in a previous pass, but we don't want that. */ 9975 address -= this_frag->tc_frag_data.text_expansion[0]; 9976 9977 /* Assume we are going to move at least opt_diff. In 9978 reality, we might not be able to, but assuming that 9979 we will helps catch cases where moving opt_diff pushes 9980 the next target from aligned to unaligned. */ 9981 address += opt_diff; 9982 9983 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); 9984 9985 /* Now cleanup for the adjustments to address. */ 9986 next_o_diff += opt_diff; 9987 next_m_diff += opt_diff; 9988 if (next_o_diff <= max_diff && next_o_diff > opt_diff) 9989 opt_diff = next_o_diff; 9990 if (next_m_diff < max_diff) 9991 max_diff = next_m_diff; 9992 fragP = fragP->fr_next; 9993 } 9994 } 9995 9996 /* If there are enough wideners in between, do it. */ 9997 if (paddable) 9998 { 9999 if (this_frag->fr_subtype == RELAX_UNREACHABLE) 10000 { 10001 gas_assert (opt_diff <= (signed) xtensa_fetch_width); 10002 return opt_diff; 10003 } 10004 return 0; 10005 } 10006 local_stretch_amount 10007 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 10008 num_widens, local_opt_diff); 10009 global_stretch_amount 10010 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 10011 num_widens, opt_diff); 10012 /* If the condition below is true, then the frag couldn't 10013 stretch the correct amount for the global case, so we just 10014 optimize locally. We'll rely on the subsequent frags to get 10015 the correct alignment in the global case. */ 10016 if (global_stretch_amount < local_stretch_amount) 10017 stretch_amount = local_stretch_amount; 10018 else 10019 stretch_amount = global_stretch_amount; 10020 10021 if (this_frag->fr_subtype == RELAX_SLOTS 10022 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 10023 gas_assert (stretch_amount <= 1); 10024 else if (this_frag->fr_subtype == RELAX_FILL_NOP) 10025 { 10026 if (this_frag->tc_frag_data.is_no_density) 10027 gas_assert (stretch_amount == 3 || stretch_amount == 0); 10028 else 10029 gas_assert (stretch_amount <= 3); 10030 } 10031 } 10032 return stretch_amount; 10033} 10034 10035 10036/* The idea: widen everything you can to get a target or loop aligned, 10037 then start using NOPs. 10038 10039 wide_nops = the number of wide NOPs available for aligning 10040 narrow_nops = the number of narrow NOPs available for aligning 10041 (a subset of wide_nops) 10042 widens = the number of narrow instructions that should be widened 10043 10044*/ 10045 10046static long 10047bytes_to_stretch (fragS *this_frag, 10048 int wide_nops, 10049 int narrow_nops, 10050 int num_widens, 10051 int desired_diff) 10052{ 10053 int nops_needed; 10054 int nop_bytes; 10055 int extra_bytes; 10056 int bytes_short = desired_diff - num_widens; 10057 10058 gas_assert (desired_diff >= 0 10059 && desired_diff < (signed) xtensa_fetch_width); 10060 if (desired_diff == 0) 10061 return 0; 10062 10063 gas_assert (wide_nops > 0 || num_widens > 0); 10064 10065 /* Always prefer widening to NOP-filling. */ 10066 if (bytes_short < 0) 10067 { 10068 /* There are enough RELAX_NARROW frags after this one 10069 to align the target without widening this frag in any way. */ 10070 return 0; 10071 } 10072 10073 if (bytes_short == 0) 10074 { 10075 /* Widen every narrow between here and the align target 10076 and the align target will be properly aligned. */ 10077 if (this_frag->fr_subtype == RELAX_FILL_NOP) 10078 return 0; 10079 else 10080 return 1; 10081 } 10082 10083 /* From here we will need at least one NOP to get an alignment. 10084 However, we may not be able to align at all, in which case, 10085 don't widen. */ 10086 nops_needed = desired_diff / 3; 10087 10088 /* If there aren't enough nops, don't widen. */ 10089 if (nops_needed > wide_nops) 10090 return 0; 10091 10092 /* First try it with all wide nops. */ 10093 nop_bytes = nops_needed * 3; 10094 extra_bytes = desired_diff - nop_bytes; 10095 10096 if (nop_bytes + num_widens >= desired_diff) 10097 { 10098 if (this_frag->fr_subtype == RELAX_FILL_NOP) 10099 return 3; 10100 else if (num_widens == extra_bytes) 10101 return 1; 10102 return 0; 10103 } 10104 10105 /* Add a narrow nop. */ 10106 nops_needed++; 10107 nop_bytes += 2; 10108 extra_bytes -= 2; 10109 if (narrow_nops == 0 || nops_needed > wide_nops) 10110 return 0; 10111 10112 if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) 10113 { 10114 if (this_frag->fr_subtype == RELAX_FILL_NOP) 10115 return !this_frag->tc_frag_data.is_no_density ? 2 : 3; 10116 else if (num_widens == extra_bytes) 10117 return 1; 10118 return 0; 10119 } 10120 10121 /* Replace a wide nop with a narrow nop--we can get here if 10122 extra_bytes was negative in the previous conditional. */ 10123 if (narrow_nops == 1) 10124 return 0; 10125 nop_bytes--; 10126 extra_bytes++; 10127 if (nop_bytes + num_widens >= desired_diff) 10128 { 10129 if (this_frag->fr_subtype == RELAX_FILL_NOP) 10130 return !this_frag->tc_frag_data.is_no_density ? 2 : 3; 10131 else if (num_widens == extra_bytes) 10132 return 1; 10133 return 0; 10134 } 10135 10136 /* If we can't satisfy any of the above cases, then we can't align 10137 using padding or fill nops. */ 10138 return 0; 10139} 10140 10141 10142static fragS * 10143xg_find_best_trampoline_for_tinsn (TInsn *tinsn, fragS *fragP) 10144{ 10145 symbolS *sym = tinsn->tok[0].X_add_symbol; 10146 addressT source = fragP->fr_address; 10147 addressT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; 10148 struct trampoline_seg *ts = find_trampoline_seg (now_seg); 10149 size_t i; 10150 10151 if (!ts || !ts->index.n_entries) 10152 return NULL; 10153 10154 i = xg_find_best_trampoline (&ts->index, source, target); 10155 10156 return ts->index.entry[i]; 10157} 10158 10159 10160/* Append jump to sym + offset to the end of the trampoline frag fragP. 10161 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var 10162 and finish the frag if it's full (but don't remove it from the trampoline 10163 frag index). Return fixup for the newly created jump. */ 10164static fixS *xg_append_jump (fragS *fragP, symbolS *sym, offsetT offset) 10165{ 10166 fixS *fixP; 10167 TInsn insn; 10168 xtensa_format fmt; 10169 xtensa_isa isa = xtensa_default_isa; 10170 10171 gas_assert (fragP->fr_var >= 3); 10172 tinsn_init (&insn); 10173 insn.insn_type = ITYPE_INSN; 10174 insn.opcode = xtensa_j_opcode; 10175 insn.ntok = 1; 10176 set_expr_symbol_offset (&insn.tok[0], sym, offset); 10177 fmt = xg_get_single_format (xtensa_j_opcode); 10178 tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); 10179 xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); 10180 xtensa_insnbuf_to_chars (isa, trampoline_buf, 10181 (unsigned char *)fragP->fr_literal + fragP->fr_fix, 3); 10182 fixP = fix_new (fragP, fragP->fr_fix, 3, sym, offset, true, 10183 BFD_RELOC_XTENSA_SLOT0_OP); 10184 fixP->tc_fix_data.slot = 0; 10185 10186 fragP->fr_fix += 3; 10187 fragP->fr_var -= 3; 10188 10189 /* Adjust the jump around this trampoline (if present). */ 10190 if (fragP->tc_frag_data.jump_around_fix) 10191 fragP->tc_frag_data.jump_around_fix->fx_offset += 3; 10192 10193 /* Do we have room for more? */ 10194 if (xg_is_trampoline_frag_full (fragP)) 10195 { 10196 frag_wane (fragP); 10197 fragP->fr_subtype = 0; 10198 } 10199 10200 return fixP; 10201} 10202 10203 10204static int 10205init_trampoline_frag (fragS *fp) 10206{ 10207 int growth = 0; 10208 10209 if (fp->fr_fix == 0) 10210 { 10211 symbolS *lsym; 10212 char label[10 + 2 * sizeof(fp)]; 10213 10214 sprintf (label, ".L0_TR_%p", fp); 10215 lsym = (symbolS *) local_symbol_make (label, now_seg, fp, 0); 10216 fp->fr_symbol = lsym; 10217 if (fp->tc_frag_data.needs_jump_around) 10218 { 10219 fp->tc_frag_data.jump_around_fix = xg_append_jump (fp, lsym, 3); 10220 growth = 3; 10221 } 10222 } 10223 return growth; 10224} 10225 10226static int 10227xg_get_single_symbol_slot (fragS *fragP) 10228{ 10229 int i; 10230 int slot = -1; 10231 10232 for (i = 0; i < MAX_SLOTS; ++i) 10233 if (fragP->tc_frag_data.slot_symbols[i]) 10234 { 10235 gas_assert (slot == -1); 10236 slot = i; 10237 } 10238 10239 gas_assert (slot >= 0 && slot < MAX_SLOTS); 10240 10241 return slot; 10242} 10243 10244static fixS * 10245add_jump_to_trampoline (fragS *tramp, fragS *origfrag) 10246{ 10247 int slot = xg_get_single_symbol_slot (origfrag); 10248 fixS *fixP; 10249 10250 /* Assemble a jump to the target label in the trampoline frag. */ 10251 fixP = xg_append_jump (tramp, 10252 origfrag->tc_frag_data.slot_symbols[slot], 10253 origfrag->tc_frag_data.slot_offsets[slot]); 10254 10255 /* Modify the original j to point here. */ 10256 origfrag->tc_frag_data.slot_symbols[slot] = tramp->fr_symbol; 10257 origfrag->tc_frag_data.slot_offsets[slot] = tramp->fr_fix - 3; 10258 10259 /* If trampoline is full, remove it from the list. */ 10260 if (xg_is_trampoline_frag_full (tramp)) 10261 { 10262 struct trampoline_seg *ts = find_trampoline_seg (now_seg); 10263 size_t tr = xg_find_trampoline (&ts->index, tramp->fr_address); 10264 10265 gas_assert (ts->index.entry[tr] == tramp); 10266 xg_remove_trampoline_from_index (&ts->index, tr); 10267 } 10268 10269 return fixP; 10270} 10271 10272 10273static long 10274relax_frag_immed (segT segP, 10275 fragS *fragP, 10276 long stretch, 10277 int min_steps, 10278 xtensa_format fmt, 10279 int slot, 10280 int *stretched_p, 10281 bool estimate_only) 10282{ 10283 TInsn tinsn; 10284 int old_size; 10285 bool negatable_branch = false; 10286 bool branch_jmp_to_next = false; 10287 bool from_wide_insn = false; 10288 xtensa_isa isa = xtensa_default_isa; 10289 IStack istack; 10290 offsetT frag_offset; 10291 int num_steps; 10292 int num_text_bytes, num_literal_bytes; 10293 int literal_diff, total_text_diff, this_text_diff; 10294 10295 gas_assert (fragP->fr_opcode != NULL); 10296 10297 xg_clear_vinsn (&cur_vinsn); 10298 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); 10299 if (cur_vinsn.num_slots > 1) 10300 from_wide_insn = true; 10301 10302 tinsn = cur_vinsn.slots[slot]; 10303 tinsn_immed_from_frag (&tinsn, fragP, slot); 10304 10305 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) 10306 return 0; 10307 10308 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 10309 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); 10310 10311 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); 10312 10313 old_size = xtensa_format_length (isa, fmt); 10314 10315 /* Special case: replace a branch to the next instruction with a NOP. 10316 This is required to work around a hardware bug in T1040.0 and also 10317 serves as an optimization. */ 10318 10319 if (branch_jmp_to_next 10320 && ((old_size == 2) || (old_size == 3)) 10321 && !next_frag_is_loop_target (fragP)) 10322 return 0; 10323 10324 /* Here is the fun stuff: Get the immediate field from this 10325 instruction. If it fits, we are done. If not, find the next 10326 instruction sequence that fits. */ 10327 10328 frag_offset = fragP->fr_opcode - fragP->fr_literal; 10329 istack_init (&istack); 10330 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, 10331 min_steps, stretch); 10332 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 10333 10334 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; 10335 10336 /* Figure out the number of bytes needed. */ 10337 num_literal_bytes = get_num_stack_literal_bytes (&istack); 10338 literal_diff 10339 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 10340 num_text_bytes = get_num_stack_text_bytes (&istack); 10341 10342 if (from_wide_insn) 10343 { 10344 int first = 0; 10345 while (istack.insn[first].opcode == XTENSA_UNDEFINED) 10346 first++; 10347 10348 num_text_bytes += old_size; 10349 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) 10350 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); 10351 else 10352 { 10353 /* The first instruction in the relaxed sequence will go after 10354 the current wide instruction, and thus its symbolic immediates 10355 might not fit. */ 10356 10357 istack_init (&istack); 10358 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, 10359 frag_offset + old_size, 10360 min_steps, stretch + old_size); 10361 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 10362 10363 fragP->tc_frag_data.slot_subtypes[slot] 10364 = (int) RELAX_IMMED + num_steps; 10365 10366 num_literal_bytes = get_num_stack_literal_bytes (&istack); 10367 literal_diff 10368 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 10369 10370 num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; 10371 } 10372 } 10373 10374 total_text_diff = num_text_bytes - old_size; 10375 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; 10376 10377 /* It MUST get larger. If not, we could get an infinite loop. */ 10378 gas_assert (num_text_bytes >= 0); 10379 gas_assert (literal_diff >= 0); 10380 gas_assert (total_text_diff >= 0); 10381 10382 fragP->tc_frag_data.text_expansion[slot] = total_text_diff; 10383 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; 10384 gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); 10385 gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); 10386 10387 /* Find the associated expandable literal for this. */ 10388 if (literal_diff != 0) 10389 { 10390 fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; 10391 if (lit_fragP) 10392 { 10393 gas_assert (literal_diff == 4); 10394 lit_fragP->tc_frag_data.unreported_expansion += literal_diff; 10395 10396 /* We expect that the literal section state has NOT been 10397 modified yet. */ 10398 gas_assert (lit_fragP->fr_type == rs_machine_dependent 10399 && lit_fragP->fr_subtype == RELAX_LITERAL); 10400 lit_fragP->fr_subtype = RELAX_LITERAL_NR; 10401 10402 /* We need to mark this section for another iteration 10403 of relaxation. */ 10404 (*stretched_p)++; 10405 } 10406 } 10407 10408 if (negatable_branch && istack.ninsn > 1) 10409 update_next_frag_state (fragP); 10410 10411 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ 10412 if (istack.ninsn > 2 && 10413 istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && 10414 istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && 10415 istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) 10416 { 10417 TInsn *jinsn = &istack.insn[istack.ninsn - 2]; 10418 struct trampoline_seg *ts = find_trampoline_seg (segP); 10419 struct trampoline_chain *tc = NULL; 10420 10421 if (ts && 10422 !xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, 10423 total_text_diff)) 10424 { 10425 int s = xg_get_single_symbol_slot (fragP); 10426 addressT offset = fragP->tc_frag_data.slot_offsets[s]; 10427 10428 tc = xg_find_best_eq_target (ts, fragP->fr_address, 10429 &fragP->tc_frag_data.slot_symbols[s], 10430 &offset); 10431 10432 if (!tc) 10433 tc = xg_create_trampoline_chain (ts, 10434 fragP->tc_frag_data.slot_symbols[s], 10435 offset); 10436 fragP->tc_frag_data.slot_offsets[s] = offset; 10437 tinsn_immed_from_frag (jinsn, fragP, s); 10438 } 10439 10440 if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, 10441 total_text_diff)) 10442 { 10443 fragS *tf = xg_find_best_trampoline_for_tinsn (jinsn, fragP); 10444 10445 if (tf) 10446 { 10447 fixS *fixP; 10448 10449 this_text_diff += init_trampoline_frag (tf) + 3; 10450 fixP = add_jump_to_trampoline (tf, fragP); 10451 xg_add_location_to_chain (tc, fixP->fx_frag->fr_symbol, 10452 fixP->fx_where); 10453 fragP->tc_frag_data.relax_seen = false; 10454 } 10455 else 10456 { 10457 /* If target symbol is undefined, assume it will reach once linked. */ 10458 expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; 10459 10460 if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) 10461 { 10462 as_bad_where (fragP->fr_file, fragP->fr_line, 10463 _("jump target out of range; no usable trampoline found")); 10464 } 10465 } 10466 } 10467 } 10468 10469 return this_text_diff; 10470} 10471 10472 10473/* md_convert_frag Hook and Helper Functions. */ 10474 10475static void convert_frag_align_next_opcode (fragS *); 10476static void convert_frag_narrow (segT, fragS *, xtensa_format, int); 10477static void convert_frag_fill_nop (fragS *); 10478static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); 10479 10480void 10481md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) 10482{ 10483 static xtensa_insnbuf vbuf = NULL; 10484 xtensa_isa isa = xtensa_default_isa; 10485 int slot; 10486 int num_slots; 10487 xtensa_format fmt; 10488 const char *file_name; 10489 unsigned line; 10490 10491 file_name = as_where (&line); 10492 new_logical_line (fragp->fr_file, fragp->fr_line); 10493 10494 switch (fragp->fr_subtype) 10495 { 10496 case RELAX_ALIGN_NEXT_OPCODE: 10497 /* Always convert. */ 10498 convert_frag_align_next_opcode (fragp); 10499 break; 10500 10501 case RELAX_DESIRE_ALIGN: 10502 /* Do nothing. If not aligned already, too bad. */ 10503 break; 10504 10505 case RELAX_LITERAL: 10506 case RELAX_LITERAL_FINAL: 10507 break; 10508 10509 case RELAX_SLOTS: 10510 if (vbuf == NULL) 10511 vbuf = xtensa_insnbuf_alloc (isa); 10512 10513 xtensa_insnbuf_from_chars 10514 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); 10515 fmt = xtensa_format_decode (isa, vbuf); 10516 num_slots = xtensa_format_num_slots (isa, fmt); 10517 10518 for (slot = 0; slot < num_slots; slot++) 10519 { 10520 switch (fragp->tc_frag_data.slot_subtypes[slot]) 10521 { 10522 case RELAX_NARROW: 10523 convert_frag_narrow (sec, fragp, fmt, slot); 10524 break; 10525 10526 case RELAX_IMMED: 10527 case RELAX_IMMED_STEP1: 10528 case RELAX_IMMED_STEP2: 10529 case RELAX_IMMED_STEP3: 10530 /* Place the immediate. */ 10531 convert_frag_immed 10532 (sec, fragp, 10533 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 10534 fmt, slot); 10535 break; 10536 10537 default: 10538 /* This is OK because some slots could have 10539 relaxations and others have none. */ 10540 break; 10541 } 10542 } 10543 break; 10544 10545 case RELAX_UNREACHABLE: 10546 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); 10547 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; 10548 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; 10549 frag_wane (fragp); 10550 break; 10551 10552 case RELAX_MAYBE_UNREACHABLE: 10553 case RELAX_MAYBE_DESIRE_ALIGN: 10554 frag_wane (fragp); 10555 break; 10556 10557 case RELAX_FILL_NOP: 10558 convert_frag_fill_nop (fragp); 10559 break; 10560 10561 case RELAX_LITERAL_NR: 10562 if (use_literal_section) 10563 { 10564 /* This should have been handled during relaxation. When 10565 relaxing a code segment, literals sometimes need to be 10566 added to the corresponding literal segment. If that 10567 literal segment has already been relaxed, then we end up 10568 in this situation. Marking the literal segments as data 10569 would make this happen less often (since GAS always relaxes 10570 code before data), but we could still get into trouble if 10571 there are instructions in a segment that is not marked as 10572 containing code. Until we can implement a better solution, 10573 cheat and adjust the addresses of all the following frags. 10574 This could break subsequent alignments, but the linker's 10575 literal coalescing will do that anyway. */ 10576 10577 fragS *f; 10578 fragp->fr_subtype = RELAX_LITERAL_FINAL; 10579 gas_assert (fragp->tc_frag_data.unreported_expansion == 4); 10580 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); 10581 fragp->fr_var -= 4; 10582 fragp->fr_fix += 4; 10583 for (f = fragp->fr_next; f; f = f->fr_next) 10584 f->fr_address += 4; 10585 } 10586 else 10587 as_bad (_("invalid relaxation fragment result")); 10588 break; 10589 10590 case RELAX_TRAMPOLINE: 10591 break; 10592 } 10593 10594 fragp->fr_var = 0; 10595 new_logical_line (file_name, line); 10596} 10597 10598 10599static void 10600convert_frag_align_next_opcode (fragS *fragp) 10601{ 10602 char *nop_buf; /* Location for Writing. */ 10603 bool use_no_density = fragp->tc_frag_data.is_no_density; 10604 addressT aligned_address; 10605 offsetT fill_size; 10606 int nop, nop_count; 10607 10608 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + 10609 fragp->fr_fix); 10610 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); 10611 nop_count = get_text_align_nop_count (fill_size, use_no_density); 10612 nop_buf = fragp->fr_literal + fragp->fr_fix; 10613 10614 for (nop = 0; nop < nop_count; nop++) 10615 { 10616 int nop_size; 10617 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); 10618 10619 assemble_nop (nop_size, nop_buf); 10620 nop_buf += nop_size; 10621 } 10622 10623 fragp->fr_fix += fill_size; 10624 fragp->fr_var -= fill_size; 10625} 10626 10627 10628static void 10629convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) 10630{ 10631 TInsn tinsn, single_target; 10632 int size, old_size, diff; 10633 offsetT frag_offset; 10634 10635 gas_assert (slot == 0); 10636 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); 10637 10638 if (fragP->tc_frag_data.is_aligning_branch == 1) 10639 { 10640 gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 10641 || fragP->tc_frag_data.text_expansion[0] == 0); 10642 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], 10643 fmt, slot); 10644 return; 10645 } 10646 10647 if (fragP->tc_frag_data.text_expansion[0] == 0) 10648 { 10649 /* No conversion. */ 10650 fragP->fr_var = 0; 10651 return; 10652 } 10653 10654 gas_assert (fragP->fr_opcode != NULL); 10655 10656 /* Frags in this relaxation state should only contain 10657 single instruction bundles. */ 10658 tinsn_immed_from_frag (&tinsn, fragP, 0); 10659 10660 /* Just convert it to a wide form.... */ 10661 size = 0; 10662 old_size = xg_get_single_size (tinsn.opcode); 10663 10664 tinsn_init (&single_target); 10665 frag_offset = fragP->fr_opcode - fragP->fr_literal; 10666 10667 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, false)) 10668 { 10669 as_bad (_("unable to widen instruction")); 10670 return; 10671 } 10672 10673 size = xg_get_single_size (single_target.opcode); 10674 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, 10675 frag_offset, true); 10676 10677 diff = size - old_size; 10678 gas_assert (diff >= 0); 10679 gas_assert (diff <= fragP->fr_var); 10680 fragP->fr_var -= diff; 10681 fragP->fr_fix += diff; 10682 10683 /* clean it up */ 10684 fragP->fr_var = 0; 10685} 10686 10687 10688static void 10689convert_frag_fill_nop (fragS *fragP) 10690{ 10691 char *loc = &fragP->fr_literal[fragP->fr_fix]; 10692 int size = fragP->tc_frag_data.text_expansion[0]; 10693 gas_assert ((unsigned) size == (fragP->fr_next->fr_address 10694 - fragP->fr_address - fragP->fr_fix)); 10695 if (size == 0) 10696 { 10697 /* No conversion. */ 10698 fragP->fr_var = 0; 10699 return; 10700 } 10701 assemble_nop (size, loc); 10702 fragP->tc_frag_data.is_insn = true; 10703 fragP->fr_var -= size; 10704 fragP->fr_fix += size; 10705 frag_wane (fragP); 10706} 10707 10708 10709static fixS *fix_new_exp_in_seg 10710 (segT, subsegT, fragS *, int, int, expressionS *, int, 10711 bfd_reloc_code_real_type); 10712 10713static void 10714convert_frag_immed (segT segP, 10715 fragS *fragP, 10716 int min_steps, 10717 xtensa_format fmt, 10718 int slot) 10719{ 10720 char *immed_instr = fragP->fr_opcode; 10721 TInsn orig_tinsn; 10722 bool expanded = false; 10723 bool branch_jmp_to_next = false; 10724 char *fr_opcode = fragP->fr_opcode; 10725 xtensa_isa isa = xtensa_default_isa; 10726 bool from_wide_insn = false; 10727 int bytes; 10728 bool is_loop; 10729 10730 gas_assert (fr_opcode != NULL); 10731 10732 xg_clear_vinsn (&cur_vinsn); 10733 10734 vinsn_from_chars (&cur_vinsn, fr_opcode); 10735 if (cur_vinsn.num_slots > 1) 10736 from_wide_insn = true; 10737 10738 orig_tinsn = cur_vinsn.slots[slot]; 10739 tinsn_immed_from_frag (&orig_tinsn, fragP, slot); 10740 10741 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; 10742 10743 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 10744 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); 10745 10746 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) 10747 { 10748 /* Conversion just inserts a NOP and marks the fix as completed. */ 10749 bytes = xtensa_format_length (isa, fmt); 10750 if (bytes >= 4) 10751 { 10752 cur_vinsn.slots[slot].opcode = 10753 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); 10754 cur_vinsn.slots[slot].ntok = 0; 10755 } 10756 else 10757 { 10758 bytes += fragP->tc_frag_data.text_expansion[0]; 10759 gas_assert (bytes == 2 || bytes == 3); 10760 build_nop (&cur_vinsn.slots[0], bytes); 10761 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; 10762 } 10763 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, true); 10764 xtensa_insnbuf_to_chars 10765 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); 10766 fragP->fr_var = 0; 10767 } 10768 else 10769 { 10770 /* Here is the fun stuff: Get the immediate field from this 10771 instruction. If it fits, we're done. If not, find the next 10772 instruction sequence that fits. */ 10773 10774 IStack istack; 10775 int i; 10776 symbolS *lit_sym = NULL; 10777 int total_size = 0; 10778 int target_offset = 0; 10779 int old_size; 10780 int diff; 10781 symbolS *gen_label = NULL; 10782 offsetT frag_offset; 10783 bool first = true; 10784 10785 /* It does not fit. Find something that does and 10786 convert immediately. */ 10787 frag_offset = fr_opcode - fragP->fr_literal; 10788 istack_init (&istack); 10789 xg_assembly_relax (&istack, &orig_tinsn, 10790 segP, fragP, frag_offset, min_steps, 0); 10791 10792 old_size = xtensa_format_length (isa, fmt); 10793 10794 /* Assemble this right inline. */ 10795 10796 /* First, create the mapping from a label name to the REAL label. */ 10797 target_offset = 0; 10798 for (i = 0; i < istack.ninsn; i++) 10799 { 10800 TInsn *tinsn = &istack.insn[i]; 10801 fragS *lit_frag; 10802 10803 switch (tinsn->insn_type) 10804 { 10805 case ITYPE_LITERAL: 10806 if (lit_sym != NULL) 10807 as_bad (_("multiple literals in expansion")); 10808 /* First find the appropriate space in the literal pool. */ 10809 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 10810 if (lit_frag == NULL) 10811 as_bad (_("no registered fragment for literal")); 10812 if (tinsn->ntok != 1) 10813 as_bad (_("number of literal tokens != 1")); 10814 10815 /* Set the literal symbol and add a fixup. */ 10816 lit_sym = lit_frag->fr_symbol; 10817 break; 10818 10819 case ITYPE_LABEL: 10820 if (align_targets && !is_loop) 10821 { 10822 fragS *unreach = fragP->fr_next; 10823 while (!(unreach->fr_type == rs_machine_dependent 10824 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 10825 || unreach->fr_subtype == RELAX_UNREACHABLE))) 10826 { 10827 unreach = unreach->fr_next; 10828 } 10829 10830 gas_assert (unreach->fr_type == rs_machine_dependent 10831 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 10832 || unreach->fr_subtype == RELAX_UNREACHABLE)); 10833 10834 target_offset += unreach->tc_frag_data.text_expansion[0]; 10835 } 10836 gas_assert (gen_label == NULL); 10837 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, fragP, 10838 fr_opcode - fragP->fr_literal 10839 + target_offset); 10840 break; 10841 10842 case ITYPE_INSN: 10843 if (first && from_wide_insn) 10844 { 10845 target_offset += xtensa_format_length (isa, fmt); 10846 first = false; 10847 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 10848 target_offset += xg_get_single_size (tinsn->opcode); 10849 } 10850 else 10851 target_offset += xg_get_single_size (tinsn->opcode); 10852 break; 10853 } 10854 } 10855 10856 total_size = 0; 10857 first = true; 10858 for (i = 0; i < istack.ninsn; i++) 10859 { 10860 TInsn *tinsn = &istack.insn[i]; 10861 fragS *lit_frag; 10862 int size; 10863 segT target_seg; 10864 bfd_reloc_code_real_type reloc_type; 10865 10866 switch (tinsn->insn_type) 10867 { 10868 case ITYPE_LITERAL: 10869 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 10870 /* Already checked. */ 10871 gas_assert (lit_frag != NULL); 10872 gas_assert (lit_sym != NULL); 10873 gas_assert (tinsn->ntok == 1); 10874 /* Add a fixup. */ 10875 target_seg = S_GET_SEGMENT (lit_sym); 10876 gas_assert (target_seg); 10877 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, true); 10878 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, 10879 &tinsn->tok[0], false, reloc_type); 10880 break; 10881 10882 case ITYPE_LABEL: 10883 break; 10884 10885 case ITYPE_INSN: 10886 xg_resolve_labels (tinsn, gen_label); 10887 xg_resolve_literals (tinsn, lit_sym); 10888 if (from_wide_insn && first) 10889 { 10890 first = false; 10891 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 10892 { 10893 cur_vinsn.slots[slot] = *tinsn; 10894 } 10895 else 10896 { 10897 cur_vinsn.slots[slot].opcode = 10898 xtensa_format_slot_nop_opcode (isa, fmt, slot); 10899 cur_vinsn.slots[slot].ntok = 0; 10900 } 10901 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, true); 10902 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, 10903 (unsigned char *) immed_instr, 0); 10904 fragP->tc_frag_data.is_insn = true; 10905 size = xtensa_format_length (isa, fmt); 10906 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 10907 { 10908 xg_emit_insn_to_buf 10909 (tinsn, immed_instr + size, fragP, 10910 immed_instr - fragP->fr_literal + size, true); 10911 size += xg_get_single_size (tinsn->opcode); 10912 } 10913 } 10914 else 10915 { 10916 size = xg_get_single_size (tinsn->opcode); 10917 xg_emit_insn_to_buf (tinsn, immed_instr, fragP, 10918 immed_instr - fragP->fr_literal, true); 10919 } 10920 immed_instr += size; 10921 total_size += size; 10922 break; 10923 } 10924 } 10925 10926 diff = total_size - old_size; 10927 gas_assert (diff >= 0); 10928 if (diff != 0) 10929 expanded = true; 10930 gas_assert (diff <= fragP->fr_var); 10931 fragP->fr_var -= diff; 10932 fragP->fr_fix += diff; 10933 } 10934 10935 /* Check for undefined immediates in LOOP instructions. */ 10936 if (is_loop) 10937 { 10938 symbolS *sym; 10939 sym = orig_tinsn.tok[1].X_add_symbol; 10940 if (sym != NULL && !S_IS_DEFINED (sym)) 10941 { 10942 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 10943 return; 10944 } 10945 sym = orig_tinsn.tok[1].X_op_symbol; 10946 if (sym != NULL && !S_IS_DEFINED (sym)) 10947 { 10948 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 10949 return; 10950 } 10951 } 10952 10953 if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) 10954 { 10955 /* Add an expansion note on the expanded instruction. */ 10956 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, 10957 &orig_tinsn.tok[0], true, 10958 BFD_RELOC_XTENSA_ASM_EXPAND); 10959 } 10960} 10961 10962 10963/* Add a new fix expression into the desired segment. We have to 10964 switch to that segment to do this. */ 10965 10966static fixS * 10967fix_new_exp_in_seg (segT new_seg, 10968 subsegT new_subseg, 10969 fragS *frag, 10970 int where, 10971 int size, 10972 expressionS *exp, 10973 int pcrel, 10974 bfd_reloc_code_real_type r_type) 10975{ 10976 fixS *new_fix; 10977 segT seg = now_seg; 10978 subsegT subseg = now_subseg; 10979 10980 gas_assert (new_seg != 0); 10981 subseg_set (new_seg, new_subseg); 10982 10983 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); 10984 subseg_set (seg, subseg); 10985 return new_fix; 10986} 10987 10988 10989 10990/* A map that keeps information on a per-subsegment basis. This is 10991 maintained during initial assembly, but is invalid once the 10992 subsegments are smashed together. I.E., it cannot be used during 10993 the relaxation. */ 10994 10995typedef struct subseg_map_struct 10996{ 10997 /* the key */ 10998 segT seg; 10999 subsegT subseg; 11000 11001 /* the data */ 11002 unsigned flags; 11003 float total_freq; /* fall-through + branch target frequency */ 11004 float target_freq; /* branch target frequency alone */ 11005 11006 struct subseg_map_struct *next; 11007} subseg_map; 11008 11009 11010static subseg_map *sseg_map = NULL; 11011 11012static subseg_map * 11013get_subseg_info (segT seg, subsegT subseg) 11014{ 11015 subseg_map *subseg_e; 11016 11017 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) 11018 { 11019 if (seg == subseg_e->seg && subseg == subseg_e->subseg) 11020 break; 11021 } 11022 return subseg_e; 11023} 11024 11025 11026static subseg_map * 11027add_subseg_info (segT seg, subsegT subseg) 11028{ 11029 subseg_map *subseg_e = XNEW (subseg_map); 11030 memset (subseg_e, 0, sizeof (subseg_map)); 11031 subseg_e->seg = seg; 11032 subseg_e->subseg = subseg; 11033 subseg_e->flags = 0; 11034 /* Start off considering every branch target very important. */ 11035 subseg_e->target_freq = 1.0; 11036 subseg_e->total_freq = 1.0; 11037 subseg_e->next = sseg_map; 11038 sseg_map = subseg_e; 11039 return subseg_e; 11040} 11041 11042 11043static unsigned 11044get_last_insn_flags (segT seg, subsegT subseg) 11045{ 11046 subseg_map *subseg_e = get_subseg_info (seg, subseg); 11047 if (subseg_e) 11048 return subseg_e->flags; 11049 return 0; 11050} 11051 11052 11053static void 11054set_last_insn_flags (segT seg, 11055 subsegT subseg, 11056 unsigned fl, 11057 bool val) 11058{ 11059 subseg_map *subseg_e = get_subseg_info (seg, subseg); 11060 if (! subseg_e) 11061 subseg_e = add_subseg_info (seg, subseg); 11062 if (val) 11063 subseg_e->flags |= fl; 11064 else 11065 subseg_e->flags &= ~fl; 11066} 11067 11068 11069static float 11070get_subseg_total_freq (segT seg, subsegT subseg) 11071{ 11072 subseg_map *subseg_e = get_subseg_info (seg, subseg); 11073 if (subseg_e) 11074 return subseg_e->total_freq; 11075 return 1.0; 11076} 11077 11078 11079static float 11080get_subseg_target_freq (segT seg, subsegT subseg) 11081{ 11082 subseg_map *subseg_e = get_subseg_info (seg, subseg); 11083 if (subseg_e) 11084 return subseg_e->target_freq; 11085 return 1.0; 11086} 11087 11088 11089static void 11090set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) 11091{ 11092 subseg_map *subseg_e = get_subseg_info (seg, subseg); 11093 if (! subseg_e) 11094 subseg_e = add_subseg_info (seg, subseg); 11095 subseg_e->total_freq = total_f; 11096 subseg_e->target_freq = target_f; 11097} 11098 11099 11100/* Segment Lists and emit_state Stuff. */ 11101 11102static void 11103xtensa_move_seg_list_to_beginning (seg_list *head) 11104{ 11105 head = head->next; 11106 while (head) 11107 { 11108 segT literal_section = head->seg; 11109 11110 /* Move the literal section to the front of the section list. */ 11111 gas_assert (literal_section); 11112 if (literal_section != stdoutput->sections) 11113 { 11114 bfd_section_list_remove (stdoutput, literal_section); 11115 bfd_section_list_prepend (stdoutput, literal_section); 11116 } 11117 head = head->next; 11118 } 11119} 11120 11121 11122static void mark_literal_frags (seg_list *); 11123 11124static void 11125xg_promote_candidate_litpool (struct litpool_seg *lps, 11126 struct litpool_frag *lp) 11127{ 11128 fragS *poolbeg; 11129 fragS *poolend; 11130 symbolS *lsym; 11131 char label[10 + 2 * sizeof (fragS *)]; 11132 11133 poolbeg = lp->fragP; 11134 lp->priority = 1; 11135 poolbeg->fr_subtype = RELAX_LITERAL_POOL_BEGIN; 11136 poolend = poolbeg->fr_next; 11137 gas_assert (poolend->fr_type == rs_machine_dependent && 11138 poolend->fr_subtype == RELAX_LITERAL_POOL_END); 11139 /* Create a local symbol pointing to the 11140 end of the pool. */ 11141 sprintf (label, ".L0_LT_%p", poolbeg); 11142 lsym = (symbolS *) local_symbol_make (label, lps->seg, poolend, 0); 11143 poolbeg->fr_symbol = lsym; 11144 /* Rest is done in xtensa_relax_frag. */ 11145} 11146 11147static struct litpool_frag *xg_find_litpool (struct litpool_seg *lps, 11148 struct litpool_frag *lpf, 11149 addressT addr) 11150{ 11151 struct litpool_frag *lp = lpf->prev; 11152 11153 gas_assert (lp->fragP); 11154 11155 while (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) 11156 { 11157 lp = lp->prev; 11158 if (lp->fragP == NULL) 11159 { 11160 /* End of list; have to bite the bullet. 11161 Take the nearest. */ 11162 lp = lpf->prev; 11163 break; 11164 } 11165 /* Does it (conservatively) reach? */ 11166 if (addr - lp->addr <= 128 * 1024) 11167 { 11168 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN && 11169 lp->literal_count < MAX_POOL_LITERALS) 11170 { 11171 /* Found a good one. */ 11172 break; 11173 } 11174 else if (lp->prev->fragP && 11175 addr - lp->prev->addr > 128 * 1024 && 11176 lp->prev->literal_count < MAX_POOL_LITERALS) 11177 { 11178 /* This is still a "candidate" but the next one 11179 will be too far away, so revert to the nearest 11180 one, convert it and add the jump around. */ 11181 lp = lpf->prev; 11182 break; 11183 } 11184 } 11185 } 11186 11187 if (lp->literal_count >= MAX_POOL_LITERALS) 11188 { 11189 lp = lpf->prev; 11190 while (lp && lp->fragP && lp->literal_count >= MAX_POOL_LITERALS) 11191 { 11192 lp = lp->prev; 11193 } 11194 gas_assert (lp); 11195 } 11196 11197 gas_assert (lp && lp->fragP && lp->literal_count < MAX_POOL_LITERALS); 11198 ++lp->literal_count; 11199 11200 /* Convert candidate and add the jump around. */ 11201 if (lp->fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN) 11202 xg_promote_candidate_litpool (lps, lp); 11203 11204 return lp; 11205} 11206 11207static bool xtensa_is_init_fini (segT seg) 11208{ 11209 if (!seg) 11210 return 0; 11211 return strcmp (segment_name (seg), INIT_SECTION_NAME) == 0 11212 || strcmp (segment_name (seg), FINI_SECTION_NAME) == 0; 11213} 11214 11215static void 11216xtensa_assign_litpool_addresses (void) 11217{ 11218 struct litpool_seg *lps; 11219 11220 for (lps = litpool_seg_list.next; lps; lps = lps->next) 11221 { 11222 frchainS *frchP = seg_info (lps->seg)->frchainP; 11223 struct litpool_frag *lpf = lps->frag_list.next; 11224 addressT addr = 0; 11225 11226 if (xtensa_is_init_fini (lps->seg)) 11227 continue; 11228 11229 for ( ; frchP; frchP = frchP->frch_next) 11230 { 11231 fragS *fragP; 11232 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 11233 { 11234 if (lpf && fragP == lpf->fragP) 11235 { 11236 gas_assert(fragP->fr_type == rs_machine_dependent && 11237 (fragP->fr_subtype == RELAX_LITERAL_POOL_BEGIN || 11238 fragP->fr_subtype == RELAX_LITERAL_POOL_CANDIDATE_BEGIN)); 11239 /* Found a litpool location. */ 11240 lpf->addr = addr; 11241 lpf = lpf->next; 11242 } 11243 if (fragP->fr_type == rs_machine_dependent && 11244 fragP->fr_subtype == RELAX_SLOTS) 11245 { 11246 int slot; 11247 for (slot = 0; slot < MAX_SLOTS; slot++) 11248 { 11249 fragS *litfrag = fragP->tc_frag_data.literal_frags[slot]; 11250 11251 if (litfrag 11252 && litfrag->tc_frag_data.is_literal 11253 && !litfrag->tc_frag_data.literal_frag) 11254 { 11255 /* L32R referring .literal or generated as a result 11256 of relaxation. Point its literal to the nearest 11257 litpool preferring non-"candidate" positions to 11258 avoid the jump-around. */ 11259 11260 struct litpool_frag *lp; 11261 11262 lp = xg_find_litpool (lps, lpf, addr); 11263 /* Take earliest use of this literal to avoid 11264 forward refs. */ 11265 litfrag->tc_frag_data.literal_frag = lp->fragP; 11266 } 11267 } 11268 } 11269 addr += fragP->fr_fix; 11270 if (fragP->fr_type == rs_fill) 11271 addr += fragP->fr_offset; 11272 } 11273 } 11274 } 11275} 11276 11277static void 11278xtensa_move_literals (void) 11279{ 11280 seg_list *segment; 11281 frchainS *frchain_from, *frchain_to; 11282 fragS *search_frag, *next_frag, *literal_pool, *insert_after; 11283 fragS **frag_splice; 11284 emit_state state; 11285 segT dest_seg; 11286 fixS *fix, *next_fix, **fix_splice; 11287 sym_list *lit; 11288 const char *init_name = INIT_SECTION_NAME; 11289 const char *fini_name = FINI_SECTION_NAME; 11290 int init_name_len = strlen(init_name); 11291 int fini_name_len = strlen(fini_name); 11292 11293 mark_literal_frags (literal_head->next); 11294 11295 if (use_literal_section) 11296 return; 11297 11298 /* Assign addresses (rough estimates) to the potential literal pool locations 11299 and create new ones if the gaps are too large. */ 11300 11301 xtensa_assign_litpool_addresses (); 11302 11303 /* Walk through the literal segments. */ 11304 for (segment = literal_head->next; segment; segment = segment->next) 11305 { 11306 const char *seg_name = segment_name (segment->seg); 11307 11308 /* Keep the literals for .init and .fini in separate sections. */ 11309 if ((!memcmp (seg_name, init_name, init_name_len) && 11310 !strcmp (seg_name + init_name_len, ".literal")) || 11311 (!memcmp (seg_name, fini_name, fini_name_len) && 11312 !strcmp (seg_name + fini_name_len, ".literal"))) 11313 continue; 11314 11315 frchain_from = seg_info (segment->seg)->frchainP; 11316 search_frag = frchain_from->frch_root; 11317 literal_pool = NULL; 11318 frchain_to = NULL; 11319 frag_splice = &(frchain_from->frch_root); 11320 11321 while (search_frag && !search_frag->tc_frag_data.literal_frag) 11322 { 11323 gas_assert (search_frag->fr_fix == 0 11324 || search_frag->fr_type == rs_align); 11325 search_frag = search_frag->fr_next; 11326 } 11327 11328 if (!search_frag) 11329 continue; 11330 11331 gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype 11332 == RELAX_LITERAL_POOL_BEGIN); 11333 xtensa_switch_section_emit_state (&state, segment->seg, 0); 11334 11335 /* Make sure that all the frags in this series are closed, and 11336 that there is at least one left over of zero-size. This 11337 prevents us from making a segment with an frchain without any 11338 frags in it. */ 11339 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 11340 xtensa_set_frag_assembly_state (frag_now); 11341 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 11342 xtensa_set_frag_assembly_state (frag_now); 11343 11344 while (search_frag != frag_now) 11345 { 11346 next_frag = search_frag->fr_next; 11347 if (search_frag->tc_frag_data.literal_frag) 11348 { 11349 literal_pool = search_frag->tc_frag_data.literal_frag; 11350 gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); 11351 frchain_to = literal_pool->tc_frag_data.lit_frchain; 11352 gas_assert (frchain_to); 11353 } 11354 11355 if (search_frag->fr_type == rs_fill && search_frag->fr_fix == 0) 11356 { 11357 /* Skip empty fill frags. */ 11358 *frag_splice = next_frag; 11359 search_frag = next_frag; 11360 continue; 11361 } 11362 11363 if (search_frag->fr_type == rs_align) 11364 { 11365 /* Skip alignment frags, because the pool as a whole will be 11366 aligned if used, and we don't want to force alignment if the 11367 pool is unused. */ 11368 *frag_splice = next_frag; 11369 search_frag = next_frag; 11370 continue; 11371 } 11372 11373 /* First, move the frag out of the literal section and 11374 to the appropriate place. */ 11375 11376 /* Insert an alignment frag at start of pool. */ 11377 if (literal_pool->fr_next->fr_type == rs_machine_dependent && 11378 literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END) 11379 { 11380 segT pool_seg = literal_pool->fr_next->tc_frag_data.lit_seg; 11381 emit_state prev_state; 11382 fragS *prev_frag; 11383 fragS *align_frag; 11384 xtensa_switch_section_emit_state (&prev_state, pool_seg, 0); 11385 prev_frag = frag_now; 11386 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 11387 align_frag = frag_now; 11388 frag_align (2, 0, 0); 11389 /* Splice it into the right place. */ 11390 prev_frag->fr_next = align_frag->fr_next; 11391 align_frag->fr_next = literal_pool->fr_next; 11392 literal_pool->fr_next = align_frag; 11393 /* Insert after this one. */ 11394 literal_pool->tc_frag_data.literal_frag = align_frag; 11395 xtensa_restore_emit_state (&prev_state); 11396 } 11397 insert_after = literal_pool->tc_frag_data.literal_frag; 11398 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; 11399 /* Skip align frag. */ 11400 if (insert_after->fr_next->fr_type == rs_align) 11401 { 11402 insert_after = insert_after->fr_next; 11403 } 11404 11405 *frag_splice = next_frag; 11406 search_frag->fr_next = insert_after->fr_next; 11407 insert_after->fr_next = search_frag; 11408 search_frag->tc_frag_data.lit_seg = dest_seg; 11409 literal_pool->tc_frag_data.literal_frag = search_frag; 11410 11411 /* Now move any fixups associated with this frag to the 11412 right section. */ 11413 fix = frchain_from->fix_root; 11414 fix_splice = &(frchain_from->fix_root); 11415 while (fix) 11416 { 11417 next_fix = fix->fx_next; 11418 if (fix->fx_frag == search_frag) 11419 { 11420 *fix_splice = next_fix; 11421 fix->fx_next = frchain_to->fix_root; 11422 frchain_to->fix_root = fix; 11423 if (frchain_to->fix_tail == NULL) 11424 frchain_to->fix_tail = fix; 11425 } 11426 else 11427 fix_splice = &(fix->fx_next); 11428 fix = next_fix; 11429 } 11430 search_frag = next_frag; 11431 } 11432 11433 if (frchain_from->fix_root != NULL) 11434 { 11435 frchain_from = seg_info (segment->seg)->frchainP; 11436 as_warn (_("fixes not all moved from %s"), segment->seg->name); 11437 11438 gas_assert (frchain_from->fix_root == NULL); 11439 } 11440 frchain_from->fix_tail = NULL; 11441 xtensa_restore_emit_state (&state); 11442 } 11443 11444 /* Now fix up the SEGMENT value for all the literal symbols. */ 11445 for (lit = literal_syms; lit; lit = lit->next) 11446 { 11447 symbolS *lit_sym = lit->sym; 11448 segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; 11449 if (dseg) 11450 S_SET_SEGMENT (lit_sym, dseg); 11451 } 11452} 11453 11454 11455/* Walk over all the frags for segments in a list and mark them as 11456 containing literals. As clunky as this is, we can't rely on frag_var 11457 and frag_variant to get called in all situations. */ 11458 11459static void 11460mark_literal_frags (seg_list *segment) 11461{ 11462 frchainS *frchain_from; 11463 fragS *search_frag; 11464 11465 while (segment) 11466 { 11467 frchain_from = seg_info (segment->seg)->frchainP; 11468 search_frag = frchain_from->frch_root; 11469 while (search_frag) 11470 { 11471 search_frag->tc_frag_data.is_literal = true; 11472 search_frag = search_frag->fr_next; 11473 } 11474 segment = segment->next; 11475 } 11476} 11477 11478 11479static void 11480xtensa_reorder_seg_list (seg_list *head, segT after) 11481{ 11482 /* Move all of the sections in the section list to come 11483 after "after" in the gnu segment list. */ 11484 11485 head = head->next; 11486 while (head) 11487 { 11488 segT literal_section = head->seg; 11489 11490 /* Move the literal section after "after". */ 11491 gas_assert (literal_section); 11492 if (literal_section != after) 11493 { 11494 bfd_section_list_remove (stdoutput, literal_section); 11495 bfd_section_list_insert_after (stdoutput, after, literal_section); 11496 } 11497 11498 head = head->next; 11499 } 11500} 11501 11502 11503/* Push all the literal segments to the end of the gnu list. */ 11504 11505static void 11506xtensa_reorder_segments (void) 11507{ 11508 segT sec; 11509 segT last_sec = 0; 11510 int old_count = 0; 11511 int new_count = 0; 11512 11513 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 11514 { 11515 last_sec = sec; 11516 old_count++; 11517 } 11518 11519 /* Now that we have the last section, push all the literal 11520 sections to the end. */ 11521 xtensa_reorder_seg_list (literal_head, last_sec); 11522 11523 /* Now perform the final error check. */ 11524 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 11525 new_count++; 11526 gas_assert (new_count == old_count); 11527} 11528 11529 11530/* Change the emit state (seg, subseg, and frag related stuff) to the 11531 correct location. Return a emit_state which can be passed to 11532 xtensa_restore_emit_state to return to current fragment. */ 11533 11534static void 11535xtensa_switch_to_literal_fragment (emit_state *result) 11536{ 11537 if (directive_state[directive_absolute_literals]) 11538 { 11539 segT lit4_seg = cache_literal_section (true); 11540 xtensa_switch_section_emit_state (result, lit4_seg, 0); 11541 } 11542 else 11543 xtensa_switch_to_non_abs_literal_fragment (result); 11544 11545 /* Do a 4-byte align here. */ 11546 frag_align (2, 0, 0); 11547 record_alignment (now_seg, 2); 11548} 11549 11550 11551static void 11552xtensa_switch_to_non_abs_literal_fragment (emit_state *result) 11553{ 11554 fragS *pool_location = get_literal_pool_location (now_seg); 11555 segT lit_seg; 11556 bool is_init_fini = xtensa_is_init_fini (now_seg); 11557 11558 if (pool_location == NULL 11559 && !use_literal_section 11560 && !is_init_fini) 11561 { 11562 if (!auto_litpools) 11563 { 11564 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); 11565 } 11566 xtensa_maybe_create_literal_pool_frag (true, true); 11567 pool_location = get_literal_pool_location (now_seg); 11568 } 11569 11570 lit_seg = cache_literal_section (false); 11571 xtensa_switch_section_emit_state (result, lit_seg, 0); 11572 11573 if (!use_literal_section 11574 && !is_init_fini 11575 && get_literal_pool_location (now_seg) != pool_location) 11576 { 11577 /* Close whatever frag is there. */ 11578 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 11579 xtensa_set_frag_assembly_state (frag_now); 11580 frag_now->tc_frag_data.literal_frag = pool_location; 11581 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 11582 xtensa_set_frag_assembly_state (frag_now); 11583 } 11584} 11585 11586 11587/* Call this function before emitting data into the literal section. 11588 This is a helper function for xtensa_switch_to_literal_fragment. 11589 This is similar to a .section new_now_seg subseg. */ 11590 11591static void 11592xtensa_switch_section_emit_state (emit_state *state, 11593 segT new_now_seg, 11594 subsegT new_now_subseg) 11595{ 11596 state->name = now_seg->name; 11597 state->now_seg = now_seg; 11598 state->now_subseg = now_subseg; 11599 state->generating_literals = generating_literals; 11600 generating_literals++; 11601 subseg_set (new_now_seg, new_now_subseg); 11602} 11603 11604 11605/* Use to restore the emitting into the normal place. */ 11606 11607static void 11608xtensa_restore_emit_state (emit_state *state) 11609{ 11610 generating_literals = state->generating_literals; 11611 subseg_set (state->now_seg, state->now_subseg); 11612} 11613 11614 11615/* Predicate function used to look up a section in a particular group. */ 11616 11617static bool 11618match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) 11619{ 11620 const char *gname = inf; 11621 const char *group_name = elf_group_name (sec); 11622 11623 return (group_name == gname 11624 || (group_name != NULL 11625 && gname != NULL 11626 && strcmp (group_name, gname) == 0)); 11627} 11628 11629 11630/* Get the literal section to be used for the current text section. 11631 The result may be cached in the default_lit_sections structure. */ 11632 11633static segT 11634cache_literal_section (bool use_abs_literals) 11635{ 11636 const char *text_name, *group_name = 0; 11637 const char *base_name, *suffix; 11638 char *name; 11639 segT *pcached; 11640 segT seg, current_section; 11641 int current_subsec; 11642 bool linkonce = false; 11643 11644 /* Save the current section/subsection. */ 11645 current_section = now_seg; 11646 current_subsec = now_subseg; 11647 11648 /* Clear the cached values if they are no longer valid. */ 11649 if (now_seg != default_lit_sections.current_text_seg) 11650 { 11651 default_lit_sections.current_text_seg = now_seg; 11652 default_lit_sections.lit_seg = NULL; 11653 default_lit_sections.lit4_seg = NULL; 11654 } 11655 11656 /* Check if the literal section is already cached. */ 11657 if (use_abs_literals) 11658 pcached = &default_lit_sections.lit4_seg; 11659 else 11660 pcached = &default_lit_sections.lit_seg; 11661 11662 if (*pcached) 11663 return *pcached; 11664 11665 text_name = default_lit_sections.lit_prefix; 11666 if (! text_name || ! *text_name) 11667 { 11668 text_name = segment_name (current_section); 11669 group_name = elf_group_name (current_section); 11670 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; 11671 } 11672 11673 base_name = use_abs_literals ? ".lit4" : ".literal"; 11674 if (group_name) 11675 { 11676 name = concat (base_name, ".", group_name, (char *) NULL); 11677 } 11678 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) 11679 { 11680 suffix = strchr (text_name + linkonce_len, '.'); 11681 11682 name = concat (".gnu.linkonce", base_name, suffix ? suffix : "", 11683 (char *) NULL); 11684 linkonce = true; 11685 } 11686 else 11687 { 11688 /* If the section name begins or ends with ".text", then replace 11689 that portion instead of appending an additional suffix. */ 11690 size_t len = strlen (text_name); 11691 if (len >= 5 11692 && (strcmp (text_name + len - 5, ".text") == 0 11693 || startswith (text_name, ".text"))) 11694 len -= 5; 11695 11696 name = XNEWVEC (char, len + strlen (base_name) + 1); 11697 if (startswith (text_name, ".text")) 11698 { 11699 strcpy (name, base_name); 11700 strcat (name, text_name + 5); 11701 } 11702 else 11703 { 11704 strcpy (name, text_name); 11705 strcpy (name + len, base_name); 11706 } 11707 } 11708 11709 /* Canonicalize section names to allow renaming literal sections. 11710 The group name, if any, came from the current text section and 11711 has already been canonicalized. */ 11712 name = tc_canonicalize_symbol_name (name); 11713 11714 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, 11715 (void *) group_name); 11716 if (! seg) 11717 { 11718 flagword flags; 11719 11720 seg = subseg_force_new (name, 0); 11721 11722 if (! use_abs_literals) 11723 { 11724 /* Add the newly created literal segment to the list. */ 11725 seg_list *n = XNEW (seg_list); 11726 n->seg = seg; 11727 n->next = literal_head->next; 11728 literal_head->next = n; 11729 } 11730 11731 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD 11732 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) 11733 | (use_abs_literals ? SEC_DATA : SEC_CODE)); 11734 11735 elf_group_name (seg) = group_name; 11736 11737 bfd_set_section_flags (seg, flags); 11738 bfd_set_section_alignment (seg, 2); 11739 } 11740 11741 *pcached = seg; 11742 subseg_set (current_section, current_subsec); 11743 return seg; 11744} 11745 11746 11747/* Property Tables Stuff. */ 11748 11749#define XTENSA_INSN_SEC_NAME ".xt.insn" 11750#define XTENSA_LIT_SEC_NAME ".xt.lit" 11751#define XTENSA_PROP_SEC_NAME ".xt.prop" 11752 11753typedef bool (*frag_predicate) (const fragS *); 11754typedef void (*frag_flags_fn) (const fragS *, frag_flags *); 11755 11756static bool get_frag_is_literal (const fragS *); 11757static void xtensa_create_property_segments 11758 (frag_predicate, frag_predicate, const char *, xt_section_type); 11759static void xtensa_create_xproperty_segments 11760 (frag_flags_fn, const char *, xt_section_type); 11761static bool exclude_section_from_property_tables (segT); 11762static bool section_has_property (segT, frag_predicate); 11763static bool section_has_xproperty (segT, frag_flags_fn); 11764static void add_xt_block_frags 11765 (segT, xtensa_block_info **, frag_predicate, frag_predicate); 11766static bool xtensa_frag_flags_is_empty (const frag_flags *); 11767static void xtensa_frag_flags_init (frag_flags *); 11768static void get_frag_property_flags (const fragS *, frag_flags *); 11769static flagword frag_flags_to_number (const frag_flags *); 11770static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); 11771 11772/* Set up property tables after relaxation. */ 11773 11774void 11775xtensa_post_relax_hook (void) 11776{ 11777 xtensa_move_seg_list_to_beginning (literal_head); 11778 11779 xtensa_find_unmarked_state_frags (); 11780 xtensa_mark_frags_for_org (); 11781 xtensa_mark_difference_of_two_symbols (); 11782 11783 xtensa_create_property_segments (get_frag_is_literal, 11784 NULL, 11785 XTENSA_LIT_SEC_NAME, 11786 xt_literal_sec); 11787 xtensa_create_xproperty_segments (get_frag_property_flags, 11788 XTENSA_PROP_SEC_NAME, 11789 xt_prop_sec); 11790 11791 if (warn_unaligned_branch_targets) 11792 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); 11793 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); 11794} 11795 11796 11797/* This function is only meaningful after xtensa_move_literals. */ 11798 11799static bool 11800get_frag_is_literal (const fragS *fragP) 11801{ 11802 gas_assert (fragP != NULL); 11803 return fragP->tc_frag_data.is_literal; 11804} 11805 11806 11807static void 11808xtensa_create_property_segments (frag_predicate property_function, 11809 frag_predicate end_property_function, 11810 const char *section_name_base, 11811 xt_section_type sec_type) 11812{ 11813 segT *seclist; 11814 11815 /* Walk over all of the current segments. 11816 Walk over each fragment 11817 For each non-empty fragment, 11818 Build a property record (append where possible). */ 11819 11820 for (seclist = &stdoutput->sections; 11821 seclist && *seclist; 11822 seclist = &(*seclist)->next) 11823 { 11824 segT sec = *seclist; 11825 11826 if (exclude_section_from_property_tables (sec)) 11827 continue; 11828 11829 if (section_has_property (sec, property_function)) 11830 { 11831 segment_info_type *xt_seg_info; 11832 xtensa_block_info **xt_blocks; 11833 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 11834 11835 prop_sec->output_section = prop_sec; 11836 subseg_set (prop_sec, 0); 11837 xt_seg_info = seg_info (prop_sec); 11838 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 11839 11840 /* Walk over all of the frchains here and add new sections. */ 11841 add_xt_block_frags (sec, xt_blocks, property_function, 11842 end_property_function); 11843 } 11844 } 11845 11846 /* Now we fill them out.... */ 11847 11848 for (seclist = &stdoutput->sections; 11849 seclist && *seclist; 11850 seclist = &(*seclist)->next) 11851 { 11852 segment_info_type *seginfo; 11853 xtensa_block_info *block; 11854 segT sec = *seclist; 11855 11856 seginfo = seg_info (sec); 11857 block = seginfo->tc_segment_info_data.blocks[sec_type]; 11858 11859 if (block) 11860 { 11861 xtensa_block_info *cur_block; 11862 int num_recs = 0; 11863 bfd_size_type rec_size; 11864 11865 for (cur_block = block; cur_block; cur_block = cur_block->next) 11866 num_recs++; 11867 11868 rec_size = num_recs * 8; 11869 bfd_set_section_size (sec, rec_size); 11870 11871 if (num_recs) 11872 { 11873 char *frag_data; 11874 int i; 11875 11876 subseg_set (sec, 0); 11877 frag_data = frag_more (rec_size); 11878 cur_block = block; 11879 for (i = 0; i < num_recs; i++) 11880 { 11881 fixS *fix; 11882 11883 /* Write the fixup. */ 11884 gas_assert (cur_block); 11885 fix = fix_new (frag_now, i * 8, 4, 11886 section_symbol (cur_block->sec), 11887 cur_block->offset, 11888 false, BFD_RELOC_32); 11889 fix->fx_file = "<internal>"; 11890 fix->fx_line = 0; 11891 11892 /* Write the length. */ 11893 md_number_to_chars (&frag_data[4 + i * 8], 11894 cur_block->size, 4); 11895 cur_block = cur_block->next; 11896 } 11897 frag_wane (frag_now); 11898 frag_new (0); 11899 frag_wane (frag_now); 11900 } 11901 } 11902 } 11903} 11904 11905 11906static void 11907xtensa_create_xproperty_segments (frag_flags_fn flag_fn, 11908 const char *section_name_base, 11909 xt_section_type sec_type) 11910{ 11911 segT *seclist; 11912 11913 /* Walk over all of the current segments. 11914 Walk over each fragment. 11915 For each fragment that has instructions, 11916 build an instruction record (append where possible). */ 11917 11918 for (seclist = &stdoutput->sections; 11919 seclist && *seclist; 11920 seclist = &(*seclist)->next) 11921 { 11922 segT sec = *seclist; 11923 11924 if (exclude_section_from_property_tables (sec)) 11925 continue; 11926 11927 if (section_has_xproperty (sec, flag_fn)) 11928 { 11929 segment_info_type *xt_seg_info; 11930 xtensa_block_info **xt_blocks; 11931 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 11932 11933 prop_sec->output_section = prop_sec; 11934 subseg_set (prop_sec, 0); 11935 xt_seg_info = seg_info (prop_sec); 11936 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 11937 11938 /* Walk over all of the frchains here and add new sections. */ 11939 add_xt_prop_frags (sec, xt_blocks, flag_fn); 11940 } 11941 } 11942 11943 /* Now we fill them out.... */ 11944 11945 for (seclist = &stdoutput->sections; 11946 seclist && *seclist; 11947 seclist = &(*seclist)->next) 11948 { 11949 segment_info_type *seginfo; 11950 xtensa_block_info *block; 11951 segT sec = *seclist; 11952 11953 seginfo = seg_info (sec); 11954 block = seginfo->tc_segment_info_data.blocks[sec_type]; 11955 11956 if (block) 11957 { 11958 xtensa_block_info *cur_block; 11959 int num_recs = 0; 11960 bfd_size_type rec_size; 11961 11962 for (cur_block = block; cur_block; cur_block = cur_block->next) 11963 num_recs++; 11964 11965 rec_size = num_recs * (8 + 4); 11966 bfd_set_section_size (sec, rec_size); 11967 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ 11968 11969 if (num_recs) 11970 { 11971 char *frag_data; 11972 int i; 11973 11974 subseg_set (sec, 0); 11975 frag_data = frag_more (rec_size); 11976 cur_block = block; 11977 for (i = 0; i < num_recs; i++) 11978 { 11979 fixS *fix; 11980 11981 /* Write the fixup. */ 11982 gas_assert (cur_block); 11983 fix = fix_new (frag_now, i * 12, 4, 11984 section_symbol (cur_block->sec), 11985 cur_block->offset, 11986 false, BFD_RELOC_32); 11987 fix->fx_file = "<internal>"; 11988 fix->fx_line = 0; 11989 11990 /* Write the length. */ 11991 md_number_to_chars (&frag_data[4 + i * 12], 11992 cur_block->size, 4); 11993 md_number_to_chars (&frag_data[8 + i * 12], 11994 frag_flags_to_number (&cur_block->flags), 11995 sizeof (flagword)); 11996 cur_block = cur_block->next; 11997 } 11998 frag_wane (frag_now); 11999 frag_new (0); 12000 frag_wane (frag_now); 12001 } 12002 } 12003 } 12004} 12005 12006 12007static bool 12008exclude_section_from_property_tables (segT sec) 12009{ 12010 flagword flags = bfd_section_flags (sec); 12011 12012 /* Sections that don't contribute to the memory footprint are excluded. */ 12013 if ((flags & SEC_DEBUGGING) 12014 || !(flags & SEC_ALLOC) 12015 || (flags & SEC_MERGE)) 12016 return true; 12017 12018 /* Linker cie and fde optimizations mess up property entries for 12019 eh_frame sections, but there is nothing inside them relevant to 12020 property tables anyway. */ 12021 if (strcmp (sec->name, ".eh_frame") == 0) 12022 return true; 12023 12024 return false; 12025} 12026 12027 12028static bool 12029section_has_property (segT sec, frag_predicate property_function) 12030{ 12031 segment_info_type *seginfo = seg_info (sec); 12032 fragS *fragP; 12033 12034 if (seginfo && seginfo->frchainP) 12035 { 12036 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 12037 { 12038 if (property_function (fragP) 12039 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 12040 return true; 12041 } 12042 } 12043 return false; 12044} 12045 12046 12047static bool 12048section_has_xproperty (segT sec, frag_flags_fn property_function) 12049{ 12050 segment_info_type *seginfo = seg_info (sec); 12051 fragS *fragP; 12052 12053 if (seginfo && seginfo->frchainP) 12054 { 12055 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 12056 { 12057 frag_flags prop_flags; 12058 property_function (fragP, &prop_flags); 12059 if (!xtensa_frag_flags_is_empty (&prop_flags)) 12060 return true; 12061 } 12062 } 12063 return false; 12064} 12065 12066 12067/* Two types of block sections exist right now: literal and insns. */ 12068 12069static void 12070add_xt_block_frags (segT sec, 12071 xtensa_block_info **xt_block, 12072 frag_predicate property_function, 12073 frag_predicate end_property_function) 12074{ 12075 fragS *fragP; 12076 12077 /* Build it if needed. */ 12078 while (*xt_block != NULL) 12079 xt_block = &(*xt_block)->next; 12080 /* We are either at NULL at the beginning or at the end. */ 12081 12082 /* Walk through the frags. */ 12083 if (seg_info (sec)->frchainP) 12084 { 12085 for (fragP = seg_info (sec)->frchainP->frch_root; 12086 fragP; 12087 fragP = fragP->fr_next) 12088 { 12089 if (property_function (fragP) 12090 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 12091 { 12092 if (*xt_block != NULL) 12093 { 12094 if ((*xt_block)->offset + (*xt_block)->size 12095 == fragP->fr_address) 12096 (*xt_block)->size += fragP->fr_fix; 12097 else 12098 xt_block = &((*xt_block)->next); 12099 } 12100 if (*xt_block == NULL) 12101 { 12102 xtensa_block_info *new_block = XNEW (xtensa_block_info); 12103 new_block->sec = sec; 12104 new_block->offset = fragP->fr_address; 12105 new_block->size = fragP->fr_fix; 12106 new_block->next = NULL; 12107 xtensa_frag_flags_init (&new_block->flags); 12108 *xt_block = new_block; 12109 } 12110 if (end_property_function 12111 && end_property_function (fragP)) 12112 { 12113 xt_block = &((*xt_block)->next); 12114 } 12115 } 12116 } 12117 } 12118} 12119 12120 12121/* Break the encapsulation of add_xt_prop_frags here. */ 12122 12123static bool 12124xtensa_frag_flags_is_empty (const frag_flags *prop_flags) 12125{ 12126 if (prop_flags->is_literal 12127 || prop_flags->is_insn 12128 || prop_flags->is_data 12129 || prop_flags->is_unreachable) 12130 return false; 12131 return true; 12132} 12133 12134 12135static void 12136xtensa_frag_flags_init (frag_flags *prop_flags) 12137{ 12138 memset (prop_flags, 0, sizeof (frag_flags)); 12139} 12140 12141 12142static void 12143get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) 12144{ 12145 xtensa_frag_flags_init (prop_flags); 12146 if (fragP->tc_frag_data.is_literal) 12147 prop_flags->is_literal = true; 12148 if (fragP->tc_frag_data.is_specific_opcode 12149 || fragP->tc_frag_data.is_no_transform) 12150 { 12151 prop_flags->is_no_transform = true; 12152 if (xtensa_frag_flags_is_empty (prop_flags)) 12153 prop_flags->is_data = true; 12154 } 12155 if (fragP->tc_frag_data.is_unreachable) 12156 prop_flags->is_unreachable = true; 12157 else if (fragP->tc_frag_data.is_insn) 12158 { 12159 prop_flags->is_insn = true; 12160 if (fragP->tc_frag_data.is_loop_target) 12161 prop_flags->insn.is_loop_target = true; 12162 if (fragP->tc_frag_data.is_branch_target) 12163 prop_flags->insn.is_branch_target = true; 12164 if (fragP->tc_frag_data.is_no_density) 12165 prop_flags->insn.is_no_density = true; 12166 if (fragP->tc_frag_data.use_absolute_literals) 12167 prop_flags->insn.is_abslit = true; 12168 } 12169 if (fragP->tc_frag_data.is_align) 12170 { 12171 prop_flags->is_align = true; 12172 prop_flags->alignment = fragP->tc_frag_data.alignment; 12173 if (xtensa_frag_flags_is_empty (prop_flags)) 12174 prop_flags->is_data = true; 12175 } 12176} 12177 12178 12179static flagword 12180frag_flags_to_number (const frag_flags *prop_flags) 12181{ 12182 flagword num = 0; 12183 if (prop_flags->is_literal) 12184 num |= XTENSA_PROP_LITERAL; 12185 if (prop_flags->is_insn) 12186 num |= XTENSA_PROP_INSN; 12187 if (prop_flags->is_data) 12188 num |= XTENSA_PROP_DATA; 12189 if (prop_flags->is_unreachable) 12190 num |= XTENSA_PROP_UNREACHABLE; 12191 if (prop_flags->insn.is_loop_target) 12192 num |= XTENSA_PROP_INSN_LOOP_TARGET; 12193 if (prop_flags->insn.is_branch_target) 12194 { 12195 num |= XTENSA_PROP_INSN_BRANCH_TARGET; 12196 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); 12197 } 12198 12199 if (prop_flags->insn.is_no_density) 12200 num |= XTENSA_PROP_INSN_NO_DENSITY; 12201 if (prop_flags->is_no_transform) 12202 num |= XTENSA_PROP_NO_TRANSFORM; 12203 if (prop_flags->insn.is_no_reorder) 12204 num |= XTENSA_PROP_INSN_NO_REORDER; 12205 if (prop_flags->insn.is_abslit) 12206 num |= XTENSA_PROP_INSN_ABSLIT; 12207 12208 if (prop_flags->is_align) 12209 { 12210 num |= XTENSA_PROP_ALIGN; 12211 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); 12212 } 12213 12214 return num; 12215} 12216 12217 12218static bool 12219xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, 12220 const frag_flags *prop_flags_2) 12221{ 12222 /* Cannot combine with an end marker. */ 12223 12224 if (prop_flags_1->is_literal != prop_flags_2->is_literal) 12225 return false; 12226 if (prop_flags_1->is_insn != prop_flags_2->is_insn) 12227 return false; 12228 if (prop_flags_1->is_data != prop_flags_2->is_data) 12229 return false; 12230 12231 if (prop_flags_1->is_insn) 12232 { 12233 /* Properties of the beginning of the frag. */ 12234 if (prop_flags_2->insn.is_loop_target) 12235 return false; 12236 if (prop_flags_2->insn.is_branch_target) 12237 return false; 12238 if (prop_flags_1->insn.is_no_density != 12239 prop_flags_2->insn.is_no_density) 12240 return false; 12241 if (prop_flags_1->is_no_transform != 12242 prop_flags_2->is_no_transform) 12243 return false; 12244 if (prop_flags_1->insn.is_no_reorder != 12245 prop_flags_2->insn.is_no_reorder) 12246 return false; 12247 if (prop_flags_1->insn.is_abslit != 12248 prop_flags_2->insn.is_abslit) 12249 return false; 12250 } 12251 12252 if (prop_flags_1->is_align) 12253 return false; 12254 12255 return true; 12256} 12257 12258 12259static bfd_vma 12260xt_block_aligned_size (const xtensa_block_info *xt_block) 12261{ 12262 bfd_vma end_addr; 12263 unsigned align_bits; 12264 12265 if (!xt_block->flags.is_align) 12266 return xt_block->size; 12267 12268 end_addr = xt_block->offset + xt_block->size; 12269 align_bits = xt_block->flags.alignment; 12270 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; 12271 return end_addr - xt_block->offset; 12272} 12273 12274 12275static bool 12276xtensa_xt_block_combine (xtensa_block_info *xt_block, 12277 const xtensa_block_info *xt_block_2) 12278{ 12279 if (xt_block->sec != xt_block_2->sec) 12280 return false; 12281 if (xt_block->offset + xt_block_aligned_size (xt_block) 12282 != xt_block_2->offset) 12283 return false; 12284 12285 if (xt_block_2->size == 0 12286 && (!xt_block_2->flags.is_unreachable 12287 || xt_block->flags.is_unreachable)) 12288 { 12289 if (xt_block_2->flags.is_align 12290 && xt_block->flags.is_align) 12291 { 12292 /* Nothing needed. */ 12293 if (xt_block->flags.alignment >= xt_block_2->flags.alignment) 12294 return true; 12295 } 12296 else 12297 { 12298 if (xt_block_2->flags.is_align) 12299 { 12300 /* Push alignment to previous entry. */ 12301 xt_block->flags.is_align = xt_block_2->flags.is_align; 12302 xt_block->flags.alignment = xt_block_2->flags.alignment; 12303 } 12304 return true; 12305 } 12306 } 12307 if (!xtensa_frag_flags_combinable (&xt_block->flags, 12308 &xt_block_2->flags)) 12309 return false; 12310 12311 xt_block->size += xt_block_2->size; 12312 12313 if (xt_block_2->flags.is_align) 12314 { 12315 xt_block->flags.is_align = true; 12316 xt_block->flags.alignment = xt_block_2->flags.alignment; 12317 } 12318 12319 return true; 12320} 12321 12322 12323static void 12324add_xt_prop_frags (segT sec, 12325 xtensa_block_info **xt_block, 12326 frag_flags_fn property_function) 12327{ 12328 fragS *fragP; 12329 12330 /* Build it if needed. */ 12331 while (*xt_block != NULL) 12332 { 12333 xt_block = &(*xt_block)->next; 12334 } 12335 /* We are either at NULL at the beginning or at the end. */ 12336 12337 /* Walk through the frags. */ 12338 if (seg_info (sec)->frchainP) 12339 { 12340 for (fragP = seg_info (sec)->frchainP->frch_root; fragP; 12341 fragP = fragP->fr_next) 12342 { 12343 xtensa_block_info tmp_block; 12344 tmp_block.sec = sec; 12345 tmp_block.offset = fragP->fr_address; 12346 tmp_block.size = fragP->fr_fix; 12347 tmp_block.next = NULL; 12348 property_function (fragP, &tmp_block.flags); 12349 12350 if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) 12351 /* && fragP->fr_fix != 0) */ 12352 { 12353 if ((*xt_block) == NULL 12354 || !xtensa_xt_block_combine (*xt_block, &tmp_block)) 12355 { 12356 xtensa_block_info *new_block; 12357 if ((*xt_block) != NULL) 12358 xt_block = &(*xt_block)->next; 12359 new_block = XNEW (xtensa_block_info); 12360 *new_block = tmp_block; 12361 *xt_block = new_block; 12362 } 12363 } 12364 } 12365 } 12366} 12367 12368 12369/* op_placement_info_table */ 12370 12371/* op_placement_info makes it easier to determine which 12372 ops can go in which slots. */ 12373 12374static void 12375init_op_placement_info_table (void) 12376{ 12377 xtensa_isa isa = xtensa_default_isa; 12378 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); 12379 xtensa_opcode opcode; 12380 xtensa_format fmt; 12381 int slot; 12382 int num_opcodes = xtensa_isa_num_opcodes (isa); 12383 12384 op_placement_table = XNEWVEC (op_placement_info, num_opcodes); 12385 gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); 12386 12387 for (opcode = 0; opcode < num_opcodes; opcode++) 12388 { 12389 op_placement_info *opi = &op_placement_table[opcode]; 12390 /* FIXME: Make tinsn allocation dynamic. */ 12391 if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) 12392 as_fatal (_("too many operands in instruction")); 12393 opi->narrowest = XTENSA_UNDEFINED; 12394 opi->narrowest_size = 0x7F; 12395 opi->narrowest_slot = 0; 12396 opi->formats = 0; 12397 opi->num_formats = 0; 12398 opi->issuef = 0; 12399 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 12400 { 12401 opi->slots[fmt] = 0; 12402 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 12403 { 12404 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) 12405 { 12406 int fmt_length = xtensa_format_length (isa, fmt); 12407 opi->issuef++; 12408 set_bit (fmt, opi->formats); 12409 set_bit (slot, opi->slots[fmt]); 12410 if (fmt_length < opi->narrowest_size 12411 || (fmt_length == opi->narrowest_size 12412 && (xtensa_format_num_slots (isa, fmt) 12413 < xtensa_format_num_slots (isa, 12414 opi->narrowest)))) 12415 { 12416 opi->narrowest = fmt; 12417 opi->narrowest_size = fmt_length; 12418 opi->narrowest_slot = slot; 12419 } 12420 } 12421 } 12422 if (opi->formats) 12423 opi->num_formats++; 12424 } 12425 } 12426 xtensa_insnbuf_free (isa, ibuf); 12427} 12428 12429 12430bool 12431opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) 12432{ 12433 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); 12434} 12435 12436 12437/* If the opcode is available in a single slot format, return its size. */ 12438 12439static int 12440xg_get_single_size (xtensa_opcode opcode) 12441{ 12442 return op_placement_table[opcode].narrowest_size; 12443} 12444 12445 12446static xtensa_format 12447xg_get_single_format (xtensa_opcode opcode) 12448{ 12449 return op_placement_table[opcode].narrowest; 12450} 12451 12452 12453static int 12454xg_get_single_slot (xtensa_opcode opcode) 12455{ 12456 return op_placement_table[opcode].narrowest_slot; 12457} 12458 12459 12460/* Instruction Stack Functions (from "xtensa-istack.h"). */ 12461 12462void 12463istack_init (IStack *stack) 12464{ 12465 stack->ninsn = 0; 12466} 12467 12468 12469bool 12470istack_empty (IStack *stack) 12471{ 12472 return (stack->ninsn == 0); 12473} 12474 12475 12476bool 12477istack_full (IStack *stack) 12478{ 12479 return (stack->ninsn == MAX_ISTACK); 12480} 12481 12482 12483/* Return a pointer to the top IStack entry. 12484 It is an error to call this if istack_empty () is TRUE. */ 12485 12486TInsn * 12487istack_top (IStack *stack) 12488{ 12489 int rec = stack->ninsn - 1; 12490 gas_assert (!istack_empty (stack)); 12491 return &stack->insn[rec]; 12492} 12493 12494 12495/* Add a new TInsn to an IStack. 12496 It is an error to call this if istack_full () is TRUE. */ 12497 12498void 12499istack_push (IStack *stack, TInsn *insn) 12500{ 12501 int rec = stack->ninsn; 12502 gas_assert (!istack_full (stack)); 12503 stack->insn[rec] = *insn; 12504 stack->ninsn++; 12505} 12506 12507 12508/* Clear space for the next TInsn on the IStack and return a pointer 12509 to it. It is an error to call this if istack_full () is TRUE. */ 12510 12511TInsn * 12512istack_push_space (IStack *stack) 12513{ 12514 int rec = stack->ninsn; 12515 TInsn *insn; 12516 gas_assert (!istack_full (stack)); 12517 insn = &stack->insn[rec]; 12518 tinsn_init (insn); 12519 stack->ninsn++; 12520 return insn; 12521} 12522 12523 12524/* Remove the last pushed instruction. It is an error to call this if 12525 istack_empty () returns TRUE. */ 12526 12527void 12528istack_pop (IStack *stack) 12529{ 12530 int rec = stack->ninsn - 1; 12531 gas_assert (!istack_empty (stack)); 12532 stack->ninsn--; 12533 tinsn_init (&stack->insn[rec]); 12534} 12535 12536 12537/* TInsn functions. */ 12538 12539void 12540tinsn_init (TInsn *dst) 12541{ 12542 memset (dst, 0, sizeof (TInsn)); 12543} 12544 12545 12546/* Return TRUE if ANY of the operands in the insn are symbolic. */ 12547 12548static bool 12549tinsn_has_symbolic_operands (const TInsn *insn) 12550{ 12551 int i; 12552 int n = insn->ntok; 12553 12554 gas_assert (insn->insn_type == ITYPE_INSN); 12555 12556 for (i = 0; i < n; ++i) 12557 { 12558 switch (insn->tok[i].X_op) 12559 { 12560 case O_register: 12561 case O_constant: 12562 break; 12563 default: 12564 return true; 12565 } 12566 } 12567 return false; 12568} 12569 12570 12571bool 12572tinsn_has_invalid_symbolic_operands (const TInsn *insn) 12573{ 12574 xtensa_isa isa = xtensa_default_isa; 12575 int i; 12576 int n = insn->ntok; 12577 12578 gas_assert (insn->insn_type == ITYPE_INSN); 12579 12580 for (i = 0; i < n; ++i) 12581 { 12582 switch (insn->tok[i].X_op) 12583 { 12584 case O_register: 12585 case O_constant: 12586 break; 12587 case O_big: 12588 case O_illegal: 12589 case O_absent: 12590 /* Errors for these types are caught later. */ 12591 break; 12592 case O_hi16: 12593 case O_lo16: 12594 default: 12595 /* Symbolic immediates are only allowed on the last immediate 12596 operand. At this time, CONST16 is the only opcode where we 12597 support non-PC-relative relocations. */ 12598 if (i != get_relaxable_immed (insn->opcode) 12599 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 12600 && insn->opcode != xtensa_const16_opcode)) 12601 { 12602 as_bad (_("invalid symbolic operand")); 12603 return true; 12604 } 12605 } 12606 } 12607 return false; 12608} 12609 12610 12611/* For assembly code with complex expressions (e.g. subtraction), 12612 we have to build them in the literal pool so that 12613 their results are calculated correctly after relaxation. 12614 The relaxation only handles expressions that 12615 boil down to SYMBOL + OFFSET. */ 12616 12617static bool 12618tinsn_has_complex_operands (const TInsn *insn) 12619{ 12620 int i; 12621 int n = insn->ntok; 12622 gas_assert (insn->insn_type == ITYPE_INSN); 12623 for (i = 0; i < n; ++i) 12624 { 12625 switch (insn->tok[i].X_op) 12626 { 12627 case O_register: 12628 case O_constant: 12629 case O_symbol: 12630 case O_lo16: 12631 case O_hi16: 12632 break; 12633 default: 12634 return true; 12635 } 12636 } 12637 return false; 12638} 12639 12640 12641/* Encode a TInsn opcode and its constant operands into slotbuf. 12642 Return TRUE if there is a symbol in the immediate field. This 12643 function assumes that: 12644 1) The number of operands are correct. 12645 2) The insn_type is ITYPE_INSN. 12646 3) The opcode can be encoded in the specified format and slot. 12647 4) Operands are either O_constant or O_symbol, and all constants fit. */ 12648 12649static bool 12650tinsn_to_slotbuf (xtensa_format fmt, 12651 int slot, 12652 TInsn *tinsn, 12653 xtensa_insnbuf slotbuf) 12654{ 12655 xtensa_isa isa = xtensa_default_isa; 12656 xtensa_opcode opcode = tinsn->opcode; 12657 bool has_fixup = false; 12658 int noperands = xtensa_opcode_num_operands (isa, opcode); 12659 int i; 12660 12661 gas_assert (tinsn->insn_type == ITYPE_INSN); 12662 if (noperands != tinsn->ntok) 12663 as_fatal (_("operand number mismatch")); 12664 12665 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) 12666 { 12667 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), 12668 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); 12669 return false; 12670 } 12671 12672 for (i = 0; i < noperands; i++) 12673 { 12674 expressionS *exp = &tinsn->tok[i]; 12675 int rc; 12676 unsigned line; 12677 const char *file_name; 12678 uint32 opnd_value; 12679 12680 switch (exp->X_op) 12681 { 12682 case O_register: 12683 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 12684 break; 12685 /* The register number has already been checked in 12686 expression_maybe_register, so we don't need to check here. */ 12687 opnd_value = exp->X_add_number; 12688 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); 12689 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, 12690 opnd_value); 12691 if (rc != 0) 12692 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); 12693 break; 12694 12695 case O_constant: 12696 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 12697 break; 12698 file_name = as_where (&line); 12699 /* It is a constant and we called this function 12700 then we have to try to fit it. */ 12701 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, 12702 exp->X_add_number, file_name, line); 12703 break; 12704 12705 default: 12706 has_fixup = true; 12707 break; 12708 } 12709 } 12710 12711 return has_fixup; 12712} 12713 12714 12715/* Encode a single TInsn into an insnbuf. If the opcode can only be encoded 12716 into a multi-slot instruction, fill the other slots with NOPs. 12717 Return TRUE if there is a symbol in the immediate field. See also the 12718 assumptions listed for tinsn_to_slotbuf. */ 12719 12720static bool 12721tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) 12722{ 12723 static xtensa_insnbuf slotbuf = 0; 12724 static vliw_insn vinsn; 12725 xtensa_isa isa = xtensa_default_isa; 12726 bool has_fixup = false; 12727 int i; 12728 12729 if (!slotbuf) 12730 { 12731 slotbuf = xtensa_insnbuf_alloc (isa); 12732 xg_init_vinsn (&vinsn); 12733 } 12734 12735 xg_clear_vinsn (&vinsn); 12736 12737 bundle_tinsn (tinsn, &vinsn); 12738 12739 xtensa_format_encode (isa, vinsn.format, insnbuf); 12740 12741 for (i = 0; i < vinsn.num_slots; i++) 12742 { 12743 /* Only one slot may have a fix-up because the rest contains NOPs. */ 12744 has_fixup |= 12745 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); 12746 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); 12747 } 12748 12749 return has_fixup; 12750} 12751 12752 12753/* Check the instruction arguments. Return TRUE on failure. */ 12754 12755static bool 12756tinsn_check_arguments (const TInsn *insn) 12757{ 12758 xtensa_isa isa = xtensa_default_isa; 12759 xtensa_opcode opcode = insn->opcode; 12760 xtensa_regfile t1_regfile, t2_regfile; 12761 int t1_reg, t2_reg; 12762 int t1_base_reg, t1_last_reg; 12763 int t2_base_reg, t2_last_reg; 12764 char t1_inout, t2_inout; 12765 int i, j; 12766 12767 if (opcode == XTENSA_UNDEFINED) 12768 { 12769 as_bad (_("invalid opcode")); 12770 return true; 12771 } 12772 12773 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) 12774 { 12775 as_bad (_("too few operands")); 12776 return true; 12777 } 12778 12779 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) 12780 { 12781 as_bad (_("too many operands")); 12782 return true; 12783 } 12784 12785 /* Check registers. */ 12786 for (j = 0; j < insn->ntok; j++) 12787 { 12788 if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) 12789 continue; 12790 12791 t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); 12792 t2_base_reg = insn->tok[j].X_add_number; 12793 t2_last_reg 12794 = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); 12795 12796 for (i = 0; i < insn->ntok; i++) 12797 { 12798 if (i == j) 12799 continue; 12800 12801 if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) 12802 continue; 12803 12804 t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); 12805 12806 if (t1_regfile != t2_regfile) 12807 continue; 12808 12809 t1_inout = xtensa_operand_inout (isa, insn->opcode, i); 12810 t2_inout = xtensa_operand_inout (isa, insn->opcode, j); 12811 12812 t1_base_reg = insn->tok[i].X_add_number; 12813 t1_last_reg = (t1_base_reg 12814 + xtensa_operand_num_regs (isa, insn->opcode, i)); 12815 12816 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 12817 { 12818 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 12819 { 12820 if (t1_reg != t2_reg) 12821 continue; 12822 12823 if (t1_inout != 'i' && t2_inout != 'i') 12824 { 12825 as_bad (_("multiple writes to the same register")); 12826 return true; 12827 } 12828 } 12829 } 12830 } 12831 } 12832 return false; 12833} 12834 12835 12836/* Load an instruction from its encoded form. */ 12837 12838static void 12839tinsn_from_chars (TInsn *tinsn, char *f, int slot) 12840{ 12841 vliw_insn vinsn; 12842 12843 xg_init_vinsn (&vinsn); 12844 vinsn_from_chars (&vinsn, f); 12845 12846 *tinsn = vinsn.slots[slot]; 12847 xg_free_vinsn (&vinsn); 12848} 12849 12850 12851static void 12852tinsn_from_insnbuf (TInsn *tinsn, 12853 xtensa_insnbuf slotbuf, 12854 xtensa_format fmt, 12855 int slot) 12856{ 12857 int i; 12858 xtensa_isa isa = xtensa_default_isa; 12859 12860 /* Find the immed. */ 12861 tinsn_init (tinsn); 12862 tinsn->insn_type = ITYPE_INSN; 12863 tinsn->is_specific_opcode = false; /* must not be specific */ 12864 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 12865 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); 12866 for (i = 0; i < tinsn->ntok; i++) 12867 { 12868 set_expr_const (&tinsn->tok[i], 12869 xtensa_insnbuf_get_operand (slotbuf, fmt, slot, 12870 tinsn->opcode, i)); 12871 } 12872} 12873 12874 12875/* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ 12876 12877static void 12878tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) 12879{ 12880 xtensa_opcode opcode = tinsn->opcode; 12881 int opnum; 12882 12883 if (fragP->tc_frag_data.slot_symbols[slot]) 12884 { 12885 opnum = get_relaxable_immed (opcode); 12886 gas_assert (opnum >= 0); 12887 set_expr_symbol_offset (&tinsn->tok[opnum], 12888 fragP->tc_frag_data.slot_symbols[slot], 12889 fragP->tc_frag_data.slot_offsets[slot]); 12890 } 12891 tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; 12892} 12893 12894 12895static int 12896get_num_stack_text_bytes (IStack *istack) 12897{ 12898 int i; 12899 int text_bytes = 0; 12900 12901 for (i = 0; i < istack->ninsn; i++) 12902 { 12903 TInsn *tinsn = &istack->insn[i]; 12904 if (tinsn->insn_type == ITYPE_INSN) 12905 text_bytes += xg_get_single_size (tinsn->opcode); 12906 } 12907 return text_bytes; 12908} 12909 12910 12911static int 12912get_num_stack_literal_bytes (IStack *istack) 12913{ 12914 int i; 12915 int lit_bytes = 0; 12916 12917 for (i = 0; i < istack->ninsn; i++) 12918 { 12919 TInsn *tinsn = &istack->insn[i]; 12920 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) 12921 lit_bytes += 4; 12922 } 12923 return lit_bytes; 12924} 12925 12926 12927/* vliw_insn functions. */ 12928 12929static void 12930xg_init_vinsn (vliw_insn *v) 12931{ 12932 int i; 12933 xtensa_isa isa = xtensa_default_isa; 12934 12935 xg_clear_vinsn (v); 12936 12937 v->insnbuf = xtensa_insnbuf_alloc (isa); 12938 if (v->insnbuf == NULL) 12939 as_fatal (_("out of memory")); 12940 12941 for (i = 0; i < config_max_slots; i++) 12942 { 12943 v->slotbuf[i] = xtensa_insnbuf_alloc (isa); 12944 if (v->slotbuf[i] == NULL) 12945 as_fatal (_("out of memory")); 12946 } 12947} 12948 12949 12950static void 12951xg_clear_vinsn (vliw_insn *v) 12952{ 12953 int i; 12954 12955 memset (v, 0, offsetof (vliw_insn, slots) 12956 + sizeof(TInsn) * config_max_slots); 12957 12958 v->format = XTENSA_UNDEFINED; 12959 v->num_slots = 0; 12960 v->inside_bundle = false; 12961 12962 if (xt_saved_debug_type != DEBUG_NONE) 12963 debug_type = xt_saved_debug_type; 12964 12965 for (i = 0; i < config_max_slots; i++) 12966 v->slots[i].opcode = XTENSA_UNDEFINED; 12967} 12968 12969 12970static void 12971xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) 12972{ 12973 memcpy (dst, src, 12974 offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); 12975 dst->insnbuf = src->insnbuf; 12976 memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); 12977} 12978 12979 12980static bool 12981vinsn_has_specific_opcodes (vliw_insn *v) 12982{ 12983 int i; 12984 12985 for (i = 0; i < v->num_slots; i++) 12986 { 12987 if (v->slots[i].is_specific_opcode) 12988 return true; 12989 } 12990 return false; 12991} 12992 12993 12994static void 12995xg_free_vinsn (vliw_insn *v) 12996{ 12997 int i; 12998 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); 12999 for (i = 0; i < config_max_slots; i++) 13000 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); 13001} 13002 13003 13004/* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic 13005 operands. See also the assumptions listed for tinsn_to_slotbuf. */ 13006 13007static bool 13008vinsn_to_insnbuf (vliw_insn *vinsn, 13009 char *frag_offset, 13010 fragS *fragP, 13011 bool record_fixup) 13012{ 13013 xtensa_isa isa = xtensa_default_isa; 13014 xtensa_format fmt = vinsn->format; 13015 xtensa_insnbuf insnbuf = vinsn->insnbuf; 13016 int slot; 13017 bool has_fixup = false; 13018 13019 xtensa_format_encode (isa, fmt, insnbuf); 13020 13021 for (slot = 0; slot < vinsn->num_slots; slot++) 13022 { 13023 TInsn *tinsn = &vinsn->slots[slot]; 13024 expressionS *extra_arg = &tinsn->extra_arg; 13025 bool tinsn_has_fixup = 13026 tinsn_to_slotbuf (vinsn->format, slot, tinsn, 13027 vinsn->slotbuf[slot]); 13028 13029 xtensa_format_set_slot (isa, fmt, slot, 13030 insnbuf, vinsn->slotbuf[slot]); 13031 if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) 13032 { 13033 if (vinsn->num_slots != 1) 13034 as_bad (_("TLS relocation not allowed in FLIX bundle")); 13035 else if (record_fixup) 13036 /* Instructions that generate TLS relocations should always be 13037 relaxed in the front-end. If "record_fixup" is set, then this 13038 function is being called during back-end relaxation, so flag 13039 the unexpected behavior as an error. */ 13040 as_bad (_("unexpected TLS relocation")); 13041 else 13042 fix_new (fragP, frag_offset - fragP->fr_literal, 13043 xtensa_format_length (isa, fmt), 13044 extra_arg->X_add_symbol, extra_arg->X_add_number, 13045 false, map_operator_to_reloc (extra_arg->X_op, false)); 13046 } 13047 if (tinsn_has_fixup) 13048 { 13049 int i; 13050 xtensa_opcode opcode = tinsn->opcode; 13051 int noperands = xtensa_opcode_num_operands (isa, opcode); 13052 has_fixup = true; 13053 13054 for (i = 0; i < noperands; i++) 13055 { 13056 expressionS* exp = &tinsn->tok[i]; 13057 switch (exp->X_op) 13058 { 13059 case O_symbol: 13060 case O_lo16: 13061 case O_hi16: 13062 if (get_relaxable_immed (opcode) == i) 13063 { 13064 /* Add a fix record for the instruction, except if this 13065 function is being called prior to relaxation, i.e., 13066 if record_fixup is false, and the instruction might 13067 be relaxed later. */ 13068 if (record_fixup 13069 || tinsn->is_specific_opcode 13070 || !xg_is_relaxable_insn (tinsn, 0)) 13071 { 13072 xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, 13073 frag_offset - fragP->fr_literal); 13074 } 13075 else 13076 { 13077 if (exp->X_op != O_symbol) 13078 as_bad (_("invalid operand")); 13079 tinsn->symbol = exp->X_add_symbol; 13080 tinsn->offset = exp->X_add_number; 13081 } 13082 } 13083 else 13084 as_bad (_("symbolic operand not allowed")); 13085 break; 13086 13087 case O_constant: 13088 case O_register: 13089 break; 13090 13091 default: 13092 as_bad (_("expression too complex")); 13093 break; 13094 } 13095 } 13096 } 13097 } 13098 13099 return has_fixup; 13100} 13101 13102 13103static void 13104vinsn_from_chars (vliw_insn *vinsn, char *f) 13105{ 13106 static xtensa_insnbuf insnbuf = NULL; 13107 static xtensa_insnbuf slotbuf = NULL; 13108 int i; 13109 xtensa_format fmt; 13110 xtensa_isa isa = xtensa_default_isa; 13111 13112 if (!insnbuf) 13113 { 13114 insnbuf = xtensa_insnbuf_alloc (isa); 13115 slotbuf = xtensa_insnbuf_alloc (isa); 13116 } 13117 13118 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); 13119 fmt = xtensa_format_decode (isa, insnbuf); 13120 if (fmt == XTENSA_UNDEFINED) 13121 as_fatal (_("cannot decode instruction format")); 13122 vinsn->format = fmt; 13123 vinsn->num_slots = xtensa_format_num_slots (isa, fmt); 13124 13125 for (i = 0; i < vinsn->num_slots; i++) 13126 { 13127 TInsn *tinsn = &vinsn->slots[i]; 13128 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); 13129 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); 13130 } 13131} 13132 13133 13134/* Expression utilities. */ 13135 13136/* Return TRUE if the expression is an integer constant. */ 13137 13138bool 13139expr_is_const (const expressionS *s) 13140{ 13141 return (s->X_op == O_constant); 13142} 13143 13144 13145/* Get the expression constant. 13146 Calling this is illegal if expr_is_const () returns TRUE. */ 13147 13148offsetT 13149get_expr_const (const expressionS *s) 13150{ 13151 gas_assert (expr_is_const (s)); 13152 return s->X_add_number; 13153} 13154 13155 13156/* Set the expression to a constant value. */ 13157 13158void 13159set_expr_const (expressionS *s, offsetT val) 13160{ 13161 s->X_op = O_constant; 13162 s->X_add_number = val; 13163 s->X_add_symbol = NULL; 13164 s->X_op_symbol = NULL; 13165} 13166 13167 13168bool 13169expr_is_register (const expressionS *s) 13170{ 13171 return (s->X_op == O_register); 13172} 13173 13174 13175/* Get the expression constant. 13176 Calling this is illegal if expr_is_const () returns TRUE. */ 13177 13178offsetT 13179get_expr_register (const expressionS *s) 13180{ 13181 gas_assert (expr_is_register (s)); 13182 return s->X_add_number; 13183} 13184 13185 13186/* Set the expression to a symbol + constant offset. */ 13187 13188void 13189set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) 13190{ 13191 s->X_op = O_symbol; 13192 s->X_add_symbol = sym; 13193 s->X_op_symbol = NULL; /* unused */ 13194 s->X_add_number = offset; 13195} 13196 13197 13198/* Return TRUE if the two expressions are equal. */ 13199 13200bool 13201expr_is_equal (expressionS *s1, expressionS *s2) 13202{ 13203 if (s1->X_op != s2->X_op) 13204 return false; 13205 if (s1->X_add_symbol != s2->X_add_symbol) 13206 return false; 13207 if (s1->X_op_symbol != s2->X_op_symbol) 13208 return false; 13209 if (s1->X_add_number != s2->X_add_number) 13210 return false; 13211 return true; 13212} 13213 13214 13215static void 13216copy_expr (expressionS *dst, const expressionS *src) 13217{ 13218 memcpy (dst, src, sizeof (expressionS)); 13219} 13220 13221 13222/* Support for the "--rename-section" option. */ 13223 13224struct rename_section_struct 13225{ 13226 const char *old_name; 13227 char *new_name; 13228 struct rename_section_struct *next; 13229}; 13230 13231static struct rename_section_struct *section_rename; 13232 13233 13234/* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add 13235 entries to the section_rename list. Note: Specifying multiple 13236 renamings separated by colons is not documented and is retained only 13237 for backward compatibility. */ 13238 13239static void 13240build_section_rename (const char *arg) 13241{ 13242 struct rename_section_struct *r; 13243 char *this_arg = NULL; 13244 char *next_arg = NULL; 13245 13246 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) 13247 { 13248 char *old_name, *new_name; 13249 13250 if (this_arg) 13251 { 13252 next_arg = strchr (this_arg, ':'); 13253 if (next_arg) 13254 { 13255 *next_arg = '\0'; 13256 next_arg++; 13257 } 13258 } 13259 13260 old_name = this_arg; 13261 new_name = strchr (this_arg, '='); 13262 13263 if (*old_name == '\0') 13264 { 13265 as_warn (_("ignoring extra '-rename-section' delimiter ':'")); 13266 continue; 13267 } 13268 if (!new_name || new_name[1] == '\0') 13269 { 13270 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), 13271 old_name); 13272 continue; 13273 } 13274 *new_name = '\0'; 13275 new_name++; 13276 13277 /* Check for invalid section renaming. */ 13278 for (r = section_rename; r != NULL; r = r->next) 13279 { 13280 if (strcmp (r->old_name, old_name) == 0) 13281 as_bad (_("section %s renamed multiple times"), old_name); 13282 if (strcmp (r->new_name, new_name) == 0) 13283 as_bad (_("multiple sections remapped to output section %s"), 13284 new_name); 13285 } 13286 13287 /* Now add it. */ 13288 r = XNEW (struct rename_section_struct); 13289 r->old_name = xstrdup (old_name); 13290 r->new_name = xstrdup (new_name); 13291 r->next = section_rename; 13292 section_rename = r; 13293 } 13294} 13295 13296 13297char * 13298xtensa_section_rename (const char *name) 13299{ 13300 struct rename_section_struct *r = section_rename; 13301 13302 for (r = section_rename; r != NULL; r = r->next) 13303 { 13304 if (strcmp (r->old_name, name) == 0) 13305 return r->new_name; 13306 } 13307 13308 return (char *) name; 13309} 13310